blob: 0f6edb14b7e436bc60fee0908e3ff7a45cd3ff41 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07007 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08008 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07009 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010010 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010011 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020012 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010013 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000014 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000015 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000016 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000017 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000018 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010019 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000020 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010021 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000022 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010023 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000024 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070025 select COMMON_CLK
Loc Ho6e681ab2015-05-22 17:32:56 -060026 select EDAC_SUPPORT
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000027 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000028 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070029 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010031 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000032 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070033 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010036 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010037 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070038 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000040 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010042 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010043 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010044 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010045 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010046 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010047 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080048 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000049 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000050 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010051 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070052 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010053 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010054 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010055 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070056 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070057 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010058 select HAVE_DMA_API_DEBUG
59 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000060 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010061 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000062 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010063 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090064 select HAVE_FUNCTION_TRACER
65 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010066 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010067 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010068 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000069 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010071 select HAVE_PERF_REGS
72 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070073 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010074 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020076 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010077 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select NO_BOOTMEM
79 select OF
80 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010081 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000083 select POWER_RESET
84 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010085 select RTC_LIB
86 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070087 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070088 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010089 help
90 ARM 64-bit (AArch64) Linux support.
91
92config 64BIT
93 def_bool y
94
95config ARCH_PHYS_ADDR_T_64BIT
96 def_bool y
97
98config MMU
99 def_bool y
100
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700101config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100102 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100103
104config STACKTRACE_SUPPORT
105 def_bool y
106
107config LOCKDEP_SUPPORT
108 def_bool y
109
110config TRACE_IRQFLAGS_SUPPORT
111 def_bool y
112
Will Deaconc209f792014-03-14 17:47:05 +0000113config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100114 def_bool y
115
116config GENERIC_HWEIGHT
117 def_bool y
118
119config GENERIC_CSUM
120 def_bool y
121
122config GENERIC_CALIBRATE_DELAY
123 def_bool y
124
Catalin Marinas19e76402014-02-27 12:09:22 +0000125config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100126 def_bool y
127
Steve Capper29e56942014-10-09 15:29:25 -0700128config HAVE_GENERIC_RCU_GUP
129 def_bool y
130
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100131config ARCH_DMA_ADDR_T_64BIT
132 def_bool y
133
134config NEED_DMA_MAP_STATE
135 def_bool y
136
137config NEED_SG_DMA_LENGTH
138 def_bool y
139
140config SWIOTLB
141 def_bool y
142
143config IOMMU_HELPER
144 def_bool SWIOTLB
145
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100146config KERNEL_MODE_NEON
147 def_bool y
148
Rob Herring92cc15f2014-04-18 17:19:59 -0500149config FIX_EARLYCON_MEM
150 def_bool y
151
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700152config PGTABLE_LEVELS
153 int
154 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
155 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
156 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
157 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
158
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100159source "init/Kconfig"
160
161source "kernel/Kconfig.freezer"
162
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100163menu "Platform selection"
164
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900165config ARCH_EXYNOS
166 bool
167 help
168 This enables support for Samsung Exynos SoC family
169
170config ARCH_EXYNOS7
171 bool "ARMv8 based Samsung Exynos7"
172 select ARCH_EXYNOS
173 select COMMON_CLK_SAMSUNG
174 select HAVE_S3C2410_WATCHDOG if WATCHDOG
175 select HAVE_S3C_RTC if RTC_CLASS
176 select PINCTRL
177 select PINCTRL_EXYNOS
178
179 help
180 This enables support for Samsung Exynos7 SoC family
181
Olof Johansson5118a6a2015-01-27 16:19:11 -0800182config ARCH_FSL_LS2085A
183 bool "Freescale LS2085A SOC"
184 help
185 This enables support for Freescale LS2085A SOC.
186
Bintian Wang85fe9462015-01-06 09:30:36 +0800187config ARCH_HISI
188 bool "Hisilicon SoC Family"
189 help
190 This enables support for Hisilicon ARMv8 SoC family
191
Eddie Huang4727a6f2015-12-01 10:14:00 +0100192config ARCH_MEDIATEK
193 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
194 select ARM_GIC
Yingjoe Chen0a233cd2015-03-06 14:24:50 +0800195 select PINCTRL
Eddie Huang4727a6f2015-12-01 10:14:00 +0100196 help
197 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
198
Abhimanyu Kapurd7f64a42013-10-15 21:11:09 -0700199config ARCH_QCOM
200 bool "Qualcomm Platforms"
201 select PINCTRL
202 help
203 This enables support for the ARMv8 based Qualcomm chipsets.
204
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700205config ARCH_SEATTLE
206 bool "AMD Seattle SoC Family"
207 help
208 This enables support for AMD Seattle SOC Family
209
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700210config ARCH_TEGRA
211 bool "NVIDIA Tegra SoC Family"
212 select ARCH_HAS_RESET_CONTROLLER
213 select ARCH_REQUIRE_GPIOLIB
214 select CLKDEV_LOOKUP
215 select CLKSRC_MMIO
216 select CLKSRC_OF
217 select GENERIC_CLOCKEVENTS
218 select HAVE_CLK
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700219 select PINCTRL
220 select RESET_CONTROLLER
221 help
222 This enables support for the NVIDIA Tegra SoC family.
223
224config ARCH_TEGRA_132_SOC
225 bool "NVIDIA Tegra132 SoC"
226 depends on ARCH_TEGRA
227 select PINCTRL_TEGRA124
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700228 select USB_ULPI if USB_PHY
229 select USB_ULPI_VIEWPORT if USB_PHY
230 help
231 Enable support for NVIDIA Tegra132 SoC, based on the Denver
232 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
233 but contains an NVIDIA Denver CPU complex in place of
234 Tegra124's "4+1" Cortex-A15 CPU complex.
235
Zhizhou Zhangc4bb7992015-03-11 02:27:08 +0000236config ARCH_SPRD
237 bool "Spreadtrum SoC platform"
238 help
239 Support for Spreadtrum ARM based SoCs
240
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530241config ARCH_THUNDER
242 bool "Cavium Inc. Thunder SoC Family"
243 help
244 This enables support for Cavium's Thunder Family of SoCs.
245
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100246config ARCH_VEXPRESS
247 bool "ARMv8 software model (Versatile Express)"
248 select ARCH_REQUIRE_GPIOLIB
249 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000250 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100251 select VEXPRESS_CONFIG
252 help
253 This enables support for the ARMv8 software model (Versatile
254 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100255
Vinayak Kale15942852013-04-24 10:06:57 +0100256config ARCH_XGENE
257 bool "AppliedMicro X-Gene SOC Family"
258 help
259 This enables support for AppliedMicro X-Gene SOC Family
260
Michal Simek5d1b79d2015-03-09 09:41:04 +0100261config ARCH_ZYNQMP
262 bool "Xilinx ZynqMP Family"
263 help
264 This enables support for Xilinx ZynqMP Family
265
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100266endmenu
267
268menu "Bus support"
269
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100270config PCI
271 bool "PCI support"
272 help
273 This feature enables support for PCI bus system. If you say Y
274 here, the kernel will include drivers and infrastructure code
275 to support PCI bus devices.
276
277config PCI_DOMAINS
278 def_bool PCI
279
280config PCI_DOMAINS_GENERIC
281 def_bool PCI
282
283config PCI_SYSCALL
284 def_bool PCI
285
286source "drivers/pci/Kconfig"
287source "drivers/pci/pcie/Kconfig"
288source "drivers/pci/hotplug/Kconfig"
289
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100290endmenu
291
292menu "Kernel Features"
293
Andre Przywarac0a01b82014-11-14 15:54:12 +0000294menu "ARM errata workarounds via the alternatives framework"
295
296config ARM64_ERRATUM_826319
297 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
298 default y
299 help
300 This option adds an alternative code sequence to work around ARM
301 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
302 AXI master interface and an L2 cache.
303
304 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
305 and is unable to accept a certain write via this interface, it will
306 not progress on read data presented on the read data channel and the
307 system can deadlock.
308
309 The workaround promotes data cache clean instructions to
310 data cache clean-and-invalidate.
311 Please note that this does not necessarily enable the workaround,
312 as it depends on the alternative framework, which will only patch
313 the kernel if an affected CPU is detected.
314
315 If unsure, say Y.
316
317config ARM64_ERRATUM_827319
318 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
319 default y
320 help
321 This option adds an alternative code sequence to work around ARM
322 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
323 master interface and an L2 cache.
324
325 Under certain conditions this erratum can cause a clean line eviction
326 to occur at the same time as another transaction to the same address
327 on the AMBA 5 CHI interface, which can cause data corruption if the
328 interconnect reorders the two transactions.
329
330 The workaround promotes data cache clean instructions to
331 data cache clean-and-invalidate.
332 Please note that this does not necessarily enable the workaround,
333 as it depends on the alternative framework, which will only patch
334 the kernel if an affected CPU is detected.
335
336 If unsure, say Y.
337
338config ARM64_ERRATUM_824069
339 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
340 default y
341 help
342 This option adds an alternative code sequence to work around ARM
343 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
344 to a coherent interconnect.
345
346 If a Cortex-A53 processor is executing a store or prefetch for
347 write instruction at the same time as a processor in another
348 cluster is executing a cache maintenance operation to the same
349 address, then this erratum might cause a clean cache line to be
350 incorrectly marked as dirty.
351
352 The workaround promotes data cache clean instructions to
353 data cache clean-and-invalidate.
354 Please note that this option does not necessarily enable the
355 workaround, as it depends on the alternative framework, which will
356 only patch the kernel if an affected CPU is detected.
357
358 If unsure, say Y.
359
360config ARM64_ERRATUM_819472
361 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
362 default y
363 help
364 This option adds an alternative code sequence to work around ARM
365 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
366 present when it is connected to a coherent interconnect.
367
368 If the processor is executing a load and store exclusive sequence at
369 the same time as a processor in another cluster is executing a cache
370 maintenance operation to the same address, then this erratum might
371 cause data corruption.
372
373 The workaround promotes data cache clean instructions to
374 data cache clean-and-invalidate.
375 Please note that this does not necessarily enable the workaround,
376 as it depends on the alternative framework, which will only patch
377 the kernel if an affected CPU is detected.
378
379 If unsure, say Y.
380
381config ARM64_ERRATUM_832075
382 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
383 default y
384 help
385 This option adds an alternative code sequence to work around ARM
386 erratum 832075 on Cortex-A57 parts up to r1p2.
387
388 Affected Cortex-A57 parts might deadlock when exclusive load/store
389 instructions to Write-Back memory are mixed with Device loads.
390
391 The workaround is to promote device loads to use Load-Acquire
392 semantics.
393 Please note that this does not necessarily enable the workaround,
394 as it depends on the alternative framework, which will only patch
395 the kernel if an affected CPU is detected.
396
397 If unsure, say Y.
398
Will Deacon905e8c52015-03-23 19:07:02 +0000399config ARM64_ERRATUM_845719
400 bool "Cortex-A53: 845719: a load might read incorrect data"
401 depends on COMPAT
402 default y
403 help
404 This option adds an alternative code sequence to work around ARM
405 erratum 845719 on Cortex-A53 parts up to r0p4.
406
407 When running a compat (AArch32) userspace on an affected Cortex-A53
408 part, a load at EL0 from a virtual address that matches the bottom 32
409 bits of the virtual address used by a recent load at (AArch64) EL1
410 might return incorrect data.
411
412 The workaround is to write the contextidr_el1 register on exception
413 return to a 32-bit task.
414 Please note that this does not necessarily enable the workaround,
415 as it depends on the alternative framework, which will only patch
416 the kernel if an affected CPU is detected.
417
418 If unsure, say Y.
419
Andre Przywarac0a01b82014-11-14 15:54:12 +0000420endmenu
421
422
Jungseok Leee41ceed2014-05-12 10:40:38 +0100423choice
424 prompt "Page size"
425 default ARM64_4K_PAGES
426 help
427 Page size (translation granule) configuration.
428
429config ARM64_4K_PAGES
430 bool "4KB"
431 help
432 This feature enables 4KB pages support.
433
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100434config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100435 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100436 help
437 This feature enables 64KB pages support (4KB by default)
438 allowing only two levels of page tables and faster TLB
439 look-up. AArch32 emulation is not available when this feature
440 is enabled.
441
Jungseok Leee41ceed2014-05-12 10:40:38 +0100442endchoice
443
444choice
445 prompt "Virtual address space size"
446 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
447 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
448 help
449 Allows choosing one of multiple possible virtual address
450 space sizes. The level of translation table is determined by
451 a combination of page size and virtual address space size.
452
453config ARM64_VA_BITS_39
454 bool "39-bit"
455 depends on ARM64_4K_PAGES
456
457config ARM64_VA_BITS_42
458 bool "42-bit"
459 depends on ARM64_64K_PAGES
460
Jungseok Leec79b9542014-05-12 18:40:51 +0900461config ARM64_VA_BITS_48
462 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900463
Jungseok Leee41ceed2014-05-12 10:40:38 +0100464endchoice
465
466config ARM64_VA_BITS
467 int
468 default 39 if ARM64_VA_BITS_39
469 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900470 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100471
Will Deacona8720132013-10-11 14:52:19 +0100472config CPU_BIG_ENDIAN
473 bool "Build big-endian kernel"
474 help
475 Say Y if you plan on running a kernel in big-endian mode.
476
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100477config SMP
478 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100479 help
480 This enables support for systems with more than one CPU. If
481 you say N here, the kernel will run on single and
482 multiprocessor machines, but will use only one CPU of a
483 multiprocessor machine. If you say Y here, the kernel will run
484 on many, but not all, single processor machines. On a single
485 processor machine, the kernel will run faster if you say N
486 here.
487
488 If you don't know what to do here, say N.
489
Mark Brownf6e763b2014-03-04 07:51:17 +0000490config SCHED_MC
491 bool "Multi-core scheduler support"
492 depends on SMP
493 help
494 Multi-core scheduler support improves the CPU scheduler's decision
495 making when dealing with multi-core CPU chips at a cost of slightly
496 increased overhead in some places. If unsure say N here.
497
498config SCHED_SMT
499 bool "SMT scheduler support"
500 depends on SMP
501 help
502 Improves the CPU scheduler's decision making when dealing with
503 MultiThreading at a cost of slightly increased overhead in some
504 places. If unsure say N here.
505
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100506config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000507 int "Maximum number of CPUs (2-4096)"
508 range 2 4096
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100509 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100510 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100511 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100512
Mark Rutland9327e2c2013-10-24 20:30:18 +0100513config HOTPLUG_CPU
514 bool "Support for hot-pluggable CPUs"
515 depends on SMP
516 help
517 Say Y here to experiment with turning CPUs off and on. CPUs
518 can be controlled through /sys/devices/system/cpu.
519
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100520source kernel/Kconfig.preempt
521
Mark Rutland137650aa2015-03-13 16:14:34 +0000522config UP_LATE_INIT
523 def_bool y
524 depends on !SMP
525
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100526config HZ
527 int
528 default 100
529
530config ARCH_HAS_HOLES_MEMORYMODEL
531 def_bool y if SPARSEMEM
532
533config ARCH_SPARSEMEM_ENABLE
534 def_bool y
535 select SPARSEMEM_VMEMMAP_ENABLE
536
537config ARCH_SPARSEMEM_DEFAULT
538 def_bool ARCH_SPARSEMEM_ENABLE
539
540config ARCH_SELECT_MEMORY_MODEL
541 def_bool ARCH_SPARSEMEM_ENABLE
542
543config HAVE_ARCH_PFN_VALID
544 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
545
546config HW_PERF_EVENTS
547 bool "Enable hardware performance counter support for perf events"
548 depends on PERF_EVENTS
549 default y
550 help
551 Enable hardware performance counter support for perf events. If
552 disabled, perf events will use software events only.
553
Steve Capper084bd292013-04-10 13:48:00 +0100554config SYS_SUPPORTS_HUGETLBFS
555 def_bool y
556
557config ARCH_WANT_GENERAL_HUGETLB
558 def_bool y
559
560config ARCH_WANT_HUGE_PMD_SHARE
561 def_bool y if !ARM64_64K_PAGES
562
Steve Capperaf074842013-04-19 16:23:57 +0100563config HAVE_ARCH_TRANSPARENT_HUGEPAGE
564 def_bool y
565
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100566config ARCH_HAS_CACHE_LINE_SIZE
567 def_bool y
568
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100569source "mm/Kconfig"
570
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000571config SECCOMP
572 bool "Enable seccomp to safely compute untrusted bytecode"
573 ---help---
574 This kernel feature is useful for number crunching applications
575 that may need to compute untrusted bytecode during their
576 execution. By using pipes or other transports made available to
577 the process as file descriptors supporting the read/write
578 syscalls, it's possible to isolate those applications in
579 their own address space using seccomp. Once seccomp is
580 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
581 and the task is only allowed to execute a few safe syscalls
582 defined by each seccomp mode.
583
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000584config XEN_DOM0
585 def_bool y
586 depends on XEN
587
588config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700589 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000590 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000591 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000592 help
593 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
594
Steve Capperd03bb142013-04-25 15:19:21 +0100595config FORCE_MAX_ZONEORDER
596 int
597 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
598 default "11"
599
Will Deacon1b907f42014-11-20 16:51:10 +0000600menuconfig ARMV8_DEPRECATED
601 bool "Emulate deprecated/obsolete ARMv8 instructions"
602 depends on COMPAT
603 help
604 Legacy software support may require certain instructions
605 that have been deprecated or obsoleted in the architecture.
606
607 Enable this config to enable selective emulation of these
608 features.
609
610 If unsure, say Y
611
612if ARMV8_DEPRECATED
613
614config SWP_EMULATION
615 bool "Emulate SWP/SWPB instructions"
616 help
617 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
618 they are always undefined. Say Y here to enable software
619 emulation of these instructions for userspace using LDXR/STXR.
620
621 In some older versions of glibc [<=2.8] SWP is used during futex
622 trylock() operations with the assumption that the code will not
623 be preempted. This invalid assumption may be more likely to fail
624 with SWP emulation enabled, leading to deadlock of the user
625 application.
626
627 NOTE: when accessing uncached shared regions, LDXR/STXR rely
628 on an external transaction monitoring block called a global
629 monitor to maintain update atomicity. If your system does not
630 implement a global monitor, this option can cause programs that
631 perform SWP operations to uncached memory to deadlock.
632
633 If unsure, say Y
634
635config CP15_BARRIER_EMULATION
636 bool "Emulate CP15 Barrier instructions"
637 help
638 The CP15 barrier instructions - CP15ISB, CP15DSB, and
639 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
640 strongly recommended to use the ISB, DSB, and DMB
641 instructions instead.
642
643 Say Y here to enable software emulation of these
644 instructions for AArch32 userspace code. When this option is
645 enabled, CP15 barrier usage is traced which can help
646 identify software that needs updating.
647
648 If unsure, say Y
649
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000650config SETEND_EMULATION
651 bool "Emulate SETEND instruction"
652 help
653 The SETEND instruction alters the data-endianness of the
654 AArch32 EL0, and is deprecated in ARMv8.
655
656 Say Y here to enable software emulation of the instruction
657 for AArch32 userspace code.
658
659 Note: All the cpus on the system must have mixed endian support at EL0
660 for this feature to be enabled. If a new CPU - which doesn't support mixed
661 endian - is hotplugged in after this feature has been enabled, there could
662 be unexpected results in the applications.
663
664 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000665endif
666
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100667endmenu
668
669menu "Boot options"
670
671config CMDLINE
672 string "Default kernel command string"
673 default ""
674 help
675 Provide a set of default command-line options at build time by
676 entering them here. As a minimum, you should specify the the
677 root device (e.g. root=/dev/nfs).
678
679config CMDLINE_FORCE
680 bool "Always use the default kernel command string"
681 help
682 Always use the default kernel command string, even if the boot
683 loader passes other arguments to the kernel.
684 This is useful if you cannot or don't want to change the
685 command-line options your boot loader passes to the kernel.
686
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200687config EFI_STUB
688 bool
689
Mark Salterf84d0272014-04-15 21:59:30 -0400690config EFI
691 bool "UEFI runtime support"
692 depends on OF && !CPU_BIG_ENDIAN
693 select LIBFDT
694 select UCS2_STRING
695 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200696 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200697 select EFI_STUB
698 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400699 default y
700 help
701 This option provides support for runtime services provided
702 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400703 clock, and platform reset). A UEFI stub is also provided to
704 allow the kernel to be booted as an EFI application. This
705 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400706
Yi Lid1ae8c02014-10-04 23:46:43 +0800707config DMI
708 bool "Enable support for SMBIOS (DMI) tables"
709 depends on EFI
710 default y
711 help
712 This enables SMBIOS/DMI feature for systems.
713
714 This option is only useful on systems that have UEFI firmware.
715 However, even with this option, the resultant kernel should
716 continue to boot on existing non-UEFI platforms.
717
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100718endmenu
719
720menu "Userspace binary formats"
721
722source "fs/Kconfig.binfmt"
723
724config COMPAT
725 bool "Kernel support for 32-bit EL0"
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000726 depends on !ARM64_64K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100727 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700728 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500729 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500730 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100731 help
732 This option enables support for a 32-bit EL0 running under a 64-bit
733 kernel at EL1. AArch32-specific components such as system calls,
734 the user helper functions, VFP support and the ptrace interface are
735 handled appropriately by the kernel.
736
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000737 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
738 will only be able to execute AArch32 binaries that were compiled with
739 64k aligned segments.
740
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100741 If you want to execute 32-bit userspace applications, say Y.
742
743config SYSVIPC_COMPAT
744 def_bool y
745 depends on COMPAT && SYSVIPC
746
747endmenu
748
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000749menu "Power management options"
750
751source "kernel/power/Kconfig"
752
753config ARCH_SUSPEND_POSSIBLE
754 def_bool y
755
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000756endmenu
757
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100758menu "CPU Power Management"
759
760source "drivers/cpuidle/Kconfig"
761
Rob Herring52e7e812014-02-24 11:27:57 +0900762source "drivers/cpufreq/Kconfig"
763
764endmenu
765
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100766source "net/Kconfig"
767
768source "drivers/Kconfig"
769
Mark Salterf84d0272014-04-15 21:59:30 -0400770source "drivers/firmware/Kconfig"
771
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000772source "drivers/acpi/Kconfig"
773
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100774source "fs/Kconfig"
775
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100776source "arch/arm64/kvm/Kconfig"
777
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100778source "arch/arm64/Kconfig.debug"
779
780source "security/Kconfig"
781
782source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800783if CRYPTO
784source "arch/arm64/crypto/Kconfig"
785endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100786
787source "lib/Kconfig"