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gerrit-public.fairphone.software / kernel / msm-4.9 / f30fb03d4d3abe2da86918a92df0964cdf933e82 / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 59e970f74e8f44afd5af5bdc72407b0e992354ec [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame^]68 dma_apbh: dma-apbh@00110000 {
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame^]71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]75 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]76 };
77
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]78 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]79 compatible = "fsl,imx6q-gpmi-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame^]90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]94 };
95
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]96 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]100 };
101
102 L2: l2-cache@00a02000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x00a02000 0x1000>;
105 interrupts = <0 92 0x04>;
106 cache-unified;
107 cache-level = <2>;
108 };
109
110 aips-bus@02000000 { /* AIPS1 */
111 compatible = "fsl,aips-bus", "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 reg = <0x02000000 0x100000>;
115 ranges;
116
117 spba-bus@02000000 {
118 compatible = "fsl,spba-bus", "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 reg = <0x02000000 0x40000>;
122 ranges;
123
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]124 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]125 reg = <0x02004000 0x4000>;
126 interrupts = <0 52 0x04>;
127 };
128
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]129 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
133 reg = <0x02008000 0x4000>;
134 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]135 clocks = <&clks 112>, <&clks 112>;
136 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]137 status = "disabled";
138 };
139
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]140 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
144 reg = <0x0200c000 0x4000>;
145 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]146 clocks = <&clks 113>, <&clks 113>;
147 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]148 status = "disabled";
149 };
150
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]151 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
155 reg = <0x02010000 0x4000>;
156 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]157 clocks = <&clks 114>, <&clks 114>;
158 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]159 status = "disabled";
160 };
161
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]162 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
166 reg = <0x02014000 0x4000>;
167 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]168 clocks = <&clks 115>, <&clks 115>;
169 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]170 status = "disabled";
171 };
172
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]173 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]174 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
175 reg = <0x02020000 0x4000>;
176 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]177 clocks = <&clks 160>, <&clks 161>;
178 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]179 status = "disabled";
180 };
181
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]182 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]183 reg = <0x02024000 0x4000>;
184 interrupts = <0 51 0x04>;
185 };
186
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]187 ssi1: ssi@02028000 {
188 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]189 reg = <0x02028000 0x4000>;
190 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]191 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]192 fsl,fifo-depth = <15>;
193 fsl,ssi-dma-events = <38 37>;
194 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]195 };
196
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]197 ssi2: ssi@0202c000 {
198 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]199 reg = <0x0202c000 0x4000>;
200 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]201 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]202 fsl,fifo-depth = <15>;
203 fsl,ssi-dma-events = <42 41>;
204 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]205 };
206
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]207 ssi3: ssi@02030000 {
208 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]209 reg = <0x02030000 0x4000>;
210 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]211 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]212 fsl,fifo-depth = <15>;
213 fsl,ssi-dma-events = <46 45>;
214 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]215 };
216
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]217 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]218 reg = <0x02034000 0x4000>;
219 interrupts = <0 50 0x04>;
220 };
221
222 spba@0203c000 {
223 reg = <0x0203c000 0x4000>;
224 };
225 };
226
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]227 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]228 reg = <0x02040000 0x3c000>;
229 interrupts = <0 3 0x04 0 12 0x04>;
230 };
231
232 aipstz@0207c000 { /* AIPSTZ1 */
233 reg = <0x0207c000 0x4000>;
234 };
235
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]236 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]237 #pwm-cells = <2>;
238 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]239 reg = <0x02080000 0x4000>;
240 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]241 clocks = <&clks 62>, <&clks 145>;
242 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]243 };
244
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]245 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]246 #pwm-cells = <2>;
247 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]248 reg = <0x02084000 0x4000>;
249 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]250 clocks = <&clks 62>, <&clks 146>;
251 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]252 };
253
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]254 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]255 #pwm-cells = <2>;
256 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]257 reg = <0x02088000 0x4000>;
258 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]259 clocks = <&clks 62>, <&clks 147>;
260 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]261 };
262
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]263 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]264 #pwm-cells = <2>;
265 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]266 reg = <0x0208c000 0x4000>;
267 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]268 clocks = <&clks 62>, <&clks 148>;
269 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]270 };
271
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]272 can1: flexcan@02090000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]273 reg = <0x02090000 0x4000>;
274 interrupts = <0 110 0x04>;
275 };
276
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]277 can2: flexcan@02094000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]278 reg = <0x02094000 0x4000>;
279 interrupts = <0 111 0x04>;
280 };
281
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]282 gpt: gpt@02098000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]283 compatible = "fsl,imx6q-gpt";
284 reg = <0x02098000 0x4000>;
285 interrupts = <0 55 0x04>;
286 };
287
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]288 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]289 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]290 reg = <0x0209c000 0x4000>;
291 interrupts = <0 66 0x04 0 67 0x04>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]295 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]296 };
297
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]298 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]299 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]300 reg = <0x020a0000 0x4000>;
301 interrupts = <0 68 0x04 0 69 0x04>;
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]305 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]306 };
307
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]308 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]309 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]310 reg = <0x020a4000 0x4000>;
311 interrupts = <0 70 0x04 0 71 0x04>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]315 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]316 };
317
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]318 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]319 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]320 reg = <0x020a8000 0x4000>;
321 interrupts = <0 72 0x04 0 73 0x04>;
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]325 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]326 };
327
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]328 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]329 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]330 reg = <0x020ac000 0x4000>;
331 interrupts = <0 74 0x04 0 75 0x04>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]335 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]336 };
337
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]338 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]339 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]340 reg = <0x020b0000 0x4000>;
341 interrupts = <0 76 0x04 0 77 0x04>;
342 gpio-controller;
343 #gpio-cells = <2>;
344 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]345 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]346 };
347
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]348 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]349 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]350 reg = <0x020b4000 0x4000>;
351 interrupts = <0 78 0x04 0 79 0x04>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]355 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]356 };
357
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]358 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]359 reg = <0x020b8000 0x4000>;
360 interrupts = <0 82 0x04>;
361 };
362
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]363 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
365 reg = <0x020bc000 0x4000>;
366 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]367 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]368 };
369
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]370 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]371 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
372 reg = <0x020c0000 0x4000>;
373 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]374 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]375 status = "disabled";
376 };
377
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]378 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]379 compatible = "fsl,imx6q-ccm";
380 reg = <0x020c4000 0x4000>;
381 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]382 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]383 };
384
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]385 anatop: anatop@020c8000 {
386 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]387 reg = <0x020c8000 0x1000>;
388 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]389
390 regulator-1p1@110 {
391 compatible = "fsl,anatop-regulator";
392 regulator-name = "vdd1p1";
393 regulator-min-microvolt = <800000>;
394 regulator-max-microvolt = <1375000>;
395 regulator-always-on;
396 anatop-reg-offset = <0x110>;
397 anatop-vol-bit-shift = <8>;
398 anatop-vol-bit-width = <5>;
399 anatop-min-bit-val = <4>;
400 anatop-min-voltage = <800000>;
401 anatop-max-voltage = <1375000>;
402 };
403
404 regulator-3p0@120 {
405 compatible = "fsl,anatop-regulator";
406 regulator-name = "vdd3p0";
407 regulator-min-microvolt = <2800000>;
408 regulator-max-microvolt = <3150000>;
409 regulator-always-on;
410 anatop-reg-offset = <0x120>;
411 anatop-vol-bit-shift = <8>;
412 anatop-vol-bit-width = <5>;
413 anatop-min-bit-val = <0>;
414 anatop-min-voltage = <2625000>;
415 anatop-max-voltage = <3400000>;
416 };
417
418 regulator-2p5@130 {
419 compatible = "fsl,anatop-regulator";
420 regulator-name = "vdd2p5";
421 regulator-min-microvolt = <2000000>;
422 regulator-max-microvolt = <2750000>;
423 regulator-always-on;
424 anatop-reg-offset = <0x130>;
425 anatop-vol-bit-shift = <8>;
426 anatop-vol-bit-width = <5>;
427 anatop-min-bit-val = <0>;
428 anatop-min-voltage = <2000000>;
429 anatop-max-voltage = <2750000>;
430 };
431
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]432 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]433 compatible = "fsl,anatop-regulator";
434 regulator-name = "cpu";
435 regulator-min-microvolt = <725000>;
436 regulator-max-microvolt = <1450000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x140>;
439 anatop-vol-bit-shift = <0>;
440 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]441 anatop-delay-reg-offset = <0x170>;
442 anatop-delay-bit-shift = <24>;
443 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]444 anatop-min-bit-val = <1>;
445 anatop-min-voltage = <725000>;
446 anatop-max-voltage = <1450000>;
447 };
448
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]449 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]450 compatible = "fsl,anatop-regulator";
451 regulator-name = "vddpu";
452 regulator-min-microvolt = <725000>;
453 regulator-max-microvolt = <1450000>;
454 regulator-always-on;
455 anatop-reg-offset = <0x140>;
456 anatop-vol-bit-shift = <9>;
457 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]458 anatop-delay-reg-offset = <0x170>;
459 anatop-delay-bit-shift = <26>;
460 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]461 anatop-min-bit-val = <1>;
462 anatop-min-voltage = <725000>;
463 anatop-max-voltage = <1450000>;
464 };
465
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]466 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]467 compatible = "fsl,anatop-regulator";
468 regulator-name = "vddsoc";
469 regulator-min-microvolt = <725000>;
470 regulator-max-microvolt = <1450000>;
471 regulator-always-on;
472 anatop-reg-offset = <0x140>;
473 anatop-vol-bit-shift = <18>;
474 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]475 anatop-delay-reg-offset = <0x170>;
476 anatop-delay-bit-shift = <28>;
477 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]478 anatop-min-bit-val = <1>;
479 anatop-min-voltage = <725000>;
480 anatop-max-voltage = <1450000>;
481 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]482 };
483
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]484 usbphy1: usbphy@020c9000 {
485 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]486 reg = <0x020c9000 0x1000>;
487 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]488 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]489 };
490
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]491 usbphy2: usbphy@020ca000 {
492 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]493 reg = <0x020ca000 0x1000>;
494 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]495 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]496 };
497
498 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]499 compatible = "fsl,sec-v4.0-mon", "simple-bus";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0 0x020cc000 0x4000>;
503
504 snvs-rtc-lp@34 {
505 compatible = "fsl,sec-v4.0-mon-rtc-lp";
506 reg = <0x34 0x58>;
507 interrupts = <0 19 0x04 0 20 0x04>;
508 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]509 };
510
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]511 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]512 reg = <0x020d0000 0x4000>;
513 interrupts = <0 56 0x04>;
514 };
515
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]516 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]517 reg = <0x020d4000 0x4000>;
518 interrupts = <0 57 0x04>;
519 };
520
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]521 src: src@020d8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]522 compatible = "fsl,imx6q-src";
523 reg = <0x020d8000 0x4000>;
524 interrupts = <0 91 0x04 0 96 0x04>;
525 };
526
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]527 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]528 compatible = "fsl,imx6q-gpc";
529 reg = <0x020dc000 0x4000>;
530 interrupts = <0 89 0x04 0 90 0x04>;
531 };
532
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]533 gpr: iomuxc-gpr@020e0000 {
534 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
535 reg = <0x020e0000 0x38>;
536 };
537
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]538 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]539 reg = <0x020e4000 0x4000>;
540 interrupts = <0 124 0x04>;
541 };
542
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]543 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]544 reg = <0x020e8000 0x4000>;
545 interrupts = <0 125 0x04>;
546 };
547
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]548 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]549 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
550 reg = <0x020ec000 0x4000>;
551 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]552 clocks = <&clks 155>, <&clks 155>;
553 clock-names = "ipg", "ahb";
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]554 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]555 };
556 };
557
558 aips-bus@02100000 { /* AIPS2 */
559 compatible = "fsl,aips-bus", "simple-bus";
560 #address-cells = <1>;
561 #size-cells = <1>;
562 reg = <0x02100000 0x100000>;
563 ranges;
564
565 caam@02100000 {
566 reg = <0x02100000 0x40000>;
567 interrupts = <0 105 0x04 0 106 0x04>;
568 };
569
570 aipstz@0217c000 { /* AIPSTZ2 */
571 reg = <0x0217c000 0x4000>;
572 };
573
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]574 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]575 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
576 reg = <0x02184000 0x200>;
577 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]578 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]579 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]580 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]581 status = "disabled";
582 };
583
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]584 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]585 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
586 reg = <0x02184200 0x200>;
587 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]588 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]589 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]590 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]591 status = "disabled";
592 };
593
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]594 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]595 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
596 reg = <0x02184400 0x200>;
597 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]598 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]599 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]600 status = "disabled";
601 };
602
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]603 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]604 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
605 reg = <0x02184600 0x200>;
606 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]607 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]608 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]609 status = "disabled";
610 };
611
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]612 usbmisc: usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]613 #index-cells = <1>;
614 compatible = "fsl,imx6q-usbmisc";
615 reg = <0x02184800 0x200>;
616 clocks = <&clks 162>;
617 };
618
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]619 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]620 compatible = "fsl,imx6q-fec";
621 reg = <0x02188000 0x4000>;
622 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]623 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]624 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]625 status = "disabled";
626 };
627
628 mlb@0218c000 {
629 reg = <0x0218c000 0x4000>;
630 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
631 };
632
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]633 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]634 compatible = "fsl,imx6q-usdhc";
635 reg = <0x02190000 0x4000>;
636 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]637 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
638 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]639 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]640 status = "disabled";
641 };
642
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]643 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]644 compatible = "fsl,imx6q-usdhc";
645 reg = <0x02194000 0x4000>;
646 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]647 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
648 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]649 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]650 status = "disabled";
651 };
652
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]653 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]654 compatible = "fsl,imx6q-usdhc";
655 reg = <0x02198000 0x4000>;
656 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]657 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
658 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]659 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]660 status = "disabled";
661 };
662
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]663 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]664 compatible = "fsl,imx6q-usdhc";
665 reg = <0x0219c000 0x4000>;
666 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]667 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
668 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]669 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]670 status = "disabled";
671 };
672
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]673 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]674 #address-cells = <1>;
675 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]676 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]677 reg = <0x021a0000 0x4000>;
678 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]679 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]680 status = "disabled";
681 };
682
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]683 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]684 #address-cells = <1>;
685 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]686 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]687 reg = <0x021a4000 0x4000>;
688 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]689 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]690 status = "disabled";
691 };
692
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]693 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]694 #address-cells = <1>;
695 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]696 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]697 reg = <0x021a8000 0x4000>;
698 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]699 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]700 status = "disabled";
701 };
702
703 romcp@021ac000 {
704 reg = <0x021ac000 0x4000>;
705 };
706
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]707 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]708 compatible = "fsl,imx6q-mmdc";
709 reg = <0x021b0000 0x4000>;
710 };
711
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]712 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]713 reg = <0x021b4000 0x4000>;
714 };
715
716 weim@021b8000 {
717 reg = <0x021b8000 0x4000>;
718 interrupts = <0 14 0x04>;
719 };
720
721 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]722 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]723 reg = <0x021bc000 0x4000>;
724 };
725
726 ocotp@021c0000 {
727 reg = <0x021c0000 0x4000>;
728 interrupts = <0 21 0x04>;
729 };
730
731 tzasc@021d0000 { /* TZASC1 */
732 reg = <0x021d0000 0x4000>;
733 interrupts = <0 108 0x04>;
734 };
735
736 tzasc@021d4000 { /* TZASC2 */
737 reg = <0x021d4000 0x4000>;
738 interrupts = <0 109 0x04>;
739 };
740
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]741 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]742 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]743 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]744 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]745 };
746
747 mipi@021dc000 { /* MIPI-CSI */
748 reg = <0x021dc000 0x4000>;
749 };
750
751 mipi@021e0000 { /* MIPI-DSI */
752 reg = <0x021e0000 0x4000>;
753 };
754
755 vdoa@021e4000 {
756 reg = <0x021e4000 0x4000>;
757 interrupts = <0 18 0x04>;
758 };
759
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]760 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]761 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
762 reg = <0x021e8000 0x4000>;
763 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]764 clocks = <&clks 160>, <&clks 161>;
765 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]766 status = "disabled";
767 };
768
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]769 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]770 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
771 reg = <0x021ec000 0x4000>;
772 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]773 clocks = <&clks 160>, <&clks 161>;
774 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]775 status = "disabled";
776 };
777
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]778 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]779 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
780 reg = <0x021f0000 0x4000>;
781 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]782 clocks = <&clks 160>, <&clks 161>;
783 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]784 status = "disabled";
785 };
786
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]787 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]788 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
789 reg = <0x021f4000 0x4000>;
790 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]791 clocks = <&clks 160>, <&clks 161>;
792 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]793 status = "disabled";
794 };
795 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]796
797 ipu1: ipu@02400000 {
798 #crtc-cells = <1>;
799 compatible = "fsl,imx6q-ipu";
800 reg = <0x02400000 0x400000>;
801 interrupts = <0 6 0x4 0 5 0x4>;
802 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
803 clock-names = "bus", "di0", "di1";
804 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]805 };
806};