Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / f31318fdf324901ce5a17ccc3d71213117fb44af / . / arch / mips / include / uapi / asm / inst.h
blob: abcdebe60e70e219a84174cf4511a6780756968e [file] [log] [blame]
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]1/*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]11 * Copyright (C) 2014 Imagination Technologies Ltd.
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]12 */
13#ifndef _UAPI_ASM_INST_H
14#define _UAPI_ASM_INST_H
15
Ralf Baechle64a17a02014-04-16 00:39:02 +0200[diff] [blame]16#include <asm/bitfield.h>
17
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]18/*
19 * Major opcodes; before MIPS IV cop1x was called cop3.
20 */
21enum major_op {
22 spec_op, bcond_op, j_op, jal_op,
23 beq_op, bne_op, blez_op, bgtz_op,
24 addi_op, addiu_op, slti_op, sltiu_op,
25 andi_op, ori_op, xori_op, lui_op,
26 cop0_op, cop1_op, cop2_op, cop1x_op,
27 beql_op, bnel_op, blezl_op, bgtzl_op,
28 daddi_op, daddiu_op, ldl_op, ldr_op,
29 spec2_op, jalx_op, mdmx_op, spec3_op,
30 lb_op, lh_op, lwl_op, lw_op,
31 lbu_op, lhu_op, lwr_op, lwu_op,
32 sb_op, sh_op, swl_op, sw_op,
33 sdl_op, sdr_op, swr_op, cache_op,
34 ll_op, lwc1_op, lwc2_op, pref_op,
35 lld_op, ldc1_op, ldc2_op, ld_op,
36 sc_op, swc1_op, swc2_op, major_3b_op,
37 scd_op, sdc1_op, sdc2_op, sd_op
38};
39
40/*
41 * func field of spec opcode.
42 */
43enum spec_op {
44 sll_op, movc_op, srl_op, sra_op,
45 sllv_op, pmon_op, srlv_op, srav_op,
46 jr_op, jalr_op, movz_op, movn_op,
47 syscall_op, break_op, spim_op, sync_op,
48 mfhi_op, mthi_op, mflo_op, mtlo_op,
49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
50 mult_op, multu_op, div_op, divu_op,
51 dmult_op, dmultu_op, ddiv_op, ddivu_op,
52 add_op, addu_op, sub_op, subu_op,
53 and_op, or_op, xor_op, nor_op,
54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
55 dadd_op, daddu_op, dsub_op, dsubu_op,
56 tge_op, tgeu_op, tlt_op, tltu_op,
57 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
58 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
60};
61
62/*
63 * func field of spec2 opcode.
64 */
65enum spec2_op {
66 madd_op, maddu_op, mul_op, spec2_3_unused_op,
67 msub_op, msubu_op, /* more unused ops */
68 clz_op = 0x20, clo_op,
69 dclz_op = 0x24, dclo_op,
70 sdbpp_op = 0x3f
71};
72
73/*
74 * func field of spec3 opcode.
75 */
76enum spec3_op {
77 ext_op, dextm_op, dextu_op, dext_op,
78 ins_op, dinsm_op, dinsu_op, dins_op,
Paul Burton6f5bb422014-03-04 15:11:12 +0000[diff] [blame]79 yield_op = 0x09, lx_op = 0x0a,
80 lwle_op = 0x19, lwre_op = 0x1a,
81 cachee_op = 0x1b, sbe_op = 0x1c,
82 she_op = 0x1d, sce_op = 0x1e,
83 swe_op = 0x1f, bshfl_op = 0x20,
84 swle_op = 0x21, swre_op = 0x22,
85 prefe_op = 0x23, dbshfl_op = 0x24,
86 lbue_op = 0x28, lhue_op = 0x29,
87 lbe_op = 0x2c, lhe_op = 0x2d,
88 lle_op = 0x2e, lwe_op = 0x2f,
89 rdhwr_op = 0x3b
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]90};
91
92/*
93 * rt field of bcond opcodes.
94 */
95enum rt_op {
96 bltz_op, bgez_op, bltzl_op, bgezl_op,
97 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
98 tgei_op, tgeiu_op, tlti_op, tltiu_op,
99 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
100 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
101 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
102 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
103 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
104};
105
106/*
107 * rs field of cop opcodes.
108 */
109enum cop_op {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]110 mfc_op = 0x00, dmfc_op = 0x01,
Leonid Yegoshin1ac944002013-11-07 12:48:28 +0000[diff] [blame]111 cfc_op = 0x02, mfhc_op = 0x03,
112 mtc_op = 0x04, dmtc_op = 0x05,
113 ctc_op = 0x06, mthc_op = 0x07,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]114 bc_op = 0x08, cop_op = 0x10,
115 copm_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]116};
117
118/*
119 * rt field of cop.bc_op opcodes
120 */
121enum bcop_op {
122 bcf_op, bct_op, bcfl_op, bctl_op
123};
124
125/*
126 * func field of cop0 coi opcodes.
127 */
128enum cop0_coi_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]129 tlbr_op = 0x01, tlbwi_op = 0x02,
130 tlbwr_op = 0x06, tlbp_op = 0x08,
Paul Burtonb0a3eae2013-12-24 03:44:28 +0000[diff] [blame]131 rfe_op = 0x10, eret_op = 0x18,
132 wait_op = 0x20,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]133};
134
135/*
136 * func field of cop0 com opcodes.
137 */
138enum cop0_com_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]139 tlbr1_op = 0x01, tlbw_op = 0x02,
140 tlbp1_op = 0x08, dctr_op = 0x09,
141 dctw_op = 0x0a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]142};
143
144/*
145 * fmt field of cop1 opcodes.
146 */
147enum cop1_fmt {
148 s_fmt, d_fmt, e_fmt, q_fmt,
149 w_fmt, l_fmt
150};
151
152/*
153 * func field of cop1 instructions using d, s or w format.
154 */
155enum cop1_sdw_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]156 fadd_op = 0x00, fsub_op = 0x01,
157 fmul_op = 0x02, fdiv_op = 0x03,
158 fsqrt_op = 0x04, fabs_op = 0x05,
159 fmov_op = 0x06, fneg_op = 0x07,
160 froundl_op = 0x08, ftruncl_op = 0x09,
161 fceill_op = 0x0a, ffloorl_op = 0x0b,
162 fround_op = 0x0c, ftrunc_op = 0x0d,
163 fceil_op = 0x0e, ffloor_op = 0x0f,
164 fmovc_op = 0x11, fmovz_op = 0x12,
165 fmovn_op = 0x13, frecip_op = 0x15,
166 frsqrt_op = 0x16, fcvts_op = 0x20,
167 fcvtd_op = 0x21, fcvte_op = 0x22,
168 fcvtw_op = 0x24, fcvtl_op = 0x25,
169 fcmp_op = 0x30
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]170};
171
172/*
173 * func field of cop1x opcodes (MIPS IV).
174 */
175enum cop1x_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]176 lwxc1_op = 0x00, ldxc1_op = 0x01,
Deng-Cheng Zhu51061b82014-03-06 17:05:27 -0800[diff] [blame]177 swxc1_op = 0x08, sdxc1_op = 0x09,
178 pfetch_op = 0x0f, madd_s_op = 0x20,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]179 madd_d_op = 0x21, madd_e_op = 0x22,
180 msub_s_op = 0x28, msub_d_op = 0x29,
181 msub_e_op = 0x2a, nmadd_s_op = 0x30,
182 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
183 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
184 nmsub_e_op = 0x3a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]185};
186
187/*
188 * func field for mad opcodes (MIPS IV).
189 */
190enum mad_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]191 madd_fp_op = 0x08, msub_fp_op = 0x0a,
192 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]193};
194
195/*
196 * func field for special3 lx opcodes (Cavium Octeon).
197 */
198enum lx_func {
199 lwx_op = 0x00,
200 lhx_op = 0x04,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]201 lbux_op = 0x06,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]202 ldx_op = 0x08,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]203 lwux_op = 0x10,
204 lhux_op = 0x14,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]205 lbx_op = 0x16,
206};
207
208/*
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]209 * (microMIPS) Major opcodes.
210 */
211enum mm_major_op {
212 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
213 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
214 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
215 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
216 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
217 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
218 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
219 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
220 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
221 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
222 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
223 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
224 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
225 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
226 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
227 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
228};
229
230/*
231 * (microMIPS) POOL32I minor opcodes.
232 */
233enum mm_32i_minor_op {
234 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
235 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
236 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
237 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
238 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
239 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
240 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
241 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
242 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
243};
244
245/*
246 * (microMIPS) POOL32A minor opcodes.
247 */
248enum mm_32a_minor_op {
249 mm_sll32_op = 0x000,
250 mm_ins_op = 0x00c,
Markos Chandrasbef581b2014-04-08 12:47:04 +0100[diff] [blame]251 mm_sllv32_op = 0x010,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]252 mm_ext_op = 0x02c,
253 mm_pool32axf_op = 0x03c,
254 mm_srl32_op = 0x040,
255 mm_sra_op = 0x080,
Markos Chandrasf31318f2014-04-08 12:47:05 +0100[diff] [blame^]256 mm_srlv32_op = 0x090,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]257 mm_rotr_op = 0x0c0,
258 mm_lwxs_op = 0x118,
259 mm_addu32_op = 0x150,
260 mm_subu32_op = 0x1d0,
261 mm_and_op = 0x250,
262 mm_or32_op = 0x290,
263 mm_xor32_op = 0x310,
264};
265
266/*
267 * (microMIPS) POOL32B functions.
268 */
269enum mm_32b_func {
270 mm_lwc2_func = 0x0,
271 mm_lwp_func = 0x1,
272 mm_ldc2_func = 0x2,
273 mm_ldp_func = 0x4,
274 mm_lwm32_func = 0x5,
275 mm_cache_func = 0x6,
276 mm_ldm_func = 0x7,
277 mm_swc2_func = 0x8,
278 mm_swp_func = 0x9,
279 mm_sdc2_func = 0xa,
280 mm_sdp_func = 0xc,
281 mm_swm32_func = 0xd,
282 mm_sdm_func = 0xf,
283};
284
285/*
286 * (microMIPS) POOL32C functions.
287 */
288enum mm_32c_func {
289 mm_pref_func = 0x2,
290 mm_ll_func = 0x3,
291 mm_swr_func = 0x9,
292 mm_sc_func = 0xb,
293 mm_lwu_func = 0xe,
294};
295
296/*
297 * (microMIPS) POOL32AXF minor opcodes.
298 */
299enum mm_32axf_minor_op {
300 mm_mfc0_op = 0x003,
301 mm_mtc0_op = 0x00b,
302 mm_tlbp_op = 0x00d,
303 mm_jalr_op = 0x03c,
304 mm_tlbr_op = 0x04d,
305 mm_jalrhb_op = 0x07c,
306 mm_tlbwi_op = 0x08d,
307 mm_tlbwr_op = 0x0cd,
308 mm_jalrs_op = 0x13c,
309 mm_jalrshb_op = 0x17c,
Paul Burton7ed82ad2014-01-09 15:27:32 +0000[diff] [blame]310 mm_sync_op = 0x1ad,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]311 mm_syscall_op = 0x22d,
Paul Burtonf2638392014-01-09 15:30:37 +0000[diff] [blame]312 mm_wait_op = 0x24d,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]313 mm_eret_op = 0x3cd,
314};
315
316/*
317 * (microMIPS) POOL32F minor opcodes.
318 */
319enum mm_32f_minor_op {
320 mm_32f_00_op = 0x00,
321 mm_32f_01_op = 0x01,
322 mm_32f_02_op = 0x02,
323 mm_32f_10_op = 0x08,
324 mm_32f_11_op = 0x09,
325 mm_32f_12_op = 0x0a,
326 mm_32f_20_op = 0x10,
327 mm_32f_30_op = 0x18,
328 mm_32f_40_op = 0x20,
329 mm_32f_41_op = 0x21,
330 mm_32f_42_op = 0x22,
331 mm_32f_50_op = 0x28,
332 mm_32f_51_op = 0x29,
333 mm_32f_52_op = 0x2a,
334 mm_32f_60_op = 0x30,
335 mm_32f_70_op = 0x38,
336 mm_32f_73_op = 0x3b,
337 mm_32f_74_op = 0x3c,
338};
339
340/*
341 * (microMIPS) POOL32F secondary minor opcodes.
342 */
343enum mm_32f_10_minor_op {
344 mm_lwxc1_op = 0x1,
345 mm_swxc1_op,
346 mm_ldxc1_op,
347 mm_sdxc1_op,
348 mm_luxc1_op,
349 mm_suxc1_op,
350};
351
352enum mm_32f_func {
353 mm_lwxc1_func = 0x048,
354 mm_swxc1_func = 0x088,
355 mm_ldxc1_func = 0x0c8,
356 mm_sdxc1_func = 0x108,
357};
358
359/*
360 * (microMIPS) POOL32F secondary minor opcodes.
361 */
362enum mm_32f_40_minor_op {
363 mm_fmovf_op,
364 mm_fmovt_op,
365};
366
367/*
368 * (microMIPS) POOL32F secondary minor opcodes.
369 */
370enum mm_32f_60_minor_op {
371 mm_fadd_op,
372 mm_fsub_op,
373 mm_fmul_op,
374 mm_fdiv_op,
375};
376
377/*
378 * (microMIPS) POOL32F secondary minor opcodes.
379 */
380enum mm_32f_70_minor_op {
381 mm_fmovn_op,
382 mm_fmovz_op,
383};
384
385/*
386 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
387 */
388enum mm_32f_73_minor_op {
389 mm_fmov0_op = 0x01,
390 mm_fcvtl_op = 0x04,
391 mm_movf0_op = 0x05,
392 mm_frsqrt_op = 0x08,
393 mm_ffloorl_op = 0x0c,
394 mm_fabs0_op = 0x0d,
395 mm_fcvtw_op = 0x24,
396 mm_movt0_op = 0x25,
397 mm_fsqrt_op = 0x28,
398 mm_ffloorw_op = 0x2c,
399 mm_fneg0_op = 0x2d,
400 mm_cfc1_op = 0x40,
401 mm_frecip_op = 0x48,
402 mm_fceill_op = 0x4c,
403 mm_fcvtd0_op = 0x4d,
404 mm_ctc1_op = 0x60,
405 mm_fceilw_op = 0x6c,
406 mm_fcvts0_op = 0x6d,
407 mm_mfc1_op = 0x80,
408 mm_fmov1_op = 0x81,
409 mm_movf1_op = 0x85,
410 mm_ftruncl_op = 0x8c,
411 mm_fabs1_op = 0x8d,
412 mm_mtc1_op = 0xa0,
413 mm_movt1_op = 0xa5,
414 mm_ftruncw_op = 0xac,
415 mm_fneg1_op = 0xad,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame]416 mm_mfhc1_op = 0xc0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]417 mm_froundl_op = 0xcc,
418 mm_fcvtd1_op = 0xcd,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame]419 mm_mthc1_op = 0xe0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]420 mm_froundw_op = 0xec,
421 mm_fcvts1_op = 0xed,
422};
423
424/*
425 * (microMIPS) POOL16C minor opcodes.
426 */
427enum mm_16c_minor_op {
428 mm_lwm16_op = 0x04,
429 mm_swm16_op = 0x05,
Tony Wudfb033f2013-06-20 12:32:30 +0000[diff] [blame]430 mm_jr16_op = 0x0c,
431 mm_jrc_op = 0x0d,
432 mm_jalr16_op = 0x0e,
433 mm_jalrs16_op = 0x0f,
434 mm_jraddiusp_op = 0x18,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]435};
436
437/*
438 * (microMIPS) POOL16D minor opcodes.
439 */
440enum mm_16d_minor_op {
441 mm_addius5_func,
442 mm_addiusp_func,
443};
444
445/*
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]446 * (MIPS16e) opcodes.
447 */
448enum MIPS16e_ops {
449 MIPS16e_jal_op = 003,
450 MIPS16e_ld_op = 007,
451 MIPS16e_i8_op = 014,
452 MIPS16e_sd_op = 017,
453 MIPS16e_lb_op = 020,
454 MIPS16e_lh_op = 021,
455 MIPS16e_lwsp_op = 022,
456 MIPS16e_lw_op = 023,
457 MIPS16e_lbu_op = 024,
458 MIPS16e_lhu_op = 025,
459 MIPS16e_lwpc_op = 026,
460 MIPS16e_lwu_op = 027,
461 MIPS16e_sb_op = 030,
462 MIPS16e_sh_op = 031,
463 MIPS16e_swsp_op = 032,
464 MIPS16e_sw_op = 033,
465 MIPS16e_rr_op = 035,
466 MIPS16e_extend_op = 036,
467 MIPS16e_i64_op = 037,
468};
469
470enum MIPS16e_i64_func {
471 MIPS16e_ldsp_func,
472 MIPS16e_sdsp_func,
473 MIPS16e_sdrasp_func,
474 MIPS16e_dadjsp_func,
475 MIPS16e_ldpc_func,
476};
477
478enum MIPS16e_rr_func {
479 MIPS16e_jr_func,
480};
481
482enum MIPS6e_i8_func {
483 MIPS16e_swrasp_func = 02,
484};
485
486/*
Leonid Yegoshin102cedc2013-03-25 12:09:02 -0500[diff] [blame]487 * (microMIPS & MIPS16e) NOP instruction.
488 */
489#define MM_NOP16 0x0c00
490
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]491struct j_format {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]492 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
493 __BITFIELD_FIELD(unsigned int target : 26,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]494 ;))
495};
496
497struct i_format { /* signed immediate format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]498 __BITFIELD_FIELD(unsigned int opcode : 6,
499 __BITFIELD_FIELD(unsigned int rs : 5,
500 __BITFIELD_FIELD(unsigned int rt : 5,
501 __BITFIELD_FIELD(signed int simmediate : 16,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]502 ;))))
503};
504
505struct u_format { /* unsigned immediate format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]506 __BITFIELD_FIELD(unsigned int opcode : 6,
507 __BITFIELD_FIELD(unsigned int rs : 5,
508 __BITFIELD_FIELD(unsigned int rt : 5,
509 __BITFIELD_FIELD(unsigned int uimmediate : 16,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]510 ;))))
511};
512
513struct c_format { /* Cache (>= R6000) format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]514 __BITFIELD_FIELD(unsigned int opcode : 6,
515 __BITFIELD_FIELD(unsigned int rs : 5,
516 __BITFIELD_FIELD(unsigned int c_op : 3,
517 __BITFIELD_FIELD(unsigned int cache : 2,
518 __BITFIELD_FIELD(unsigned int simmediate : 16,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]519 ;)))))
520};
521
522struct r_format { /* Register format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]523 __BITFIELD_FIELD(unsigned int opcode : 6,
524 __BITFIELD_FIELD(unsigned int rs : 5,
525 __BITFIELD_FIELD(unsigned int rt : 5,
526 __BITFIELD_FIELD(unsigned int rd : 5,
527 __BITFIELD_FIELD(unsigned int re : 5,
528 __BITFIELD_FIELD(unsigned int func : 6,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]529 ;))))))
530};
531
532struct p_format { /* Performance counter format (R10000) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]533 __BITFIELD_FIELD(unsigned int opcode : 6,
534 __BITFIELD_FIELD(unsigned int rs : 5,
535 __BITFIELD_FIELD(unsigned int rt : 5,
536 __BITFIELD_FIELD(unsigned int rd : 5,
537 __BITFIELD_FIELD(unsigned int re : 5,
538 __BITFIELD_FIELD(unsigned int func : 6,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]539 ;))))))
540};
541
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]542struct f_format { /* FPU register format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]543 __BITFIELD_FIELD(unsigned int opcode : 6,
544 __BITFIELD_FIELD(unsigned int : 1,
545 __BITFIELD_FIELD(unsigned int fmt : 4,
546 __BITFIELD_FIELD(unsigned int rt : 5,
547 __BITFIELD_FIELD(unsigned int rd : 5,
548 __BITFIELD_FIELD(unsigned int re : 5,
549 __BITFIELD_FIELD(unsigned int func : 6,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]550 ;)))))))
551};
552
553struct ma_format { /* FPU multiply and add format (MIPS IV) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]554 __BITFIELD_FIELD(unsigned int opcode : 6,
555 __BITFIELD_FIELD(unsigned int fr : 5,
556 __BITFIELD_FIELD(unsigned int ft : 5,
557 __BITFIELD_FIELD(unsigned int fs : 5,
558 __BITFIELD_FIELD(unsigned int fd : 5,
559 __BITFIELD_FIELD(unsigned int func : 4,
560 __BITFIELD_FIELD(unsigned int fmt : 2,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]561 ;)))))))
562};
563
564struct b_format { /* BREAK and SYSCALL */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]565 __BITFIELD_FIELD(unsigned int opcode : 6,
566 __BITFIELD_FIELD(unsigned int code : 20,
567 __BITFIELD_FIELD(unsigned int func : 6,
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]568 ;)))
569};
570
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]571struct ps_format { /* MIPS-3D / paired single format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]572 __BITFIELD_FIELD(unsigned int opcode : 6,
573 __BITFIELD_FIELD(unsigned int rs : 5,
574 __BITFIELD_FIELD(unsigned int ft : 5,
575 __BITFIELD_FIELD(unsigned int fs : 5,
576 __BITFIELD_FIELD(unsigned int fd : 5,
577 __BITFIELD_FIELD(unsigned int func : 6,
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]578 ;))))))
579};
580
581struct v_format { /* MDMX vector format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]582 __BITFIELD_FIELD(unsigned int opcode : 6,
583 __BITFIELD_FIELD(unsigned int sel : 4,
584 __BITFIELD_FIELD(unsigned int fmt : 1,
585 __BITFIELD_FIELD(unsigned int vt : 5,
586 __BITFIELD_FIELD(unsigned int vs : 5,
587 __BITFIELD_FIELD(unsigned int vd : 5,
588 __BITFIELD_FIELD(unsigned int func : 6,
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]589 ;)))))))
590};
591
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]592struct spec3_format { /* SPEC3 */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]593 __BITFIELD_FIELD(unsigned int opcode:6,
594 __BITFIELD_FIELD(unsigned int rs:5,
595 __BITFIELD_FIELD(unsigned int rt:5,
596 __BITFIELD_FIELD(signed int simmediate:9,
597 __BITFIELD_FIELD(unsigned int func:7,
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]598 ;)))))
599};
600
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]601/*
602 * microMIPS instruction formats (32-bit length)
603 *
604 * NOTE:
605 * Parenthesis denote whether the format is a microMIPS instruction or
606 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
607 */
608struct fb_format { /* FPU branch format (MIPS32) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]609 __BITFIELD_FIELD(unsigned int opcode : 6,
610 __BITFIELD_FIELD(unsigned int bc : 5,
611 __BITFIELD_FIELD(unsigned int cc : 3,
612 __BITFIELD_FIELD(unsigned int flag : 2,
613 __BITFIELD_FIELD(signed int simmediate : 16,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]614 ;)))))
615};
616
617struct fp0_format { /* FPU multiply and add format (MIPS32) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]618 __BITFIELD_FIELD(unsigned int opcode : 6,
619 __BITFIELD_FIELD(unsigned int fmt : 5,
620 __BITFIELD_FIELD(unsigned int ft : 5,
621 __BITFIELD_FIELD(unsigned int fs : 5,
622 __BITFIELD_FIELD(unsigned int fd : 5,
623 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]624 ;))))))
625};
626
627struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]628 __BITFIELD_FIELD(unsigned int opcode : 6,
629 __BITFIELD_FIELD(unsigned int ft : 5,
630 __BITFIELD_FIELD(unsigned int fs : 5,
631 __BITFIELD_FIELD(unsigned int fd : 5,
632 __BITFIELD_FIELD(unsigned int fmt : 3,
633 __BITFIELD_FIELD(unsigned int op : 2,
634 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]635 ;)))))))
636};
637
638struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]639 __BITFIELD_FIELD(unsigned int opcode : 6,
640 __BITFIELD_FIELD(unsigned int op : 5,
641 __BITFIELD_FIELD(unsigned int rt : 5,
642 __BITFIELD_FIELD(unsigned int fs : 5,
643 __BITFIELD_FIELD(unsigned int fd : 5,
644 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]645 ;))))))
646};
647
648struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]649 __BITFIELD_FIELD(unsigned int opcode : 6,
650 __BITFIELD_FIELD(unsigned int rt : 5,
651 __BITFIELD_FIELD(unsigned int fs : 5,
652 __BITFIELD_FIELD(unsigned int fmt : 2,
653 __BITFIELD_FIELD(unsigned int op : 8,
654 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]655 ;))))))
656};
657
658struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]659 __BITFIELD_FIELD(unsigned int opcode : 6,
660 __BITFIELD_FIELD(unsigned int fd : 5,
661 __BITFIELD_FIELD(unsigned int fs : 5,
662 __BITFIELD_FIELD(unsigned int cc : 3,
663 __BITFIELD_FIELD(unsigned int zero : 2,
664 __BITFIELD_FIELD(unsigned int fmt : 2,
665 __BITFIELD_FIELD(unsigned int op : 3,
666 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]667 ;))))))))
668};
669
670struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]671 __BITFIELD_FIELD(unsigned int opcode : 6,
672 __BITFIELD_FIELD(unsigned int rt : 5,
673 __BITFIELD_FIELD(unsigned int fs : 5,
674 __BITFIELD_FIELD(unsigned int fmt : 3,
675 __BITFIELD_FIELD(unsigned int op : 7,
676 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]677 ;))))))
678};
679
680struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]681 __BITFIELD_FIELD(unsigned int opcode : 6,
682 __BITFIELD_FIELD(unsigned int rt : 5,
683 __BITFIELD_FIELD(unsigned int fs : 5,
684 __BITFIELD_FIELD(unsigned int cc : 3,
685 __BITFIELD_FIELD(unsigned int fmt : 3,
686 __BITFIELD_FIELD(unsigned int cond : 4,
687 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]688 ;)))))))
689};
690
691struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]692 __BITFIELD_FIELD(unsigned int opcode : 6,
693 __BITFIELD_FIELD(unsigned int index : 5,
694 __BITFIELD_FIELD(unsigned int base : 5,
695 __BITFIELD_FIELD(unsigned int fd : 5,
696 __BITFIELD_FIELD(unsigned int op : 5,
697 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]698 ;))))))
699};
700
701struct fp6_format { /* FPU madd and msub format (MIPS IV) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]702 __BITFIELD_FIELD(unsigned int opcode : 6,
703 __BITFIELD_FIELD(unsigned int fr : 5,
704 __BITFIELD_FIELD(unsigned int ft : 5,
705 __BITFIELD_FIELD(unsigned int fs : 5,
706 __BITFIELD_FIELD(unsigned int fd : 5,
707 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]708 ;))))))
709};
710
711struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]712 __BITFIELD_FIELD(unsigned int opcode : 6,
713 __BITFIELD_FIELD(unsigned int ft : 5,
714 __BITFIELD_FIELD(unsigned int fs : 5,
715 __BITFIELD_FIELD(unsigned int fd : 5,
716 __BITFIELD_FIELD(unsigned int fr : 5,
717 __BITFIELD_FIELD(unsigned int func : 6,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]718 ;))))))
719};
720
721struct mm_i_format { /* Immediate format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]722 __BITFIELD_FIELD(unsigned int opcode : 6,
723 __BITFIELD_FIELD(unsigned int rt : 5,
724 __BITFIELD_FIELD(unsigned int rs : 5,
725 __BITFIELD_FIELD(signed int simmediate : 16,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]726 ;))))
727};
728
729struct mm_m_format { /* Multi-word load/store format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]730 __BITFIELD_FIELD(unsigned int opcode : 6,
731 __BITFIELD_FIELD(unsigned int rd : 5,
732 __BITFIELD_FIELD(unsigned int base : 5,
733 __BITFIELD_FIELD(unsigned int func : 4,
734 __BITFIELD_FIELD(signed int simmediate : 12,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]735 ;)))))
736};
737
738struct mm_x_format { /* Scaled indexed load format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]739 __BITFIELD_FIELD(unsigned int opcode : 6,
740 __BITFIELD_FIELD(unsigned int index : 5,
741 __BITFIELD_FIELD(unsigned int base : 5,
742 __BITFIELD_FIELD(unsigned int rd : 5,
743 __BITFIELD_FIELD(unsigned int func : 11,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]744 ;)))))
745};
746
747/*
748 * microMIPS instruction formats (16-bit length)
749 */
750struct mm_b0_format { /* Unconditional branch format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]751 __BITFIELD_FIELD(unsigned int opcode : 6,
752 __BITFIELD_FIELD(signed int simmediate : 10,
753 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]754 ;)))
755};
756
757struct mm_b1_format { /* Conditional branch format (microMIPS) */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]758 __BITFIELD_FIELD(unsigned int opcode : 6,
759 __BITFIELD_FIELD(unsigned int rs : 3,
760 __BITFIELD_FIELD(signed int simmediate : 7,
761 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]762 ;))))
763};
764
765struct mm16_m_format { /* Multi-word load/store format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]766 __BITFIELD_FIELD(unsigned int opcode : 6,
767 __BITFIELD_FIELD(unsigned int func : 4,
768 __BITFIELD_FIELD(unsigned int rlist : 2,
769 __BITFIELD_FIELD(unsigned int imm : 4,
770 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]771 ;)))))
772};
773
774struct mm16_rb_format { /* Signed immediate format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]775 __BITFIELD_FIELD(unsigned int opcode : 6,
776 __BITFIELD_FIELD(unsigned int rt : 3,
777 __BITFIELD_FIELD(unsigned int base : 3,
778 __BITFIELD_FIELD(signed int simmediate : 4,
779 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]780 ;)))))
781};
782
783struct mm16_r3_format { /* Load from global pointer format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]784 __BITFIELD_FIELD(unsigned int opcode : 6,
785 __BITFIELD_FIELD(unsigned int rt : 3,
786 __BITFIELD_FIELD(signed int simmediate : 7,
787 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]788 ;))))
789};
790
791struct mm16_r5_format { /* Load/store from stack pointer format */
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]792 __BITFIELD_FIELD(unsigned int opcode : 6,
793 __BITFIELD_FIELD(unsigned int rt : 5,
794 __BITFIELD_FIELD(signed int simmediate : 5,
795 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]796 ;))))
797};
798
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]799/*
800 * MIPS16e instruction formats (16-bit length)
801 */
802struct m16e_rr {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]803 __BITFIELD_FIELD(unsigned int opcode : 5,
804 __BITFIELD_FIELD(unsigned int rx : 3,
805 __BITFIELD_FIELD(unsigned int nd : 1,
806 __BITFIELD_FIELD(unsigned int l : 1,
807 __BITFIELD_FIELD(unsigned int ra : 1,
808 __BITFIELD_FIELD(unsigned int func : 5,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]809 ;))))))
810};
811
812struct m16e_jal {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]813 __BITFIELD_FIELD(unsigned int opcode : 5,
814 __BITFIELD_FIELD(unsigned int x : 1,
815 __BITFIELD_FIELD(unsigned int imm20_16 : 5,
816 __BITFIELD_FIELD(signed int imm25_21 : 5,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]817 ;))))
818};
819
820struct m16e_i64 {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]821 __BITFIELD_FIELD(unsigned int opcode : 5,
822 __BITFIELD_FIELD(unsigned int func : 3,
823 __BITFIELD_FIELD(unsigned int imm : 8,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]824 ;)))
825};
826
827struct m16e_ri64 {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]828 __BITFIELD_FIELD(unsigned int opcode : 5,
829 __BITFIELD_FIELD(unsigned int func : 3,
830 __BITFIELD_FIELD(unsigned int ry : 3,
831 __BITFIELD_FIELD(unsigned int imm : 5,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]832 ;))))
833};
834
835struct m16e_ri {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]836 __BITFIELD_FIELD(unsigned int opcode : 5,
837 __BITFIELD_FIELD(unsigned int rx : 3,
838 __BITFIELD_FIELD(unsigned int imm : 8,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]839 ;)))
840};
841
842struct m16e_rri {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]843 __BITFIELD_FIELD(unsigned int opcode : 5,
844 __BITFIELD_FIELD(unsigned int rx : 3,
845 __BITFIELD_FIELD(unsigned int ry : 3,
846 __BITFIELD_FIELD(unsigned int imm : 5,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]847 ;))))
848};
849
850struct m16e_i8 {
Ralf Baechle8471ac12014-04-16 00:31:51 +0200[diff] [blame]851 __BITFIELD_FIELD(unsigned int opcode : 5,
852 __BITFIELD_FIELD(unsigned int func : 3,
853 __BITFIELD_FIELD(unsigned int imm : 8,
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]854 ;)))
855};
856
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]857union mips_instruction {
858 unsigned int word;
859 unsigned short halfword[2];
860 unsigned char byte[4];
861 struct j_format j_format;
862 struct i_format i_format;
863 struct u_format u_format;
864 struct c_format c_format;
865 struct r_format r_format;
866 struct p_format p_format;
867 struct f_format f_format;
868 struct ma_format ma_format;
869 struct b_format b_format;
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]870 struct ps_format ps_format;
871 struct v_format v_format;
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]872 struct spec3_format spec3_format;
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]873 struct fb_format fb_format;
874 struct fp0_format fp0_format;
875 struct mm_fp0_format mm_fp0_format;
876 struct fp1_format fp1_format;
877 struct mm_fp1_format mm_fp1_format;
878 struct mm_fp2_format mm_fp2_format;
879 struct mm_fp3_format mm_fp3_format;
880 struct mm_fp4_format mm_fp4_format;
881 struct mm_fp5_format mm_fp5_format;
882 struct fp6_format fp6_format;
883 struct mm_fp6_format mm_fp6_format;
884 struct mm_i_format mm_i_format;
885 struct mm_m_format mm_m_format;
886 struct mm_x_format mm_x_format;
887 struct mm_b0_format mm_b0_format;
888 struct mm_b1_format mm_b1_format;
889 struct mm16_m_format mm16_m_format ;
890 struct mm16_rb_format mm16_rb_format;
891 struct mm16_r3_format mm16_r3_format;
892 struct mm16_r5_format mm16_r5_format;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]893};
894
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]895union mips16e_instruction {
896 unsigned int full : 16;
897 struct m16e_rr rr;
898 struct m16e_jal jal;
899 struct m16e_i64 i64;
900 struct m16e_ri64 ri64;
901 struct m16e_ri ri;
902 struct m16e_rri rri;
903 struct m16e_i8 i8;
904};
905
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]906#endif /* _UAPI_ASM_INST_H */