blob: a8608129963313268c0b8223795f5528f8368020 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/types.h>
19#include <linux/kernel.h>
Paul Gortmaker363c75d2011-05-27 09:37:25 -040020#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040024#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070025#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080026#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050027#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090028#include <linux/ioport.h>
Arjan van de Ven32098742012-01-30 20:52:07 -080029#include <linux/sched.h>
30#include <linux/ktime.h>
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010031#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090032#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Yuji Shimada32a9a6822009-03-16 17:13:39 +090034/*
Yuji Shimada0cdbe302009-04-06 10:24:21 +090035 * This quirk function disables memory decoding and releases memory resources
36 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090037 * It also rounds up size to specified alignment.
38 * Later on, the kernel will assign page-aligned memory resource back
Yuji Shimada0cdbe302009-04-06 10:24:21 +090039 * to the device.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090040 */
41static void __devinit quirk_resource_alignment(struct pci_dev *dev)
42{
43 int i;
44 struct resource *r;
45 resource_size_t align, size;
Yuji Shimada0cdbe302009-04-06 10:24:21 +090046 u16 command;
Yuji Shimada32a9a6822009-03-16 17:13:39 +090047
48 if (!pci_is_reassigndev(dev))
49 return;
50
51 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
52 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
53 dev_warn(&dev->dev,
54 "Can't reassign resources to host bridge.\n");
55 return;
56 }
57
Yuji Shimada0cdbe302009-04-06 10:24:21 +090058 dev_info(&dev->dev,
59 "Disabling memory decoding and releasing memory resources.\n");
60 pci_read_config_word(dev, PCI_COMMAND, &command);
61 command &= ~PCI_COMMAND_MEMORY;
62 pci_write_config_word(dev, PCI_COMMAND, command);
Yuji Shimada32a9a6822009-03-16 17:13:39 +090063
64 align = pci_specified_resource_alignment(dev);
65 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
66 r = &dev->resource[i];
67 if (!(r->flags & IORESOURCE_MEM))
68 continue;
69 size = resource_size(r);
70 if (size < align) {
71 size = align;
72 dev_info(&dev->dev,
73 "Rounding up size of resource #%d to %#llx.\n",
74 i, (unsigned long long)size);
75 }
76 r->end = size - 1;
77 r->start = 0;
78 }
79 /* Need to disable bridge's resource window,
80 * to enable the kernel to reassign new resource
81 * window later on.
82 */
83 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
84 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
85 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
86 r = &dev->resource[i];
87 if (!(r->flags & IORESOURCE_MEM))
88 continue;
89 r->end = resource_size(r) - 1;
90 r->start = 0;
91 }
92 pci_disable_bridge_window(dev);
93 }
94}
95DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
96
Jacob Pan253d2e52010-07-16 10:19:22 -070097/*
98 * Decoding should be disabled for a PCI device during BAR sizing to avoid
99 * conflict. But doing so may cause problems on host bridge and perhaps other
100 * key system devices. For devices that need to have mmio decoding always-on,
101 * we need to set the dev->mmio_always_on bit.
102 */
103static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
104{
Yinghai Lu52d21b52012-02-23 23:46:53 -0800105 dev->mmio_always_on = 1;
Jacob Pan253d2e52010-07-16 10:19:22 -0700106}
Yinghai Lu52d21b52012-02-23 23:46:53 -0800107DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
108 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
Jacob Pan253d2e52010-07-16 10:19:22 -0700109
Doug Thompsonbd8481e2006-05-08 17:06:09 -0700110/* The Mellanox Tavor device gives false positive parity errors
111 * Mark this device with a broken_parity_status, to allow
112 * PCI scanning code to "skip" this now blacklisted device.
113 */
114static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
115{
116 dev->broken_parity_status = 1; /* This device gives false positives */
117}
118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
120
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121/* Deal with broken BIOS'es that neglect to enable passive release,
122 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -0800123static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124{
125 struct pci_dev *d = NULL;
126 unsigned char dlc;
127
128 /* We have to make sure a particular bit is set in the PIIX3
129 ISA bridge, so we have to go out and find it. */
130 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
131 pci_read_config_byte(d, 0x82, &dlc);
132 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -0800133 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 dlc |= 1<<1;
135 pci_write_config_byte(d, 0x82, dlc);
136 }
137 }
138}
Andrew Morton652c5382007-11-21 15:07:13 -0800139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
140DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
143 but VIA don't answer queries. If you happen to have good contacts at VIA
144 ask them for me please -- Alan
145
146 This appears to be BIOS not version dependent. So presumably there is a
147 chipset level fix */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148
149static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
150{
151 if (!isa_dma_bridge_buggy) {
152 isa_dma_bridge_buggy=1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700153 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 }
155}
156 /*
157 * Its not totally clear which chipsets are the problematic ones
158 * We know 82C586 and 82C596 variants are affected.
159 */
Andrew Morton652c5382007-11-21 15:07:13 -0800160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168/*
Len Brown4731fdc2010-09-24 21:02:27 -0400169 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
170 * for some HT machines to use C4 w/o hanging.
171 */
172static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
173{
174 u32 pmbase;
175 u16 pm1a;
176
177 pci_read_config_dword(dev, 0x40, &pmbase);
178 pmbase = pmbase & 0xff80;
179 pm1a = inw(pmbase);
180
181 if (pm1a & 0x10) {
182 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
183 outw(0x10, pmbase);
184 }
185}
186DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
187
188/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 * Chipsets where PCI->PCI transfers vanish or hang
190 */
191static void __devinit quirk_nopcipci(struct pci_dev *dev)
192{
193 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700194 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 pci_pci_problems |= PCIPCI_FAIL;
196 }
197}
Andrew Morton652c5382007-11-21 15:07:13 -0800198DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700200
201static void __devinit quirk_nopciamd(struct pci_dev *dev)
202{
203 u8 rev;
204 pci_read_config_byte(dev, 0x08, &rev);
205 if (rev == 0x13) {
206 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700207 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700208 pci_pci_problems |= PCIAGP_FAIL;
209 }
210}
Andrew Morton652c5382007-11-21 15:07:13 -0800211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212
213/*
214 * Triton requires workarounds to be used by the drivers
215 */
216static void __devinit quirk_triton(struct pci_dev *dev)
217{
218 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700219 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 pci_pci_problems |= PCIPCI_TRITON;
221 }
222}
Andrew Morton652c5382007-11-21 15:07:13 -0800223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227
228/*
229 * VIA Apollo KT133 needs PCI latency patch
230 * Made according to a windows driver based patch by George E. Breese
231 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
Justin P. Mattock631dd1a2010-10-18 11:03:14 +0200232 * and http://www.georgebreese.com/net/software/#PCI
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
234 * the info on which Mr Breese based his work.
235 *
236 * Updated based on further information from the site and also on
237 * information provided by VIA
238 */
Alan Cox1597cac2006-12-04 15:14:45 -0800239static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240{
241 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 u8 busarb;
243 /* Ok we have a potential problem chipset here. Now see if we have
244 a buggy southbridge */
245
246 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
247 if (p!=NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
249 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700250 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 goto exit;
252 } else {
253 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
254 if (p==NULL) /* No problem parts */
255 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700257 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 goto exit;
259 }
260
261 /*
262 * Ok we have the problem. Now set the PCI master grant to
263 * occur every master grant. The apparent bug is that under high
264 * PCI load (quite common in Linux of course) you can get data
265 * loss when the CPU is held off the bus for 3 bus master requests
266 * This happens to include the IDE controllers....
267 *
268 * VIA only apply this fix when an SB Live! is present but under
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300269 * both Linux and Windows this isn't enough, and we have seen
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 * corruption without SB Live! but with things like 3 UDMA IDE
271 * controllers. So we ignore that bit of the VIA recommendation..
272 */
273
274 pci_read_config_byte(dev, 0x76, &busarb);
275 /* Set bit 4 and bi 5 of byte 76 to 0x01
276 "Master priority rotation on every PCI master grant */
277 busarb &= ~(1<<5);
278 busarb |= (1<<4);
279 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700280 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281exit:
282 pci_dev_put(p);
283}
Andrew Morton652c5382007-11-21 15:07:13 -0800284DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
285DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
286DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800287/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800288DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
289DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
290DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291
292/*
293 * VIA Apollo VP3 needs ETBF on BT848/878
294 */
295static void __devinit quirk_viaetbf(struct pci_dev *dev)
296{
297 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700298 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 pci_pci_problems |= PCIPCI_VIAETBF;
300 }
301}
Andrew Morton652c5382007-11-21 15:07:13 -0800302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304static void __devinit quirk_vsfx(struct pci_dev *dev)
305{
306 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700307 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 pci_pci_problems |= PCIPCI_VSFX;
309 }
310}
Andrew Morton652c5382007-11-21 15:07:13 -0800311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312
313/*
314 * Ali Magik requires workarounds to be used by the drivers
315 * that DMA to AGP space. Latency must be set to 0xA and triton
316 * workaround applied too
317 * [Info kindly provided by ALi]
318 */
319static void __init quirk_alimagik(struct pci_dev *dev)
320{
321 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700322 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
324 }
325}
Andrew Morton652c5382007-11-21 15:07:13 -0800326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328
329/*
330 * Natoma has some interesting boundary conditions with Zoran stuff
331 * at least
332 */
333static void __devinit quirk_natoma(struct pci_dev *dev)
334{
335 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700336 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 pci_pci_problems |= PCIPCI_NATOMA;
338 }
339}
Andrew Morton652c5382007-11-21 15:07:13 -0800340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
343DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
344DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
345DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346
347/*
348 * This chip can cause PCI parity errors if config register 0xA0 is read
349 * while DMAs are occurring.
350 */
351static void __devinit quirk_citrine(struct pci_dev *dev)
352{
353 dev->cfg_size = 0xA0;
354}
Andrew Morton652c5382007-11-21 15:07:13 -0800355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356
357/*
358 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
359 * If it's needed, re-allocate the region.
360 */
361static void __devinit quirk_s3_64M(struct pci_dev *dev)
362{
363 struct resource *r = &dev->resource[0];
364
365 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
366 r->start = 0;
367 r->end = 0x3ffffff;
368 }
369}
Andrew Morton652c5382007-11-21 15:07:13 -0800370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500373/*
374 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
375 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
376 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
377 * (which conflicts w/ BAR1's memory range).
378 */
379static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
380{
381 if (pci_resource_len(dev, 0) != 8) {
382 struct resource *res = &dev->resource[0];
383 res->end = res->start + 8 - 1;
384 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
385 "(incorrect header); workaround applied.\n");
386 }
387}
388DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
389
Linus Torvalds6693e742005-10-25 20:40:09 -0700390static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
391 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392{
393 region &= ~(size-1);
394 if (region) {
David S. Miller085ae412005-08-08 13:19:08 -0700395 struct pci_bus_region bus_region;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 struct resource *res = dev->resource + nr;
397
398 res->name = pci_name(dev);
399 res->start = region;
400 res->end = region + size - 1;
401 res->flags = IORESOURCE_IO;
David S. Miller085ae412005-08-08 13:19:08 -0700402
403 /* Convert from PCI bus to resource space. */
404 bus_region.start = res->start;
405 bus_region.end = res->end;
406 pcibios_bus_to_resource(dev, res, &bus_region);
407
Bjorn Helgaasf967a442010-03-22 16:34:05 -0600408 if (pci_claim_resource(dev, nr) == 0)
409 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
410 res, name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 }
412}
413
414/*
415 * ATI Northbridge setups MCE the processor if you even
416 * read somewhere between 0x3b0->0x3bb or read 0x3d3
417 */
418static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
419{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700420 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
422 request_region(0x3b0, 0x0C, "RadeonIGP");
423 request_region(0x3d3, 0x01, "RadeonIGP");
424}
Andrew Morton652c5382007-11-21 15:07:13 -0800425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426
427/*
428 * Let's make the southbridge information explicit instead
429 * of having to worry about people probing the ACPI areas,
430 * for example.. (Yes, it happens, and if you read the wrong
431 * ACPI register it will put the machine to sleep with no
432 * way of waking it up again. Bummer).
433 *
434 * ALI M7101: Two IO regions pointed to by words at
435 * 0xE0 (64 bytes of ACPI registers)
436 * 0xE2 (32 bytes of SMB registers)
437 */
438static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
439{
440 u16 region;
441
442 pci_read_config_word(dev, 0xE0, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700443 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 pci_read_config_word(dev, 0xE2, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700445 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446}
Andrew Morton652c5382007-11-21 15:07:13 -0800447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
Linus Torvalds6693e742005-10-25 20:40:09 -0700449static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
450{
451 u32 devres;
452 u32 mask, size, base;
453
454 pci_read_config_dword(dev, port, &devres);
455 if ((devres & enable) != enable)
456 return;
457 mask = (devres >> 16) & 15;
458 base = devres & 0xffff;
459 size = 16;
460 for (;;) {
461 unsigned bit = size >> 1;
462 if ((bit & mask) == bit)
463 break;
464 size = bit;
465 }
466 /*
467 * For now we only print it out. Eventually we'll want to
468 * reserve it (at least if it's in the 0x1000+ range), but
469 * let's get enough confirmation reports first.
470 */
471 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700472 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700473}
474
475static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
476{
477 u32 devres;
478 u32 mask, size, base;
479
480 pci_read_config_dword(dev, port, &devres);
481 if ((devres & enable) != enable)
482 return;
483 base = devres & 0xffff0000;
484 mask = (devres & 0x3f) << 16;
485 size = 128 << 16;
486 for (;;) {
487 unsigned bit = size >> 1;
488 if ((bit & mask) == bit)
489 break;
490 size = bit;
491 }
492 /*
493 * For now we only print it out. Eventually we'll want to
494 * reserve it, but let's get enough confirmation reports first.
495 */
496 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700497 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700498}
499
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500/*
501 * PIIX4 ACPI: Two IO regions pointed to by longwords at
502 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800503 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700504 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 */
506static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
507{
Linus Torvalds6693e742005-10-25 20:40:09 -0700508 u32 region, res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509
510 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700511 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512 pci_read_config_dword(dev, 0x90, &region);
Linus Torvalds08db2a72005-10-30 14:40:07 -0800513 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700514
515 /* Device resource A has enables for some of the other ones */
516 pci_read_config_dword(dev, 0x5c, &res_a);
517
518 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
519 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
520
521 /* Device resource D is just bitfields for static resources */
522
523 /* Device 12 enabled? */
524 if (res_a & (1 << 29)) {
525 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
526 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
527 }
528 /* Device 13 enabled? */
529 if (res_a & (1 << 30)) {
530 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
531 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
532 }
533 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
534 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535}
Andrew Morton652c5382007-11-21 15:07:13 -0800536DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
537DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
Jiri Slabycdb97552011-02-28 10:45:09 +0100539#define ICH_PMBASE 0x40
540#define ICH_ACPI_CNTL 0x44
541#define ICH4_ACPI_EN 0x10
542#define ICH6_ACPI_EN 0x80
543#define ICH4_GPIOBASE 0x58
544#define ICH4_GPIO_CNTL 0x5c
545#define ICH4_GPIO_EN 0x10
546#define ICH6_GPIOBASE 0x48
547#define ICH6_GPIO_CNTL 0x4c
548#define ICH6_GPIO_EN 0x10
549
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550/*
551 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
552 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
553 * 0x58 (64 bytes of GPIO I/O space)
554 */
555static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
556{
557 u32 region;
Jiri Slabycdb97552011-02-28 10:45:09 +0100558 u8 enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100560 /*
561 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
562 * with low legacy (and fixed) ports. We don't know the decoding
563 * priority and can't tell whether the legacy device or the one created
564 * here is really at that address. This happens on boards with broken
565 * BIOSes.
566 */
567
Jiri Slabycdb97552011-02-28 10:45:09 +0100568 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
569 if (enable & ICH4_ACPI_EN) {
570 pci_read_config_dword(dev, ICH_PMBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100571 region &= PCI_BASE_ADDRESS_IO_MASK;
572 if (region >= PCIBIOS_MIN_IO)
573 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
574 "ICH4 ACPI/GPIO/TCO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100575 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576
Jiri Slabycdb97552011-02-28 10:45:09 +0100577 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
578 if (enable & ICH4_GPIO_EN) {
579 pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100580 region &= PCI_BASE_ADDRESS_IO_MASK;
581 if (region >= PCIBIOS_MIN_IO)
582 quirk_io_region(dev, region, 64,
583 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100584 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585}
Andrew Morton652c5382007-11-21 15:07:13 -0800586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
593DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
594DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596
Linus Torvalds894886e2008-12-06 10:10:10 -0800597static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000598{
599 u32 region;
Jiri Slabycdb97552011-02-28 10:45:09 +0100600 u8 enable;
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000601
Jiri Slabycdb97552011-02-28 10:45:09 +0100602 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
603 if (enable & ICH6_ACPI_EN) {
604 pci_read_config_dword(dev, ICH_PMBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100605 region &= PCI_BASE_ADDRESS_IO_MASK;
606 if (region >= PCIBIOS_MIN_IO)
607 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
608 "ICH6 ACPI/GPIO/TCO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100609 }
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000610
Jiri Slabycdb97552011-02-28 10:45:09 +0100611 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
Jean Delvareb6d95bb2011-04-15 10:24:07 +0200612 if (enable & ICH6_GPIO_EN) {
Jiri Slabycdb97552011-02-28 10:45:09 +0100613 pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100614 region &= PCI_BASE_ADDRESS_IO_MASK;
615 if (region >= PCIBIOS_MIN_IO)
616 quirk_io_region(dev, region, 64,
617 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100618 }
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000619}
Linus Torvalds894886e2008-12-06 10:10:10 -0800620
621static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
622{
623 u32 val;
624 u32 size, base;
625
626 pci_read_config_dword(dev, reg, &val);
627
628 /* Enabled? */
629 if (!(val & 1))
630 return;
631 base = val & 0xfffc;
632 if (dynsize) {
633 /*
634 * This is not correct. It is 16, 32 or 64 bytes depending on
635 * register D31:F0:ADh bits 5:4.
636 *
637 * But this gets us at least _part_ of it.
638 */
639 size = 16;
640 } else {
641 size = 128;
642 }
643 base &= ~(size-1);
644
645 /* Just print it out for now. We should reserve it after more debugging */
646 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
647}
648
649static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
650{
651 /* Shared ACPI/GPIO decode with all ICH6+ */
652 ich6_lpc_acpi_gpio(dev);
653
654 /* ICH6-specific generic IO decode */
655 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
656 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
657}
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
660
661static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
662{
663 u32 val;
664 u32 mask, base;
665
666 pci_read_config_dword(dev, reg, &val);
667
668 /* Enabled? */
669 if (!(val & 1))
670 return;
671
672 /*
673 * IO base in bits 15:2, mask in bits 23:18, both
674 * are dword-based
675 */
676 base = val & 0xfffc;
677 mask = (val >> 16) & 0xfc;
678 mask |= 3;
679
680 /* Just print it out for now. We should reserve it after more debugging */
681 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
682}
683
684/* ICH7-10 has the same common LPC generic IO decode registers */
685static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
686{
Jean Delvare5d9c0a72011-04-15 10:03:53 +0200687 /* We share the common ACPI/GPIO decode with ICH6 */
Linus Torvalds894886e2008-12-06 10:10:10 -0800688 ich6_lpc_acpi_gpio(dev);
689
690 /* And have 4 ICH7+ generic decodes */
691 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
692 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
693 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
694 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
695}
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000709
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710/*
711 * VIA ACPI: One IO region pointed to by longword at
712 * 0x48 or 0x20 (256 bytes of ACPI registers)
713 */
714static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
715{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 u32 region;
717
Auke Kok651472f2007-08-27 16:18:10 -0700718 if (dev->revision & 0x10) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 pci_read_config_dword(dev, 0x48, &region);
720 region &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700721 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 }
723}
Andrew Morton652c5382007-11-21 15:07:13 -0800724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725
726/*
727 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
728 * 0x48 (256 bytes of ACPI registers)
729 * 0x70 (128 bytes of hardware monitoring register)
730 * 0x90 (16 bytes of SMB registers)
731 */
732static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
733{
734 u16 hm;
735 u32 smb;
736
737 quirk_vt82c586_acpi(dev);
738
739 pci_read_config_word(dev, 0x70, &hm);
740 hm &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300741 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742
743 pci_read_config_dword(dev, 0x90, &smb);
744 smb &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300745 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746}
Andrew Morton652c5382007-11-21 15:07:13 -0800747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400749/*
750 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
751 * 0x88 (128 bytes of power management registers)
752 * 0xd0 (16 bytes of SMB registers)
753 */
754static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
755{
756 u16 pm, smb;
757
758 pci_read_config_word(dev, 0x88, &pm);
759 pm &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700760 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400761
762 pci_read_config_word(dev, 0xd0, &smb);
763 smb &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700764 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400765}
766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
767
Gabe Black1f56f4a2009-10-06 09:19:45 -0500768/*
769 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
770 * Disable fast back-to-back on the secondary bus segment
771 */
772static void __devinit quirk_xio2000a(struct pci_dev *dev)
773{
774 struct pci_dev *pdev;
775 u16 command;
776
777 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
778 "secondary bus fast back-to-back transfers disabled\n");
779 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
780 pci_read_config_word(pdev, PCI_COMMAND, &command);
781 if (command & PCI_COMMAND_FAST_BACK)
782 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
783 }
784}
785DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
786 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787
788#ifdef CONFIG_X86_IO_APIC
789
790#include <asm/io_apic.h>
791
792/*
793 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
794 * devices to the external APIC.
795 *
796 * TODO: When we have device-specific interrupt routers,
797 * this code will go away from quirks.
798 */
Alan Cox1597cac2006-12-04 15:14:45 -0800799static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800{
801 u8 tmp;
802
803 if (nr_ioapics < 1)
804 tmp = 0; /* nothing routed to external APIC */
805 else
806 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
807
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700808 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 tmp == 0 ? "Disa" : "Ena");
810
811 /* Offset 0x58: External APIC IRQ output control */
812 pci_write_config_byte (dev, 0x58, tmp);
813}
Andrew Morton652c5382007-11-21 15:07:13 -0800814DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200815DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816
817/*
Karsten Wiesea1740912005-09-03 15:56:33 -0700818 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
819 * This leads to doubled level interrupt rates.
820 * Set this bit to get rid of cycle wastage.
821 * Otherwise uncritical.
822 */
Alan Cox1597cac2006-12-04 15:14:45 -0800823static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700824{
825 u8 misc_control2;
826#define BYPASS_APIC_DEASSERT 8
827
828 pci_read_config_byte(dev, 0x5B, &misc_control2);
829 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700830 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700831 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
832 }
833}
834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200835DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700836
837/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 * The AMD io apic can hang the box when an apic irq is masked.
839 * We check all revs >= B0 (yet not in the pre production!) as the bug
840 * is currently marked NoFix
841 *
842 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700843 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844 * of course. However the advice is demonstrably good even if so..
845 */
846static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
847{
Auke Kok44c10132007-06-08 15:46:36 -0700848 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700849 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
850 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 }
852}
Andrew Morton652c5382007-11-21 15:07:13 -0800853DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854
855static void __init quirk_ioapic_rmw(struct pci_dev *dev)
856{
857 if (dev->devfn == 0 && dev->bus->number == 0)
858 sis_apic_bug = 1;
859}
Andrew Morton652c5382007-11-21 15:07:13 -0800860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861#endif /* CONFIG_X86_IO_APIC */
862
Peter Orubad556ad42007-05-15 13:59:13 +0200863/*
864 * Some settings of MMRBC can lead to data corruption so block changes.
865 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
866 */
867static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
868{
Auke Kokaa288d42007-08-27 16:17:47 -0700869 if (dev->subordinate && dev->revision <= 0x12) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700870 dev_info(&dev->dev, "AMD8131 rev %x detected; "
871 "disabling PCI-X MMRBC\n", dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200872 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
873 }
874}
875DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876
877/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 * FIXME: it is questionable that quirk_via_acpi
879 * is needed. It shows up as an ISA bridge, and does not
880 * support the PCI_INTERRUPT_LINE register at all. Therefore
881 * it seems like setting the pci_dev's 'irq' to the
882 * value of the ACPI SCI interrupt is only done for convenience.
883 * -jgarzik
884 */
885static void __devinit quirk_via_acpi(struct pci_dev *d)
886{
887 /*
888 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
889 */
890 u8 irq;
891 pci_read_config_byte(d, 0x42, &irq);
892 irq &= 0xf;
893 if (irq && (irq != 2))
894 d->irq = irq;
895}
Andrew Morton652c5382007-11-21 15:07:13 -0800896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898
Daniel Drake09d60292006-09-25 16:52:19 -0700899
900/*
Alan Cox1597cac2006-12-04 15:14:45 -0800901 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700902 */
Alan Cox1597cac2006-12-04 15:14:45 -0800903
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800904static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
905
906static void quirk_via_bridge(struct pci_dev *dev)
907{
908 /* See what bridge we have and find the device ranges */
909 switch (dev->device) {
910 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800911 /* The VT82C686 is special, it attaches to PCI and can have
912 any device number. All its subdevices are functions of
913 that single device. */
914 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
915 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800916 break;
917 case PCI_DEVICE_ID_VIA_8237:
918 case PCI_DEVICE_ID_VIA_8237A:
919 via_vlink_dev_lo = 15;
920 break;
921 case PCI_DEVICE_ID_VIA_8235:
922 via_vlink_dev_lo = 16;
923 break;
924 case PCI_DEVICE_ID_VIA_8231:
925 case PCI_DEVICE_ID_VIA_8233_0:
926 case PCI_DEVICE_ID_VIA_8233A:
927 case PCI_DEVICE_ID_VIA_8233C_0:
928 via_vlink_dev_lo = 17;
929 break;
930 }
931}
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
938DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
939DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700940
Alan Cox1597cac2006-12-04 15:14:45 -0800941/**
942 * quirk_via_vlink - VIA VLink IRQ number update
943 * @dev: PCI device
944 *
945 * If the device we are dealing with is on a PIC IRQ we need to
946 * ensure that the IRQ line register which usually is not relevant
947 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800948 * to the right place.
949 * We only do this on systems where a VIA south bridge was detected,
950 * and only for VIA devices on the motherboard (see quirk_via_bridge
951 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800952 */
953
954static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400955{
956 u8 irq, new_irq;
957
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800958 /* Check if we have VLink at all */
959 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700960 return;
961
962 new_irq = dev->irq;
963
964 /* Don't quirk interrupts outside the legacy IRQ range */
965 if (!new_irq || new_irq > 15)
966 return;
967
Alan Cox1597cac2006-12-04 15:14:45 -0800968 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800969 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
970 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800971 return;
972
973 /* This is an internal VLink device on a PIC interrupt. The BIOS
974 ought to have set this but may not have, so we redo it */
975
Len Brown25be5e62005-05-27 04:21:50 -0400976 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
977 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700978 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
979 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400980 udelay(15); /* unknown if delay really needed */
981 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
982 }
983}
Alan Cox1597cac2006-12-04 15:14:45 -0800984DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400985
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 * VIA VT82C598 has its device ID settable and many BIOSes
988 * set it to the ID of VT82C597 for backward compatibility.
989 * We need to switch it off to be able to recognize the real
990 * type of the chip.
991 */
992static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
993{
994 pci_write_config_byte(dev, 0xfc, 0);
995 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
996}
Andrew Morton652c5382007-11-21 15:07:13 -0800997DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998
999/*
1000 * CardBus controllers have a legacy base address that enables them
1001 * to respond as i82365 pcmcia controllers. We don't want them to
1002 * do this even if the Linux CardBus driver is not loaded, because
1003 * the Linux i82365 driver does not (and should not) handle CardBus.
1004 */
Alan Cox1597cac2006-12-04 15:14:45 -08001005static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1008}
Yinghai Luae9de562012-02-23 23:46:54 -08001009DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1010 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1011DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1012 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013
1014/*
1015 * Following the PCI ordering rules is optional on the AMD762. I'm not
1016 * sure what the designers were smoking but let's not inhale...
1017 *
1018 * To be fair to AMD, it follows the spec by default, its BIOS people
1019 * who turn it off!
1020 */
Alan Cox1597cac2006-12-04 15:14:45 -08001021static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022{
1023 u32 pcic;
1024 pci_read_config_dword(dev, 0x4C, &pcic);
1025 if ((pcic&6)!=6) {
1026 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001027 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 pci_write_config_dword(dev, 0x4C, pcic);
1029 pci_read_config_dword(dev, 0x84, &pcic);
1030 pcic |= (1<<23); /* Required in this mode */
1031 pci_write_config_dword(dev, 0x84, pcic);
1032 }
1033}
Andrew Morton652c5382007-11-21 15:07:13 -08001034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001035DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036
1037/*
1038 * DreamWorks provided workaround for Dunord I-3000 problem
1039 *
1040 * This card decodes and responds to addresses not apparently
1041 * assigned to it. We force a larger allocation to ensure that
1042 * nothing gets put too close to it.
1043 */
1044static void __devinit quirk_dunord ( struct pci_dev * dev )
1045{
1046 struct resource *r = &dev->resource [1];
1047 r->start = 0;
1048 r->end = 0xffffff;
1049}
Andrew Morton652c5382007-11-21 15:07:13 -08001050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051
1052/*
1053 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1054 * is subtractive decoding (transparent), and does indicate this
1055 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1056 * instead of 0x01.
1057 */
1058static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1059{
1060 dev->transparent = 1;
1061}
Andrew Morton652c5382007-11-21 15:07:13 -08001062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064
1065/*
1066 * Common misconfiguration of the MediaGX/Geode PCI master that will
1067 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
Justin P. Mattock631dd1a2010-10-18 11:03:14 +02001068 * datasheets found at http://www.national.com/analog for info on what
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 * these bits do. <christer@weinigel.se>
1070 */
Alan Cox1597cac2006-12-04 15:14:45 -08001071static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072{
1073 u8 reg;
1074 pci_read_config_byte(dev, 0x41, &reg);
1075 if (reg & 2) {
1076 reg &= ~2;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001077 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 pci_write_config_byte(dev, 0x41, reg);
1079 }
1080}
Andrew Morton652c5382007-11-21 15:07:13 -08001081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1082DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083
1084/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085 * Ensure C0 rev restreaming is off. This is normally done by
1086 * the BIOS but in the odd case it is not the results are corruption
1087 * hence the presence of a Linux check
1088 */
Alan Cox1597cac2006-12-04 15:14:45 -08001089static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090{
1091 u16 config;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092
Auke Kok44c10132007-06-08 15:46:36 -07001093 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 return;
1095 pci_read_config_word(pdev, 0x40, &config);
1096 if (config & (1<<6)) {
1097 config &= ~(1<<6);
1098 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001099 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 }
1101}
Andrew Morton652c5382007-11-21 15:07:13 -08001102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001103DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104
Crane Cai05a7d222008-02-02 13:56:56 +08001105static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001106{
Shane Huang5deab532009-10-13 11:14:00 +08001107 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001108 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001109
Crane Cai05a7d222008-02-02 13:56:56 +08001110 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1111 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001112 pci_read_config_byte(pdev, 0x40, &tmp);
1113 pci_write_config_byte(pdev, 0x40, tmp|1);
1114 pci_write_config_byte(pdev, 0x9, 1);
1115 pci_write_config_byte(pdev, 0xa, 6);
1116 pci_write_config_byte(pdev, 0x40, tmp);
1117
Conke Huc9f89472007-01-09 05:32:51 -05001118 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001119 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001120 }
1121}
Crane Cai05a7d222008-02-02 13:56:56 +08001122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001123DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001125DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huang5deab532009-10-13 11:14:00 +08001126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1127DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001128
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129/*
1130 * Serverworks CSB5 IDE does not fully support native mode
1131 */
1132static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1133{
1134 u8 prog;
1135 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1136 if (prog & 5) {
1137 prog &= ~5;
1138 pdev->class &= ~5;
1139 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001140 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 }
1142}
Andrew Morton652c5382007-11-21 15:07:13 -08001143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144
1145/*
1146 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1147 */
1148static void __init quirk_ide_samemode(struct pci_dev *pdev)
1149{
1150 u8 prog;
1151
1152 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1153
1154 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001155 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 prog &= ~5;
1157 pdev->class &= ~5;
1158 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 }
1160}
Alan Cox368c73d2006-10-04 00:41:26 +01001161DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162
Alan Cox979b1792008-07-24 17:18:38 +01001163/*
1164 * Some ATA devices break if put into D3
1165 */
1166
1167static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1168{
Yinghai Lufaa738b2012-02-23 23:46:55 -08001169 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
Alan Cox979b1792008-07-24 17:18:38 +01001170}
Yinghai Lufaa738b2012-02-23 23:46:55 -08001171/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1172DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1174DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1175 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001176/* ALi loses some register settings that we cannot then restore */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001177DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1178 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001179/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1180 occur when mode detecting */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001181DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1182 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001183
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184/* This was originally an Alpha specific thing, but it really fits here.
1185 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1186 */
1187static void __init quirk_eisa_bridge(struct pci_dev *dev)
1188{
1189 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1190}
Andrew Morton652c5382007-11-21 15:07:13 -08001191DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001193
1194/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1196 * is not activated. The myth is that Asus said that they do not want the
1197 * users to be irritated by just another PCI Device in the Win98 device
1198 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1199 * package 2.7.0 for details)
1200 *
1201 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1202 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001203 * becomes necessary to do this tweak in two steps -- the chosen trigger
1204 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001205 *
1206 * Note that we used to unhide the SMBus that way on Toshiba laptops
1207 * (Satellite A40 and Tecra M2) but then found that the thermal management
1208 * was done by SMM code, which could cause unsynchronized concurrent
1209 * accesses to the SMBus registers, with potentially bad effects. Thus you
1210 * should be very careful when adding new entries: if SMM is accessing the
1211 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001212 *
1213 * Likewise, many recent laptops use ACPI for thermal management. If the
1214 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1215 * natively, and keeping the SMBus hidden is the right thing to do. If you
1216 * are about to add an entry in the table below, please first disassemble
1217 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001219static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220
1221static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1222{
1223 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1224 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1225 switch(dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001226 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 case 0x8070: /* P4B */
1228 case 0x8088: /* P4B533 */
1229 case 0x1626: /* L3C notebook */
1230 asus_hides_smbus = 1;
1231 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001232 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 switch(dev->subsystem_device) {
1234 case 0x80b1: /* P4GE-V */
1235 case 0x80b2: /* P4PE */
1236 case 0x8093: /* P4B533-V */
1237 asus_hides_smbus = 1;
1238 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001239 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 switch(dev->subsystem_device) {
1241 case 0x8030: /* P4T533 */
1242 asus_hides_smbus = 1;
1243 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001244 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 switch (dev->subsystem_device) {
1246 case 0x8070: /* P4G8X Deluxe */
1247 asus_hides_smbus = 1;
1248 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001249 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001250 switch (dev->subsystem_device) {
1251 case 0x80c9: /* PU-DLS */
1252 asus_hides_smbus = 1;
1253 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001254 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255 switch (dev->subsystem_device) {
1256 case 0x1751: /* M2N notebook */
1257 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001258 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001259 asus_hides_smbus = 1;
1260 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001261 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 switch (dev->subsystem_device) {
1263 case 0x184b: /* W1N notebook */
1264 case 0x186a: /* M6Ne notebook */
1265 asus_hides_smbus = 1;
1266 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001267 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001268 switch (dev->subsystem_device) {
1269 case 0x80f2: /* P4P800-X */
1270 asus_hides_smbus = 1;
1271 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001272 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001273 switch (dev->subsystem_device) {
1274 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001275 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001276 asus_hides_smbus = 1;
1277 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1279 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1280 switch(dev->subsystem_device) {
1281 case 0x088C: /* HP Compaq nc8000 */
1282 case 0x0890: /* HP Compaq nc6000 */
1283 asus_hides_smbus = 1;
1284 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001285 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286 switch (dev->subsystem_device) {
1287 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001288 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001289 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290 asus_hides_smbus = 1;
1291 }
Jean Delvare677cc642007-11-21 18:29:06 +01001292 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1293 switch (dev->subsystem_device) {
1294 case 0x12bf: /* HP xw4100 */
1295 asus_hides_smbus = 1;
1296 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1298 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1299 switch(dev->subsystem_device) {
1300 case 0xC00C: /* Samsung P35 notebook */
1301 asus_hides_smbus = 1;
1302 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001303 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1304 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1305 switch(dev->subsystem_device) {
1306 case 0x0058: /* Compaq Evo N620c */
1307 asus_hides_smbus = 1;
1308 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001309 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1310 switch(dev->subsystem_device) {
1311 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1312 /* Motherboard doesn't have Host bridge
1313 * subvendor/subdevice IDs, therefore checking
1314 * its on-board VGA controller */
1315 asus_hides_smbus = 1;
1316 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001317 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Jean Delvare10260d92008-06-04 13:53:31 +02001318 switch(dev->subsystem_device) {
1319 case 0x00b8: /* Compaq Evo D510 CMT */
1320 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001321 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001322 /* Motherboard doesn't have Host bridge
1323 * subvendor/subdevice IDs and on-board VGA
1324 * controller is disabled if an AGP card is
1325 * inserted, therefore checking USB UHCI
1326 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001327 asus_hides_smbus = 1;
1328 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001329 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1330 switch (dev->subsystem_device) {
1331 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1332 /* Motherboard doesn't have host bridge
1333 * subvendor/subdevice IDs, therefore checking
1334 * its on-board VGA controller */
1335 asus_hides_smbus = 1;
1336 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 }
1338}
Andrew Morton652c5382007-11-21 15:07:13 -08001339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349
Andrew Morton652c5382007-11-21 15:07:13 -08001350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001353
Alan Cox1597cac2006-12-04 15:14:45 -08001354static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355{
1356 u16 val;
1357
1358 if (likely(!asus_hides_smbus))
1359 return;
1360
1361 pci_read_config_word(dev, 0xF2, &val);
1362 if (val & 0x8) {
1363 pci_write_config_word(dev, 0xF2, val & (~0x8));
1364 pci_read_config_word(dev, 0xF2, &val);
1365 if (val & 0x8)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001366 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001368 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369 }
1370}
Andrew Morton652c5382007-11-21 15:07:13 -08001371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1377DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001378DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1379DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1380DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1381DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1382DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1383DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1384DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001386/* It appears we just have one such device. If not, we have a warning */
1387static void __iomem *asus_rcba_base;
1388static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001389{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001390 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001391
1392 if (likely(!asus_hides_smbus))
1393 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001394 WARN_ON(asus_rcba_base);
1395
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001396 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001397 /* use bits 31:14, 16 kB aligned */
1398 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1399 if (asus_rcba_base == NULL)
1400 return;
1401}
1402
1403static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1404{
1405 u32 val;
1406
1407 if (likely(!asus_hides_smbus || !asus_rcba_base))
1408 return;
1409 /* read the Function Disable register, dword mode only */
1410 val = readl(asus_rcba_base + 0x3418);
1411 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1412}
1413
1414static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1415{
1416 if (likely(!asus_hides_smbus || !asus_rcba_base))
1417 return;
1418 iounmap(asus_rcba_base);
1419 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001420 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001421}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001422
1423static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1424{
1425 asus_hides_smbus_lpc_ich6_suspend(dev);
1426 asus_hides_smbus_lpc_ich6_resume_early(dev);
1427 asus_hides_smbus_lpc_ich6_resume(dev);
1428}
Andrew Morton652c5382007-11-21 15:07:13 -08001429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001430DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1431DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1432DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001433
Linus Torvalds1da177e2005-04-16 15:20:36 -07001434/*
1435 * SiS 96x south bridge: BIOS typically hides SMBus device...
1436 */
Alan Cox1597cac2006-12-04 15:14:45 -08001437static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438{
1439 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001441 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001442 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001443 pci_write_config_byte(dev, 0x77, val & ~0x10);
1444 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445}
Andrew Morton652c5382007-11-21 15:07:13 -08001446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001450DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1451DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1452DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1453DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455/*
1456 * ... This is further complicated by the fact that some SiS96x south
1457 * bridges pretend to be 85C503/5513 instead. In that case see if we
1458 * spotted a compatible north bridge to make sure.
1459 * (pci_find_device doesn't work yet)
1460 *
1461 * We can also enable the sis96x bit in the discovery register..
1462 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463#define SIS_DETECT_REGISTER 0x40
1464
Alan Cox1597cac2006-12-04 15:14:45 -08001465static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466{
1467 u8 reg;
1468 u16 devid;
1469
1470 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1471 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1472 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1473 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1474 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1475 return;
1476 }
1477
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001479 * Ok, it now shows up as a 96x.. run the 96x quirk by
1480 * hand in case it has already been processed.
1481 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 */
1483 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001484 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001485}
Andrew Morton652c5382007-11-21 15:07:13 -08001486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001487DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001490/*
1491 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1492 * and MC97 modem controller are disabled when a second PCI soundcard is
1493 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1494 * -- bjd
1495 */
Alan Cox1597cac2006-12-04 15:14:45 -08001496static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001497{
1498 u8 val;
1499 int asus_hides_ac97 = 0;
1500
1501 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1502 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1503 asus_hides_ac97 = 1;
1504 }
1505
1506 if (!asus_hides_ac97)
1507 return;
1508
1509 pci_read_config_byte(dev, 0x50, &val);
1510 if (val & 0xc0) {
1511 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1512 pci_read_config_byte(dev, 0x50, &val);
1513 if (val & 0xc0)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001514 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001515 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001516 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001517 }
1518}
Andrew Morton652c5382007-11-21 15:07:13 -08001519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001520DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001521
Tejun Heo77967052006-08-19 03:54:39 +09001522#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001523
1524/*
1525 * If we are using libata we can drive this chip properly but must
1526 * do this early on to make the additional device appear during
1527 * the PCI scanning.
1528 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001529static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001530{
Tejun Heoe34bb372007-02-26 20:24:03 +09001531 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001532 u8 hdr;
1533
1534 /* Only poke fn 0 */
1535 if (PCI_FUNC(pdev->devfn))
1536 return;
1537
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001538 pci_read_config_dword(pdev, 0x40, &conf1);
1539 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001540
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001541 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1542 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001543
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001544 switch (pdev->device) {
Tejun Heo4daedcf2010-06-03 11:57:04 +02001545 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1546 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001547 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001548 /* The controller should be in single function ahci mode */
1549 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1550 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001551
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001552 case PCI_DEVICE_ID_JMICRON_JMB365:
1553 case PCI_DEVICE_ID_JMICRON_JMB366:
1554 /* Redirect IDE second PATA port to the right spot */
1555 conf5 |= (1 << 24);
1556 /* Fall through */
1557 case PCI_DEVICE_ID_JMICRON_JMB361:
1558 case PCI_DEVICE_ID_JMICRON_JMB363:
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001559 case PCI_DEVICE_ID_JMICRON_JMB369:
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001560 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1561 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001562 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001563 break;
1564
1565 case PCI_DEVICE_ID_JMICRON_JMB368:
1566 /* The controller should be in single function IDE mode */
1567 conf1 |= 0x00C00000; /* Set 22, 23 */
1568 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001569 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001570
1571 pci_write_config_dword(pdev, 0x40, conf1);
1572 pci_write_config_dword(pdev, 0x80, conf5);
1573
1574 /* Update pdev accordingly */
1575 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1576 pdev->hdr_type = hdr & 0x7f;
1577 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001578
1579 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1580 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001581}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1589DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001590DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001593DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001594DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001595DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001596DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1597DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1598DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001599DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001600
1601#endif
1602
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603#ifdef CONFIG_X86_IO_APIC
1604static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1605{
1606 int i;
1607
1608 if ((pdev->class >> 8) != 0xff00)
1609 return;
1610
1611 /* the first BAR is the location of the IO APIC...we must
1612 * not touch this (and it's already covered by the fixmap), so
1613 * forcibly insert it into the resource tree */
1614 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1615 insert_resource(&iomem_resource, &pdev->resource[0]);
1616
1617 /* The next five BARs all seem to be rubbish, so just clean
1618 * them out */
1619 for (i=1; i < 6; i++) {
1620 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1621 }
1622
1623}
Andrew Morton652c5382007-11-21 15:07:13 -08001624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625#endif
1626
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1628{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001629 pci_msi_off(pdev);
1630 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631}
Andrew Morton652c5382007-11-21 15:07:13 -08001632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001635
Kristen Accardi4602b882005-08-16 15:15:58 -07001636
1637/*
1638 * It's possible for the MSI to get corrupted if shpc and acpi
1639 * are used together on certain PXH-based systems.
1640 */
1641static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1642{
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001643 pci_msi_off(dev);
Kristen Accardi4602b882005-08-16 15:15:58 -07001644 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001645 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001646}
1647DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1648DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1649DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1650DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1652
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001653/*
1654 * Some Intel PCI Express chipsets have trouble with downstream
1655 * device power management.
1656 */
1657static void quirk_intel_pcie_pm(struct pci_dev * dev)
1658{
1659 pci_pm_d3_delay = 120;
1660 dev->no_d1d2 = 1;
1661}
1662
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001684
Stefan Assmann426b3b82008-06-11 16:35:16 +02001685#ifdef CONFIG_X86_IO_APIC
1686/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001687 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1688 * remap the original interrupt in the linux kernel to the boot interrupt, so
1689 * that a PCI device's interrupt handler is installed on the boot interrupt
1690 * line instead.
1691 */
1692static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1693{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001694 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001695 return;
1696
1697 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001698 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1699 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001700}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1711DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1712DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1713DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1714DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1716DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001717
1718/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001719 * On some chipsets we can disable the generation of legacy INTx boot
1720 * interrupts.
1721 */
1722
1723/*
1724 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1725 * 300641-004US, section 5.7.3.
1726 */
1727#define INTEL_6300_IOAPIC_ABAR 0x40
1728#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1729
1730static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1731{
1732 u16 pci_config_word;
1733
1734 if (noioapicquirk)
1735 return;
1736
1737 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1738 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1739 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1740
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001741 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1742 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001743}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001744DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1745DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001746
1747/*
1748 * disable boot interrupts on HT-1000
1749 */
1750#define BC_HT1000_FEATURE_REG 0x64
1751#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1752#define BC_HT1000_MAP_IDX 0xC00
1753#define BC_HT1000_MAP_DATA 0xC01
1754
1755static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1756{
1757 u32 pci_config_dword;
1758 u8 irq;
1759
1760 if (noioapicquirk)
1761 return;
1762
1763 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1764 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1765 BC_HT1000_PIC_REGS_ENABLE);
1766
1767 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1768 outb(irq, BC_HT1000_MAP_IDX);
1769 outb(0x00, BC_HT1000_MAP_DATA);
1770 }
1771
1772 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1773
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001774 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1775 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001776}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001777DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1778DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001779
1780/*
1781 * disable boot interrupts on AMD and ATI chipsets
1782 */
1783/*
1784 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1785 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1786 * (due to an erratum).
1787 */
1788#define AMD_813X_MISC 0x40
1789#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001790#define AMD_813X_REV_B1 0x12
Stefan Assmannbbe19442009-02-26 10:46:48 -08001791#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001792
1793static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1794{
1795 u32 pci_config_dword;
1796
1797 if (noioapicquirk)
1798 return;
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001799 if ((dev->revision == AMD_813X_REV_B1) ||
1800 (dev->revision == AMD_813X_REV_B2))
Stefan Assmannbbe19442009-02-26 10:46:48 -08001801 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001802
1803 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1804 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1805 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1806
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001807 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1808 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001809}
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001810DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1811DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1813DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001814
1815#define AMD_8111_PCI_IRQ_ROUTING 0x56
1816
1817static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1818{
1819 u16 pci_config_word;
1820
1821 if (noioapicquirk)
1822 return;
1823
1824 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1825 if (!pci_config_word) {
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001826 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1827 "already disabled\n", dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001828 return;
1829 }
1830 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001831 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1832 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001833}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1835DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001836#endif /* CONFIG_X86_IO_APIC */
1837
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001838/*
1839 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1840 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1841 * Re-allocate the region if needed...
1842 */
1843static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1844{
1845 struct resource *r = &dev->resource[0];
1846
1847 if (r->start & 0x8) {
1848 r->start = 0;
1849 r->end = 0xf;
1850 }
1851}
1852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1853 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1854 quirk_tc86c001_ide);
1855
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856static void __devinit quirk_netmos(struct pci_dev *dev)
1857{
1858 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1859 unsigned int num_serial = dev->subsystem_device & 0xf;
1860
1861 /*
1862 * These Netmos parts are multiport serial devices with optional
1863 * parallel ports. Even when parallel ports are present, they
1864 * are identified as class SERIAL, which means the serial driver
1865 * will claim them. To prevent this, mark them as class OTHER.
1866 * These combo devices should be claimed by parport_serial.
1867 *
1868 * The subdevice ID is of the form 0x00PS, where <P> is the number
1869 * of parallel ports and <S> is the number of serial ports.
1870 */
1871 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001872 case PCI_DEVICE_ID_NETMOS_9835:
1873 /* Well, this rule doesn't hold for the following 9835 device */
1874 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1875 dev->subsystem_device == 0x0299)
1876 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877 case PCI_DEVICE_ID_NETMOS_9735:
1878 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001879 case PCI_DEVICE_ID_NETMOS_9845:
1880 case PCI_DEVICE_ID_NETMOS_9855:
1881 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1882 num_parallel) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001883 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884 "%u serial); changing class SERIAL to OTHER "
1885 "(use parport_serial)\n",
1886 dev->device, num_parallel, num_serial);
1887 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1888 (dev->class & 0xff);
1889 }
1890 }
1891}
1892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1893
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001894static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1895{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001896 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001897 u8 __iomem *csr;
1898 u8 cmd_hi;
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001899 int pm;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001900
1901 switch (dev->device) {
1902 /* PCI IDs taken from drivers/net/e100.c */
1903 case 0x1029:
1904 case 0x1030 ... 0x1034:
1905 case 0x1038 ... 0x103E:
1906 case 0x1050 ... 0x1057:
1907 case 0x1059:
1908 case 0x1064 ... 0x106B:
1909 case 0x1091 ... 0x1095:
1910 case 0x1209:
1911 case 0x1229:
1912 case 0x2449:
1913 case 0x2459:
1914 case 0x245D:
1915 case 0x27DC:
1916 break;
1917 default:
1918 return;
1919 }
1920
1921 /*
1922 * Some firmware hands off the e100 with interrupts enabled,
1923 * which can cause a flood of interrupts if packets are
1924 * received before the driver attaches to the device. So
1925 * disable all e100 interrupts here. The driver will
1926 * re-enable them when it's ready.
1927 */
1928 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001929
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001930 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001931 return;
1932
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001933 /*
1934 * Check that the device is in the D0 power state. If it's not,
1935 * there is no point to look any further.
1936 */
1937 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1938 if (pm) {
1939 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1940 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1941 return;
1942 }
1943
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001944 /* Convert from PCI bus to resource space. */
1945 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001946 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001947 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001948 return;
1949 }
1950
1951 cmd_hi = readb(csr + 3);
1952 if (cmd_hi == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001953 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1954 "disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001955 writeb(1, csr + 3);
1956 }
1957
1958 iounmap(csr);
1959}
Marian Balakowicz4e68fc92007-07-03 11:03:18 +02001960DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001961
Alexander Duyck649426e2009-03-05 13:57:28 -05001962/*
1963 * The 82575 and 82598 may experience data corruption issues when transitioning
1964 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1965 */
1966static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1967{
1968 dev_info(&dev->dev, "Disabling L0s\n");
1969 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1970}
1971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1973DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1979DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1980DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1981DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1982DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1983DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1984DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1985
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001986static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1987{
1988 /* rev 1 ncr53c810 chips don't set the class at all which means
1989 * they don't get their resources remapped. Fix that here.
1990 */
1991
1992 if (dev->class == PCI_CLASS_NOT_DEFINED) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001993 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001994 dev->class = PCI_CLASS_STORAGE_SCSI;
1995 }
1996}
1997DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1998
Daniel Yeisley9d265122005-12-05 07:06:43 -05001999/* Enable 1k I/O space granularity on the Intel P64H2 */
2000static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
2001{
2002 u16 en1k;
2003 u8 io_base_lo, io_limit_lo;
2004 unsigned long base, limit;
2005 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2006
2007 pci_read_config_word(dev, 0x40, &en1k);
2008
2009 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002010 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Daniel Yeisley9d265122005-12-05 07:06:43 -05002011
2012 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2013 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2014 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2015 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2016
2017 if (base <= limit) {
2018 res->start = base;
2019 res->end = limit + 0x3ff;
2020 }
2021 }
2022}
2023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2024
Daniel Yeisley15a260d2006-12-21 14:34:57 -05002025/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2026 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2027 * in drivers/pci/setup-bus.c
2028 */
2029static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2030{
2031 u16 en1k, iobl_adr, iobl_adr_1k;
2032 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2033
2034 pci_read_config_word(dev, 0x40, &en1k);
2035
2036 if (en1k & 0x200) {
2037 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2038
2039 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2040
2041 if (iobl_adr != iobl_adr_1k) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002042 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
Daniel Yeisley15a260d2006-12-21 14:34:57 -05002043 iobl_adr,iobl_adr_1k);
2044 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2045 }
2046 }
2047}
2048DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2049
Brice Goglincf34a8e2006-06-13 14:35:42 -04002050/* Under some circumstances, AER is not linked with extended capabilities.
2051 * Force it to be linked by setting the corresponding control bit in the
2052 * config space.
2053 */
Alan Cox1597cac2006-12-04 15:14:45 -08002054static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04002055{
2056 uint8_t b;
2057 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2058 if (!(b & 0x20)) {
2059 pci_write_config_byte(dev, 0xf41, b | 0x20);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002060 dev_info(&dev->dev,
2061 "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04002062 }
2063 }
2064}
2065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2066 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02002067DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08002068 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04002069
Tim Yamin53a9bf42007-11-01 23:14:54 +00002070static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2071{
2072 /*
2073 * Disable PCI Bus Parking and PCI Master read caching on CX700
2074 * which causes unspecified timing errors with a VT6212L on the PCI
Tim Yaminca846392010-03-19 14:22:58 -07002075 * bus leading to USB2.0 packet loss.
2076 *
2077 * This quirk is only enabled if a second (on the external PCI bus)
2078 * VT6212L is found -- the CX700 core itself also contains a USB
2079 * host controller with the same PCI ID as the VT6212L.
Tim Yamin53a9bf42007-11-01 23:14:54 +00002080 */
2081
Tim Yaminca846392010-03-19 14:22:58 -07002082 /* Count VT6212L instances */
2083 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2084 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002085 uint8_t b;
Tim Yaminca846392010-03-19 14:22:58 -07002086
2087 /* p should contain the first (internal) VT6212L -- see if we have
2088 an external one by searching again */
2089 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2090 if (!p)
2091 return;
2092 pci_dev_put(p);
2093
Tim Yamin53a9bf42007-11-01 23:14:54 +00002094 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2095 if (b & 0x40) {
2096 /* Turn off PCI Bus Parking */
2097 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2098
Tim Yaminbc043272008-03-30 20:58:59 +01002099 dev_info(&dev->dev,
2100 "Disabling VIA CX700 PCI parking\n");
2101 }
2102 }
2103
2104 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2105 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00002106 /* Turn off PCI Master read caching */
2107 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01002108
2109 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002110 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01002111
2112 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002113 pci_write_config_byte(dev, 0x77, 0x0);
2114
Bjorn Helgaasd6505a52008-02-29 16:12:18 -07002115 dev_info(&dev->dev,
Tim Yaminbc043272008-03-30 20:58:59 +01002116 "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00002117 }
2118 }
2119}
Tim Yaminca846392010-03-19 14:22:58 -07002120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002121
Benjamin Li99cb233d2008-07-02 10:59:04 -07002122/*
2123 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2124 * VPD end tag will hang the device. This problem was initially
2125 * observed when a vpd entry was created in sysfs
2126 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2127 * will dump 32k of data. Reading a full 32k will cause an access
2128 * beyond the VPD end tag causing the device to hang. Once the device
2129 * is hung, the bnx2 driver will not be able to reset the device.
2130 * We believe that it is legal to read beyond the end tag and
2131 * therefore the solution is to limit the read/write length.
2132 */
2133static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2134{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002135 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002136 * Only disable the VPD capability for 5706, 5706S, 5708,
2137 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002138 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002139 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002140 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002141 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002142 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002143 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2144 (dev->revision & 0xf0) == 0x0)) {
2145 if (dev->vpd)
2146 dev->vpd->len = 0x80;
2147 }
2148}
2149
Yu Zhaobffadff2008-10-28 14:44:11 +08002150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2151 PCI_DEVICE_ID_NX2_5706,
2152 quirk_brcm_570x_limit_vpd);
2153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2154 PCI_DEVICE_ID_NX2_5706S,
2155 quirk_brcm_570x_limit_vpd);
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2157 PCI_DEVICE_ID_NX2_5708,
2158 quirk_brcm_570x_limit_vpd);
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2160 PCI_DEVICE_ID_NX2_5708S,
2161 quirk_brcm_570x_limit_vpd);
2162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2163 PCI_DEVICE_ID_NX2_5709,
2164 quirk_brcm_570x_limit_vpd);
2165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2166 PCI_DEVICE_ID_NX2_5709S,
2167 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002168
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002169/* Originally in EDAC sources for i82875P:
2170 * Intel tells BIOS developers to hide device 6 which
2171 * configures the overflow device access containing
2172 * the DRBs - this is where we expose device 6.
2173 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2174 */
2175static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2176{
2177 u8 reg;
2178
2179 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2180 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2181 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2182 }
2183}
2184
2185DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2186 quirk_unhide_mch_dev6);
2187DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2188 quirk_unhide_mch_dev6);
2189
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002190#ifdef CONFIG_TILE
2191/*
2192 * The Tilera TILEmpower platform needs to set the link speed
2193 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2194 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2195 * capability register of the PEX8624 PCIe switch. The switch
2196 * supports link speed auto negotiation, but falsely sets
2197 * the link speed to 5GT/s.
2198 */
2199static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2200{
2201 if (tile_plx_gen1) {
2202 pci_write_config_dword(dev, 0x98, 0x1);
2203 mdelay(50);
2204 }
2205}
2206DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2207#endif /* CONFIG_TILE */
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002208
Brice Goglin3f79e102006-08-31 01:54:56 -04002209#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002210/* Some chipsets do not support MSI. We cannot easily rely on setting
2211 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2212 * some other busses controlled by the chipset even if Linux is not
2213 * aware of it. Instead of setting the flag on all busses in the
2214 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002215 */
Tejun Heoebdf7d32007-05-31 00:40:48 -07002216static void __init quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002217{
Michael Ellerman88187df2007-01-25 19:34:07 +11002218 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002219 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002220}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Tejun Heo549e1562010-05-23 10:22:55 +02002227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002228
2229/* Disable MSI on chipsets that are known to not support it */
2230static void __devinit quirk_disable_msi(struct pci_dev *dev)
2231{
2232 if (dev->subordinate) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002233 dev_warn(&dev->dev, "MSI quirk detected; "
2234 "subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002235 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2236 }
2237}
2238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Matthew Wilcox134b3452010-03-24 07:11:01 -06002239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
Alex Deucher9313ff42010-05-18 10:42:53 -04002240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002241
Clemens Ladischaff61362010-05-26 12:21:10 +02002242/*
2243 * The APC bridge device in AMD 780 family northbridges has some random
2244 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2245 * we use the possible vendor/device IDs of the host bridge for the
2246 * declared quirk, and search for the APC bridge by slot number.
2247 */
2248static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2249{
2250 struct pci_dev *apc_bridge;
2251
2252 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2253 if (apc_bridge) {
2254 if (apc_bridge->device == 0x9602)
2255 quirk_disable_msi(apc_bridge);
2256 pci_dev_put(apc_bridge);
2257 }
2258}
2259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2261
Brice Goglin6397c752006-08-31 01:55:32 -04002262/* Go through the list of Hypertransport capabilities and
2263 * return 1 if a HT MSI capability is found and enabled */
2264static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2265{
Michael Ellerman7a380502006-11-22 18:26:21 +11002266 int pos, ttl = 48;
2267
2268 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2269 while (pos && ttl--) {
2270 u8 flags;
2271
2272 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2273 &flags) == 0)
2274 {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002275 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002276 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002277 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002278 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002279 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002280
2281 pos = pci_find_next_ht_capability(dev, pos,
2282 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002283 }
2284 return 0;
2285}
2286
2287/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2288static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2289{
2290 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002291 dev_warn(&dev->dev, "MSI quirk detected; "
2292 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002293 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2294 }
2295}
2296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2297 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002298
Brice Goglin6397c752006-08-31 01:55:32 -04002299/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2300 * MSI are supported if the MSI capability set in any of these mappings.
2301 */
2302static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2303{
2304 struct pci_dev *pdev;
2305
2306 if (!dev->subordinate)
2307 return;
2308
2309 /* check HT MSI cap on this chipset and the root one.
2310 * a single one having MSI is enough to be sure that MSI are supported.
2311 */
Alan Cox11f242f2006-10-10 14:39:00 -07002312 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002313 if (!pdev)
2314 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002315 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002316 dev_warn(&dev->dev, "MSI quirk detected; "
2317 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002318 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2319 }
Alan Cox11f242f2006-10-10 14:39:00 -07002320 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002321}
2322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2323 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002324
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002325/* Force enable MSI mapping capability on HT bridges */
2326static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002327{
2328 int pos, ttl = 48;
2329
2330 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2331 while (pos && ttl--) {
2332 u8 flags;
2333
2334 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2335 &flags) == 0) {
2336 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2337
2338 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2339 flags | HT_MSI_FLAGS_ENABLE);
2340 }
2341 pos = pci_find_next_ht_capability(dev, pos,
2342 HT_CAPTYPE_MSI_MAPPING);
2343 }
2344}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2346 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2347 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002348
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2350 ht_enable_msi_mapping);
2351
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002352/* The P5N32-SLI motherboards from Asus have a problem with msi
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002353 * for the MCP55 NIC. It is not yet determined whether the msi problem
2354 * also affects other devices. As for now, turn off msi for this device.
2355 */
2356static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2357{
Jean Delvare9251bac2011-05-15 18:13:46 +02002358 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2359
2360 if (board_name &&
2361 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2362 strstr(board_name, "P5N32-E SLI"))) {
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002363 dev_info(&dev->dev,
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002364 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002365 dev->no_msi = 1;
2366 }
2367}
2368DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2369 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2370 nvenet_msi_disable);
2371
Neil Horman66db60e2010-09-21 13:54:39 -04002372/*
2373 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2374 * config register. This register controls the routing of legacy interrupts
2375 * from devices that route through the MCP55. If this register is misprogramed
2376 * interrupts are only sent to the bsp, unlike conventional systems where the
2377 * irq is broadxast to all online cpus. Not having this register set
2378 * properly prevents kdump from booting up properly, so lets make sure that
2379 * we have it set correctly.
2380 * Note this is an undocumented register.
2381 */
2382static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2383{
2384 u32 cfg;
2385
Neil Horman49c2fa082010-12-08 09:47:48 -05002386 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2387 return;
2388
Neil Horman66db60e2010-09-21 13:54:39 -04002389 pci_read_config_dword(dev, 0x74, &cfg);
2390
2391 if (cfg & ((1 << 2) | (1 << 15))) {
2392 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2393 cfg &= ~((1 << 2) | (1 << 15));
2394 pci_write_config_dword(dev, 0x74, cfg);
2395 }
2396}
2397
2398DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2399 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2400 nvbridge_check_legacy_irq_routing);
2401
2402DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2403 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2404 nvbridge_check_legacy_irq_routing);
2405
Yinghai Lude745302009-03-20 19:29:41 -07002406static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2407{
2408 int pos, ttl = 48;
2409 int found = 0;
2410
2411 /* check if there is HT MSI cap or enabled on this device */
2412 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2413 while (pos && ttl--) {
2414 u8 flags;
2415
2416 if (found < 1)
2417 found = 1;
2418 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2419 &flags) == 0) {
2420 if (flags & HT_MSI_FLAGS_ENABLE) {
2421 if (found < 2) {
2422 found = 2;
2423 break;
2424 }
2425 }
2426 }
2427 pos = pci_find_next_ht_capability(dev, pos,
2428 HT_CAPTYPE_MSI_MAPPING);
2429 }
2430
2431 return found;
2432}
2433
2434static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2435{
2436 struct pci_dev *dev;
2437 int pos;
2438 int i, dev_no;
2439 int found = 0;
2440
2441 dev_no = host_bridge->devfn >> 3;
2442 for (i = dev_no + 1; i < 0x20; i++) {
2443 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2444 if (!dev)
2445 continue;
2446
2447 /* found next host bridge ?*/
2448 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2449 if (pos != 0) {
2450 pci_dev_put(dev);
2451 break;
2452 }
2453
2454 if (ht_check_msi_mapping(dev)) {
2455 found = 1;
2456 pci_dev_put(dev);
2457 break;
2458 }
2459 pci_dev_put(dev);
2460 }
2461
2462 return found;
2463}
2464
Yinghai Lueeafda72009-03-29 12:30:05 -07002465#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2466#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2467
2468static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2469{
2470 int pos, ctrl_off;
2471 int end = 0;
2472 u16 flags, ctrl;
2473
2474 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2475
2476 if (!pos)
2477 goto out;
2478
2479 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2480
2481 ctrl_off = ((flags >> 10) & 1) ?
2482 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2483 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2484
2485 if (ctrl & (1 << 6))
2486 end = 1;
2487
2488out:
2489 return end;
2490}
2491
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002492static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2493{
2494 struct pci_dev *host_bridge;
2495 int pos;
2496 int i, dev_no;
2497 int found = 0;
2498
2499 dev_no = dev->devfn >> 3;
2500 for (i = dev_no; i >= 0; i--) {
2501 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2502 if (!host_bridge)
2503 continue;
2504
2505 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2506 if (pos != 0) {
2507 found = 1;
2508 break;
2509 }
2510 pci_dev_put(host_bridge);
2511 }
2512
2513 if (!found)
2514 return;
2515
Yinghai Lueeafda72009-03-29 12:30:05 -07002516 /* don't enable end_device/host_bridge with leaf directly here */
2517 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2518 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002519 goto out;
2520
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002521 /* root did that ! */
2522 if (msi_ht_cap_enabled(host_bridge))
2523 goto out;
2524
2525 ht_enable_msi_mapping(dev);
2526
2527out:
2528 pci_dev_put(host_bridge);
2529}
2530
2531static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2532{
2533 int pos, ttl = 48;
2534
2535 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2536 while (pos && ttl--) {
2537 u8 flags;
2538
2539 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2540 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002541 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002542
2543 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2544 flags & ~HT_MSI_FLAGS_ENABLE);
2545 }
2546 pos = pci_find_next_ht_capability(dev, pos,
2547 HT_CAPTYPE_MSI_MAPPING);
2548 }
2549}
2550
Yinghai Lude745302009-03-20 19:29:41 -07002551static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002552{
2553 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002554 int pos;
2555 int found;
2556
Rafael J. Wysocki3d2a5312010-07-23 22:19:55 +02002557 if (!pci_msi_enabled())
2558 return;
2559
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002560 /* check if there is HT MSI cap or enabled on this device */
2561 found = ht_check_msi_mapping(dev);
2562
2563 /* no HT MSI CAP */
2564 if (found == 0)
2565 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002566
2567 /*
2568 * HT MSI mapping should be disabled on devices that are below
2569 * a non-Hypertransport host bridge. Locate the host bridge...
2570 */
2571 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2572 if (host_bridge == NULL) {
2573 dev_warn(&dev->dev,
2574 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2575 return;
2576 }
2577
2578 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2579 if (pos != 0) {
2580 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002581 if (found == 1) {
2582 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002583 if (all)
2584 ht_enable_msi_mapping(dev);
2585 else
2586 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002587 }
Peer Chen9dc625e2008-02-04 23:50:13 -08002588 return;
2589 }
2590
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002591 /* HT MSI is not enabled */
2592 if (found == 1)
2593 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002594
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002595 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2596 ht_disable_msi_mapping(dev);
Peer Chen9dc625e2008-02-04 23:50:13 -08002597}
Yinghai Lude745302009-03-20 19:29:41 -07002598
2599static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2600{
2601 return __nv_msi_ht_cap_quirk(dev, 1);
2602}
2603
2604static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2605{
2606 return __nv_msi_ht_cap_quirk(dev, 0);
2607}
2608
2609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002610DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002611
2612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002613DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002614
David Millerba698ad2007-10-25 01:16:30 -07002615static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2616{
2617 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2618}
Shane Huang4600c9d2008-01-25 15:46:24 +09002619static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2620{
2621 struct pci_dev *p;
2622
2623 /* SB700 MSI issue will be fixed at HW level from revision A21,
2624 * we need check PCI REVISION ID of SMBus controller to get SB700
2625 * revision.
2626 */
2627 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2628 NULL);
2629 if (!p)
2630 return;
2631
2632 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2633 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2634 pci_dev_put(p);
2635}
David Millerba698ad2007-10-25 01:16:30 -07002636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2637 PCI_DEVICE_ID_TIGON3_5780,
2638 quirk_msi_intx_disable_bug);
2639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2640 PCI_DEVICE_ID_TIGON3_5780S,
2641 quirk_msi_intx_disable_bug);
2642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2643 PCI_DEVICE_ID_TIGON3_5714,
2644 quirk_msi_intx_disable_bug);
2645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2646 PCI_DEVICE_ID_TIGON3_5714S,
2647 quirk_msi_intx_disable_bug);
2648DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2649 PCI_DEVICE_ID_TIGON3_5715,
2650 quirk_msi_intx_disable_bug);
2651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2652 PCI_DEVICE_ID_TIGON3_5715S,
2653 quirk_msi_intx_disable_bug);
2654
David Millerbc38b412007-10-25 01:16:52 -07002655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002656 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002658 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002660 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002662 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002664 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002665
2666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2667 quirk_msi_intx_disable_bug);
2668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2669 quirk_msi_intx_disable_bug);
2670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2671 quirk_msi_intx_disable_bug);
2672
Brice Goglin3f79e102006-08-31 01:54:56 -04002673#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002674
Felix Radensky33223402010-03-28 16:02:02 +03002675/* Allow manual resource allocation for PCI hotplug bridges
2676 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2677 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2678 * kernel fails to allocate resources when hotplug device is
2679 * inserted and PCI bus is rescanned.
2680 */
2681static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2682{
2683 dev->is_hotplug_bridge = 1;
2684}
2685
2686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2687
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002688/*
2689 * This is a quirk for the Ricoh MMC controller found as a part of
2690 * some mulifunction chips.
2691
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002692 * This is very similar and based on the ricoh_mmc driver written by
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002693 * Philip Langdale. Thank you for these magic sequences.
2694 *
2695 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2696 * and one or both of cardbus or firewire.
2697 *
2698 * It happens that they implement SD and MMC
2699 * support as separate controllers (and PCI functions). The linux SDHCI
2700 * driver supports MMC cards but the chip detects MMC cards in hardware
2701 * and directs them to the MMC controller - so the SDHCI driver never sees
2702 * them.
2703 *
2704 * To get around this, we must disable the useless MMC controller.
2705 * At that point, the SDHCI controller will start seeing them
2706 * It seems to be the case that the relevant PCI registers to deactivate the
2707 * MMC controller live on PCI function 0, which might be the cardbus controller
2708 * or the firewire controller, depending on the particular chip in question
2709 *
2710 * This has to be done early, because as soon as we disable the MMC controller
2711 * other pci functions shift up one level, e.g. function #2 becomes function
2712 * #1, and this will confuse the pci core.
2713 */
2714
2715#ifdef CONFIG_MMC_RICOH_MMC
2716static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2717{
2718 /* disable via cardbus interface */
2719 u8 write_enable;
2720 u8 write_target;
2721 u8 disable;
2722
2723 /* disable must be done via function #0 */
2724 if (PCI_FUNC(dev->devfn))
2725 return;
2726
2727 pci_read_config_byte(dev, 0xB7, &disable);
2728 if (disable & 0x02)
2729 return;
2730
2731 pci_read_config_byte(dev, 0x8E, &write_enable);
2732 pci_write_config_byte(dev, 0x8E, 0xAA);
2733 pci_read_config_byte(dev, 0x8D, &write_target);
2734 pci_write_config_byte(dev, 0x8D, 0xB7);
2735 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2736 pci_write_config_byte(dev, 0x8E, write_enable);
2737 pci_write_config_byte(dev, 0x8D, write_target);
2738
2739 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2740 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2741}
2742DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2743DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2744
2745static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2746{
2747 /* disable via firewire interface */
2748 u8 write_enable;
2749 u8 disable;
2750
2751 /* disable must be done via function #0 */
2752 if (PCI_FUNC(dev->devfn))
2753 return;
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002754 /*
2755 * RICOH 0xe823 SD/MMC card reader fails to recognize
2756 * certain types of SD/MMC cards. Lowering the SD base
2757 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2758 *
2759 * 0x150 - SD2.0 mode enable for changing base clock
2760 * frequency to 50Mhz
2761 * 0xe1 - Base clock frequency
2762 * 0x32 - 50Mhz new clock frequency
2763 * 0xf9 - Key register for 0x150
2764 * 0xfc - key register for 0xe1
2765 */
2766 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2767 pci_write_config_byte(dev, 0xf9, 0xfc);
2768 pci_write_config_byte(dev, 0x150, 0x10);
2769 pci_write_config_byte(dev, 0xf9, 0x00);
2770 pci_write_config_byte(dev, 0xfc, 0x01);
2771 pci_write_config_byte(dev, 0xe1, 0x32);
2772 pci_write_config_byte(dev, 0xfc, 0x00);
2773
2774 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2775 }
Josh Boyer3e309cd2011-10-05 11:44:50 -04002776
2777 pci_read_config_byte(dev, 0xCB, &disable);
2778
2779 if (disable & 0x02)
2780 return;
2781
2782 pci_read_config_byte(dev, 0xCA, &write_enable);
2783 pci_write_config_byte(dev, 0xCA, 0x57);
2784 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2785 pci_write_config_byte(dev, 0xCA, write_enable);
2786
2787 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2788 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2789
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002790}
2791DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2792DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
Manoj Iyerbe98ca62011-05-26 11:19:05 -05002793DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2794DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002795#endif /*CONFIG_MMC_RICOH_MMC*/
2796
Suresh Siddhad3f13812011-08-23 17:05:25 -07002797#ifdef CONFIG_DMAR_TABLE
Suresh Siddha254e42002010-12-06 12:26:30 -08002798#define VTUNCERRMSK_REG 0x1ac
2799#define VTD_MSK_SPEC_ERRORS (1 << 31)
2800/*
2801 * This is a quirk for masking vt-d spec defined errors to platform error
2802 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2803 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2804 * on the RAS config settings of the platform) when a vt-d fault happens.
2805 * The resulting SMI caused the system to hang.
2806 *
2807 * VT-d spec related errors are already handled by the VT-d OS code, so no
2808 * need to report the same error through other channels.
2809 */
2810static void vtd_mask_spec_errors(struct pci_dev *dev)
2811{
2812 u32 word;
2813
2814 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2815 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2816}
2817DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2818DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2819#endif
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002820
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302821static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2822{
2823 /* TI 816x devices do not have class code set when in PCIe boot mode */
2824 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2825 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2826 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2827 }
2828}
2829DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2830
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002831/* Some PCIe devices do not work reliably with the claimed maximum
2832 * payload size supported.
2833 */
2834static void __devinit fixup_mpss_256(struct pci_dev *dev)
2835{
2836 dev->pcie_mpss = 1; /* 256 bytes */
2837}
2838DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2839 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2841 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2843 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2844
Jon Masond387a8d2011-10-14 14:56:13 -05002845/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2846 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2847 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2848 * until all of the devices are discovered and buses walked, read completion
2849 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2850 * it is possible to hotplug a device with MPS of 256B.
2851 */
2852static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2853{
2854 int err;
2855 u16 rcc;
2856
2857 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2858 return;
2859
2860 /* Intel errata specifies bits to change but does not say what they are.
2861 * Keeping them magical until such time as the registers and values can
2862 * be explained.
2863 */
2864 err = pci_read_config_word(dev, 0x48, &rcc);
2865 if (err) {
2866 dev_err(&dev->dev, "Error attempting to read the read "
2867 "completion coalescing register.\n");
2868 return;
2869 }
2870
2871 if (!(rcc & (1 << 10)))
2872 return;
2873
2874 rcc &= ~(1 << 10);
2875
2876 err = pci_write_config_word(dev, 0x48, rcc);
2877 if (err) {
2878 dev_err(&dev->dev, "Error attempting to write the read "
2879 "completion coalescing register.\n");
2880 return;
2881 }
2882
2883 pr_info_once("Read completion coalescing disabled due to hardware "
2884 "errata relating to 256B MPS.\n");
2885}
2886/* Intel 5000 series memory controllers and ports 2-7 */
2887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2901/* Intel 5100 series memory controllers and ports 2-7 */
2902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2913
Arjan van de Ven32098742012-01-30 20:52:07 -08002914
2915static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev)
2916{
2917 ktime_t calltime, delta, rettime;
2918 unsigned long long duration;
2919
2920 printk(KERN_DEBUG "calling %pF @ %i\n", fn, task_pid_nr(current));
2921 calltime = ktime_get();
2922 fn(dev);
2923 rettime = ktime_get();
2924 delta = ktime_sub(rettime, calltime);
2925 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2926 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs\n", fn,
2927 duration);
2928}
2929
Thomas Jaroschf67fd552011-12-07 22:08:11 +01002930/*
2931 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2932 * even though no one is handling them (f.e. i915 driver is never loaded).
2933 * Additionally the interrupt destination is not set up properly
2934 * and the interrupt ends up -somewhere-.
2935 *
2936 * These spurious interrupts are "sticky" and the kernel disables
2937 * the (shared) interrupt line after 100.000+ generated interrupts.
2938 *
2939 * Fix it by disabling the still enabled interrupts.
2940 * This resolves crashes often seen on monitor unplug.
2941 */
2942#define I915_DEIER_REG 0x4400c
2943static void __devinit disable_igfx_irq(struct pci_dev *dev)
2944{
2945 void __iomem *regs = pci_iomap(dev, 0, 0);
2946 if (regs == NULL) {
2947 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2948 return;
2949 }
2950
2951 /* Check if any interrupt line is still enabled */
2952 if (readl(regs + I915_DEIER_REG) != 0) {
2953 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2954 "disabling\n");
2955
2956 writel(0, regs + I915_DEIER_REG);
2957 }
2958
2959 pci_iounmap(dev, regs);
2960}
2961DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2962DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2963
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002964static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2965 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002966{
Yinghai Luf4ca5c62012-02-23 23:46:49 -08002967 for (; f < end; f++)
2968 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2969 f->class == (u32) PCI_ANY_ID) &&
2970 (f->vendor == dev->vendor ||
2971 f->vendor == (u16) PCI_ANY_ID) &&
2972 (f->device == dev->device ||
2973 f->device == (u16) PCI_ANY_ID)) {
Yinghai Luc9bbb4a2008-09-24 19:04:33 -07002974 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
Arjan van de Ven32098742012-01-30 20:52:07 -08002975 if (initcall_debug)
2976 do_one_fixup_debug(f->hook, dev);
2977 else
2978 f->hook(dev);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002979 }
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002980}
2981
2982extern struct pci_fixup __start_pci_fixups_early[];
2983extern struct pci_fixup __end_pci_fixups_early[];
2984extern struct pci_fixup __start_pci_fixups_header[];
2985extern struct pci_fixup __end_pci_fixups_header[];
2986extern struct pci_fixup __start_pci_fixups_final[];
2987extern struct pci_fixup __end_pci_fixups_final[];
2988extern struct pci_fixup __start_pci_fixups_enable[];
2989extern struct pci_fixup __end_pci_fixups_enable[];
2990extern struct pci_fixup __start_pci_fixups_resume[];
2991extern struct pci_fixup __end_pci_fixups_resume[];
2992extern struct pci_fixup __start_pci_fixups_resume_early[];
2993extern struct pci_fixup __end_pci_fixups_resume_early[];
2994extern struct pci_fixup __start_pci_fixups_suspend[];
2995extern struct pci_fixup __end_pci_fixups_suspend[];
2996
2997
2998void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2999{
3000 struct pci_fixup *start, *end;
3001
3002 switch(pass) {
3003 case pci_fixup_early:
3004 start = __start_pci_fixups_early;
3005 end = __end_pci_fixups_early;
3006 break;
3007
3008 case pci_fixup_header:
3009 start = __start_pci_fixups_header;
3010 end = __end_pci_fixups_header;
3011 break;
3012
3013 case pci_fixup_final:
3014 start = __start_pci_fixups_final;
3015 end = __end_pci_fixups_final;
3016 break;
3017
3018 case pci_fixup_enable:
3019 start = __start_pci_fixups_enable;
3020 end = __end_pci_fixups_enable;
3021 break;
3022
3023 case pci_fixup_resume:
3024 start = __start_pci_fixups_resume;
3025 end = __end_pci_fixups_resume;
3026 break;
3027
3028 case pci_fixup_resume_early:
3029 start = __start_pci_fixups_resume_early;
3030 end = __end_pci_fixups_resume_early;
3031 break;
3032
3033 case pci_fixup_suspend:
3034 start = __start_pci_fixups_suspend;
3035 end = __end_pci_fixups_suspend;
3036 break;
3037
3038 default:
3039 /* stupid compiler warning, you would think with an enum... */
3040 return;
3041 }
3042 pci_do_fixups(dev, start, end);
3043}
Rafael J. Wysocki93177a72010-01-02 22:57:24 +01003044EXPORT_SYMBOL(pci_fixup_device);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003045
David Woodhouse00010262009-10-12 12:50:34 +01003046static int __init pci_apply_final_quirks(void)
David Woodhouse8d86fb22009-10-12 12:48:43 +01003047{
3048 struct pci_dev *dev = NULL;
Jesse Barnesac1aa472009-10-26 13:20:44 -07003049 u8 cls = 0;
3050 u8 tmp;
3051
3052 if (pci_cache_line_size)
3053 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3054 pci_cache_line_size << 2);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003055
Kulikov Vasiliy4e344b12010-07-03 20:04:39 +04003056 for_each_pci_dev(dev) {
David Woodhouse8d86fb22009-10-12 12:48:43 +01003057 pci_fixup_device(pci_fixup_final, dev);
Jesse Barnesac1aa472009-10-26 13:20:44 -07003058 /*
3059 * If arch hasn't set it explicitly yet, use the CLS
3060 * value shared by all PCI devices. If there's a
3061 * mismatch, fall back to the default value.
3062 */
3063 if (!pci_cache_line_size) {
3064 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3065 if (!cls)
3066 cls = tmp;
3067 if (!tmp || cls == tmp)
3068 continue;
3069
3070 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3071 "using %u bytes\n", cls << 2, tmp << 2,
3072 pci_dfl_cache_line_size << 2);
3073 pci_cache_line_size = pci_dfl_cache_line_size;
3074 }
3075 }
3076 if (!pci_cache_line_size) {
3077 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3078 cls << 2, pci_dfl_cache_line_size << 2);
Csaba Henk2820f332009-12-15 17:55:25 +05303079 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
David Woodhouse8d86fb22009-10-12 12:48:43 +01003080 }
3081
3082 return 0;
3083}
3084
David Woodhousecf6f3bf2009-10-12 12:51:22 +01003085fs_initcall_sync(pci_apply_final_quirks);
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003086
3087/*
3088 * Followings are device-specific reset methods which can be used to
3089 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3090 * not available.
3091 */
Dexuan Cuiaeb30012009-12-07 13:03:22 +08003092static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3093{
3094 int pos;
3095
3096 /* only implement PCI_CLASS_SERIAL_USB at present */
3097 if (dev->class == PCI_CLASS_SERIAL_USB) {
3098 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3099 if (!pos)
3100 return -ENOTTY;
3101
3102 if (probe)
3103 return 0;
3104
3105 pci_write_config_byte(dev, pos + 0x4, 1);
3106 msleep(100);
3107
3108 return 0;
3109 } else {
3110 return -ENOTTY;
3111 }
3112}
3113
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003114static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3115{
3116 int pos;
3117
3118 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3119 if (!pos)
3120 return -ENOTTY;
3121
3122 if (probe)
3123 return 0;
3124
3125 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3126 PCI_EXP_DEVCTL_BCR_FLR);
3127 msleep(100);
3128
3129 return 0;
3130}
3131
3132#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3133
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003134static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003135 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3136 reset_intel_82599_sfp_virtfn },
Dexuan Cuiaeb30012009-12-07 13:03:22 +08003137 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3138 reset_intel_generic_dev },
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003139 { 0 }
3140};
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003141
3142int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3143{
Linus Torvaldsdf9d1e82009-12-31 16:44:43 -08003144 const struct pci_dev_reset_methods *i;
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003145
3146 for (i = pci_dev_reset_methods; i->reset; i++) {
3147 if ((i->vendor == dev->vendor ||
3148 i->vendor == (u16)PCI_ANY_ID) &&
3149 (i->device == dev->device ||
3150 i->device == (u16)PCI_ANY_ID))
3151 return i->reset(dev, probe);
3152 }
3153
3154 return -ENOTTY;
3155}