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gerrit-public.fairphone.software / kernel / msm-5.4 / 070bd7e49171d1f4effef4d5edb718ba4743ec0a / . / arch / arm / boot / dts / imx53.dtsi
blob: faceb22f2f6562b6c9aa553de8cdea241ea7b4b3 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 gpio5 = &gpio6;
24 gpio6 = &gpio7;
Philipp Zabelc60dc1d2013-04-09 19:18:47 +0200[diff] [blame]25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
Sascha Hauercf4e5772013-06-25 15:51:56 +0200[diff] [blame]28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 spi0 = &ecspi1;
34 spi1 = &ecspi2;
35 spi2 = &cspi;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]36 };
37
Fabio Estevam070bd7e2013-07-07 10:12:30 -0300[diff] [blame^]38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a8";
44 reg = <0x0>;
45 };
46 };
47
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]48 tzic: tz-interrupt-controller@0fffc000 {
49 compatible = "fsl,imx53-tzic", "fsl,tzic";
50 interrupt-controller;
51 #interrupt-cells = <1>;
52 reg = <0x0fffc000 0x4000>;
53 };
54
55 clocks {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 ckil {
60 compatible = "fsl,imx-ckil", "fixed-clock";
61 clock-frequency = <32768>;
62 };
63
64 ckih1 {
65 compatible = "fsl,imx-ckih1", "fixed-clock";
66 clock-frequency = <22579200>;
67 };
68
69 ckih2 {
70 compatible = "fsl,imx-ckih2", "fixed-clock";
71 clock-frequency = <0>;
72 };
73
74 osc {
75 compatible = "fsl,imx-osc", "fixed-clock";
76 clock-frequency = <24000000>;
77 };
78 };
79
80 soc {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "simple-bus";
84 interrupt-parent = <&tzic>;
85 ranges;
86
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]87 ipu: ipu@18000000 {
88 #crtc-cells = <1>;
89 compatible = "fsl,imx53-ipu";
90 reg = <0x18000000 0x080000000>;
91 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]92 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
93 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]94 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]95 };
96
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]97 aips@50000000 { /* AIPS1 */
98 compatible = "fsl,aips-bus", "simple-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 reg = <0x50000000 0x10000000>;
102 ranges;
103
104 spba@50000000 {
105 compatible = "fsl,spba-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x50000000 0x40000>;
109 ranges;
110
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]111 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]112 compatible = "fsl,imx53-esdhc";
113 reg = <0x50004000 0x4000>;
114 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]115 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
116 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]117 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]118 status = "disabled";
119 };
120
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]121 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]122 compatible = "fsl,imx53-esdhc";
123 reg = <0x50008000 0x4000>;
124 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]125 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
126 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]127 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]128 status = "disabled";
129 };
130
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]131 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]132 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
133 reg = <0x5000c000 0x4000>;
134 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]135 clocks = <&clks 32>, <&clks 33>;
136 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]137 status = "disabled";
138 };
139
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]140 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
144 reg = <0x50010000 0x4000>;
145 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]146 clocks = <&clks 51>, <&clks 52>;
147 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]148 status = "disabled";
149 };
150
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]151 ssi2: ssi@50014000 {
152 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
153 reg = <0x50014000 0x4000>;
154 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]155 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]156 fsl,fifo-depth = <15>;
157 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
158 status = "disabled";
159 };
160
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]161 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]162 compatible = "fsl,imx53-esdhc";
163 reg = <0x50020000 0x4000>;
164 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]165 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
166 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]167 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]168 status = "disabled";
169 };
170
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]171 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]172 compatible = "fsl,imx53-esdhc";
173 reg = <0x50024000 0x4000>;
174 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]175 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
176 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]177 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]178 status = "disabled";
179 };
180 };
181
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]182 usbphy0: usbphy@0 {
183 compatible = "usb-nop-xceiv";
184 clocks = <&clks 124>;
185 clock-names = "main_clk";
186 status = "okay";
187 };
188
189 usbphy1: usbphy@1 {
190 compatible = "usb-nop-xceiv";
191 clocks = <&clks 125>;
192 clock-names = "main_clk";
193 status = "okay";
194 };
195
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]196 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]197 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
198 reg = <0x53f80000 0x0200>;
199 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]200 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]201 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]202 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]203 status = "disabled";
204 };
205
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]206 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]207 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
208 reg = <0x53f80200 0x0200>;
209 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]210 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]211 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]212 fsl,usbphy = <&usbphy1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]213 status = "disabled";
214 };
215
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]216 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]217 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
218 reg = <0x53f80400 0x0200>;
219 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]220 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]221 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]222 status = "disabled";
223 };
224
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]225 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]226 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
227 reg = <0x53f80600 0x0200>;
228 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]229 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]230 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]231 status = "disabled";
232 };
233
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]234 usbmisc: usbmisc@53f80800 {
235 #index-cells = <1>;
236 compatible = "fsl,imx53-usbmisc";
237 reg = <0x53f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]238 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]239 };
240
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]241 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]242 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]243 reg = <0x53f84000 0x4000>;
244 interrupts = <50 51>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]248 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]249 };
250
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]251 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]252 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]253 reg = <0x53f88000 0x4000>;
254 interrupts = <52 53>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]258 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]259 };
260
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]261 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]262 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]263 reg = <0x53f8c000 0x4000>;
264 interrupts = <54 55>;
265 gpio-controller;
266 #gpio-cells = <2>;
267 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]268 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]269 };
270
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]271 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]272 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]273 reg = <0x53f90000 0x4000>;
274 interrupts = <56 57>;
275 gpio-controller;
276 #gpio-cells = <2>;
277 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]278 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]279 };
280
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]281 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]282 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
283 reg = <0x53f98000 0x4000>;
284 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]285 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]286 };
287
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]288 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]289 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
290 reg = <0x53f9c000 0x4000>;
291 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]292 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]293 status = "disabled";
294 };
295
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]296 gpt: timer@53fa0000 {
297 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
298 reg = <0x53fa0000 0x4000>;
299 interrupts = <39>;
300 clocks = <&clks 36>, <&clks 41>;
301 clock-names = "ipg", "per";
302 };
303
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]304 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]305 compatible = "fsl,imx53-iomuxc";
306 reg = <0x53fa8000 0x4000>;
307
308 audmux {
309 pinctrl_audmux_1: audmuxgrp-1 {
310 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]311 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
312 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
313 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
314 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]315 >;
316 };
Marek Vasutdd04c172013-04-21 23:30:01 +0200[diff] [blame]317
318 pinctrl_audmux_2: audmuxgrp-2 {
319 fsl,pins = <
320 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
321 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
322 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
323 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
324 >;
325 };
Steffen Trumtrarbb6e2fa2013-04-24 11:41:20 +0200[diff] [blame]326
327 pinctrl_audmux_3: audmuxgrp-3 {
328 fsl,pins = <
329 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
330 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
331 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
332 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
333 >;
334 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]335 };
336
337 fec {
338 pinctrl_fec_1: fecgrp-1 {
339 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]340 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
341 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
342 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
343 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
344 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
345 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
346 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
347 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
348 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
349 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]350 >;
351 };
Jonas Anderssonfad1ea02013-05-27 10:52:54 +0200[diff] [blame]352
353 pinctrl_fec_2: fecgrp-2 {
354 fsl,pins = <
355 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
356 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
357 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
358 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
359 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
360 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
361 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
362 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
363 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
364 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
365 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
366 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
367 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
368 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
369 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
370 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
371 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
372 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
373 >;
374 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]375 };
376
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]377 csi {
378 pinctrl_csi_1: csigrp-1 {
379 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]380 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
381 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
382 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
383 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
384 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
385 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
386 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
387 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
388 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
389 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
390 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
391 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
392 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
393 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
394 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
395 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
396 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
397 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
398 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
399 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
400 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]401 >;
402 };
Steffen Trumtrard0cae682013-04-24 11:41:21 +0200[diff] [blame]403
404 pinctrl_csi_2: csigrp-2 {
405 fsl,pins = <
406 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
407 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
408 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
409 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
410 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
411 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
412 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
413 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
414 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
415 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
416 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
417 >;
418 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]419 };
420
421 cspi {
422 pinctrl_cspi_1: cspigrp-1 {
423 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]424 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
425 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
426 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]427 >;
428 };
Jonas Andersson4017f792013-05-27 10:52:21 +0200[diff] [blame]429
430 pinctrl_cspi_2: cspigrp-2 {
431 fsl,pins = <
432 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
433 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
434 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
435 >;
436 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]437 };
438
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]439 ecspi1 {
440 pinctrl_ecspi1_1: ecspi1grp-1 {
441 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]442 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
443 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
444 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]445 >;
446 };
Steffen Trumtrar6a079e62013-04-24 11:41:22 +0200[diff] [blame]447
448 pinctrl_ecspi1_2: ecspi1grp-2 {
449 fsl,pins = <
450 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
451 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
452 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
453 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
454 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
455 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
456 >;
457 };
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]458 };
459
Jonas Andersson1a6c5602013-05-27 10:52:45 +0200[diff] [blame]460 ecspi2 {
461 pinctrl_ecspi2_1: ecspi2grp-1 {
462 fsl,pins = <
463 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
464 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
465 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
466 >;
467 };
468 };
469
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]470 esdhc1 {
471 pinctrl_esdhc1_1: esdhc1grp-1 {
472 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]473 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
474 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
475 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
476 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
477 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
478 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]479 >;
480 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]481
482 pinctrl_esdhc1_2: esdhc1grp-2 {
483 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]484 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
485 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
486 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
487 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
488 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
489 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
490 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
491 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
492 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
493 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]494 >;
495 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]496 };
497
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]498 esdhc2 {
499 pinctrl_esdhc2_1: esdhc2grp-1 {
500 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]501 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
502 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
503 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
504 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
505 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
506 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]507 >;
508 };
509 };
510
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]511 esdhc3 {
512 pinctrl_esdhc3_1: esdhc3grp-1 {
513 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]514 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
515 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
516 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
517 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
518 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
519 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
520 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
521 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
522 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
523 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]524 >;
525 };
526 };
527
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]528 can1 {
529 pinctrl_can1_1: can1grp-1 {
530 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]531 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
532 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]533 >;
534 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]535
536 pinctrl_can1_2: can1grp-2 {
537 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]538 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
539 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]540 >;
541 };
Marek Vasut0f14ac42013-04-21 23:30:02 +0200[diff] [blame]542
543 pinctrl_can1_3: can1grp-3 {
544 fsl,pins = <
545 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
546 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
547 >;
548 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]549 };
550
551 can2 {
552 pinctrl_can2_1: can2grp-1 {
553 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]554 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
555 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]556 >;
557 };
558 };
559
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]560 i2c1 {
561 pinctrl_i2c1_1: i2c1grp-1 {
562 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]563 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
564 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]565 >;
566 };
Marek Vasutd7974712013-04-21 23:30:03 +0200[diff] [blame]567
568 pinctrl_i2c1_2: i2c1grp-2 {
569 fsl,pins = <
570 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
571 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
572 >;
573 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]574 };
575
576 i2c2 {
577 pinctrl_i2c2_1: i2c2grp-1 {
578 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]579 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
580 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]581 >;
582 };
Marek Vasuted5be462013-04-21 23:30:04 +0200[diff] [blame]583
584 pinctrl_i2c2_2: i2c2grp-2 {
585 fsl,pins = <
586 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
587 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
588 >;
589 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]590 };
591
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]592 i2c3 {
593 pinctrl_i2c3_1: i2c3grp-1 {
594 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]595 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
596 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]597 >;
598 };
599 };
600
Rogerio Pimentelc2689472013-05-24 11:09:30 -0300[diff] [blame]601 ipu_disp0 {
602 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
603 fsl,pins = <
604 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
605 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
606 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
607 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
608 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
609 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
610 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
611 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
612 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
613 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
614 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
615 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
616 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
617 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
618 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
619 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
620 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
621 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
622 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
623 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
624 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
625 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
626 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
627 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
628 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
629 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
630 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
631 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
632 >;
633 };
634 };
635
Marek Vasut9f7fbb12013-04-21 23:30:06 +0200[diff] [blame]636 ipu_disp1 {
637 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
638 fsl,pins = <
639 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
640 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
641 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
642 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
643 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
644 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
645 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
646 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
647 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
648 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
649 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
650 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
651 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
652 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
653 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
654 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
655 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
656 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
657 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
658 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
659 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
660 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
661 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
662 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
663 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
664 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
665 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
666 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
667 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
668 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
669 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
670 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
671 >;
672 };
673 };
674
675 ipu_disp2 {
676 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
677 fsl,pins = <
678 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
679 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
680 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
681 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
682 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
683 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
684 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
685 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
686 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
687 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
688 >;
689 };
690 };
691
Marek Vasutefee5e12013-04-21 23:30:05 +0200[diff] [blame]692 nand {
693 pinctrl_nand_1: nandgrp-1 {
694 fsl,pins = <
695 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
696 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
697 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
698 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
699 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
700 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
701 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
702 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
703 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
704 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
705 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
706 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
707 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
708 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
709 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
710 >;
711 };
712 };
713
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]714 owire {
715 pinctrl_owire_1: owiregrp-1 {
716 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]717 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]718 >;
719 };
720 };
721
Marek Vasut95050492013-04-21 23:30:07 +0200[diff] [blame]722 pwm1 {
723 pinctrl_pwm1_1: pwm1grp-1 {
724 fsl,pins = <
725 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
726 >;
727 };
728 };
729
Steffen Trumtrar20e081c2013-04-24 11:41:23 +0200[diff] [blame]730 pwm2 {
731 pinctrl_pwm2_1: pwm2grp-1 {
732 fsl,pins = <
733 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
734 >;
735 };
736 };
737
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]738 uart1 {
739 pinctrl_uart1_1: uart1grp-1 {
740 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]741 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
742 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]743 >;
744 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]745
746 pinctrl_uart1_2: uart1grp-2 {
747 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]748 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
749 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]750 >;
751 };
Steffen Trumtrar47d63392013-04-24 11:41:24 +0200[diff] [blame]752
753 pinctrl_uart1_3: uart1grp-3 {
754 fsl,pins = <
755 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
756 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
757 >;
758 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]759 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]760
761 uart2 {
762 pinctrl_uart2_1: uart2grp-1 {
763 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]764 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
765 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]766 >;
767 };
Steffen Trumtrarc3fcca22013-04-24 11:41:25 +0200[diff] [blame]768
769 pinctrl_uart2_2: uart2grp-2 {
770 fsl,pins = <
771 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
772 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
773 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
774 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
775 >;
776 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]777 };
778
779 uart3 {
780 pinctrl_uart3_1: uart3grp-1 {
781 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]782 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
783 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
784 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
785 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]786 >;
787 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]788
789 pinctrl_uart3_2: uart3grp-2 {
790 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]791 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
792 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]793 >;
794 };
795
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]796 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]797
798 uart4 {
799 pinctrl_uart4_1: uart4grp-1 {
800 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]801 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
802 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]803 >;
804 };
805 };
806
807 uart5 {
808 pinctrl_uart5_1: uart5grp-1 {
809 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]810 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
811 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]812 >;
813 };
814 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]815 };
816
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]817 gpr: iomuxc-gpr@53fa8000 {
818 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
819 reg = <0x53fa8000 0xc>;
820 };
821
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]822 ldb: ldb@53fa8008 {
823 #address-cells = <1>;
824 #size-cells = <0>;
825 compatible = "fsl,imx53-ldb";
826 reg = <0x53fa8008 0x4>;
827 gpr = <&gpr>;
828 clocks = <&clks 122>, <&clks 120>,
829 <&clks 115>, <&clks 116>,
830 <&clks 123>, <&clks 85>;
831 clock-names = "di0_pll", "di1_pll",
832 "di0_sel", "di1_sel",
833 "di0", "di1";
834 status = "disabled";
835
836 lvds-channel@0 {
837 reg = <0>;
838 crtcs = <&ipu 0>;
839 status = "disabled";
840 };
841
842 lvds-channel@1 {
843 reg = <1>;
844 crtcs = <&ipu 1>;
845 status = "disabled";
846 };
847 };
848
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]849 pwm1: pwm@53fb4000 {
850 #pwm-cells = <2>;
851 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
852 reg = <0x53fb4000 0x4000>;
853 clocks = <&clks 37>, <&clks 38>;
854 clock-names = "ipg", "per";
855 interrupts = <61>;
856 };
857
858 pwm2: pwm@53fb8000 {
859 #pwm-cells = <2>;
860 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
861 reg = <0x53fb8000 0x4000>;
862 clocks = <&clks 39>, <&clks 40>;
863 clock-names = "ipg", "per";
864 interrupts = <94>;
865 };
866
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]867 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]868 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
869 reg = <0x53fbc000 0x4000>;
870 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]871 clocks = <&clks 28>, <&clks 29>;
872 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]873 status = "disabled";
874 };
875
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]876 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]877 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
878 reg = <0x53fc0000 0x4000>;
879 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]880 clocks = <&clks 30>, <&clks 31>;
881 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]882 status = "disabled";
883 };
884
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]885 can1: can@53fc8000 {
886 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
887 reg = <0x53fc8000 0x4000>;
888 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]889 clocks = <&clks 158>, <&clks 157>;
890 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]891 status = "disabled";
892 };
893
894 can2: can@53fcc000 {
895 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
896 reg = <0x53fcc000 0x4000>;
897 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]898 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]899 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]900 status = "disabled";
901 };
902
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]903 src: src@53fd0000 {
904 compatible = "fsl,imx53-src", "fsl,imx51-src";
905 reg = <0x53fd0000 0x4000>;
906 #reset-cells = <1>;
907 };
908
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]909 clks: ccm@53fd4000{
910 compatible = "fsl,imx53-ccm";
911 reg = <0x53fd4000 0x4000>;
912 interrupts = <0 71 0x04 0 72 0x04>;
913 #clock-cells = <1>;
914 };
915
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]916 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]917 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]918 reg = <0x53fdc000 0x4000>;
919 interrupts = <103 104>;
920 gpio-controller;
921 #gpio-cells = <2>;
922 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]923 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]924 };
925
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]926 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]927 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]928 reg = <0x53fe0000 0x4000>;
929 interrupts = <105 106>;
930 gpio-controller;
931 #gpio-cells = <2>;
932 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]933 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]934 };
935
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]936 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]937 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]938 reg = <0x53fe4000 0x4000>;
939 interrupts = <107 108>;
940 gpio-controller;
941 #gpio-cells = <2>;
942 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]943 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]944 };
945
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]946 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]947 #address-cells = <1>;
948 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]949 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]950 reg = <0x53fec000 0x4000>;
951 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]952 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]953 status = "disabled";
954 };
955
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]956 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]957 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
958 reg = <0x53ff0000 0x4000>;
959 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]960 clocks = <&clks 65>, <&clks 66>;
961 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]962 status = "disabled";
963 };
964 };
965
966 aips@60000000 { /* AIPS2 */
967 compatible = "fsl,aips-bus", "simple-bus";
968 #address-cells = <1>;
969 #size-cells = <1>;
970 reg = <0x60000000 0x10000000>;
971 ranges;
972
Sascha Hauer4f3b2a42013-06-25 15:51:52 +0200[diff] [blame]973 iim: iim@63f98000 {
974 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
975 reg = <0x63f98000 0x4000>;
976 interrupts = <69>;
977 clocks = <&clks 107>;
978 };
979
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]980 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]981 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
982 reg = <0x63f90000 0x4000>;
983 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]984 clocks = <&clks 67>, <&clks 68>;
985 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]986 status = "disabled";
987 };
988
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]989 owire: owire@63fa4000 {
990 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
991 reg = <0x63fa4000 0x4000>;
992 clocks = <&clks 159>;
993 status = "disabled";
994 };
995
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]996 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]997 #address-cells = <1>;
998 #size-cells = <0>;
999 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1000 reg = <0x63fac000 0x4000>;
1001 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1002 clocks = <&clks 53>, <&clks 54>;
1003 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1004 status = "disabled";
1005 };
1006
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1007 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1008 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1009 reg = <0x63fb0000 0x4000>;
1010 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1011 clocks = <&clks 56>, <&clks 56>;
1012 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]1013 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]1014 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1015 };
1016
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1017 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1021 reg = <0x63fc0000 0x4000>;
1022 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]1023 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1024 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1025 status = "disabled";
1026 };
1027
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1028 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1029 #address-cells = <1>;
1030 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1031 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1032 reg = <0x63fc4000 0x4000>;
1033 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1034 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1035 status = "disabled";
1036 };
1037
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1038 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1039 #address-cells = <1>;
1040 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1041 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1042 reg = <0x63fc8000 0x4000>;
1043 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1044 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1045 status = "disabled";
1046 };
1047
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1048 ssi1: ssi@63fcc000 {
1049 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1050 reg = <0x63fcc000 0x4000>;
1051 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1052 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1053 fsl,fifo-depth = <15>;
1054 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1055 status = "disabled";
1056 };
1057
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1058 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1059 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1060 reg = <0x63fd0000 0x4000>;
1061 status = "disabled";
1062 };
1063
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1064 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]1065 compatible = "fsl,imx53-nand";
1066 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1067 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1068 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]1069 status = "disabled";
1070 };
1071
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1072 ssi3: ssi@63fe8000 {
1073 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1074 reg = <0x63fe8000 0x4000>;
1075 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1076 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1077 fsl,fifo-depth = <15>;
1078 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1079 status = "disabled";
1080 };
1081
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1082 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1083 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1084 reg = <0x63fec000 0x4000>;
1085 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1086 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1087 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1088 status = "disabled";
1089 };
Philipp Zabel19194c22013-06-04 12:12:22 +0200[diff] [blame]1090
1091 tve: tve@63ff0000 {
1092 compatible = "fsl,imx53-tve";
1093 reg = <0x63ff0000 0x1000>;
1094 interrupts = <92>;
1095 clocks = <&clks 69>, <&clks 116>;
1096 clock-names = "tve", "di_sel";
1097 crtcs = <&ipu 1>;
1098 status = "disabled";
1099 };
Fabio Estevamfbf970f2013-06-28 19:49:18 -0300[diff] [blame]1100
1101 vpu: vpu@63ff4000 {
1102 compatible = "fsl,imx53-vpu";
1103 reg = <0x63ff4000 0x1000>;
1104 interrupts = <9>;
1105 clocks = <&clks 63>, <&clks 63>;
1106 clock-names = "per", "ahb";
1107 iram = <&ocram>;
1108 status = "disabled";
1109 };
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1110 };
Philipp Zabel481fbe12013-07-01 11:06:09 +0200[diff] [blame]1111
1112 ocram: sram@f8000000 {
1113 compatible = "mmio-sram";
1114 reg = <0xf8000000 0x20000>;
1115 };
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1116 };
1117};