Greg Kroah-Hartman | 5fd54ac | 2017-11-03 11:28:30 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/clk.h> |
| 9 | #include <linux/dma-mapping.h> |
| 10 | #include <linux/iopoll.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/of_address.h> |
| 14 | #include <linux/of_irq.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | |
| 17 | #include "mtu3.h" |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 18 | #include "mtu3_dr.h" |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 19 | |
| 20 | /* u2-port0 should be powered on and enabled; */ |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 21 | int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 22 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 23 | void __iomem *ibase = ssusb->ippc_base; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 24 | u32 value, check_val; |
| 25 | int ret; |
| 26 | |
| 27 | check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | |
| 28 | SSUSB_REF_RST_B_STS; |
| 29 | |
| 30 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, |
| 31 | (check_val == (value & check_val)), 100, 20000); |
| 32 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 33 | dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 34 | return ret; |
| 35 | } |
| 36 | |
| 37 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, |
| 38 | (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000); |
| 39 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 40 | dev_err(ssusb->dev, "mac2 clock is not stable\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 41 | return ret; |
| 42 | } |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 47 | static int ssusb_phy_init(struct ssusb_mtk *ssusb) |
| 48 | { |
| 49 | int i; |
| 50 | int ret; |
| 51 | |
| 52 | for (i = 0; i < ssusb->num_phys; i++) { |
| 53 | ret = phy_init(ssusb->phys[i]); |
| 54 | if (ret) |
| 55 | goto exit_phy; |
| 56 | } |
| 57 | return 0; |
| 58 | |
| 59 | exit_phy: |
| 60 | for (; i > 0; i--) |
| 61 | phy_exit(ssusb->phys[i - 1]); |
| 62 | |
| 63 | return ret; |
| 64 | } |
| 65 | |
| 66 | static int ssusb_phy_exit(struct ssusb_mtk *ssusb) |
| 67 | { |
| 68 | int i; |
| 69 | |
| 70 | for (i = 0; i < ssusb->num_phys; i++) |
| 71 | phy_exit(ssusb->phys[i]); |
| 72 | |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | static int ssusb_phy_power_on(struct ssusb_mtk *ssusb) |
| 77 | { |
| 78 | int i; |
| 79 | int ret; |
| 80 | |
| 81 | for (i = 0; i < ssusb->num_phys; i++) { |
| 82 | ret = phy_power_on(ssusb->phys[i]); |
| 83 | if (ret) |
| 84 | goto power_off_phy; |
| 85 | } |
| 86 | return 0; |
| 87 | |
| 88 | power_off_phy: |
| 89 | for (; i > 0; i--) |
| 90 | phy_power_off(ssusb->phys[i - 1]); |
| 91 | |
| 92 | return ret; |
| 93 | } |
| 94 | |
| 95 | static void ssusb_phy_power_off(struct ssusb_mtk *ssusb) |
| 96 | { |
| 97 | unsigned int i; |
| 98 | |
| 99 | for (i = 0; i < ssusb->num_phys; i++) |
| 100 | phy_power_off(ssusb->phys[i]); |
| 101 | } |
| 102 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 103 | static int ssusb_clks_enable(struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 104 | { |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 105 | int ret; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 106 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 107 | ret = clk_prepare_enable(ssusb->sys_clk); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 108 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 109 | dev_err(ssusb->dev, "failed to enable sys_clk\n"); |
Chunfeng Yun | 4d70d0c | 2017-01-18 14:08:23 +0800 | [diff] [blame] | 110 | goto sys_clk_err; |
| 111 | } |
| 112 | |
| 113 | ret = clk_prepare_enable(ssusb->ref_clk); |
| 114 | if (ret) { |
| 115 | dev_err(ssusb->dev, "failed to enable ref_clk\n"); |
| 116 | goto ref_clk_err; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 117 | } |
| 118 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 119 | ret = clk_prepare_enable(ssusb->mcu_clk); |
| 120 | if (ret) { |
| 121 | dev_err(ssusb->dev, "failed to enable mcu_clk\n"); |
| 122 | goto mcu_clk_err; |
| 123 | } |
| 124 | |
| 125 | ret = clk_prepare_enable(ssusb->dma_clk); |
| 126 | if (ret) { |
| 127 | dev_err(ssusb->dev, "failed to enable dma_clk\n"); |
| 128 | goto dma_clk_err; |
| 129 | } |
| 130 | |
| 131 | return 0; |
| 132 | |
| 133 | dma_clk_err: |
| 134 | clk_disable_unprepare(ssusb->mcu_clk); |
| 135 | mcu_clk_err: |
| 136 | clk_disable_unprepare(ssusb->ref_clk); |
| 137 | ref_clk_err: |
| 138 | clk_disable_unprepare(ssusb->sys_clk); |
| 139 | sys_clk_err: |
| 140 | return ret; |
| 141 | } |
| 142 | |
| 143 | static void ssusb_clks_disable(struct ssusb_mtk *ssusb) |
| 144 | { |
| 145 | clk_disable_unprepare(ssusb->dma_clk); |
| 146 | clk_disable_unprepare(ssusb->mcu_clk); |
| 147 | clk_disable_unprepare(ssusb->ref_clk); |
| 148 | clk_disable_unprepare(ssusb->sys_clk); |
| 149 | } |
| 150 | |
| 151 | static int ssusb_rscs_init(struct ssusb_mtk *ssusb) |
| 152 | { |
| 153 | int ret = 0; |
| 154 | |
| 155 | ret = regulator_enable(ssusb->vusb33); |
| 156 | if (ret) { |
| 157 | dev_err(ssusb->dev, "failed to enable vusb33\n"); |
| 158 | goto vusb33_err; |
| 159 | } |
| 160 | |
| 161 | ret = ssusb_clks_enable(ssusb); |
| 162 | if (ret) |
| 163 | goto clks_err; |
| 164 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 165 | ret = ssusb_phy_init(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 166 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 167 | dev_err(ssusb->dev, "failed to init phy\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 168 | goto phy_init_err; |
| 169 | } |
| 170 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 171 | ret = ssusb_phy_power_on(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 172 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 173 | dev_err(ssusb->dev, "failed to power on phy\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 174 | goto phy_err; |
| 175 | } |
| 176 | |
| 177 | return 0; |
| 178 | |
| 179 | phy_err: |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 180 | ssusb_phy_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 181 | phy_init_err: |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 182 | ssusb_clks_disable(ssusb); |
| 183 | clks_err: |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 184 | regulator_disable(ssusb->vusb33); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 185 | vusb33_err: |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 186 | return ret; |
| 187 | } |
| 188 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 189 | static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 190 | { |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 191 | ssusb_clks_disable(ssusb); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 192 | regulator_disable(ssusb->vusb33); |
| 193 | ssusb_phy_power_off(ssusb); |
| 194 | ssusb_phy_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 195 | } |
| 196 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 197 | static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 198 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 199 | /* reset whole ip (xhci & u3d) */ |
| 200 | mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 201 | udelay(1); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 202 | mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 203 | } |
| 204 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 205 | /* ignore the error if the clock does not exist */ |
| 206 | static struct clk *get_optional_clk(struct device *dev, const char *id) |
| 207 | { |
| 208 | struct clk *opt_clk; |
| 209 | |
| 210 | opt_clk = devm_clk_get(dev, id); |
| 211 | /* ignore error number except EPROBE_DEFER */ |
| 212 | if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER)) |
| 213 | opt_clk = NULL; |
| 214 | |
| 215 | return opt_clk; |
| 216 | } |
| 217 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 218 | static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 219 | { |
| 220 | struct device_node *node = pdev->dev.of_node; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 221 | struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 222 | struct device *dev = &pdev->dev; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 223 | struct regulator *vbus; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 224 | struct resource *res; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 225 | int i; |
| 226 | int ret; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 227 | |
Chunfeng Yun | 5cbf2d6 | 2017-01-18 14:08:22 +0800 | [diff] [blame] | 228 | ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33"); |
| 229 | if (IS_ERR(ssusb->vusb33)) { |
| 230 | dev_err(dev, "failed to get vusb33\n"); |
| 231 | return PTR_ERR(ssusb->vusb33); |
| 232 | } |
| 233 | |
| 234 | ssusb->sys_clk = devm_clk_get(dev, "sys_ck"); |
| 235 | if (IS_ERR(ssusb->sys_clk)) { |
| 236 | dev_err(dev, "failed to get sys clock\n"); |
| 237 | return PTR_ERR(ssusb->sys_clk); |
| 238 | } |
| 239 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 240 | ssusb->ref_clk = get_optional_clk(dev, "ref_ck"); |
| 241 | if (IS_ERR(ssusb->ref_clk)) |
| 242 | return PTR_ERR(ssusb->ref_clk); |
Chunfeng Yun | ca12cb7 | 2017-02-07 14:13:32 +0800 | [diff] [blame] | 243 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 244 | ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck"); |
| 245 | if (IS_ERR(ssusb->mcu_clk)) |
| 246 | return PTR_ERR(ssusb->mcu_clk); |
| 247 | |
| 248 | ssusb->dma_clk = get_optional_clk(dev, "dma_ck"); |
| 249 | if (IS_ERR(ssusb->dma_clk)) |
| 250 | return PTR_ERR(ssusb->dma_clk); |
Chunfeng Yun | 4d70d0c | 2017-01-18 14:08:23 +0800 | [diff] [blame] | 251 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 252 | ssusb->num_phys = of_count_phandle_with_args(node, |
| 253 | "phys", "#phy-cells"); |
| 254 | if (ssusb->num_phys > 0) { |
| 255 | ssusb->phys = devm_kcalloc(dev, ssusb->num_phys, |
| 256 | sizeof(*ssusb->phys), GFP_KERNEL); |
| 257 | if (!ssusb->phys) |
| 258 | return -ENOMEM; |
| 259 | } else { |
| 260 | ssusb->num_phys = 0; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 261 | } |
| 262 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 263 | for (i = 0; i < ssusb->num_phys; i++) { |
| 264 | ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i); |
| 265 | if (IS_ERR(ssusb->phys[i])) { |
| 266 | dev_err(dev, "failed to get phy-%d\n", i); |
| 267 | return PTR_ERR(ssusb->phys[i]); |
| 268 | } |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 272 | ssusb->ippc_base = devm_ioremap_resource(dev, res); |
Wei Yongjun | b7ecfe7 | 2017-02-05 16:25:38 +0000 | [diff] [blame] | 273 | if (IS_ERR(ssusb->ippc_base)) |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 274 | return PTR_ERR(ssusb->ippc_base); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 275 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 276 | ssusb->dr_mode = usb_get_dr_mode(dev); |
Chunfeng Yun | dd9d2f3 | 2017-10-13 17:10:45 +0800 | [diff] [blame] | 277 | if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) |
| 278 | ssusb->dr_mode = USB_DR_MODE_OTG; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 279 | |
| 280 | if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) |
| 281 | return 0; |
| 282 | |
| 283 | /* if host role is supported */ |
| 284 | ret = ssusb_wakeup_of_property_parse(ssusb, node); |
Chunfeng Yun | f0ede2c | 2018-01-03 16:53:18 +0800 | [diff] [blame] | 285 | if (ret) { |
| 286 | dev_err(dev, "failed to parse uwk property\n"); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 287 | return ret; |
Chunfeng Yun | f0ede2c | 2018-01-03 16:53:18 +0800 | [diff] [blame] | 288 | } |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 289 | |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 290 | /* optional property, ignore the error if it does not exist */ |
| 291 | of_property_read_u32(node, "mediatek,u3p-dis-msk", |
| 292 | &ssusb->u3p_dis_msk); |
| 293 | |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 294 | vbus = devm_regulator_get(&pdev->dev, "vbus"); |
| 295 | if (IS_ERR(vbus)) { |
| 296 | dev_err(dev, "failed to get vbus\n"); |
| 297 | return PTR_ERR(vbus); |
| 298 | } |
| 299 | otg_sx->vbus = vbus; |
| 300 | |
Chunfeng Yun | 6638ec5 | 2017-10-13 17:10:44 +0800 | [diff] [blame] | 301 | if (ssusb->dr_mode == USB_DR_MODE_HOST) |
| 302 | return 0; |
| 303 | |
| 304 | /* if dual-role mode is supported */ |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 305 | otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd"); |
| 306 | otg_sx->manual_drd_enabled = |
| 307 | of_property_read_bool(node, "enable-manual-drd"); |
| 308 | |
| 309 | if (of_property_read_bool(node, "extcon")) { |
| 310 | otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0); |
| 311 | if (IS_ERR(otg_sx->edev)) { |
| 312 | dev_err(ssusb->dev, "couldn't get extcon device\n"); |
Chunfeng Yun | 3849c29 | 2018-01-03 16:53:17 +0800 | [diff] [blame] | 313 | return PTR_ERR(otg_sx->edev); |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 314 | } |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 315 | } |
| 316 | |
Chunfeng Yun | c776f2c | 2017-10-13 17:10:42 +0800 | [diff] [blame] | 317 | dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n", |
| 318 | ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk, |
| 319 | otg_sx->manual_drd_enabled ? "manual" : "auto"); |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 320 | |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static int mtu3_probe(struct platform_device *pdev) |
| 325 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 326 | struct device_node *node = pdev->dev.of_node; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 327 | struct device *dev = &pdev->dev; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 328 | struct ssusb_mtk *ssusb; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 329 | int ret = -ENOMEM; |
| 330 | |
| 331 | /* all elements are set to ZERO as default value */ |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 332 | ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL); |
| 333 | if (!ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 334 | return -ENOMEM; |
| 335 | |
| 336 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
| 337 | if (ret) { |
| 338 | dev_err(dev, "No suitable DMA config available\n"); |
| 339 | return -ENOTSUPP; |
| 340 | } |
| 341 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 342 | platform_set_drvdata(pdev, ssusb); |
| 343 | ssusb->dev = dev; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 344 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 345 | ret = get_ssusb_rscs(pdev, ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 346 | if (ret) |
| 347 | return ret; |
| 348 | |
| 349 | /* enable power domain */ |
| 350 | pm_runtime_enable(dev); |
| 351 | pm_runtime_get_sync(dev); |
| 352 | device_enable_async_suspend(dev); |
| 353 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 354 | ret = ssusb_rscs_init(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 355 | if (ret) |
| 356 | goto comm_init_err; |
| 357 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 358 | ssusb_ip_sw_reset(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 359 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 360 | if (IS_ENABLED(CONFIG_USB_MTU3_HOST)) |
| 361 | ssusb->dr_mode = USB_DR_MODE_HOST; |
| 362 | else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET)) |
| 363 | ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; |
| 364 | |
| 365 | /* default as host */ |
| 366 | ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL); |
| 367 | |
| 368 | switch (ssusb->dr_mode) { |
| 369 | case USB_DR_MODE_PERIPHERAL: |
| 370 | ret = ssusb_gadget_init(ssusb); |
| 371 | if (ret) { |
| 372 | dev_err(dev, "failed to initialize gadget\n"); |
| 373 | goto comm_exit; |
| 374 | } |
| 375 | break; |
| 376 | case USB_DR_MODE_HOST: |
| 377 | ret = ssusb_host_init(ssusb, node); |
| 378 | if (ret) { |
| 379 | dev_err(dev, "failed to initialize host\n"); |
| 380 | goto comm_exit; |
| 381 | } |
| 382 | break; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 383 | case USB_DR_MODE_OTG: |
| 384 | ret = ssusb_gadget_init(ssusb); |
| 385 | if (ret) { |
| 386 | dev_err(dev, "failed to initialize gadget\n"); |
| 387 | goto comm_exit; |
| 388 | } |
| 389 | |
| 390 | ret = ssusb_host_init(ssusb, node); |
| 391 | if (ret) { |
| 392 | dev_err(dev, "failed to initialize host\n"); |
| 393 | goto gadget_exit; |
| 394 | } |
| 395 | |
| 396 | ssusb_otg_switch_init(ssusb); |
| 397 | break; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 398 | default: |
| 399 | dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode); |
| 400 | ret = -EINVAL; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 401 | goto comm_exit; |
| 402 | } |
| 403 | |
| 404 | return 0; |
| 405 | |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 406 | gadget_exit: |
| 407 | ssusb_gadget_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 408 | comm_exit: |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 409 | ssusb_rscs_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 410 | comm_init_err: |
| 411 | pm_runtime_put_sync(dev); |
| 412 | pm_runtime_disable(dev); |
| 413 | |
| 414 | return ret; |
| 415 | } |
| 416 | |
| 417 | static int mtu3_remove(struct platform_device *pdev) |
| 418 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 419 | struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 420 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 421 | switch (ssusb->dr_mode) { |
| 422 | case USB_DR_MODE_PERIPHERAL: |
| 423 | ssusb_gadget_exit(ssusb); |
| 424 | break; |
| 425 | case USB_DR_MODE_HOST: |
| 426 | ssusb_host_exit(ssusb); |
| 427 | break; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 428 | case USB_DR_MODE_OTG: |
| 429 | ssusb_otg_switch_exit(ssusb); |
| 430 | ssusb_gadget_exit(ssusb); |
| 431 | ssusb_host_exit(ssusb); |
| 432 | break; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 433 | default: |
| 434 | return -EINVAL; |
| 435 | } |
| 436 | |
| 437 | ssusb_rscs_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 438 | pm_runtime_put_sync(&pdev->dev); |
| 439 | pm_runtime_disable(&pdev->dev); |
| 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 444 | /* |
| 445 | * when support dual-role mode, we reject suspend when |
| 446 | * it works as device mode; |
| 447 | */ |
| 448 | static int __maybe_unused mtu3_suspend(struct device *dev) |
| 449 | { |
Wolfram Sang | f86c688 | 2018-04-19 16:06:25 +0200 | [diff] [blame] | 450 | struct ssusb_mtk *ssusb = dev_get_drvdata(dev); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 451 | |
| 452 | dev_dbg(dev, "%s\n", __func__); |
| 453 | |
| 454 | /* REVISIT: disconnect it for only device mode? */ |
| 455 | if (!ssusb->is_host) |
| 456 | return 0; |
| 457 | |
| 458 | ssusb_host_disable(ssusb, true); |
| 459 | ssusb_phy_power_off(ssusb); |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 460 | ssusb_clks_disable(ssusb); |
Chunfeng Yun | f0ede2c | 2018-01-03 16:53:18 +0800 | [diff] [blame] | 461 | ssusb_wakeup_set(ssusb, true); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | static int __maybe_unused mtu3_resume(struct device *dev) |
| 467 | { |
Wolfram Sang | f86c688 | 2018-04-19 16:06:25 +0200 | [diff] [blame] | 468 | struct ssusb_mtk *ssusb = dev_get_drvdata(dev); |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 469 | int ret; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 470 | |
| 471 | dev_dbg(dev, "%s\n", __func__); |
| 472 | |
| 473 | if (!ssusb->is_host) |
| 474 | return 0; |
| 475 | |
Chunfeng Yun | f0ede2c | 2018-01-03 16:53:18 +0800 | [diff] [blame] | 476 | ssusb_wakeup_set(ssusb, false); |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 477 | ret = ssusb_clks_enable(ssusb); |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 478 | if (ret) |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 479 | goto clks_err; |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 480 | |
| 481 | ret = ssusb_phy_power_on(ssusb); |
| 482 | if (ret) |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 483 | goto phy_err; |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 484 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 485 | ssusb_host_enable(ssusb); |
| 486 | |
| 487 | return 0; |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 488 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 489 | phy_err: |
| 490 | ssusb_clks_disable(ssusb); |
| 491 | clks_err: |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 492 | return ret; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 493 | } |
| 494 | |
| 495 | static const struct dev_pm_ops mtu3_pm_ops = { |
| 496 | SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume) |
| 497 | }; |
| 498 | |
| 499 | #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL) |
| 500 | |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 501 | #ifdef CONFIG_OF |
| 502 | |
| 503 | static const struct of_device_id mtu3_of_match[] = { |
| 504 | {.compatible = "mediatek,mt8173-mtu3",}, |
Chunfeng Yun | dfcdcba | 2017-08-08 13:42:49 +0800 | [diff] [blame] | 505 | {.compatible = "mediatek,mtu3",}, |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 506 | {}, |
| 507 | }; |
| 508 | |
| 509 | MODULE_DEVICE_TABLE(of, mtu3_of_match); |
| 510 | |
| 511 | #endif |
| 512 | |
| 513 | static struct platform_driver mtu3_driver = { |
| 514 | .probe = mtu3_probe, |
| 515 | .remove = mtu3_remove, |
| 516 | .driver = { |
| 517 | .name = MTU3_DRIVER_NAME, |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 518 | .pm = DEV_PM_OPS, |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 519 | .of_match_table = of_match_ptr(mtu3_of_match), |
| 520 | }, |
| 521 | }; |
| 522 | module_platform_driver(mtu3_driver); |
| 523 | |
| 524 | MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); |
| 525 | MODULE_LICENSE("GPL v2"); |
| 526 | MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver"); |