blob: 5b87d5284a8448bb5bf0679231634e6a422502c0 [file] [log] [blame]
Oscar Mateob20385f2014-07-24 17:04:10 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
28 *
29 */
30
Oscar Mateo73e4d072014-07-24 17:04:48 +010031/**
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
33 *
34 * Motivation:
Oscar Mateob20385f2014-07-24 17:04:10 +010035 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
38 *
Oscar Mateo73e4d072014-07-24 17:04:48 +010039 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
42 *
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
47 *
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
55 *
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
58 *
59 * LRC implementation:
60 * Regarding the creation of contexts, we have:
61 *
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
65 *
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
69 *
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
72 *
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
77 * contexts:
78 *
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
83 * so on.
84 *
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
88 *
89 * Execlists implementation:
Oscar Mateob20385f2014-07-24 17:04:10 +010090 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
Oscar Mateo73e4d072014-07-24 17:04:48 +010092 * This method works as follows:
93 *
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
101 * context itself.
102 *
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
108 *
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
114 *
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
122 *
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
132 *
Oscar Mateob20385f2014-07-24 17:04:10 +0100133 */
Tvrtko Ursulin27af5ee2016-04-04 12:11:56 +0100134#include <linux/interrupt.h>
Oscar Mateob20385f2014-07-24 17:04:10 +0100135
136#include <drm/drmP.h>
137#include <drm/i915_drm.h>
138#include "i915_drv.h"
Peter Antoine3bbaba02015-07-10 20:13:11 +0300139#include "intel_mocs.h"
Oscar Mateo127f1002014-07-24 17:04:11 +0100140
Thomas Daniele981e7b2014-07-24 17:04:39 +0100141#define RING_EXECLIST_QFULL (1 << 0x2)
142#define RING_EXECLIST1_VALID (1 << 0x3)
143#define RING_EXECLIST0_VALID (1 << 0x4)
144#define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
145#define RING_EXECLIST1_ACTIVE (1 << 0x11)
146#define RING_EXECLIST0_ACTIVE (1 << 0x12)
147
148#define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
149#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
150#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
151#define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
152#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
153#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100154
Chris Wilson70c2a242016-09-09 14:11:46 +0100155#define GEN8_CTX_STATUS_COMPLETED_MASK \
156 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
157 GEN8_CTX_STATUS_PREEMPTED | \
158 GEN8_CTX_STATUS_ELEMENT_SWITCH)
159
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100160#define CTX_LRI_HEADER_0 0x01
161#define CTX_CONTEXT_CONTROL 0x02
162#define CTX_RING_HEAD 0x04
163#define CTX_RING_TAIL 0x06
164#define CTX_RING_BUFFER_START 0x08
165#define CTX_RING_BUFFER_CONTROL 0x0a
166#define CTX_BB_HEAD_U 0x0c
167#define CTX_BB_HEAD_L 0x0e
168#define CTX_BB_STATE 0x10
169#define CTX_SECOND_BB_HEAD_U 0x12
170#define CTX_SECOND_BB_HEAD_L 0x14
171#define CTX_SECOND_BB_STATE 0x16
172#define CTX_BB_PER_CTX_PTR 0x18
173#define CTX_RCS_INDIRECT_CTX 0x1a
174#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
175#define CTX_LRI_HEADER_1 0x21
176#define CTX_CTX_TIMESTAMP 0x22
177#define CTX_PDP3_UDW 0x24
178#define CTX_PDP3_LDW 0x26
179#define CTX_PDP2_UDW 0x28
180#define CTX_PDP2_LDW 0x2a
181#define CTX_PDP1_UDW 0x2c
182#define CTX_PDP1_LDW 0x2e
183#define CTX_PDP0_UDW 0x30
184#define CTX_PDP0_LDW 0x32
185#define CTX_LRI_HEADER_2 0x41
186#define CTX_R_PWR_CLK_STATE 0x42
187#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +0000189#define CTX_REG(reg_state, pos, reg, val) do { \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200190 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
Ville Syrjälä0d925ea2015-11-04 23:20:11 +0200191 (reg_state)[(pos)+1] = (val); \
192} while (0)
193
194#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
Mika Kuoppalad852c7b2015-06-25 18:35:06 +0300195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
Michel Thierrye5815a22015-04-08 12:13:32 +0100196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
Ville Syrjälä9244a812015-11-04 23:20:09 +0200198} while (0)
Michel Thierrye5815a22015-04-08 12:13:32 +0100199
Ville Syrjälä9244a812015-11-04 23:20:09 +0200200#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
Michel Thierry2dba3232015-07-30 11:06:23 +0100201 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
202 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
Ville Syrjälä9244a812015-11-04 23:20:09 +0200203} while (0)
Michel Thierry2dba3232015-07-30 11:06:23 +0100204
Michel Thierry71562912016-02-23 10:31:49 +0000205#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
206#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
Michel Thierry7bd0a2c2017-06-06 13:30:38 -0700207#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
Ben Widawsky84b790f2014-07-24 17:04:36 +0100208
Chris Wilson0e93cdd2016-04-29 09:07:06 +0100209/* Typical size of the average request (2 pipecontrols and a MI_BB) */
210#define EXECLISTS_REQUEST_SIZE 64 /* bytes */
Chris Wilsona3aabe82016-10-04 21:11:26 +0100211#define WA_TAIL_DWORDS 2
Chris Wilson7e4992a2017-09-28 20:38:59 +0100212#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
Chris Wilsonbeecec92017-10-03 21:34:52 +0100213#define PREEMPT_ID 0x1
Chris Wilsona3aabe82016-10-04 21:11:26 +0100214
Chris Wilsone2efd132016-05-24 14:53:34 +0100215static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
Chris Wilson978f1e02016-04-28 09:56:54 +0100216 struct intel_engine_cs *engine);
Chris Wilsona3aabe82016-10-04 21:11:26 +0100217static void execlists_init_reg_state(u32 *reg_state,
218 struct i915_gem_context *ctx,
219 struct intel_engine_cs *engine,
220 struct intel_ring *ring);
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000221
Oscar Mateo73e4d072014-07-24 17:04:48 +0100222/**
223 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
Tvrtko Ursulin14bb2c12016-06-03 14:02:17 +0100224 * @dev_priv: i915 device private
Oscar Mateo73e4d072014-07-24 17:04:48 +0100225 * @enable_execlists: value of i915.enable_execlists module parameter.
226 *
227 * Only certain platforms support Execlists (the prerequisites being
Thomas Daniel27401d12014-12-11 12:48:35 +0000228 * support for Logical Ring Contexts and Aliasing PPGTT or better).
Oscar Mateo73e4d072014-07-24 17:04:48 +0100229 *
230 * Return: 1 if Execlists is supported and has to be enabled.
231 */
Chris Wilsonc0336662016-05-06 15:40:21 +0100232int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
Oscar Mateo127f1002014-07-24 17:04:11 +0100233{
Zhiyuan Lva0bd6c32015-08-28 15:41:16 +0800234 /* On platforms with execlist available, vGPU will only
235 * support execlist mode, no ring buffer mode.
236 */
Chris Wilsonc0336662016-05-06 15:40:21 +0100237 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
Zhiyuan Lva0bd6c32015-08-28 15:41:16 +0800238 return 1;
239
Chris Wilsonc0336662016-05-06 15:40:21 +0100240 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau70ee45e2014-11-14 15:05:59 +0000241 return 1;
242
Oscar Mateo127f1002014-07-24 17:04:11 +0100243 if (enable_execlists == 0)
244 return 0;
245
Daniel Vetter5a21b662016-05-24 17:13:53 +0200246 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
Maarten Lankhorst8279aaf2017-10-04 11:44:16 +0200247 USES_PPGTT(dev_priv))
Oscar Mateo127f1002014-07-24 17:04:11 +0100248 return 1;
249
250 return 0;
251}
Oscar Mateoede7d422014-07-24 17:04:12 +0100252
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000253/**
254 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
255 * descriptor for a pinned context
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000256 * @ctx: Context to work on
Chris Wilson9021ad02016-05-24 14:53:37 +0100257 * @engine: Engine the descriptor will be used with
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000258 *
259 * The context descriptor encodes various attributes of a context,
260 * including its GTT address and some flags. Because it's fairly
261 * expensive to calculate, we'll just do it once and cache the result,
262 * which remains valid until the context is unpinned.
263 *
Daniel Vetter6e5248b2016-07-15 21:48:06 +0200264 * This is what a descriptor looks like, from LSB to MSB::
265 *
Mika Kuoppala2355cf02017-01-27 15:03:09 +0200266 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
Daniel Vetter6e5248b2016-07-15 21:48:06 +0200267 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
268 * bits 32-52: ctx ID, a globally unique tag
269 * bits 53-54: mbz, reserved for use by hardware
270 * bits 55-63: group ID, currently unused and set to 0
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000271 */
272static void
Chris Wilsone2efd132016-05-24 14:53:34 +0100273intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000274 struct intel_engine_cs *engine)
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000275{
Chris Wilson9021ad02016-05-24 14:53:37 +0100276 struct intel_context *ce = &ctx->engine[engine->id];
Chris Wilson7069b142016-04-28 09:56:52 +0100277 u64 desc;
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000278
Chris Wilson7069b142016-04-28 09:56:52 +0100279 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
280
Mika Kuoppala2355cf02017-01-27 15:03:09 +0200281 desc = ctx->desc_template; /* bits 0-11 */
Michel Thierry0b29c752017-09-13 09:56:00 +0100282 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
Chris Wilson9021ad02016-05-24 14:53:37 +0100283 /* bits 12-31 */
Chris Wilson7069b142016-04-28 09:56:52 +0100284 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000285
Chris Wilson9021ad02016-05-24 14:53:37 +0100286 ce->lrc_desc = desc;
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000287}
288
Chris Wilson27606fd2017-09-16 21:44:13 +0100289static struct i915_priolist *
290lookup_priolist(struct intel_engine_cs *engine,
291 struct i915_priotree *pt,
292 int prio)
Chris Wilson08dd3e12017-09-16 21:44:12 +0100293{
Mika Kuoppalab620e872017-09-22 15:43:03 +0300294 struct intel_engine_execlists * const execlists = &engine->execlists;
Chris Wilson08dd3e12017-09-16 21:44:12 +0100295 struct i915_priolist *p;
296 struct rb_node **parent, *rb;
297 bool first = true;
298
Mika Kuoppalab620e872017-09-22 15:43:03 +0300299 if (unlikely(execlists->no_priolist))
Chris Wilson08dd3e12017-09-16 21:44:12 +0100300 prio = I915_PRIORITY_NORMAL;
301
302find_priolist:
303 /* most positive priority is scheduled first, equal priorities fifo */
304 rb = NULL;
Mika Kuoppalab620e872017-09-22 15:43:03 +0300305 parent = &execlists->queue.rb_node;
Chris Wilson08dd3e12017-09-16 21:44:12 +0100306 while (*parent) {
307 rb = *parent;
308 p = rb_entry(rb, typeof(*p), node);
309 if (prio > p->priority) {
310 parent = &rb->rb_left;
311 } else if (prio < p->priority) {
312 parent = &rb->rb_right;
313 first = false;
314 } else {
Chris Wilson27606fd2017-09-16 21:44:13 +0100315 return p;
Chris Wilson08dd3e12017-09-16 21:44:12 +0100316 }
317 }
318
319 if (prio == I915_PRIORITY_NORMAL) {
Mika Kuoppalab620e872017-09-22 15:43:03 +0300320 p = &execlists->default_priolist;
Chris Wilson08dd3e12017-09-16 21:44:12 +0100321 } else {
322 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
323 /* Convert an allocation failure to a priority bump */
324 if (unlikely(!p)) {
325 prio = I915_PRIORITY_NORMAL; /* recurses just once */
326
327 /* To maintain ordering with all rendering, after an
328 * allocation failure we have to disable all scheduling.
329 * Requests will then be executed in fifo, and schedule
330 * will ensure that dependencies are emitted in fifo.
331 * There will be still some reordering with existing
332 * requests, so if userspace lied about their
333 * dependencies that reordering may be visible.
334 */
Mika Kuoppalab620e872017-09-22 15:43:03 +0300335 execlists->no_priolist = true;
Chris Wilson08dd3e12017-09-16 21:44:12 +0100336 goto find_priolist;
337 }
338 }
339
340 p->priority = prio;
Chris Wilson27606fd2017-09-16 21:44:13 +0100341 INIT_LIST_HEAD(&p->requests);
Chris Wilson08dd3e12017-09-16 21:44:12 +0100342 rb_link_node(&p->node, rb, parent);
Mika Kuoppalab620e872017-09-22 15:43:03 +0300343 rb_insert_color(&p->node, &execlists->queue);
Chris Wilson08dd3e12017-09-16 21:44:12 +0100344
Chris Wilson08dd3e12017-09-16 21:44:12 +0100345 if (first)
Mika Kuoppalab620e872017-09-22 15:43:03 +0300346 execlists->first = &p->node;
Chris Wilson08dd3e12017-09-16 21:44:12 +0100347
Chris Wilson27606fd2017-09-16 21:44:13 +0100348 return ptr_pack_bits(p, first, 1);
Chris Wilson08dd3e12017-09-16 21:44:12 +0100349}
350
Chris Wilson7e4992a2017-09-28 20:38:59 +0100351static void unwind_wa_tail(struct drm_i915_gem_request *rq)
352{
353 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
354 assert_ring_tail_valid(rq->ring, rq->tail);
355}
356
357static void unwind_incomplete_requests(struct intel_engine_cs *engine)
358{
359 struct drm_i915_gem_request *rq, *rn;
Michał Winiarski097a9482017-09-28 20:39:01 +0100360 struct i915_priolist *uninitialized_var(p);
361 int last_prio = I915_PRIORITY_INVALID;
Chris Wilson7e4992a2017-09-28 20:38:59 +0100362
363 lockdep_assert_held(&engine->timeline->lock);
364
365 list_for_each_entry_safe_reverse(rq, rn,
366 &engine->timeline->requests,
367 link) {
Chris Wilson7e4992a2017-09-28 20:38:59 +0100368 if (i915_gem_request_completed(rq))
369 return;
370
371 __i915_gem_request_unsubmit(rq);
372 unwind_wa_tail(rq);
373
Michał Winiarski097a9482017-09-28 20:39:01 +0100374 GEM_BUG_ON(rq->priotree.priority == I915_PRIORITY_INVALID);
375 if (rq->priotree.priority != last_prio) {
376 p = lookup_priolist(engine,
377 &rq->priotree,
378 rq->priotree.priority);
379 p = ptr_mask_bits(p, 1);
380
381 last_prio = rq->priotree.priority;
382 }
383
384 list_add(&rq->priotree.link, &p->requests);
Chris Wilson7e4992a2017-09-28 20:38:59 +0100385 }
386}
387
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100388static inline void
389execlists_context_status_change(struct drm_i915_gem_request *rq,
390 unsigned long status)
Ben Widawsky84b790f2014-07-24 17:04:36 +0100391{
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100392 /*
393 * Only used when GVT-g is enabled now. When GVT-g is disabled,
394 * The compiler should eliminate this function as dead-code.
395 */
396 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
397 return;
Ben Widawsky84b790f2014-07-24 17:04:36 +0100398
Changbin Du3fc03062017-03-13 10:47:11 +0800399 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
400 status, rq);
Ben Widawsky84b790f2014-07-24 17:04:36 +0100401}
402
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000403static void
404execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
405{
406 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
407 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
408 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
409 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
410}
411
Chris Wilson70c2a242016-09-09 14:11:46 +0100412static u64 execlists_update_context(struct drm_i915_gem_request *rq)
Oscar Mateoae1250b2014-07-24 17:04:37 +0100413{
Chris Wilson70c2a242016-09-09 14:11:46 +0100414 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
Zhi Wang04da8112017-02-06 18:37:16 +0800415 struct i915_hw_ppgtt *ppgtt =
416 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
Chris Wilson70c2a242016-09-09 14:11:46 +0100417 u32 *reg_state = ce->lrc_reg_state;
Oscar Mateoae1250b2014-07-24 17:04:37 +0100418
Chris Wilsone6ba9992017-04-25 14:00:49 +0100419 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
Oscar Mateoae1250b2014-07-24 17:04:37 +0100420
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000421 /* True 32b PPGTT with dynamic page allocation: update PDP
422 * registers and point the unallocated PDPs to scratch page.
423 * PML4 is allocated during ppgtt init, so this is not needed
424 * in 48-bit mode.
425 */
Chris Wilson949e8ab2017-02-09 14:40:36 +0000426 if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000427 execlists_update_context_pdps(ppgtt, reg_state);
Chris Wilson70c2a242016-09-09 14:11:46 +0100428
429 return ce->lrc_desc;
Oscar Mateoae1250b2014-07-24 17:04:37 +0100430}
431
Chris Wilsonbeecec92017-10-03 21:34:52 +0100432static inline void elsp_write(u64 desc, u32 __iomem *elsp)
433{
434 writel(upper_32_bits(desc), elsp);
435 writel(lower_32_bits(desc), elsp);
436}
437
Chris Wilson70c2a242016-09-09 14:11:46 +0100438static void execlists_submit_ports(struct intel_engine_cs *engine)
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100439{
Mika Kuoppalab620e872017-09-22 15:43:03 +0300440 struct execlist_port *port = engine->execlists.port;
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100441 u32 __iomem *elsp =
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100442 engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
443 unsigned int n;
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100444
Mika Kuoppala76e70082017-09-22 15:43:07 +0300445 for (n = execlists_num_ports(&engine->execlists); n--; ) {
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100446 struct drm_i915_gem_request *rq;
447 unsigned int count;
448 u64 desc;
Chris Wilson70c2a242016-09-09 14:11:46 +0100449
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100450 rq = port_unpack(&port[n], &count);
451 if (rq) {
452 GEM_BUG_ON(count > !n);
453 if (!count++)
454 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
455 port_set(&port[n], port_pack(rq, count));
456 desc = execlists_update_context(rq);
457 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
458 } else {
459 GEM_BUG_ON(!n);
460 desc = 0;
461 }
462
Chris Wilsonbeecec92017-10-03 21:34:52 +0100463 elsp_write(desc, elsp);
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100464 }
Chris Wilsonbbd6c472016-09-09 14:11:45 +0100465}
466
Chris Wilson70c2a242016-09-09 14:11:46 +0100467static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
Ben Widawsky84b790f2014-07-24 17:04:36 +0100468{
Chris Wilson70c2a242016-09-09 14:11:46 +0100469 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
Chris Wilson60958682016-12-31 11:20:11 +0000470 i915_gem_context_force_single_submission(ctx));
Ben Widawsky84b790f2014-07-24 17:04:36 +0100471}
472
Chris Wilson70c2a242016-09-09 14:11:46 +0100473static bool can_merge_ctx(const struct i915_gem_context *prev,
474 const struct i915_gem_context *next)
Michel Thierryacdd8842014-07-24 17:04:38 +0100475{
Chris Wilson70c2a242016-09-09 14:11:46 +0100476 if (prev != next)
477 return false;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100478
Chris Wilson70c2a242016-09-09 14:11:46 +0100479 if (ctx_single_port_submission(prev))
480 return false;
Michel Thierryacdd8842014-07-24 17:04:38 +0100481
Chris Wilson70c2a242016-09-09 14:11:46 +0100482 return true;
483}
Peter Antoine779949f2015-05-11 16:03:27 +0100484
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100485static void port_assign(struct execlist_port *port,
486 struct drm_i915_gem_request *rq)
487{
488 GEM_BUG_ON(rq == port_request(port));
489
490 if (port_isset(port))
491 i915_gem_request_put(port_request(port));
492
493 port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
494}
495
Chris Wilsonbeecec92017-10-03 21:34:52 +0100496static void inject_preempt_context(struct intel_engine_cs *engine)
497{
498 struct intel_context *ce =
499 &engine->i915->preempt_context->engine[engine->id];
500 u32 __iomem *elsp =
501 engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
502 unsigned int n;
503
504 GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID);
505 GEM_BUG_ON(!IS_ALIGNED(ce->ring->size, WA_TAIL_BYTES));
506
507 memset(ce->ring->vaddr + ce->ring->tail, 0, WA_TAIL_BYTES);
508 ce->ring->tail += WA_TAIL_BYTES;
509 ce->ring->tail &= (ce->ring->size - 1);
510 ce->lrc_reg_state[CTX_RING_TAIL+1] = ce->ring->tail;
511
512 for (n = execlists_num_ports(&engine->execlists); --n; )
513 elsp_write(0, elsp);
514
515 elsp_write(ce->lrc_desc, elsp);
516}
517
518static bool can_preempt(struct intel_engine_cs *engine)
519{
520 return INTEL_INFO(engine->i915)->has_logical_ring_preemption;
521}
522
Chris Wilson70c2a242016-09-09 14:11:46 +0100523static void execlists_dequeue(struct intel_engine_cs *engine)
524{
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300525 struct intel_engine_execlists * const execlists = &engine->execlists;
526 struct execlist_port *port = execlists->port;
Mika Kuoppala76e70082017-09-22 15:43:07 +0300527 const struct execlist_port * const last_port =
528 &execlists->port[execlists->port_mask];
Chris Wilsonbeecec92017-10-03 21:34:52 +0100529 struct drm_i915_gem_request *last = port_request(port);
Chris Wilson20311bd2016-11-14 20:41:03 +0000530 struct rb_node *rb;
Chris Wilson70c2a242016-09-09 14:11:46 +0100531 bool submit = false;
Michel Thierryacdd8842014-07-24 17:04:38 +0100532
Chris Wilson70c2a242016-09-09 14:11:46 +0100533 /* Hardware submission is through 2 ports. Conceptually each port
534 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
535 * static for a context, and unique to each, so we only execute
536 * requests belonging to a single context from each ring. RING_HEAD
537 * is maintained by the CS in the context image, it marks the place
538 * where it got up to last time, and through RING_TAIL we tell the CS
539 * where we want to execute up to this time.
540 *
541 * In this list the requests are in order of execution. Consecutive
542 * requests from the same context are adjacent in the ringbuffer. We
543 * can combine these requests into a single RING_TAIL update:
544 *
545 * RING_HEAD...req1...req2
546 * ^- RING_TAIL
547 * since to execute req2 the CS must first execute req1.
548 *
549 * Our goal then is to point each port to the end of a consecutive
550 * sequence of requests as being the most optimal (fewest wake ups
551 * and context switches) submission.
552 */
553
Tvrtko Ursulin9f7886d2017-03-21 10:55:11 +0000554 spin_lock_irq(&engine->timeline->lock);
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300555 rb = execlists->first;
556 GEM_BUG_ON(rb_first(&execlists->queue) != rb);
Chris Wilsonbeecec92017-10-03 21:34:52 +0100557 if (!rb)
558 goto unlock;
559
560 if (last) {
561 /*
562 * Don't resubmit or switch until all outstanding
563 * preemptions (lite-restore) are seen. Then we
564 * know the next preemption status we see corresponds
565 * to this ELSP update.
566 */
567 if (port_count(&port[0]) > 1)
568 goto unlock;
569
570 if (can_preempt(engine) &&
571 rb_entry(rb, struct i915_priolist, node)->priority >
572 max(last->priotree.priority, 0)) {
573 /*
574 * Switch to our empty preempt context so
575 * the state of the GPU is known (idle).
576 */
577 inject_preempt_context(engine);
Chris Wilson4a118ec2017-10-23 22:32:36 +0100578 execlists_set_active(execlists,
579 EXECLISTS_ACTIVE_PREEMPT);
Chris Wilsonbeecec92017-10-03 21:34:52 +0100580 goto unlock;
581 } else {
582 /*
583 * In theory, we could coalesce more requests onto
584 * the second port (the first port is active, with
585 * no preemptions pending). However, that means we
586 * then have to deal with the possible lite-restore
587 * of the second port (as we submit the ELSP, there
588 * may be a context-switch) but also we may complete
589 * the resubmission before the context-switch. Ergo,
590 * coalescing onto the second port will cause a
591 * preemption event, but we cannot predict whether
592 * that will affect port[0] or port[1].
593 *
594 * If the second port is already active, we can wait
595 * until the next context-switch before contemplating
596 * new requests. The GPU will be busy and we should be
597 * able to resubmit the new ELSP before it idles,
598 * avoiding pipeline bubbles (momentary pauses where
599 * the driver is unable to keep up the supply of new
600 * work).
601 */
602 if (port_count(&port[1]))
603 goto unlock;
604
605 /* WaIdleLiteRestore:bdw,skl
606 * Apply the wa NOOPs to prevent
607 * ring:HEAD == req:TAIL as we resubmit the
608 * request. See gen8_emit_breadcrumb() for
609 * where we prepare the padding after the
610 * end of the request.
611 */
612 last->tail = last->wa_tail;
613 }
614 }
615
616 do {
Chris Wilson6c067572017-05-17 13:10:03 +0100617 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
618 struct drm_i915_gem_request *rq, *rn;
Chris Wilson20311bd2016-11-14 20:41:03 +0000619
Chris Wilson6c067572017-05-17 13:10:03 +0100620 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
621 /*
622 * Can we combine this request with the current port?
623 * It has to be the same context/ringbuffer and not
624 * have any exceptions (e.g. GVT saying never to
625 * combine contexts).
626 *
627 * If we can combine the requests, we can execute both
628 * by updating the RING_TAIL to point to the end of the
629 * second request, and so we never need to tell the
630 * hardware about the first.
Chris Wilson70c2a242016-09-09 14:11:46 +0100631 */
Chris Wilson6c067572017-05-17 13:10:03 +0100632 if (last && !can_merge_ctx(rq->ctx, last->ctx)) {
633 /*
634 * If we are on the second port and cannot
635 * combine this request with the last, then we
636 * are done.
637 */
Mika Kuoppala76e70082017-09-22 15:43:07 +0300638 if (port == last_port) {
Chris Wilson6c067572017-05-17 13:10:03 +0100639 __list_del_many(&p->requests,
640 &rq->priotree.link);
641 goto done;
642 }
Chris Wilson70c2a242016-09-09 14:11:46 +0100643
Chris Wilson6c067572017-05-17 13:10:03 +0100644 /*
645 * If GVT overrides us we only ever submit
646 * port[0], leaving port[1] empty. Note that we
647 * also have to be careful that we don't queue
648 * the same context (even though a different
649 * request) to the second port.
650 */
651 if (ctx_single_port_submission(last->ctx) ||
652 ctx_single_port_submission(rq->ctx)) {
653 __list_del_many(&p->requests,
654 &rq->priotree.link);
655 goto done;
656 }
Chris Wilson70c2a242016-09-09 14:11:46 +0100657
Chris Wilson6c067572017-05-17 13:10:03 +0100658 GEM_BUG_ON(last->ctx == rq->ctx);
Chris Wilson70c2a242016-09-09 14:11:46 +0100659
Chris Wilson6c067572017-05-17 13:10:03 +0100660 if (submit)
661 port_assign(port, last);
662 port++;
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300663
664 GEM_BUG_ON(port_isset(port));
Chris Wilson6c067572017-05-17 13:10:03 +0100665 }
666
667 INIT_LIST_HEAD(&rq->priotree.link);
Chris Wilson6c067572017-05-17 13:10:03 +0100668 __i915_gem_request_submit(rq);
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300669 trace_i915_gem_request_in(rq, port_index(port, execlists));
Chris Wilson6c067572017-05-17 13:10:03 +0100670 last = rq;
671 submit = true;
Chris Wilson70c2a242016-09-09 14:11:46 +0100672 }
Chris Wilsond55ac5b2016-11-14 20:40:59 +0000673
Chris Wilson20311bd2016-11-14 20:41:03 +0000674 rb = rb_next(rb);
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300675 rb_erase(&p->node, &execlists->queue);
Chris Wilson6c067572017-05-17 13:10:03 +0100676 INIT_LIST_HEAD(&p->requests);
677 if (p->priority != I915_PRIORITY_NORMAL)
Chris Wilsonc5cf9a92017-05-17 13:10:04 +0100678 kmem_cache_free(engine->i915->priorities, p);
Chris Wilsonbeecec92017-10-03 21:34:52 +0100679 } while (rb);
Chris Wilson6c067572017-05-17 13:10:03 +0100680done:
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300681 execlists->first = rb;
Chris Wilson6c067572017-05-17 13:10:03 +0100682 if (submit)
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100683 port_assign(port, last);
Chris Wilsonbeecec92017-10-03 21:34:52 +0100684unlock:
Tvrtko Ursulin9f7886d2017-03-21 10:55:11 +0000685 spin_unlock_irq(&engine->timeline->lock);
Chris Wilson70c2a242016-09-09 14:11:46 +0100686
Chris Wilson4a118ec2017-10-23 22:32:36 +0100687 if (submit) {
688 execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
Chris Wilson70c2a242016-09-09 14:11:46 +0100689 execlists_submit_ports(engine);
Chris Wilson4a118ec2017-10-23 22:32:36 +0100690 }
Michel Thierryacdd8842014-07-24 17:04:38 +0100691}
692
Chris Wilson3f9e6cd2017-09-25 13:49:27 +0100693static void
694execlist_cancel_port_requests(struct intel_engine_execlists *execlists)
Mika Kuoppalacf4591d2017-09-22 15:43:05 +0300695{
Chris Wilson3f9e6cd2017-09-25 13:49:27 +0100696 struct execlist_port *port = execlists->port;
Mika Kuoppaladc2279e2017-10-10 14:48:57 +0300697 unsigned int num_ports = execlists_num_ports(execlists);
Mika Kuoppalacf4591d2017-09-22 15:43:05 +0300698
Chris Wilson3f9e6cd2017-09-25 13:49:27 +0100699 while (num_ports-- && port_isset(port)) {
Chris Wilson7e44fc22017-09-26 11:17:19 +0100700 struct drm_i915_gem_request *rq = port_request(port);
701
Chris Wilson4a118ec2017-10-23 22:32:36 +0100702 GEM_BUG_ON(!execlists->active);
Chris Wilsond6c05112017-10-03 21:34:47 +0100703 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_PREEMPTED);
Chris Wilson7e44fc22017-09-26 11:17:19 +0100704 i915_gem_request_put(rq);
705
Chris Wilson3f9e6cd2017-09-25 13:49:27 +0100706 memset(port, 0, sizeof(*port));
707 port++;
708 }
Mika Kuoppalacf4591d2017-09-22 15:43:05 +0300709}
710
Chris Wilson27a5f612017-09-15 18:31:00 +0100711static void execlists_cancel_requests(struct intel_engine_cs *engine)
712{
Mika Kuoppalab620e872017-09-22 15:43:03 +0300713 struct intel_engine_execlists * const execlists = &engine->execlists;
Chris Wilson27a5f612017-09-15 18:31:00 +0100714 struct drm_i915_gem_request *rq, *rn;
715 struct rb_node *rb;
716 unsigned long flags;
Chris Wilson27a5f612017-09-15 18:31:00 +0100717
718 spin_lock_irqsave(&engine->timeline->lock, flags);
719
720 /* Cancel the requests on the HW and clear the ELSP tracker. */
Mika Kuoppalacf4591d2017-09-22 15:43:05 +0300721 execlist_cancel_port_requests(execlists);
Chris Wilson27a5f612017-09-15 18:31:00 +0100722
723 /* Mark all executing requests as skipped. */
724 list_for_each_entry(rq, &engine->timeline->requests, link) {
725 GEM_BUG_ON(!rq->global_seqno);
726 if (!i915_gem_request_completed(rq))
727 dma_fence_set_error(&rq->fence, -EIO);
728 }
729
730 /* Flush the queued requests to the timeline list (for retiring). */
Mika Kuoppalab620e872017-09-22 15:43:03 +0300731 rb = execlists->first;
Chris Wilson27a5f612017-09-15 18:31:00 +0100732 while (rb) {
733 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
734
735 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
736 INIT_LIST_HEAD(&rq->priotree.link);
737 rq->priotree.priority = INT_MAX;
738
739 dma_fence_set_error(&rq->fence, -EIO);
740 __i915_gem_request_submit(rq);
741 }
742
743 rb = rb_next(rb);
Mika Kuoppalab620e872017-09-22 15:43:03 +0300744 rb_erase(&p->node, &execlists->queue);
Chris Wilson27a5f612017-09-15 18:31:00 +0100745 INIT_LIST_HEAD(&p->requests);
746 if (p->priority != I915_PRIORITY_NORMAL)
747 kmem_cache_free(engine->i915->priorities, p);
748 }
749
750 /* Remaining _unready_ requests will be nop'ed when submitted */
751
Mika Kuoppalacf4591d2017-09-22 15:43:05 +0300752
Mika Kuoppalab620e872017-09-22 15:43:03 +0300753 execlists->queue = RB_ROOT;
754 execlists->first = NULL;
Chris Wilson3f9e6cd2017-09-25 13:49:27 +0100755 GEM_BUG_ON(port_isset(execlists->port));
Chris Wilson27a5f612017-09-15 18:31:00 +0100756
757 /*
758 * The port is checked prior to scheduling a tasklet, but
759 * just in case we have suspended the tasklet to do the
760 * wedging make sure that when it wakes, it decides there
761 * is no work to do by clearing the irq_posted bit.
762 */
763 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
764
765 spin_unlock_irqrestore(&engine->timeline->lock, flags);
766}
767
Daniel Vetter6e5248b2016-07-15 21:48:06 +0200768/*
Oscar Mateo73e4d072014-07-24 17:04:48 +0100769 * Check the unread Context Status Buffers and manage the submission of new
770 * contexts to the ELSP accordingly.
771 */
Tvrtko Ursulin27af5ee2016-04-04 12:11:56 +0100772static void intel_lrc_irq_handler(unsigned long data)
Thomas Daniele981e7b2014-07-24 17:04:39 +0100773{
Mika Kuoppalab620e872017-09-22 15:43:03 +0300774 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
775 struct intel_engine_execlists * const execlists = &engine->execlists;
Chris Wilsonbeecec92017-10-03 21:34:52 +0100776 struct execlist_port * const port = execlists->port;
Chris Wilsonc0336662016-05-06 15:40:21 +0100777 struct drm_i915_private *dev_priv = engine->i915;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100778
Chris Wilson48921262017-04-11 18:58:50 +0100779 /* We can skip acquiring intel_runtime_pm_get() here as it was taken
780 * on our behalf by the request (see i915_gem_mark_busy()) and it will
781 * not be relinquished until the device is idle (see
782 * i915_gem_idle_work_handler()). As a precaution, we make sure
783 * that all ELSP are drained i.e. we have processed the CSB,
784 * before allowing ourselves to idle and calling intel_runtime_pm_put().
785 */
786 GEM_BUG_ON(!dev_priv->gt.awake);
787
Mika Kuoppalab620e872017-09-22 15:43:03 +0300788 intel_uncore_forcewake_get(dev_priv, execlists->fw_domains);
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000789
Chris Wilson899f6202017-03-21 11:33:20 +0000790 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
791 * imposing the cost of a locked atomic transaction when submitting a
792 * new request (outside of the context-switch interrupt).
793 */
794 while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
Chris Wilson6d2cb5a2017-09-13 14:35:34 +0100795 /* The HWSP contains a (cacheable) mirror of the CSB */
796 const u32 *buf =
797 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
Chris Wilson4af0d722017-03-25 20:10:53 +0000798 unsigned int head, tail;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100799
Mika Kuoppalab620e872017-09-22 15:43:03 +0300800 if (unlikely(execlists->csb_use_mmio)) {
Chris Wilson6d2cb5a2017-09-13 14:35:34 +0100801 buf = (u32 * __force)
802 (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
Mika Kuoppalab620e872017-09-22 15:43:03 +0300803 execlists->csb_head = -1; /* force mmio read of CSB ptrs */
Chris Wilson6d2cb5a2017-09-13 14:35:34 +0100804 }
805
Chris Wilson2e70b8c2017-03-23 13:48:03 +0000806 /* The write will be ordered by the uncached read (itself
807 * a memory barrier), so we do not need another in the form
808 * of a locked instruction. The race between the interrupt
809 * handler and the split test/clear is harmless as we order
810 * our clear before the CSB read. If the interrupt arrived
811 * first between the test and the clear, we read the updated
812 * CSB and clear the bit. If the interrupt arrives as we read
813 * the CSB or later (i.e. after we had cleared the bit) the bit
814 * is set and we do a new loop.
815 */
816 __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
Mika Kuoppalab620e872017-09-22 15:43:03 +0300817 if (unlikely(execlists->csb_head == -1)) { /* following a reset */
Chris Wilson767a9832017-09-13 09:56:05 +0100818 head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
819 tail = GEN8_CSB_WRITE_PTR(head);
820 head = GEN8_CSB_READ_PTR(head);
Mika Kuoppalab620e872017-09-22 15:43:03 +0300821 execlists->csb_head = head;
Chris Wilson767a9832017-09-13 09:56:05 +0100822 } else {
823 const int write_idx =
824 intel_hws_csb_write_index(dev_priv) -
825 I915_HWS_CSB_BUF0_INDEX;
826
Mika Kuoppalab620e872017-09-22 15:43:03 +0300827 head = execlists->csb_head;
Chris Wilson767a9832017-09-13 09:56:05 +0100828 tail = READ_ONCE(buf[write_idx]);
829 }
Mika Kuoppalab620e872017-09-22 15:43:03 +0300830
Chris Wilson4af0d722017-03-25 20:10:53 +0000831 while (head != tail) {
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100832 struct drm_i915_gem_request *rq;
Chris Wilson4af0d722017-03-25 20:10:53 +0000833 unsigned int status;
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100834 unsigned int count;
Chris Wilsona37951a2017-01-24 11:00:06 +0000835
Chris Wilson4af0d722017-03-25 20:10:53 +0000836 if (++head == GEN8_CSB_ENTRIES)
837 head = 0;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100838
Chris Wilson2ffe80a2017-02-06 17:05:02 +0000839 /* We are flying near dragons again.
840 *
841 * We hold a reference to the request in execlist_port[]
842 * but no more than that. We are operating in softirq
843 * context and so cannot hold any mutex or sleep. That
844 * prevents us stopping the requests we are processing
845 * in port[] from being retired simultaneously (the
846 * breadcrumb will be complete before we see the
847 * context-switch). As we only hold the reference to the
848 * request, any pointer chasing underneath the request
849 * is subject to a potential use-after-free. Thus we
850 * store all of the bookkeeping within port[] as
851 * required, and avoid using unguarded pointers beneath
852 * request itself. The same applies to the atomic
853 * status notifier.
854 */
855
Chris Wilson6d2cb5a2017-09-13 14:35:34 +0100856 status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
Chris Wilson70c2a242016-09-09 14:11:46 +0100857 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
858 continue;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100859
Chris Wilsonbeecec92017-10-03 21:34:52 +0100860 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE &&
861 buf[2*head + 1] == PREEMPT_ID) {
862 execlist_cancel_port_requests(execlists);
863
864 spin_lock_irq(&engine->timeline->lock);
865 unwind_incomplete_requests(engine);
866 spin_unlock_irq(&engine->timeline->lock);
867
Chris Wilson4a118ec2017-10-23 22:32:36 +0100868 GEM_BUG_ON(!execlists_is_active(execlists,
869 EXECLISTS_ACTIVE_PREEMPT));
870 execlists_clear_active(execlists,
871 EXECLISTS_ACTIVE_PREEMPT);
Chris Wilsonbeecec92017-10-03 21:34:52 +0100872 continue;
873 }
874
875 if (status & GEN8_CTX_STATUS_PREEMPTED &&
Chris Wilson4a118ec2017-10-23 22:32:36 +0100876 execlists_is_active(execlists,
877 EXECLISTS_ACTIVE_PREEMPT))
Chris Wilsonbeecec92017-10-03 21:34:52 +0100878 continue;
879
Chris Wilson4a118ec2017-10-23 22:32:36 +0100880 GEM_BUG_ON(!execlists_is_active(execlists,
881 EXECLISTS_ACTIVE_USER));
882
Chris Wilson86aa7e72017-01-23 11:31:32 +0000883 /* Check the context/desc id for this event matches */
Chris Wilson6d2cb5a2017-09-13 14:35:34 +0100884 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
Chris Wilson86aa7e72017-01-23 11:31:32 +0000885
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100886 rq = port_unpack(port, &count);
887 GEM_BUG_ON(count == 0);
888 if (--count == 0) {
Chris Wilson70c2a242016-09-09 14:11:46 +0100889 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100890 GEM_BUG_ON(!i915_gem_request_completed(rq));
891 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
Thomas Daniele981e7b2014-07-24 17:04:39 +0100892
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100893 trace_i915_gem_request_out(rq);
Chris Wilson1f181222017-10-03 21:34:50 +0100894 rq->priotree.priority = INT_MAX;
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100895 i915_gem_request_put(rq);
896
Mika Kuoppala7a62cc62017-09-22 15:43:06 +0300897 execlists_port_complete(execlists, port);
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100898 } else {
899 port_set(port, port_pack(rq, count));
Chris Wilson70c2a242016-09-09 14:11:46 +0100900 }
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000901
Chris Wilson77f0d0e2017-05-17 13:10:00 +0100902 /* After the final element, the hw should be idle */
903 GEM_BUG_ON(port_count(port) == 0 &&
Chris Wilson70c2a242016-09-09 14:11:46 +0100904 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
Chris Wilson4a118ec2017-10-23 22:32:36 +0100905 if (port_count(port) == 0)
906 execlists_clear_active(execlists,
907 EXECLISTS_ACTIVE_USER);
Chris Wilson4af0d722017-03-25 20:10:53 +0000908 }
Tvrtko Ursulin26720ab2016-03-17 12:59:46 +0000909
Mika Kuoppalab620e872017-09-22 15:43:03 +0300910 if (head != execlists->csb_head) {
911 execlists->csb_head = head;
Chris Wilson767a9832017-09-13 09:56:05 +0100912 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
913 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
914 }
Tvrtko Ursulin26720ab2016-03-17 12:59:46 +0000915 }
916
Chris Wilson4a118ec2017-10-23 22:32:36 +0100917 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
Chris Wilson70c2a242016-09-09 14:11:46 +0100918 execlists_dequeue(engine);
Tvrtko Ursulin26720ab2016-03-17 12:59:46 +0000919
Mika Kuoppalab620e872017-09-22 15:43:03 +0300920 intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
Thomas Daniele981e7b2014-07-24 17:04:39 +0100921}
922
Chris Wilson27606fd2017-09-16 21:44:13 +0100923static void insert_request(struct intel_engine_cs *engine,
924 struct i915_priotree *pt,
925 int prio)
926{
927 struct i915_priolist *p = lookup_priolist(engine, pt, prio);
928
929 list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
Chris Wilsonbeecec92017-10-03 21:34:52 +0100930 if (ptr_unmask_bits(p, 1))
Mika Kuoppalab620e872017-09-22 15:43:03 +0300931 tasklet_hi_schedule(&engine->execlists.irq_tasklet);
Chris Wilson27606fd2017-09-16 21:44:13 +0100932}
933
Chris Wilsonf4ea6bd2016-08-02 22:50:32 +0100934static void execlists_submit_request(struct drm_i915_gem_request *request)
Michel Thierryacdd8842014-07-24 17:04:38 +0100935{
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +0000936 struct intel_engine_cs *engine = request->engine;
Chris Wilson5590af32016-09-09 14:11:54 +0100937 unsigned long flags;
Michel Thierryacdd8842014-07-24 17:04:38 +0100938
Chris Wilson663f71e2016-11-14 20:41:00 +0000939 /* Will be called from irq-context when using foreign fences. */
940 spin_lock_irqsave(&engine->timeline->lock, flags);
Michel Thierryacdd8842014-07-24 17:04:38 +0100941
Chris Wilson27606fd2017-09-16 21:44:13 +0100942 insert_request(engine, &request->priotree, request->priotree.priority);
Michel Thierryacdd8842014-07-24 17:04:38 +0100943
Mika Kuoppalab620e872017-09-22 15:43:03 +0300944 GEM_BUG_ON(!engine->execlists.first);
Chris Wilson6c067572017-05-17 13:10:03 +0100945 GEM_BUG_ON(list_empty(&request->priotree.link));
946
Chris Wilson663f71e2016-11-14 20:41:00 +0000947 spin_unlock_irqrestore(&engine->timeline->lock, flags);
Michel Thierryacdd8842014-07-24 17:04:38 +0100948}
949
Chris Wilson1f181222017-10-03 21:34:50 +0100950static struct drm_i915_gem_request *pt_to_request(struct i915_priotree *pt)
951{
952 return container_of(pt, struct drm_i915_gem_request, priotree);
953}
954
Chris Wilson20311bd2016-11-14 20:41:03 +0000955static struct intel_engine_cs *
956pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
957{
Chris Wilson1f181222017-10-03 21:34:50 +0100958 struct intel_engine_cs *engine = pt_to_request(pt)->engine;
Chris Wilson20311bd2016-11-14 20:41:03 +0000959
Chris Wilsona79a5242017-03-27 21:21:43 +0100960 GEM_BUG_ON(!locked);
961
Chris Wilson20311bd2016-11-14 20:41:03 +0000962 if (engine != locked) {
Chris Wilsona79a5242017-03-27 21:21:43 +0100963 spin_unlock(&locked->timeline->lock);
964 spin_lock(&engine->timeline->lock);
Chris Wilson20311bd2016-11-14 20:41:03 +0000965 }
966
967 return engine;
968}
969
970static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
971{
Chris Wilsona79a5242017-03-27 21:21:43 +0100972 struct intel_engine_cs *engine;
Chris Wilson20311bd2016-11-14 20:41:03 +0000973 struct i915_dependency *dep, *p;
974 struct i915_dependency stack;
975 LIST_HEAD(dfs);
976
Chris Wilson7d1ea602017-09-28 20:39:00 +0100977 GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
978
Chris Wilson20311bd2016-11-14 20:41:03 +0000979 if (prio <= READ_ONCE(request->priotree.priority))
980 return;
981
Chris Wilson70cd1472016-11-28 14:36:49 +0000982 /* Need BKL in order to use the temporary link inside i915_dependency */
983 lockdep_assert_held(&request->i915->drm.struct_mutex);
Chris Wilson20311bd2016-11-14 20:41:03 +0000984
985 stack.signaler = &request->priotree;
986 list_add(&stack.dfs_link, &dfs);
987
988 /* Recursively bump all dependent priorities to match the new request.
989 *
990 * A naive approach would be to use recursion:
991 * static void update_priorities(struct i915_priotree *pt, prio) {
992 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
993 * update_priorities(dep->signal, prio)
994 * insert_request(pt);
995 * }
996 * but that may have unlimited recursion depth and so runs a very
997 * real risk of overunning the kernel stack. Instead, we build
998 * a flat list of all dependencies starting with the current request.
999 * As we walk the list of dependencies, we add all of its dependencies
1000 * to the end of the list (this may include an already visited
1001 * request) and continue to walk onwards onto the new dependencies. The
1002 * end result is a topological list of requests in reverse order, the
1003 * last element in the list is the request we must execute first.
1004 */
1005 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
1006 struct i915_priotree *pt = dep->signaler;
1007
Chris Wilsona79a5242017-03-27 21:21:43 +01001008 /* Within an engine, there can be no cycle, but we may
1009 * refer to the same dependency chain multiple times
1010 * (redundant dependencies are not eliminated) and across
1011 * engines.
1012 */
1013 list_for_each_entry(p, &pt->signalers_list, signal_link) {
Chris Wilson1f181222017-10-03 21:34:50 +01001014 if (i915_gem_request_completed(pt_to_request(p->signaler)))
1015 continue;
1016
Chris Wilsona79a5242017-03-27 21:21:43 +01001017 GEM_BUG_ON(p->signaler->priority < pt->priority);
Chris Wilson20311bd2016-11-14 20:41:03 +00001018 if (prio > READ_ONCE(p->signaler->priority))
1019 list_move_tail(&p->dfs_link, &dfs);
Chris Wilsona79a5242017-03-27 21:21:43 +01001020 }
Chris Wilson20311bd2016-11-14 20:41:03 +00001021
Chris Wilson0798cff2016-12-05 14:29:41 +00001022 list_safe_reset_next(dep, p, dfs_link);
Chris Wilson20311bd2016-11-14 20:41:03 +00001023 }
1024
Chris Wilson349bdb62017-05-17 13:10:05 +01001025 /* If we didn't need to bump any existing priorities, and we haven't
1026 * yet submitted this request (i.e. there is no potential race with
1027 * execlists_submit_request()), we can set our own priority and skip
1028 * acquiring the engine locks.
1029 */
Chris Wilson7d1ea602017-09-28 20:39:00 +01001030 if (request->priotree.priority == I915_PRIORITY_INVALID) {
Chris Wilson349bdb62017-05-17 13:10:05 +01001031 GEM_BUG_ON(!list_empty(&request->priotree.link));
1032 request->priotree.priority = prio;
1033 if (stack.dfs_link.next == stack.dfs_link.prev)
1034 return;
1035 __list_del_entry(&stack.dfs_link);
1036 }
1037
Chris Wilsona79a5242017-03-27 21:21:43 +01001038 engine = request->engine;
1039 spin_lock_irq(&engine->timeline->lock);
1040
Chris Wilson20311bd2016-11-14 20:41:03 +00001041 /* Fifo and depth-first replacement ensure our deps execute before us */
1042 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1043 struct i915_priotree *pt = dep->signaler;
1044
1045 INIT_LIST_HEAD(&dep->dfs_link);
1046
1047 engine = pt_lock_engine(pt, engine);
1048
1049 if (prio <= pt->priority)
1050 continue;
1051
Chris Wilson20311bd2016-11-14 20:41:03 +00001052 pt->priority = prio;
Chris Wilson6c067572017-05-17 13:10:03 +01001053 if (!list_empty(&pt->link)) {
1054 __list_del_entry(&pt->link);
1055 insert_request(engine, pt, prio);
Chris Wilsona79a5242017-03-27 21:21:43 +01001056 }
Chris Wilson20311bd2016-11-14 20:41:03 +00001057 }
1058
Chris Wilsona79a5242017-03-27 21:21:43 +01001059 spin_unlock_irq(&engine->timeline->lock);
Chris Wilson20311bd2016-11-14 20:41:03 +00001060}
1061
Chris Wilson266a2402017-05-04 10:33:08 +01001062static struct intel_ring *
1063execlists_context_pin(struct intel_engine_cs *engine,
1064 struct i915_gem_context *ctx)
Oscar Mateodcb4c122014-11-13 10:28:10 +00001065{
Chris Wilson9021ad02016-05-24 14:53:37 +01001066 struct intel_context *ce = &ctx->engine[engine->id];
Chris Wilson2947e402016-12-18 15:37:23 +00001067 unsigned int flags;
Tvrtko Ursulin7d774ca2016-04-12 15:40:42 +01001068 void *vaddr;
Tvrtko Ursulinca825802016-01-15 15:10:27 +00001069 int ret;
Oscar Mateodcb4c122014-11-13 10:28:10 +00001070
Chris Wilson91c8a322016-07-05 10:40:23 +01001071 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
Tvrtko Ursulinca825802016-01-15 15:10:27 +00001072
Chris Wilson266a2402017-05-04 10:33:08 +01001073 if (likely(ce->pin_count++))
1074 goto out;
Chris Wilsona533b4b2017-03-16 17:16:28 +00001075 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
Chris Wilson24f1d3c2016-04-28 09:56:53 +01001076
Chris Wilsone8a9c582016-12-18 15:37:20 +00001077 if (!ce->state) {
1078 ret = execlists_context_deferred_alloc(ctx, engine);
1079 if (ret)
1080 goto err;
1081 }
Chris Wilson56f6e0a2017-01-05 15:30:20 +00001082 GEM_BUG_ON(!ce->state);
Chris Wilsone8a9c582016-12-18 15:37:20 +00001083
Chris Wilson72b72ae2017-02-10 10:14:22 +00001084 flags = PIN_GLOBAL | PIN_HIGH;
Daniele Ceraolo Spuriofeef2a72016-12-23 15:56:22 -08001085 if (ctx->ggtt_offset_bias)
1086 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
Chris Wilson2947e402016-12-18 15:37:23 +00001087
1088 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
Nick Hoathe84fe802015-09-11 12:53:46 +01001089 if (ret)
Chris Wilson24f1d3c2016-04-28 09:56:53 +01001090 goto err;
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001091
Chris Wilsonbf3783e2016-08-15 10:48:54 +01001092 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
Tvrtko Ursulin7d774ca2016-04-12 15:40:42 +01001093 if (IS_ERR(vaddr)) {
1094 ret = PTR_ERR(vaddr);
Chris Wilsonbf3783e2016-08-15 10:48:54 +01001095 goto unpin_vma;
Tvrtko Ursulin82352e92016-01-15 17:12:45 +00001096 }
1097
Chris Wilsond822bb12017-04-03 12:34:25 +01001098 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
Nick Hoathe84fe802015-09-11 12:53:46 +01001099 if (ret)
Tvrtko Ursulin7d774ca2016-04-12 15:40:42 +01001100 goto unpin_map;
Alex Daid1675192015-08-12 15:43:43 +01001101
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001102 intel_lr_context_descriptor_update(ctx, engine);
Chris Wilson9021ad02016-05-24 14:53:37 +01001103
Chris Wilsona3aabe82016-10-04 21:11:26 +01001104 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1105 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
Chris Wilsonbde13eb2016-08-15 10:49:07 +01001106 i915_ggtt_offset(ce->ring->vma);
Chris Wilsona3aabe82016-10-04 21:11:26 +01001107
Chris Wilsona4f5ea62016-10-28 13:58:35 +01001108 ce->state->obj->mm.dirty = true;
Chris Wilson3d574a62017-10-13 21:26:16 +01001109 ce->state->obj->pin_global++;
Daniel Vettere93c28f2015-09-02 14:33:42 +02001110
Chris Wilson9a6feaf2016-07-20 13:31:50 +01001111 i915_gem_context_get(ctx);
Chris Wilson266a2402017-05-04 10:33:08 +01001112out:
1113 return ce->ring;
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001114
Tvrtko Ursulin7d774ca2016-04-12 15:40:42 +01001115unpin_map:
Chris Wilsonbf3783e2016-08-15 10:48:54 +01001116 i915_gem_object_unpin_map(ce->state->obj);
1117unpin_vma:
1118 __i915_vma_unpin(ce->state);
Chris Wilson24f1d3c2016-04-28 09:56:53 +01001119err:
Chris Wilson9021ad02016-05-24 14:53:37 +01001120 ce->pin_count = 0;
Chris Wilson266a2402017-05-04 10:33:08 +01001121 return ERR_PTR(ret);
Oscar Mateodcb4c122014-11-13 10:28:10 +00001122}
1123
Chris Wilsone8a9c582016-12-18 15:37:20 +00001124static void execlists_context_unpin(struct intel_engine_cs *engine,
1125 struct i915_gem_context *ctx)
Oscar Mateodcb4c122014-11-13 10:28:10 +00001126{
Chris Wilson9021ad02016-05-24 14:53:37 +01001127 struct intel_context *ce = &ctx->engine[engine->id];
Daniel Vetteraf3302b2015-12-04 17:27:15 +01001128
Chris Wilson91c8a322016-07-05 10:40:23 +01001129 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
Chris Wilson9021ad02016-05-24 14:53:37 +01001130 GEM_BUG_ON(ce->pin_count == 0);
Tvrtko Ursulin321fe302016-01-28 10:29:55 +00001131
Chris Wilson9021ad02016-05-24 14:53:37 +01001132 if (--ce->pin_count)
Chris Wilson24f1d3c2016-04-28 09:56:53 +01001133 return;
1134
Chris Wilsonaad29fb2016-08-02 22:50:23 +01001135 intel_ring_unpin(ce->ring);
Chris Wilson24f1d3c2016-04-28 09:56:53 +01001136
Chris Wilson3d574a62017-10-13 21:26:16 +01001137 ce->state->obj->pin_global--;
Chris Wilsonbf3783e2016-08-15 10:48:54 +01001138 i915_gem_object_unpin_map(ce->state->obj);
1139 i915_vma_unpin(ce->state);
Chris Wilson24f1d3c2016-04-28 09:56:53 +01001140
Chris Wilson9a6feaf2016-07-20 13:31:50 +01001141 i915_gem_context_put(ctx);
Oscar Mateodcb4c122014-11-13 10:28:10 +00001142}
1143
Chris Wilsonf73e7392016-12-18 15:37:24 +00001144static int execlists_request_alloc(struct drm_i915_gem_request *request)
Chris Wilsonef11c012016-12-18 15:37:19 +00001145{
1146 struct intel_engine_cs *engine = request->engine;
1147 struct intel_context *ce = &request->ctx->engine[engine->id];
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001148 u32 *cs;
Chris Wilsonef11c012016-12-18 15:37:19 +00001149 int ret;
1150
Chris Wilsone8a9c582016-12-18 15:37:20 +00001151 GEM_BUG_ON(!ce->pin_count);
1152
Chris Wilsonef11c012016-12-18 15:37:19 +00001153 /* Flush enough space to reduce the likelihood of waiting after
1154 * we start building the request - in which case we will just
1155 * have to repeat work.
1156 */
1157 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1158
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001159 cs = intel_ring_begin(request, 0);
Michał Winiarski85e2fe62017-09-14 10:32:13 +02001160 if (IS_ERR(cs))
1161 return PTR_ERR(cs);
Chris Wilsonef11c012016-12-18 15:37:19 +00001162
1163 if (!ce->initialised) {
1164 ret = engine->init_context(request);
1165 if (ret)
Michał Winiarski85e2fe62017-09-14 10:32:13 +02001166 return ret;
Chris Wilsonef11c012016-12-18 15:37:19 +00001167
1168 ce->initialised = true;
1169 }
1170
1171 /* Note that after this point, we have committed to using
1172 * this request as it is being used to both track the
1173 * state of engine initialisation and liveness of the
1174 * golden renderstate above. Think twice before you try
1175 * to cancel/unwind this request now.
1176 */
1177
1178 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1179 return 0;
Chris Wilsonef11c012016-12-18 15:37:19 +00001180}
1181
Arun Siluvery9e000842015-07-03 14:27:31 +01001182/*
1183 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1184 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1185 * but there is a slight complication as this is applied in WA batch where the
1186 * values are only initialized once so we cannot take register value at the
1187 * beginning and reuse it further; hence we save its value to memory, upload a
1188 * constant value with bit21 set and then we restore it back with the saved value.
1189 * To simplify the WA, a constant value is formed by using the default value
1190 * of this register. This shouldn't be a problem because we are only modifying
1191 * it for a short period and this batch in non-premptible. We can ofcourse
1192 * use additional instructions that read the actual value of the register
1193 * at that time and set our bit of interest but it makes the WA complicated.
1194 *
1195 * This WA is also required for Gen9 so extracting as a function avoids
1196 * code duplication.
1197 */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001198static u32 *
1199gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
Arun Siluvery9e000842015-07-03 14:27:31 +01001200{
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001201 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1202 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1203 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1204 *batch++ = 0;
Arun Siluvery9e000842015-07-03 14:27:31 +01001205
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001206 *batch++ = MI_LOAD_REGISTER_IMM(1);
1207 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1208 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
Arun Siluvery9e000842015-07-03 14:27:31 +01001209
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001210 batch = gen8_emit_pipe_control(batch,
1211 PIPE_CONTROL_CS_STALL |
1212 PIPE_CONTROL_DC_FLUSH_ENABLE,
1213 0);
Arun Siluvery9e000842015-07-03 14:27:31 +01001214
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001215 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1216 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1217 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1218 *batch++ = 0;
Arun Siluvery9e000842015-07-03 14:27:31 +01001219
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001220 return batch;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001221}
1222
Daniel Vetter6e5248b2016-07-15 21:48:06 +02001223/*
1224 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1225 * initialized at the beginning and shared across all contexts but this field
1226 * helps us to have multiple batches at different offsets and select them based
1227 * on a criteria. At the moment this batch always start at the beginning of the page
1228 * and at this point we don't have multiple wa_ctx batch buffers.
Arun Siluvery17ee9502015-06-19 19:07:01 +01001229 *
Daniel Vetter6e5248b2016-07-15 21:48:06 +02001230 * The number of WA applied are not known at the beginning; we use this field
1231 * to return the no of DWORDS written.
Arun Siluvery17ee9502015-06-19 19:07:01 +01001232 *
Daniel Vetter6e5248b2016-07-15 21:48:06 +02001233 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1234 * so it adds NOOPs as padding to make it cacheline aligned.
1235 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1236 * makes a complete batch buffer.
Arun Siluvery17ee9502015-06-19 19:07:01 +01001237 */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001238static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
Arun Siluvery17ee9502015-06-19 19:07:01 +01001239{
Arun Siluvery7ad00d12015-06-19 18:37:12 +01001240 /* WaDisableCtxRestoreArbitration:bdw,chv */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001241 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001242
Arun Siluveryc82435b2015-06-19 18:37:13 +01001243 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001244 if (IS_BROADWELL(engine->i915))
1245 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
Arun Siluveryc82435b2015-06-19 18:37:13 +01001246
Arun Siluvery0160f052015-06-23 15:46:57 +01001247 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1248 /* Actual scratch location is at 128 bytes offset */
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001249 batch = gen8_emit_pipe_control(batch,
1250 PIPE_CONTROL_FLUSH_L3 |
1251 PIPE_CONTROL_GLOBAL_GTT_IVB |
1252 PIPE_CONTROL_CS_STALL |
1253 PIPE_CONTROL_QW_WRITE,
1254 i915_ggtt_offset(engine->scratch) +
1255 2 * CACHELINE_BYTES);
Arun Siluvery0160f052015-06-23 15:46:57 +01001256
Chris Wilsonbeecec92017-10-03 21:34:52 +01001257 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1258
Arun Siluvery17ee9502015-06-19 19:07:01 +01001259 /* Pad to end of cacheline */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001260 while ((unsigned long)batch % CACHELINE_BYTES)
1261 *batch++ = MI_NOOP;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001262
1263 /*
1264 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1265 * execution depends on the length specified in terms of cache lines
1266 * in the register CTX_RCS_INDIRECT_CTX
1267 */
1268
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001269 return batch;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001270}
1271
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001272static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
Arun Siluvery0504cff2015-07-14 15:01:27 +01001273{
Chris Wilsonbeecec92017-10-03 21:34:52 +01001274 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1275
Ander Conselvan de Oliveira9fb50262017-01-26 11:16:58 +02001276 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001277 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
Arun Siluverya4106a72015-07-14 15:01:29 +01001278
Ander Conselvan de Oliveira9fb50262017-01-26 11:16:58 +02001279 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001280 *batch++ = MI_LOAD_REGISTER_IMM(1);
1281 *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1282 *batch++ = _MASKED_BIT_DISABLE(
1283 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1284 *batch++ = MI_NOOP;
Mika Kuoppala873e8172016-07-20 14:26:13 +03001285
Mika Kuoppala066d4622016-06-07 17:19:15 +03001286 /* WaClearSlmSpaceAtContextSwitch:kbl */
1287 /* Actual scratch location is at 128 bytes offset */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001288 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001289 batch = gen8_emit_pipe_control(batch,
1290 PIPE_CONTROL_FLUSH_L3 |
1291 PIPE_CONTROL_GLOBAL_GTT_IVB |
1292 PIPE_CONTROL_CS_STALL |
1293 PIPE_CONTROL_QW_WRITE,
1294 i915_ggtt_offset(engine->scratch)
1295 + 2 * CACHELINE_BYTES);
Mika Kuoppala066d4622016-06-07 17:19:15 +03001296 }
Tim Gore3485d992016-07-05 10:01:30 +01001297
Ander Conselvan de Oliveira9fb50262017-01-26 11:16:58 +02001298 /* WaMediaPoolStateCmdInWABB:bxt,glk */
Tim Gore3485d992016-07-05 10:01:30 +01001299 if (HAS_POOLED_EU(engine->i915)) {
1300 /*
1301 * EU pool configuration is setup along with golden context
1302 * during context initialization. This value depends on
1303 * device type (2x6 or 3x6) and needs to be updated based
1304 * on which subslice is disabled especially for 2x6
1305 * devices, however it is safe to load default
1306 * configuration of 3x6 device instead of masking off
1307 * corresponding bits because HW ignores bits of a disabled
1308 * subslice and drops down to appropriate config. Please
1309 * see render_state_setup() in i915_gem_render_state.c for
1310 * possible configurations, to avoid duplication they are
1311 * not shown here again.
1312 */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001313 *batch++ = GEN9_MEDIA_POOL_STATE;
1314 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1315 *batch++ = 0x00777000;
1316 *batch++ = 0;
1317 *batch++ = 0;
1318 *batch++ = 0;
Tim Gore3485d992016-07-05 10:01:30 +01001319 }
1320
Chris Wilsonbeecec92017-10-03 21:34:52 +01001321 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1322
Arun Siluvery0504cff2015-07-14 15:01:27 +01001323 /* Pad to end of cacheline */
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001324 while ((unsigned long)batch % CACHELINE_BYTES)
1325 *batch++ = MI_NOOP;
Arun Siluvery0504cff2015-07-14 15:01:27 +01001326
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001327 return batch;
Arun Siluvery0504cff2015-07-14 15:01:27 +01001328}
1329
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001330#define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1331
1332static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
Arun Siluvery17ee9502015-06-19 19:07:01 +01001333{
Chris Wilson48bb74e2016-08-15 10:49:04 +01001334 struct drm_i915_gem_object *obj;
1335 struct i915_vma *vma;
1336 int err;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001337
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001338 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
Chris Wilson48bb74e2016-08-15 10:49:04 +01001339 if (IS_ERR(obj))
1340 return PTR_ERR(obj);
1341
Chris Wilsona01cb372017-01-16 15:21:30 +00001342 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
Chris Wilson48bb74e2016-08-15 10:49:04 +01001343 if (IS_ERR(vma)) {
1344 err = PTR_ERR(vma);
1345 goto err;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001346 }
1347
Chris Wilson48bb74e2016-08-15 10:49:04 +01001348 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1349 if (err)
1350 goto err;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001351
Chris Wilson48bb74e2016-08-15 10:49:04 +01001352 engine->wa_ctx.vma = vma;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001353 return 0;
Chris Wilson48bb74e2016-08-15 10:49:04 +01001354
1355err:
1356 i915_gem_object_put(obj);
1357 return err;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001358}
1359
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001360static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
Arun Siluvery17ee9502015-06-19 19:07:01 +01001361{
Chris Wilson19880c42016-08-15 10:49:05 +01001362 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
Arun Siluvery17ee9502015-06-19 19:07:01 +01001363}
1364
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001365typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1366
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001367static int intel_init_workaround_bb(struct intel_engine_cs *engine)
Arun Siluvery17ee9502015-06-19 19:07:01 +01001368{
Chris Wilson48bb74e2016-08-15 10:49:04 +01001369 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001370 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1371 &wa_ctx->per_ctx };
1372 wa_bb_func_t wa_bb_fn[2];
Arun Siluvery17ee9502015-06-19 19:07:01 +01001373 struct page *page;
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001374 void *batch, *batch_ptr;
1375 unsigned int i;
Chris Wilson48bb74e2016-08-15 10:49:04 +01001376 int ret;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001377
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001378 if (WARN_ON(engine->id != RCS || !engine->scratch))
1379 return -EINVAL;
Arun Siluvery17ee9502015-06-19 19:07:01 +01001380
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001381 switch (INTEL_GEN(engine->i915)) {
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07001382 case 10:
1383 return 0;
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001384 case 9:
1385 wa_bb_fn[0] = gen9_init_indirectctx_bb;
Chris Wilsonb8aa2232017-09-21 14:54:44 +01001386 wa_bb_fn[1] = NULL;
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001387 break;
1388 case 8:
1389 wa_bb_fn[0] = gen8_init_indirectctx_bb;
Chris Wilson3ad7b522017-10-03 21:34:49 +01001390 wa_bb_fn[1] = NULL;
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001391 break;
1392 default:
1393 MISSING_CASE(INTEL_GEN(engine->i915));
Arun Siluvery5e60d792015-06-23 15:50:44 +01001394 return 0;
Arun Siluvery0504cff2015-07-14 15:01:27 +01001395 }
Arun Siluvery5e60d792015-06-23 15:50:44 +01001396
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001397 ret = lrc_setup_wa_ctx(engine);
Arun Siluvery17ee9502015-06-19 19:07:01 +01001398 if (ret) {
1399 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1400 return ret;
1401 }
1402
Chris Wilson48bb74e2016-08-15 10:49:04 +01001403 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001404 batch = batch_ptr = kmap_atomic(page);
Arun Siluvery17ee9502015-06-19 19:07:01 +01001405
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001406 /*
1407 * Emit the two workaround batch buffers, recording the offset from the
1408 * start of the workaround batch buffer object for each and their
1409 * respective sizes.
1410 */
1411 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1412 wa_bb[i]->offset = batch_ptr - batch;
1413 if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) {
1414 ret = -EINVAL;
1415 break;
1416 }
Chris Wilson604a8f62017-09-21 14:54:43 +01001417 if (wa_bb_fn[i])
1418 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001419 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
Arun Siluvery17ee9502015-06-19 19:07:01 +01001420 }
1421
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001422 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1423
Arun Siluvery17ee9502015-06-19 19:07:01 +01001424 kunmap_atomic(batch);
1425 if (ret)
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001426 lrc_destroy_wa_ctx(engine);
Arun Siluvery17ee9502015-06-19 19:07:01 +01001427
1428 return ret;
1429}
1430
Chris Wilson64f09f02017-08-07 13:19:19 +01001431static u8 gtiir[] = {
1432 [RCS] = 0,
1433 [BCS] = 0,
1434 [VCS] = 1,
1435 [VCS2] = 1,
1436 [VECS] = 3,
1437};
1438
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001439static int gen8_init_common_ring(struct intel_engine_cs *engine)
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001440{
Chris Wilsonc0336662016-05-06 15:40:21 +01001441 struct drm_i915_private *dev_priv = engine->i915;
Mika Kuoppalab620e872017-09-22 15:43:03 +03001442 struct intel_engine_execlists * const execlists = &engine->execlists;
Chris Wilson821ed7d2016-09-09 14:11:53 +01001443 int ret;
1444
1445 ret = intel_mocs_init_engine(engine);
1446 if (ret)
1447 return ret;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001448
Chris Wilsonad07dfc2016-10-07 07:53:26 +01001449 intel_engine_reset_breadcrumbs(engine);
Chris Wilsonf3b8f912017-01-05 15:30:21 +00001450 intel_engine_init_hangcheck(engine);
Chris Wilson821ed7d2016-09-09 14:11:53 +01001451
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001452 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001453 I915_WRITE(RING_MODE_GEN7(engine),
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001454 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
Chris Wilsonf3b8f912017-01-05 15:30:21 +00001455 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1456 engine->status_page.ggtt_offset);
1457 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
Michel Thierrydfc53c52015-09-28 13:25:12 +01001458
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001459 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001460
Chris Wilson64f09f02017-08-07 13:19:19 +01001461 GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
1462
1463 /*
1464 * Clear any pending interrupt state.
1465 *
1466 * We do it twice out of paranoia that some of the IIR are double
1467 * buffered, and if we only reset it once there may still be
1468 * an interrupt pending.
1469 */
1470 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1471 GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1472 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1473 GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
Chris Wilsonf7470262017-01-24 15:20:21 +00001474 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
Mika Kuoppalab620e872017-09-22 15:43:03 +03001475 execlists->csb_head = -1;
Chris Wilson4a118ec2017-10-23 22:32:36 +01001476 execlists->active = 0;
Chris Wilson6b764a52017-04-25 11:38:35 +01001477
Chris Wilson64f09f02017-08-07 13:19:19 +01001478 /* After a GPU reset, we may have requests to replay */
Mika Kuoppalab620e872017-09-22 15:43:03 +03001479 if (!i915_modparams.enable_guc_submission && execlists->first)
1480 tasklet_schedule(&execlists->irq_tasklet);
Chris Wilson6b764a52017-04-25 11:38:35 +01001481
Chris Wilson821ed7d2016-09-09 14:11:53 +01001482 return 0;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001483}
1484
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001485static int gen8_init_render_ring(struct intel_engine_cs *engine)
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001486{
Chris Wilsonc0336662016-05-06 15:40:21 +01001487 struct drm_i915_private *dev_priv = engine->i915;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001488 int ret;
1489
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001490 ret = gen8_init_common_ring(engine);
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001491 if (ret)
1492 return ret;
1493
1494 /* We need to disable the AsyncFlip performance optimisations in order
1495 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1496 * programmed to '1' on all products.
1497 *
1498 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1499 */
1500 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1501
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001502 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1503
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001504 return init_workarounds_ring(engine);
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001505}
1506
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001507static int gen9_init_render_ring(struct intel_engine_cs *engine)
Damien Lespiau82ef8222015-02-09 19:33:08 +00001508{
1509 int ret;
1510
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001511 ret = gen8_init_common_ring(engine);
Damien Lespiau82ef8222015-02-09 19:33:08 +00001512 if (ret)
1513 return ret;
1514
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001515 return init_workarounds_ring(engine);
Damien Lespiau82ef8222015-02-09 19:33:08 +00001516}
1517
Chris Wilson821ed7d2016-09-09 14:11:53 +01001518static void reset_common_ring(struct intel_engine_cs *engine,
1519 struct drm_i915_gem_request *request)
1520{
Mika Kuoppalab620e872017-09-22 15:43:03 +03001521 struct intel_engine_execlists * const execlists = &engine->execlists;
Chris Wilsonc0dcb202017-02-07 15:24:37 +00001522 struct intel_context *ce;
Chris Wilson221ab97192017-09-16 21:44:14 +01001523 unsigned long flags;
Chris Wilsoncdb6ded2017-07-21 13:32:22 +01001524
Chris Wilson221ab97192017-09-16 21:44:14 +01001525 spin_lock_irqsave(&engine->timeline->lock, flags);
1526
Chris Wilsoncdb6ded2017-07-21 13:32:22 +01001527 /*
1528 * Catch up with any missed context-switch interrupts.
1529 *
1530 * Ideally we would just read the remaining CSB entries now that we
1531 * know the gpu is idle. However, the CSB registers are sometimes^W
1532 * often trashed across a GPU reset! Instead we have to rely on
1533 * guessing the missed context-switch events by looking at what
1534 * requests were completed.
1535 */
Mika Kuoppalacf4591d2017-09-22 15:43:05 +03001536 execlist_cancel_port_requests(execlists);
Chris Wilson221ab97192017-09-16 21:44:14 +01001537
1538 /* Push back any incomplete requests for replay after the reset. */
Chris Wilson7e4992a2017-09-28 20:38:59 +01001539 unwind_incomplete_requests(engine);
Chris Wilsoncdb6ded2017-07-21 13:32:22 +01001540
Chris Wilson221ab97192017-09-16 21:44:14 +01001541 spin_unlock_irqrestore(&engine->timeline->lock, flags);
Chris Wilsonc0dcb202017-02-07 15:24:37 +00001542
1543 /* If the request was innocent, we leave the request in the ELSP
1544 * and will try to replay it on restarting. The context image may
1545 * have been corrupted by the reset, in which case we may have
1546 * to service a new GPU hang, but more likely we can continue on
1547 * without impact.
1548 *
1549 * If the request was guilty, we presume the context is corrupt
1550 * and have to at least restore the RING register in the context
1551 * image back to the expected values to skip over the guilty request.
1552 */
Chris Wilson221ab97192017-09-16 21:44:14 +01001553 if (!request || request->fence.error != -EIO)
Chris Wilsonc0dcb202017-02-07 15:24:37 +00001554 return;
Chris Wilson821ed7d2016-09-09 14:11:53 +01001555
Chris Wilsona3aabe82016-10-04 21:11:26 +01001556 /* We want a simple context + ring to execute the breadcrumb update.
1557 * We cannot rely on the context being intact across the GPU hang,
1558 * so clear it and rebuild just what we need for the breadcrumb.
1559 * All pending requests for this context will be zapped, and any
1560 * future request will be after userspace has had the opportunity
1561 * to recreate its own state.
1562 */
Chris Wilsonc0dcb202017-02-07 15:24:37 +00001563 ce = &request->ctx->engine[engine->id];
Chris Wilsona3aabe82016-10-04 21:11:26 +01001564 execlists_init_reg_state(ce->lrc_reg_state,
1565 request->ctx, engine, ce->ring);
1566
Chris Wilson821ed7d2016-09-09 14:11:53 +01001567 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
Chris Wilsona3aabe82016-10-04 21:11:26 +01001568 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1569 i915_ggtt_offset(ce->ring->vma);
Chris Wilson821ed7d2016-09-09 14:11:53 +01001570 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
Chris Wilsona3aabe82016-10-04 21:11:26 +01001571
Chris Wilson821ed7d2016-09-09 14:11:53 +01001572 request->ring->head = request->postfix;
Chris Wilson821ed7d2016-09-09 14:11:53 +01001573 intel_ring_update_space(request->ring);
1574
Chris Wilsona3aabe82016-10-04 21:11:26 +01001575 /* Reset WaIdleLiteRestore:bdw,skl as well */
Chris Wilson7e4992a2017-09-28 20:38:59 +01001576 unwind_wa_tail(request);
Chris Wilson821ed7d2016-09-09 14:11:53 +01001577}
1578
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001579static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1580{
1581 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00001582 struct intel_engine_cs *engine = req->engine;
Mika Kuoppalae7167762017-02-28 17:28:10 +02001583 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001584 u32 *cs;
1585 int i;
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001586
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001587 cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1588 if (IS_ERR(cs))
1589 return PTR_ERR(cs);
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001590
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001591 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
Mika Kuoppalae7167762017-02-28 17:28:10 +02001592 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001593 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1594
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001595 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1596 *cs++ = upper_32_bits(pd_daddr);
1597 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1598 *cs++ = lower_32_bits(pd_daddr);
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001599 }
1600
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001601 *cs++ = MI_NOOP;
1602 intel_ring_advance(req, cs);
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001603
1604 return 0;
1605}
1606
John Harrisonbe795fc2015-05-29 17:44:03 +01001607static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
Chris Wilson803688b2016-08-02 22:50:27 +01001608 u64 offset, u32 len,
Mika Kuoppala54af56d2017-02-28 17:28:08 +02001609 const unsigned int flags)
Oscar Mateo15648582014-07-24 17:04:32 +01001610{
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001611 u32 *cs;
Oscar Mateo15648582014-07-24 17:04:32 +01001612 int ret;
1613
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001614 /* Don't rely in hw updating PDPs, specially in lite-restore.
1615 * Ideally, we should set Force PD Restore in ctx descriptor,
1616 * but we can't. Force Restore would be a second option, but
1617 * it is unsafe in case of lite-restore (because the ctx is
Michel Thierry2dba3232015-07-30 11:06:23 +01001618 * not idle). PML4 is allocated during ppgtt init so this is
1619 * not needed in 48-bit.*/
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001620 if (req->ctx->ppgtt &&
Mika Kuoppala54af56d2017-02-28 17:28:08 +02001621 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) &&
1622 !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1623 !intel_vgpu_active(req->i915)) {
1624 ret = intel_logical_ring_emit_pdps(req);
1625 if (ret)
1626 return ret;
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001627
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001628 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
Michel Thierry7a01a0a2015-06-26 13:46:14 +01001629 }
1630
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001631 cs = intel_ring_begin(req, 4);
1632 if (IS_ERR(cs))
1633 return PTR_ERR(cs);
Oscar Mateo15648582014-07-24 17:04:32 +01001634
Chris Wilson279f5a02017-10-05 20:10:05 +01001635 /*
1636 * WaDisableCtxRestoreArbitration:bdw,chv
1637 *
1638 * We don't need to perform MI_ARB_ENABLE as often as we do (in
1639 * particular all the gen that do not need the w/a at all!), if we
1640 * took care to make sure that on every switch into this context
1641 * (both ordinary and for preemption) that arbitrartion was enabled
1642 * we would be fine. However, there doesn't seem to be a downside to
1643 * being paranoid and making sure it is set before each batch and
1644 * every context-switch.
1645 *
1646 * Note that if we fail to enable arbitration before the request
1647 * is complete, then we do not see the context-switch interrupt and
1648 * the engine hangs (with RING_HEAD == RING_TAIL).
1649 *
1650 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
1651 */
Chris Wilson3ad7b522017-10-03 21:34:49 +01001652 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1653
Oscar Mateo15648582014-07-24 17:04:32 +01001654 /* FIXME(BDW): Address space and security selectors. */
Mika Kuoppala54af56d2017-02-28 17:28:08 +02001655 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1656 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
1657 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001658 *cs++ = lower_32_bits(offset);
1659 *cs++ = upper_32_bits(offset);
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001660 intel_ring_advance(req, cs);
Oscar Mateo15648582014-07-24 17:04:32 +01001661
1662 return 0;
1663}
1664
Chris Wilson31bb59c2016-07-01 17:23:27 +01001665static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
Oscar Mateo73d477f2014-07-24 17:04:31 +01001666{
Chris Wilsonc0336662016-05-06 15:40:21 +01001667 struct drm_i915_private *dev_priv = engine->i915;
Chris Wilson31bb59c2016-07-01 17:23:27 +01001668 I915_WRITE_IMR(engine,
1669 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1670 POSTING_READ_FW(RING_IMR(engine->mmio_base));
Oscar Mateo73d477f2014-07-24 17:04:31 +01001671}
1672
Chris Wilson31bb59c2016-07-01 17:23:27 +01001673static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
Oscar Mateo73d477f2014-07-24 17:04:31 +01001674{
Chris Wilsonc0336662016-05-06 15:40:21 +01001675 struct drm_i915_private *dev_priv = engine->i915;
Chris Wilson31bb59c2016-07-01 17:23:27 +01001676 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
Oscar Mateo73d477f2014-07-24 17:04:31 +01001677}
1678
Chris Wilson7c9cf4e2016-08-02 22:50:25 +01001679static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
Oscar Mateo47122742014-07-24 17:04:28 +01001680{
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001681 u32 cmd, *cs;
Oscar Mateo47122742014-07-24 17:04:28 +01001682
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001683 cs = intel_ring_begin(request, 4);
1684 if (IS_ERR(cs))
1685 return PTR_ERR(cs);
Oscar Mateo47122742014-07-24 17:04:28 +01001686
1687 cmd = MI_FLUSH_DW + 1;
1688
Chris Wilsonf0a1fb12015-01-22 13:42:00 +00001689 /* We always require a command barrier so that subsequent
1690 * commands, such as breadcrumb interrupts, are strictly ordered
1691 * wrt the contents of the write cache being flushed to memory
1692 * (and thus being coherent from the CPU).
1693 */
1694 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1695
Chris Wilson7c9cf4e2016-08-02 22:50:25 +01001696 if (mode & EMIT_INVALIDATE) {
Chris Wilsonf0a1fb12015-01-22 13:42:00 +00001697 cmd |= MI_INVALIDATE_TLB;
Chris Wilson1dae2df2016-08-02 22:50:19 +01001698 if (request->engine->id == VCS)
Chris Wilsonf0a1fb12015-01-22 13:42:00 +00001699 cmd |= MI_INVALIDATE_BSD;
Oscar Mateo47122742014-07-24 17:04:28 +01001700 }
1701
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001702 *cs++ = cmd;
1703 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1704 *cs++ = 0; /* upper addr */
1705 *cs++ = 0; /* value */
1706 intel_ring_advance(request, cs);
Oscar Mateo47122742014-07-24 17:04:28 +01001707
1708 return 0;
1709}
1710
John Harrison7deb4d32015-05-29 17:43:59 +01001711static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
Chris Wilson7c9cf4e2016-08-02 22:50:25 +01001712 u32 mode)
Oscar Mateo47122742014-07-24 17:04:28 +01001713{
Chris Wilsonb5321f32016-08-02 22:50:18 +01001714 struct intel_engine_cs *engine = request->engine;
Chris Wilsonbde13eb2016-08-15 10:49:07 +01001715 u32 scratch_addr =
1716 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001717 bool vf_flush_wa = false, dc_flush_wa = false;
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001718 u32 *cs, flags = 0;
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001719 int len;
Oscar Mateo47122742014-07-24 17:04:28 +01001720
1721 flags |= PIPE_CONTROL_CS_STALL;
1722
Chris Wilson7c9cf4e2016-08-02 22:50:25 +01001723 if (mode & EMIT_FLUSH) {
Oscar Mateo47122742014-07-24 17:04:28 +01001724 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1725 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
Francisco Jerez965fd602016-01-13 18:59:39 -08001726 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
Chris Wilson40a24482015-08-21 16:08:41 +01001727 flags |= PIPE_CONTROL_FLUSH_ENABLE;
Oscar Mateo47122742014-07-24 17:04:28 +01001728 }
1729
Chris Wilson7c9cf4e2016-08-02 22:50:25 +01001730 if (mode & EMIT_INVALIDATE) {
Oscar Mateo47122742014-07-24 17:04:28 +01001731 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1732 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1733 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1734 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1735 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1736 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1737 flags |= PIPE_CONTROL_QW_WRITE;
1738 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
Oscar Mateo47122742014-07-24 17:04:28 +01001739
Ben Widawsky1a5a9ce2015-12-17 09:49:57 -08001740 /*
1741 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1742 * pipe control.
1743 */
Chris Wilsonc0336662016-05-06 15:40:21 +01001744 if (IS_GEN9(request->i915))
Ben Widawsky1a5a9ce2015-12-17 09:49:57 -08001745 vf_flush_wa = true;
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001746
1747 /* WaForGAMHang:kbl */
1748 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1749 dc_flush_wa = true;
Ben Widawsky1a5a9ce2015-12-17 09:49:57 -08001750 }
Imre Deak9647ff32015-01-25 13:27:11 -08001751
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001752 len = 6;
1753
1754 if (vf_flush_wa)
1755 len += 6;
1756
1757 if (dc_flush_wa)
1758 len += 12;
1759
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001760 cs = intel_ring_begin(request, len);
1761 if (IS_ERR(cs))
1762 return PTR_ERR(cs);
Oscar Mateo47122742014-07-24 17:04:28 +01001763
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001764 if (vf_flush_wa)
1765 cs = gen8_emit_pipe_control(cs, 0, 0);
Imre Deak9647ff32015-01-25 13:27:11 -08001766
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001767 if (dc_flush_wa)
1768 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1769 0);
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001770
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001771 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001772
Tvrtko Ursulin9f235df2017-02-16 12:23:25 +00001773 if (dc_flush_wa)
1774 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
Mika Kuoppala0b2d0932016-06-07 17:19:10 +03001775
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001776 intel_ring_advance(request, cs);
Oscar Mateo47122742014-07-24 17:04:28 +01001777
1778 return 0;
1779}
1780
Chris Wilson7c17d372016-01-20 15:43:35 +02001781/*
1782 * Reserve space for 2 NOOPs at the end of each request to be
1783 * used as a workaround for not being allowed to do lite
1784 * restore with HEAD==TAIL (WaIdleLiteRestore).
1785 */
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001786static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
Oscar Mateo4da46e12014-07-24 17:04:27 +01001787{
Chris Wilsonbeecec92017-10-03 21:34:52 +01001788 /* Ensure there's always at least one preemption point per-request. */
1789 *cs++ = MI_ARB_CHECK;
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001790 *cs++ = MI_NOOP;
1791 request->wa_tail = intel_ring_offset(request, cs);
Chris Wilsoncaddfe72016-10-28 13:58:52 +01001792}
Oscar Mateo4da46e12014-07-24 17:04:27 +01001793
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001794static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
Chris Wilsoncaddfe72016-10-28 13:58:52 +01001795{
Chris Wilson7c17d372016-01-20 15:43:35 +02001796 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1797 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
Oscar Mateo4da46e12014-07-24 17:04:27 +01001798
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001799 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1800 *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1801 *cs++ = 0;
1802 *cs++ = request->global_seqno;
1803 *cs++ = MI_USER_INTERRUPT;
1804 *cs++ = MI_NOOP;
1805 request->tail = intel_ring_offset(request, cs);
Chris Wilsoned1501d2017-03-27 14:14:12 +01001806 assert_ring_tail_valid(request->ring, request->tail);
Chris Wilsoncaddfe72016-10-28 13:58:52 +01001807
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001808 gen8_emit_wa_tail(request, cs);
Chris Wilson7c17d372016-01-20 15:43:35 +02001809}
Chris Wilson98f29e82016-10-28 13:58:51 +01001810static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1811
Chris Wilsoncaddfe72016-10-28 13:58:52 +01001812static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001813 u32 *cs)
Chris Wilson7c17d372016-01-20 15:43:35 +02001814{
Michał Winiarskice81a652016-04-12 15:51:55 +02001815 /* We're using qword write, seqno should be aligned to 8 bytes. */
1816 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1817
Chris Wilson7c17d372016-01-20 15:43:35 +02001818 /* w/a for post sync ops following a GPGPU operation we
1819 * need a prior CS_STALL, which is emitted by the flush
1820 * following the batch.
Michel Thierry53292cd2015-04-15 18:11:33 +01001821 */
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001822 *cs++ = GFX_OP_PIPE_CONTROL(6);
1823 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
1824 PIPE_CONTROL_QW_WRITE;
1825 *cs++ = intel_hws_seqno_address(request->engine);
1826 *cs++ = 0;
1827 *cs++ = request->global_seqno;
Michał Winiarskice81a652016-04-12 15:51:55 +02001828 /* We're thrashing one dword of HWS. */
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001829 *cs++ = 0;
1830 *cs++ = MI_USER_INTERRUPT;
1831 *cs++ = MI_NOOP;
1832 request->tail = intel_ring_offset(request, cs);
Chris Wilsoned1501d2017-03-27 14:14:12 +01001833 assert_ring_tail_valid(request->ring, request->tail);
Chris Wilsoncaddfe72016-10-28 13:58:52 +01001834
Tvrtko Ursulin73dec952017-02-14 11:32:42 +00001835 gen8_emit_wa_tail(request, cs);
Oscar Mateo4da46e12014-07-24 17:04:27 +01001836}
Chris Wilson98f29e82016-10-28 13:58:51 +01001837static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1838
John Harrison87531812015-05-29 17:43:44 +01001839static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
Thomas Daniele7778be2014-12-02 12:50:48 +00001840{
1841 int ret;
1842
Tvrtko Ursulin4ac96592017-02-14 15:00:17 +00001843 ret = intel_ring_workarounds_emit(req);
Thomas Daniele7778be2014-12-02 12:50:48 +00001844 if (ret)
1845 return ret;
1846
Peter Antoine3bbaba02015-07-10 20:13:11 +03001847 ret = intel_rcs_context_init_mocs(req);
1848 /*
1849 * Failing to program the MOCS is non-fatal.The system will not
1850 * run at peak performance. So generate an error and carry on.
1851 */
1852 if (ret)
1853 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1854
Chris Wilson4e50f082016-10-28 13:58:31 +01001855 return i915_gem_render_state_emit(req);
Thomas Daniele7778be2014-12-02 12:50:48 +00001856}
1857
Oscar Mateo73e4d072014-07-24 17:04:48 +01001858/**
1859 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
Tvrtko Ursulin14bb2c12016-06-03 14:02:17 +01001860 * @engine: Engine Command Streamer.
Oscar Mateo73e4d072014-07-24 17:04:48 +01001861 */
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001862void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
Oscar Mateo454afeb2014-07-24 17:04:22 +01001863{
John Harrison6402c332014-10-31 12:00:26 +00001864 struct drm_i915_private *dev_priv;
Oscar Mateo9832b9d2014-07-24 17:04:30 +01001865
Tvrtko Ursulin27af5ee2016-04-04 12:11:56 +01001866 /*
1867 * Tasklet cannot be active at this point due intel_mark_active/idle
1868 * so this is just for documentation.
1869 */
Mika Kuoppalab620e872017-09-22 15:43:03 +03001870 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state)))
1871 tasklet_kill(&engine->execlists.irq_tasklet);
Tvrtko Ursulin27af5ee2016-04-04 12:11:56 +01001872
Chris Wilsonc0336662016-05-06 15:40:21 +01001873 dev_priv = engine->i915;
John Harrison6402c332014-10-31 12:00:26 +00001874
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001875 if (engine->buffer) {
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001876 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
Dave Gordonb0366a52015-12-08 15:02:36 +00001877 }
Oscar Mateo48d82382014-07-24 17:04:23 +01001878
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001879 if (engine->cleanup)
1880 engine->cleanup(engine);
Oscar Mateo48d82382014-07-24 17:04:23 +01001881
Chris Wilsone8a9c582016-12-18 15:37:20 +00001882 intel_engine_cleanup_common(engine);
Arun Siluvery17ee9502015-06-19 19:07:01 +01001883
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00001884 lrc_destroy_wa_ctx(engine);
Chris Wilsonc0336662016-05-06 15:40:21 +01001885 engine->i915 = NULL;
Akash Goel3b3f1652016-10-13 22:44:48 +05301886 dev_priv->engine[engine->id] = NULL;
1887 kfree(engine);
Oscar Mateo454afeb2014-07-24 17:04:22 +01001888}
1889
Chris Wilsonff44ad52017-03-16 17:13:03 +00001890static void execlists_set_default_submission(struct intel_engine_cs *engine)
Chris Wilsonddd66c52016-08-02 22:50:31 +01001891{
Chris Wilsonff44ad52017-03-16 17:13:03 +00001892 engine->submit_request = execlists_submit_request;
Chris Wilson27a5f612017-09-15 18:31:00 +01001893 engine->cancel_requests = execlists_cancel_requests;
Chris Wilsonff44ad52017-03-16 17:13:03 +00001894 engine->schedule = execlists_schedule;
Mika Kuoppalab620e872017-09-22 15:43:03 +03001895 engine->execlists.irq_tasklet.func = intel_lrc_irq_handler;
Chris Wilsonddd66c52016-08-02 22:50:31 +01001896}
1897
Tvrtko Ursulinc9cacf92016-01-12 17:32:34 +00001898static void
Chris Wilsone1382ef2016-05-06 15:40:20 +01001899logical_ring_default_vfuncs(struct intel_engine_cs *engine)
Tvrtko Ursulinc9cacf92016-01-12 17:32:34 +00001900{
1901 /* Default vfuncs which can be overriden by each engine. */
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001902 engine->init_hw = gen8_init_common_ring;
Chris Wilson821ed7d2016-09-09 14:11:53 +01001903 engine->reset_hw = reset_common_ring;
Chris Wilsone8a9c582016-12-18 15:37:20 +00001904
1905 engine->context_pin = execlists_context_pin;
1906 engine->context_unpin = execlists_context_unpin;
1907
Chris Wilsonf73e7392016-12-18 15:37:24 +00001908 engine->request_alloc = execlists_request_alloc;
1909
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001910 engine->emit_flush = gen8_emit_flush;
Chris Wilson9b81d552016-10-28 13:58:50 +01001911 engine->emit_breadcrumb = gen8_emit_breadcrumb;
Chris Wilson98f29e82016-10-28 13:58:51 +01001912 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
Chris Wilsonff44ad52017-03-16 17:13:03 +00001913
1914 engine->set_default_submission = execlists_set_default_submission;
Chris Wilsonddd66c52016-08-02 22:50:31 +01001915
Chris Wilson31bb59c2016-07-01 17:23:27 +01001916 engine->irq_enable = gen8_logical_ring_enable_irq;
1917 engine->irq_disable = gen8_logical_ring_disable_irq;
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001918 engine->emit_bb_start = gen8_emit_bb_start;
Tvrtko Ursulinc9cacf92016-01-12 17:32:34 +00001919}
1920
Tvrtko Ursulind9f3af92016-01-12 17:32:35 +00001921static inline void
Dave Gordonc2c7f242016-07-13 16:03:35 +01001922logical_ring_default_irqs(struct intel_engine_cs *engine)
Tvrtko Ursulind9f3af92016-01-12 17:32:35 +00001923{
Dave Gordonc2c7f242016-07-13 16:03:35 +01001924 unsigned shift = engine->irq_shift;
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001925 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1926 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
Tvrtko Ursulind9f3af92016-01-12 17:32:35 +00001927}
1928
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001929static void
1930logical_ring_setup(struct intel_engine_cs *engine)
1931{
1932 struct drm_i915_private *dev_priv = engine->i915;
1933 enum forcewake_domains fw_domains;
1934
Tvrtko Ursulin019bf272016-07-13 16:03:41 +01001935 intel_engine_setup_common(engine);
1936
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001937 /* Intentionally left blank. */
1938 engine->buffer = NULL;
1939
1940 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1941 RING_ELSP(engine),
1942 FW_REG_WRITE);
1943
1944 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1945 RING_CONTEXT_STATUS_PTR(engine),
1946 FW_REG_READ | FW_REG_WRITE);
1947
1948 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1949 RING_CONTEXT_STATUS_BUF_BASE(engine),
1950 FW_REG_READ);
1951
Mika Kuoppalab620e872017-09-22 15:43:03 +03001952 engine->execlists.fw_domains = fw_domains;
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001953
Mika Kuoppalab620e872017-09-22 15:43:03 +03001954 tasklet_init(&engine->execlists.irq_tasklet,
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001955 intel_lrc_irq_handler, (unsigned long)engine);
1956
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001957 logical_ring_default_vfuncs(engine);
1958 logical_ring_default_irqs(engine);
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001959}
1960
Daniele Ceraolo Spurio486e93f2017-09-13 09:56:02 +01001961static int logical_ring_init(struct intel_engine_cs *engine)
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001962{
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001963 int ret;
1964
Tvrtko Ursulin019bf272016-07-13 16:03:41 +01001965 ret = intel_engine_init_common(engine);
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001966 if (ret)
1967 goto error;
1968
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001969 return 0;
1970
1971error:
1972 intel_logical_ring_cleanup(engine);
1973 return ret;
1974}
1975
Tvrtko Ursulin88d2ba22016-07-13 16:03:40 +01001976int logical_render_ring_init(struct intel_engine_cs *engine)
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001977{
1978 struct drm_i915_private *dev_priv = engine->i915;
1979 int ret;
1980
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01001981 logical_ring_setup(engine);
1982
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001983 if (HAS_L3_DPF(dev_priv))
1984 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1985
1986 /* Override some for render ring. */
1987 if (INTEL_GEN(dev_priv) >= 9)
1988 engine->init_hw = gen9_init_render_ring;
1989 else
1990 engine->init_hw = gen8_init_render_ring;
1991 engine->init_context = gen8_init_rcs_context;
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001992 engine->emit_flush = gen8_emit_flush_render;
Chris Wilson9b81d552016-10-28 13:58:50 +01001993 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
Chris Wilson98f29e82016-10-28 13:58:51 +01001994 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001995
Chris Wilsonf51455d2017-01-10 14:47:34 +00001996 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01001997 if (ret)
1998 return ret;
1999
2000 ret = intel_init_workaround_bb(engine);
2001 if (ret) {
2002 /*
2003 * We continue even if we fail to initialize WA batch
2004 * because we only expect rare glitches but nothing
2005 * critical to prevent us from using GPU
2006 */
2007 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2008 ret);
2009 }
2010
Tvrtko Ursulind038fc72016-12-16 13:18:42 +00002011 return logical_ring_init(engine);
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002012}
2013
Tvrtko Ursulin88d2ba22016-07-13 16:03:40 +01002014int logical_xcs_ring_init(struct intel_engine_cs *engine)
Tvrtko Ursulinbb454382016-07-13 16:03:36 +01002015{
2016 logical_ring_setup(engine);
2017
2018 return logical_ring_init(engine);
2019}
2020
Jeff McGee0cea6502015-02-13 10:27:56 -06002021static u32
Chris Wilsonc0336662016-05-06 15:40:21 +01002022make_rpcs(struct drm_i915_private *dev_priv)
Jeff McGee0cea6502015-02-13 10:27:56 -06002023{
2024 u32 rpcs = 0;
2025
2026 /*
2027 * No explicit RPCS request is needed to ensure full
2028 * slice/subslice/EU enablement prior to Gen9.
2029 */
Chris Wilsonc0336662016-05-06 15:40:21 +01002030 if (INTEL_GEN(dev_priv) < 9)
Jeff McGee0cea6502015-02-13 10:27:56 -06002031 return 0;
2032
2033 /*
2034 * Starting in Gen9, render power gating can leave
2035 * slice/subslice/EU in a partially enabled state. We
2036 * must make an explicit request through RPCS for full
2037 * enablement.
2038 */
Imre Deak43b67992016-08-31 19:13:02 +03002039 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
Jeff McGee0cea6502015-02-13 10:27:56 -06002040 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
Imre Deakf08a0c92016-08-31 19:13:04 +03002041 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
Jeff McGee0cea6502015-02-13 10:27:56 -06002042 GEN8_RPCS_S_CNT_SHIFT;
2043 rpcs |= GEN8_RPCS_ENABLE;
2044 }
2045
Imre Deak43b67992016-08-31 19:13:02 +03002046 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
Jeff McGee0cea6502015-02-13 10:27:56 -06002047 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
Imre Deak57ec1712016-08-31 19:13:05 +03002048 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
Jeff McGee0cea6502015-02-13 10:27:56 -06002049 GEN8_RPCS_SS_CNT_SHIFT;
2050 rpcs |= GEN8_RPCS_ENABLE;
2051 }
2052
Imre Deak43b67992016-08-31 19:13:02 +03002053 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2054 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
Jeff McGee0cea6502015-02-13 10:27:56 -06002055 GEN8_RPCS_EU_MIN_SHIFT;
Imre Deak43b67992016-08-31 19:13:02 +03002056 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
Jeff McGee0cea6502015-02-13 10:27:56 -06002057 GEN8_RPCS_EU_MAX_SHIFT;
2058 rpcs |= GEN8_RPCS_ENABLE;
2059 }
2060
2061 return rpcs;
2062}
2063
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00002064static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
Michel Thierry71562912016-02-23 10:31:49 +00002065{
2066 u32 indirect_ctx_offset;
2067
Chris Wilsonc0336662016-05-06 15:40:21 +01002068 switch (INTEL_GEN(engine->i915)) {
Michel Thierry71562912016-02-23 10:31:49 +00002069 default:
Chris Wilsonc0336662016-05-06 15:40:21 +01002070 MISSING_CASE(INTEL_GEN(engine->i915));
Michel Thierry71562912016-02-23 10:31:49 +00002071 /* fall through */
Michel Thierry7bd0a2c2017-06-06 13:30:38 -07002072 case 10:
2073 indirect_ctx_offset =
2074 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2075 break;
Michel Thierry71562912016-02-23 10:31:49 +00002076 case 9:
2077 indirect_ctx_offset =
2078 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2079 break;
2080 case 8:
2081 indirect_ctx_offset =
2082 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2083 break;
2084 }
2085
2086 return indirect_ctx_offset;
2087}
2088
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002089static void execlists_init_reg_state(u32 *regs,
Chris Wilsona3aabe82016-10-04 21:11:26 +01002090 struct i915_gem_context *ctx,
2091 struct intel_engine_cs *engine,
2092 struct intel_ring *ring)
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002093{
Chris Wilsona3aabe82016-10-04 21:11:26 +01002094 struct drm_i915_private *dev_priv = engine->i915;
2095 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002096 u32 base = engine->mmio_base;
2097 bool rcs = engine->id == RCS;
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002098
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002099 /* A context is actually a big batch buffer with several
2100 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2101 * values we are setting here are only for the first context restore:
2102 * on a subsequent save, the GPU will recreate this batchbuffer with new
2103 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2104 * we are not initializing here).
2105 */
2106 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2107 MI_LRI_FORCE_POSTED;
2108
2109 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2110 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2111 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2112 (HAS_RESOURCE_STREAMER(dev_priv) ?
2113 CTX_CTRL_RS_CTX_ENABLE : 0)));
2114 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2115 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2116 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2117 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2118 RING_CTL_SIZE(ring->size) | RING_VALID);
2119 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2120 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2121 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2122 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2123 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2124 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2125 if (rcs) {
Chris Wilson604a8f62017-09-21 14:54:43 +01002126 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2127
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002128 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2129 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2130 RING_INDIRECT_CTX_OFFSET(base), 0);
Chris Wilson604a8f62017-09-21 14:54:43 +01002131 if (wa_ctx->indirect_ctx.size) {
Chris Wilsonbde13eb2016-08-15 10:49:07 +01002132 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
Arun Siluvery17ee9502015-06-19 19:07:01 +01002133
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002134 regs[CTX_RCS_INDIRECT_CTX + 1] =
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00002135 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2136 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
Arun Siluvery17ee9502015-06-19 19:07:01 +01002137
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002138 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00002139 intel_lr_indirect_ctx_offset(engine) << 6;
Chris Wilson604a8f62017-09-21 14:54:43 +01002140 }
2141
2142 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2143 if (wa_ctx->per_ctx.size) {
2144 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
Arun Siluvery17ee9502015-06-19 19:07:01 +01002145
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002146 regs[CTX_BB_PER_CTX_PTR + 1] =
Tvrtko Ursulin097d4f12017-02-17 07:58:59 +00002147 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
Arun Siluvery17ee9502015-06-19 19:07:01 +01002148 }
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002149 }
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002150
2151 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2152
2153 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
Ville Syrjälä0d925ea2015-11-04 23:20:11 +02002154 /* PDP values well be assigned later if needed */
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002155 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2156 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2157 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2158 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2159 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2160 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2161 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2162 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
Michel Thierryd7b26332015-04-08 12:13:34 +01002163
Chris Wilson949e8ab2017-02-09 14:40:36 +00002164 if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
Michel Thierry2dba3232015-07-30 11:06:23 +01002165 /* 64b PPGTT (48bit canonical)
2166 * PDP0_DESCRIPTOR contains the base address to PML4 and
2167 * other PDP Descriptors are ignored.
2168 */
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002169 ASSIGN_CTX_PML4(ppgtt, regs);
Michel Thierry2dba3232015-07-30 11:06:23 +01002170 }
2171
Tvrtko Ursulin56e51bf2017-02-21 09:58:39 +00002172 if (rcs) {
2173 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2174 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2175 make_rpcs(dev_priv));
Robert Bragg19f81df2017-06-13 12:23:03 +01002176
2177 i915_oa_init_reg_state(engine, ctx, regs);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002178 }
Chris Wilsona3aabe82016-10-04 21:11:26 +01002179}
2180
2181static int
2182populate_lr_context(struct i915_gem_context *ctx,
2183 struct drm_i915_gem_object *ctx_obj,
2184 struct intel_engine_cs *engine,
2185 struct intel_ring *ring)
2186{
2187 void *vaddr;
2188 int ret;
2189
2190 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2191 if (ret) {
2192 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2193 return ret;
2194 }
2195
2196 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2197 if (IS_ERR(vaddr)) {
2198 ret = PTR_ERR(vaddr);
2199 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2200 return ret;
2201 }
Chris Wilsona4f5ea62016-10-28 13:58:35 +01002202 ctx_obj->mm.dirty = true;
Chris Wilsona3aabe82016-10-04 21:11:26 +01002203
2204 /* The second page of the context object contains some fields which must
2205 * be set up prior to the first execution. */
2206
2207 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
2208 ctx, engine, ring);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002209
Tvrtko Ursulin7d774ca2016-04-12 15:40:42 +01002210 i915_gem_object_unpin_map(ctx_obj);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002211
2212 return 0;
2213}
2214
Chris Wilsone2efd132016-05-24 14:53:34 +01002215static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
Chris Wilson978f1e02016-04-28 09:56:54 +01002216 struct intel_engine_cs *engine)
Oscar Mateoede7d422014-07-24 17:04:12 +01002217{
Oscar Mateo8c8579172014-07-24 17:04:14 +01002218 struct drm_i915_gem_object *ctx_obj;
Chris Wilson9021ad02016-05-24 14:53:37 +01002219 struct intel_context *ce = &ctx->engine[engine->id];
Chris Wilsonbf3783e2016-08-15 10:48:54 +01002220 struct i915_vma *vma;
Oscar Mateo8c8579172014-07-24 17:04:14 +01002221 uint32_t context_size;
Chris Wilson7e37f882016-08-02 22:50:21 +01002222 struct intel_ring *ring;
Oscar Mateo8c8579172014-07-24 17:04:14 +01002223 int ret;
2224
Chris Wilson9021ad02016-05-24 14:53:37 +01002225 WARN_ON(ce->state);
Oscar Mateoede7d422014-07-24 17:04:12 +01002226
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +03002227 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
Oscar Mateo8c8579172014-07-24 17:04:14 +01002228
Michel Thierry0b29c752017-09-13 09:56:00 +01002229 /*
2230 * Before the actual start of the context image, we insert a few pages
2231 * for our own use and for sharing with the GuC.
2232 */
2233 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
Alex Daid1675192015-08-12 15:43:43 +01002234
Tvrtko Ursulin12d79d72016-12-01 14:16:37 +00002235 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
Chris Wilsonfe3db792016-04-25 13:32:13 +01002236 if (IS_ERR(ctx_obj)) {
Dan Carpenter3126a662015-04-30 17:30:50 +03002237 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
Chris Wilsonfe3db792016-04-25 13:32:13 +01002238 return PTR_ERR(ctx_obj);
Oscar Mateo8c8579172014-07-24 17:04:14 +01002239 }
2240
Chris Wilsona01cb372017-01-16 15:21:30 +00002241 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
Chris Wilsonbf3783e2016-08-15 10:48:54 +01002242 if (IS_ERR(vma)) {
2243 ret = PTR_ERR(vma);
2244 goto error_deref_obj;
2245 }
2246
Chris Wilson7e37f882016-08-02 22:50:21 +01002247 ring = intel_engine_create_ring(engine, ctx->ring_size);
Chris Wilsondca33ec2016-08-02 22:50:20 +01002248 if (IS_ERR(ring)) {
2249 ret = PTR_ERR(ring);
Nick Hoathe84fe802015-09-11 12:53:46 +01002250 goto error_deref_obj;
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002251 }
2252
Chris Wilsondca33ec2016-08-02 22:50:20 +01002253 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002254 if (ret) {
2255 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
Chris Wilsondca33ec2016-08-02 22:50:20 +01002256 goto error_ring_free;
Oscar Mateo84c23772014-07-24 17:04:15 +01002257 }
2258
Chris Wilsondca33ec2016-08-02 22:50:20 +01002259 ce->ring = ring;
Chris Wilsonbf3783e2016-08-15 10:48:54 +01002260 ce->state = vma;
Chuanxiao Dong0d402a22017-05-11 18:07:42 +08002261 ce->initialised |= engine->init_context == NULL;
Oscar Mateoede7d422014-07-24 17:04:12 +01002262
2263 return 0;
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002264
Chris Wilsondca33ec2016-08-02 22:50:20 +01002265error_ring_free:
Chris Wilson7e37f882016-08-02 22:50:21 +01002266 intel_ring_free(ring);
Nick Hoathe84fe802015-09-11 12:53:46 +01002267error_deref_obj:
Chris Wilsonf8c417c2016-07-20 13:31:53 +01002268 i915_gem_object_put(ctx_obj);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01002269 return ret;
Oscar Mateoede7d422014-07-24 17:04:12 +01002270}
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002271
Chris Wilson821ed7d2016-09-09 14:11:53 +01002272void intel_lr_context_resume(struct drm_i915_private *dev_priv)
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002273{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002274 struct intel_engine_cs *engine;
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002275 struct i915_gem_context *ctx;
Akash Goel3b3f1652016-10-13 22:44:48 +05302276 enum intel_engine_id id;
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002277
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002278 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2279 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2280 * that stored in context. As we only write new commands from
2281 * ce->ring->tail onwards, everything before that is junk. If the GPU
2282 * starts reading from its RING_HEAD from the context, it may try to
2283 * execute that junk and die.
2284 *
2285 * So to avoid that we reset the context images upon resume. For
2286 * simplicity, we just zero everything out.
2287 */
Chris Wilson829a0af2017-06-20 12:05:45 +01002288 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
Akash Goel3b3f1652016-10-13 22:44:48 +05302289 for_each_engine(engine, dev_priv, id) {
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002290 struct intel_context *ce = &ctx->engine[engine->id];
2291 u32 *reg;
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002292
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002293 if (!ce->state)
2294 continue;
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002295
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002296 reg = i915_gem_object_pin_map(ce->state->obj,
2297 I915_MAP_WB);
2298 if (WARN_ON(IS_ERR(reg)))
2299 continue;
Tvrtko Ursulin7d774ca2016-04-12 15:40:42 +01002300
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002301 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2302 reg[CTX_RING_HEAD+1] = 0;
2303 reg[CTX_RING_TAIL+1] = 0;
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002304
Chris Wilsona4f5ea62016-10-28 13:58:35 +01002305 ce->state->obj->mm.dirty = true;
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002306 i915_gem_object_unpin_map(ce->state->obj);
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002307
Chris Wilsone6ba9992017-04-25 14:00:49 +01002308 intel_ring_reset(ce->ring, 0);
Chris Wilsonbafb2f72016-09-21 14:51:08 +01002309 }
Thomas Daniel3e5b6f02015-02-16 16:12:53 +00002310 }
2311}