blob: 3189791a92897654701118ed2733432dceba57dd [file] [log] [blame]
Bryan Wud7df69f2013-01-02 15:53:51 -08001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra30.dtsi"
Bryan Wud7df69f2013-01-02 15:53:51 -08004
5/ {
6 model = "NVIDIA Tegra30 Beaver evaluation board";
7 compatible = "nvidia,beaver", "nvidia,tegra30";
8
Stephen Warren553c0a22013-12-09 14:43:59 -07009 aliases {
10 rtc0 = "/i2c@7000d000/tps65911@2d";
11 rtc1 = "/rtc@7000e000";
12 };
13
Bryan Wud7df69f2013-01-02 15:53:51 -080014 memory {
Stephen Warren30022bb2013-05-13 09:47:31 +000015 reg = <0x80000000 0x7ff00000>;
Bryan Wud7df69f2013-01-02 15:53:51 -080016 };
17
Stephen Warren58ecb232013-11-25 17:53:16 -070018 pcie-controller@00003000 {
Thierry Redingbb034cb2013-08-09 16:49:28 +020019 status = "okay";
20 pex-clk-supply = <&sys_3v3_pexs_reg>;
21 vdd-supply = <&ldo1_reg>;
22 avdd-supply = <&ldo2_reg>;
23
24 pci@1,0 {
25 status = "okay";
Stephen Warren44fefab2013-08-09 16:49:29 +020026 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020027 };
28
29 pci@2,0 {
Stephen Warren44fefab2013-08-09 16:49:29 +020030 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020031 };
32
33 pci@3,0 {
Stephen Warren44fefab2013-08-09 16:49:29 +020034 status = "okay";
35 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020036 };
37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -070039 host1x@50000000 {
40 hdmi@54280000 {
Thierry Reding9bd80b42013-08-12 17:49:03 +020041 status = "okay";
42
Thierry Reding597eb8e2014-04-25 17:44:49 +020043 hdmi-supply = <&vdd_5v0_hdmi>;
Thierry Reding9bd80b42013-08-12 17:49:03 +020044 vdd-supply = <&sys_3v3_reg>;
45 pll-supply = <&vio_reg>;
46
47 nvidia,hpd-gpio =
48 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
49 nvidia,ddc-i2c-bus = <&hdmiddc>;
50 };
51 };
52
Stephen Warren58ecb232013-11-25 17:53:16 -070053 pinmux@70000868 {
Bryan Wud7df69f2013-01-02 15:53:51 -080054 pinctrl-names = "default";
55 pinctrl-0 = <&state_default>;
56
57 state_default: pinmux {
58 sdmmc1_clk_pz0 {
59 nvidia,pins = "sdmmc1_clk_pz0";
60 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +053061 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080063 };
64 sdmmc1_cmd_pz1 {
65 nvidia,pins = "sdmmc1_cmd_pz1",
66 "sdmmc1_dat0_py7",
67 "sdmmc1_dat1_py6",
68 "sdmmc1_dat2_py5",
69 "sdmmc1_dat3_py4";
70 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +053071 nvidia,pull = <TEGRA_PIN_PULL_UP>;
72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080073 };
74 sdmmc3_clk_pa6 {
75 nvidia,pins = "sdmmc3_clk_pa6";
76 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +053077 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080079 };
80 sdmmc3_cmd_pa7 {
81 nvidia,pins = "sdmmc3_cmd_pa7",
82 "sdmmc3_dat0_pb7",
83 "sdmmc3_dat1_pb6",
84 "sdmmc3_dat2_pb5",
85 "sdmmc3_dat3_pb4";
86 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +053087 nvidia,pull = <TEGRA_PIN_PULL_UP>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080089 };
90 sdmmc4_clk_pcc4 {
91 nvidia,pins = "sdmmc4_clk_pcc4",
92 "sdmmc4_rst_n_pcc3";
93 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +053094 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080096 };
97 sdmmc4_dat0_paa0 {
98 nvidia,pins = "sdmmc4_dat0_paa0",
99 "sdmmc4_dat1_paa1",
100 "sdmmc4_dat2_paa2",
101 "sdmmc4_dat3_paa3",
102 "sdmmc4_dat4_paa4",
103 "sdmmc4_dat5_paa5",
104 "sdmmc4_dat6_paa6",
105 "sdmmc4_dat7_paa7";
106 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530107 nvidia,pull = <TEGRA_PIN_PULL_UP>;
108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800109 };
110 dap2_fs_pa2 {
111 nvidia,pins = "dap2_fs_pa2",
112 "dap2_sclk_pa3",
113 "dap2_din_pa4",
114 "dap2_dout_pa5";
115 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800118 };
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300119 pex_l1_prsnt_n_pdd4 {
120 nvidia,pins = "pex_l1_prsnt_n_pdd4",
121 "pex_l1_clkreq_n_pdd6";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530122 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300123 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800124 sdio3 {
125 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530126 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
127 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800128 nvidia,pull-down-strength = <46>;
129 nvidia,pull-up-strength = <42>;
130 nvidia,slew-rate-rising = <1>;
131 nvidia,slew-rate-falling = <1>;
132 };
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300133 gpv {
134 nvidia,pins = "drive_gpv";
135 nvidia,pull-up-strength = <16>;
136 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800137 };
138 };
139
140 serial@70006000 {
141 status = "okay";
Bryan Wud7df69f2013-01-02 15:53:51 -0800142 };
143
144 i2c@7000c000 {
145 status = "okay";
146 clock-frequency = <100000>;
147 };
148
149 i2c@7000c400 {
150 status = "okay";
151 clock-frequency = <100000>;
152 };
153
154 i2c@7000c500 {
155 status = "okay";
156 clock-frequency = <100000>;
157 };
158
Thierry Reding9bd80b42013-08-12 17:49:03 +0200159 hdmiddc: i2c@7000c700 {
Bryan Wud7df69f2013-01-02 15:53:51 -0800160 status = "okay";
161 clock-frequency = <100000>;
162 };
163
164 i2c@7000d000 {
165 status = "okay";
166 clock-frequency = <100000>;
167
Stephen Warren58ecb232013-11-25 17:53:16 -0700168 rt5640: rt5640@1c {
Stephen Warren23037bb2013-03-27 16:53:20 -0600169 compatible = "realtek,rt5640";
170 reg = <0x1c>;
171 interrupt-parent = <&gpio>;
172 interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
173 realtek,ldo1-en-gpios =
174 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
175 };
176
Bryan Wud7df69f2013-01-02 15:53:51 -0800177 pmic: tps65911@2d {
178 compatible = "ti,tps65911";
179 reg = <0x2d>;
180
Stephen Warren6cecf912013-02-13 12:51:51 -0700181 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800182 #interrupt-cells = <2>;
183 interrupt-controller;
184
185 ti,system-power-controller;
186
187 #gpio-cells = <2>;
188 gpio-controller;
189
190 vcc1-supply = <&vdd_5v_in_reg>;
191 vcc2-supply = <&vdd_5v_in_reg>;
192 vcc3-supply = <&vio_reg>;
193 vcc4-supply = <&vdd_5v_in_reg>;
194 vcc5-supply = <&vdd_5v_in_reg>;
195 vcc6-supply = <&vdd2_reg>;
196 vcc7-supply = <&vdd_5v_in_reg>;
197 vccio-supply = <&vdd_5v_in_reg>;
198
199 regulators {
200 #address-cells = <1>;
201 #size-cells = <0>;
202
203 vdd1_reg: vdd1 {
204 regulator-name = "vddio_ddr_1v2";
205 regulator-min-microvolt = <1200000>;
206 regulator-max-microvolt = <1200000>;
207 regulator-always-on;
208 };
209
210 vdd2_reg: vdd2 {
211 regulator-name = "vdd_1v5_gen";
212 regulator-min-microvolt = <1500000>;
213 regulator-max-microvolt = <1500000>;
214 regulator-always-on;
215 };
216
217 vddctrl_reg: vddctrl {
218 regulator-name = "vdd_cpu,vdd_sys";
219 regulator-min-microvolt = <1000000>;
220 regulator-max-microvolt = <1000000>;
221 regulator-always-on;
222 };
223
224 vio_reg: vio {
225 regulator-name = "vdd_1v8_gen";
226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <1800000>;
228 regulator-always-on;
229 };
230
231 ldo1_reg: ldo1 {
232 regulator-name = "vdd_pexa,vdd_pexb";
233 regulator-min-microvolt = <1050000>;
234 regulator-max-microvolt = <1050000>;
235 };
236
237 ldo2_reg: ldo2 {
238 regulator-name = "vdd_sata,avdd_plle";
239 regulator-min-microvolt = <1050000>;
240 regulator-max-microvolt = <1050000>;
241 };
242
243 /* LDO3 is not connected to anything */
244
245 ldo4_reg: ldo4 {
246 regulator-name = "vdd_rtc";
247 regulator-min-microvolt = <1200000>;
248 regulator-max-microvolt = <1200000>;
249 regulator-always-on;
250 };
251
252 ldo5_reg: ldo5 {
253 regulator-name = "vddio_sdmmc,avdd_vdac";
254 regulator-min-microvolt = <3300000>;
255 regulator-max-microvolt = <3300000>;
256 regulator-always-on;
257 };
258
259 ldo6_reg: ldo6 {
260 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
261 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1200000>;
263 };
264
265 ldo7_reg: ldo7 {
266 regulator-name = "vdd_pllm,x,u,a_p_c_s";
267 regulator-min-microvolt = <1200000>;
268 regulator-max-microvolt = <1200000>;
269 regulator-always-on;
270 };
271
272 ldo8_reg: ldo8 {
273 regulator-name = "vdd_ddr_hs";
274 regulator-min-microvolt = <1000000>;
275 regulator-max-microvolt = <1000000>;
276 regulator-always-on;
277 };
278 };
279 };
Stephen Warren57899052013-11-26 14:43:45 -0700280
281 tps62361@60 {
282 compatible = "ti,tps62361";
283 reg = <0x60>;
284
285 regulator-name = "tps62361-vout";
286 regulator-min-microvolt = <500000>;
287 regulator-max-microvolt = <1500000>;
288 regulator-boot-on;
289 regulator-always-on;
290 ti,vsel0-state-high;
291 ti,vsel1-state-high;
292 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800293 };
294
295 spi@7000da00 {
296 status = "okay";
297 spi-max-frequency = <25000000>;
298 spi-flash@1 {
299 compatible = "winbond,w25q32";
300 reg = <1>;
301 spi-max-frequency = <20000000>;
302 };
303 };
304
Stephen Warren58ecb232013-11-25 17:53:16 -0700305 pmc@7000e400 {
Bryan Wud7df69f2013-01-02 15:53:51 -0800306 status = "okay";
307 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800308 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800309 nvidia,cpu-pwr-good-time = <2000>;
310 nvidia,cpu-pwr-off-time = <200>;
311 nvidia,core-pwr-good-time = <3845 3845>;
312 nvidia,core-pwr-off-time = <0>;
313 nvidia,core-power-req-active-high;
314 nvidia,sys-clock-req-active-high;
Bryan Wud7df69f2013-01-02 15:53:51 -0800315 };
316
Stephen Warren57899052013-11-26 14:43:45 -0700317 ahub@70080000 {
318 i2s@70080400 {
319 status = "okay";
320 };
321 };
322
Bryan Wud7df69f2013-01-02 15:53:51 -0800323 sdhci@78000000 {
324 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700325 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
326 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
327 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800328 bus-width = <4>;
329 };
330
331 sdhci@78000600 {
332 status = "okay";
333 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600334 non-removable;
Bryan Wud7df69f2013-01-02 15:53:51 -0800335 };
336
Eric Brower4c696502013-12-19 18:08:53 -0800337 usb@7d004000 {
338 status = "okay";
339 };
340
341 phy2: usb-phy@7d004000 {
342 vbus-supply = <&sys_3v3_reg>;
343 status = "okay";
344 };
345
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300346 usb@7d008000 {
347 status = "okay";
348 };
349
350 usb-phy@7d008000 {
351 vbus-supply = <&usb3_vbus_reg>;
352 status = "okay";
353 };
354
Joseph Lo7021d122013-04-03 19:31:27 +0800355 clocks {
356 compatible = "simple-bus";
357 #address-cells = <1>;
358 #size-cells = <0>;
359
Stephen Warren58ecb232013-11-25 17:53:16 -0700360 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800361 compatible = "fixed-clock";
362 reg=<0>;
363 #clock-cells = <0>;
364 clock-frequency = <32768>;
365 };
366 };
367
Stephen Warren57899052013-11-26 14:43:45 -0700368 gpio-leds {
369 compatible = "gpio-leds";
370
371 gpled1 {
372 label = "LED1"; /* CR5A1 (blue) */
373 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
374 };
375 gpled2 {
376 label = "LED2"; /* CR4A2 (green) */
377 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
378 };
379 };
380
Bryan Wud7df69f2013-01-02 15:53:51 -0800381 regulators {
382 compatible = "simple-bus";
383 #address-cells = <1>;
384 #size-cells = <0>;
385
386 vdd_5v_in_reg: regulator@0 {
387 compatible = "regulator-fixed";
388 reg = <0>;
389 regulator-name = "vdd_5v_in";
390 regulator-min-microvolt = <5000000>;
391 regulator-max-microvolt = <5000000>;
392 regulator-always-on;
393 };
394
395 chargepump_5v_reg: regulator@1 {
396 compatible = "regulator-fixed";
397 reg = <1>;
398 regulator-name = "chargepump_5v";
399 regulator-min-microvolt = <5000000>;
400 regulator-max-microvolt = <5000000>;
401 regulator-boot-on;
402 regulator-always-on;
403 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700404 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800405 };
406
407 ddr_reg: regulator@2 {
408 compatible = "regulator-fixed";
409 reg = <2>;
410 regulator-name = "vdd_ddr";
411 regulator-min-microvolt = <1500000>;
412 regulator-max-microvolt = <1500000>;
413 regulator-always-on;
414 regulator-boot-on;
415 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700416 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800417 vin-supply = <&vdd_5v_in_reg>;
418 };
419
420 vdd_5v_sata_reg: regulator@3 {
421 compatible = "regulator-fixed";
422 reg = <3>;
423 regulator-name = "vdd_5v_sata";
424 regulator-min-microvolt = <5000000>;
425 regulator-max-microvolt = <5000000>;
426 regulator-always-on;
427 regulator-boot-on;
428 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700429 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800430 vin-supply = <&vdd_5v_in_reg>;
431 };
432
433 usb1_vbus_reg: regulator@4 {
434 compatible = "regulator-fixed";
435 reg = <4>;
436 regulator-name = "usb1_vbus";
437 regulator-min-microvolt = <5000000>;
438 regulator-max-microvolt = <5000000>;
439 enable-active-high;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300440 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800441 gpio-open-drain;
442 vin-supply = <&vdd_5v_in_reg>;
443 };
444
445 usb3_vbus_reg: regulator@5 {
446 compatible = "regulator-fixed";
447 reg = <5>;
448 regulator-name = "usb3_vbus";
449 regulator-min-microvolt = <5000000>;
450 regulator-max-microvolt = <5000000>;
451 enable-active-high;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300452 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800453 gpio-open-drain;
454 vin-supply = <&vdd_5v_in_reg>;
455 };
456
457 sys_3v3_reg: regulator@6 {
458 compatible = "regulator-fixed";
459 reg = <6>;
460 regulator-name = "sys_3v3,vdd_3v3_alw";
461 regulator-min-microvolt = <3300000>;
462 regulator-max-microvolt = <3300000>;
463 regulator-always-on;
464 regulator-boot-on;
465 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700466 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800467 vin-supply = <&vdd_5v_in_reg>;
468 };
469
470 sys_3v3_pexs_reg: regulator@7 {
471 compatible = "regulator-fixed";
472 reg = <7>;
473 regulator-name = "sys_3v3_pexs";
474 regulator-min-microvolt = <3300000>;
475 regulator-max-microvolt = <3300000>;
476 regulator-always-on;
477 regulator-boot-on;
478 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700479 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800480 vin-supply = <&sys_3v3_reg>;
481 };
Thierry Reding597eb8e2014-04-25 17:44:49 +0200482
483 vdd_5v0_hdmi: regulator@8 {
484 compatible = "regulator-fixed";
485 reg = <8>;
486 regulator-name = "+VDD_5V_HDMI";
487 regulator-min-microvolt = <5000000>;
488 regulator-max-microvolt = <5000000>;
489 regulator-always-on;
490 regulator-boot-on;
491 vin-supply = <&sys_3v3_reg>;
492 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800493 };
Eric Browerb4dd3e02013-05-10 14:40:29 +0000494
Stephen Warren23037bb2013-03-27 16:53:20 -0600495 sound {
496 compatible = "nvidia,tegra-audio-rt5640-beaver",
497 "nvidia,tegra-audio-rt5640";
498 nvidia,model = "NVIDIA Tegra Beaver";
499
500 nvidia,audio-routing =
501 "Headphones", "HPOR",
Stephen Warrenac472282013-08-14 13:54:24 -0600502 "Headphones", "HPOL",
503 "Mic Jack", "MICBIAS1",
504 "IN2P", "Mic Jack";
Stephen Warren23037bb2013-03-27 16:53:20 -0600505
506 nvidia,i2s-controller = <&tegra_i2s1>;
507 nvidia,audio-codec = <&rt5640>;
508
509 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
510
511 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
512 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
513 <&tegra_car TEGRA30_CLK_EXTERN1>;
514 clock-names = "pll_a", "pll_a_out0", "mclk";
515 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800516};