Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ethernet/mellanox/mlxsw/spectrum.h |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 3 | * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved. |
| 4 | * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 5 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> |
| 6 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
| 10 | * |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. Neither the names of the copyright holders nor the names of its |
| 17 | * contributors may be used to endorse or promote products derived from |
| 18 | * this software without specific prior written permission. |
| 19 | * |
| 20 | * Alternatively, this software may be distributed under the terms of the |
| 21 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 22 | * Software Foundation. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 34 | * POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | #ifndef _MLXSW_SPECTRUM_H |
| 38 | #define _MLXSW_SPECTRUM_H |
| 39 | |
| 40 | #include <linux/types.h> |
| 41 | #include <linux/netdevice.h> |
Jiri Pirko | 6cf3c97 | 2016-07-05 11:27:39 +0200 | [diff] [blame] | 42 | #include <linux/rhashtable.h> |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 43 | #include <linux/bitops.h> |
| 44 | #include <linux/if_vlan.h> |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 45 | #include <linux/list.h> |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 46 | #include <linux/dcbnl.h> |
Jiri Pirko | 5e9c16c | 2016-07-04 08:23:04 +0200 | [diff] [blame] | 47 | #include <linux/in6.h> |
Jiri Pirko | b45f64d | 2016-09-26 12:52:31 +0200 | [diff] [blame] | 48 | #include <linux/notifier.h> |
Yotam Gigi | 98d0f7b | 2017-01-23 11:07:11 +0100 | [diff] [blame] | 49 | #include <net/psample.h> |
Jiri Pirko | 7aa0f5a | 2017-02-03 10:29:09 +0100 | [diff] [blame] | 50 | #include <net/pkt_cls.h> |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 51 | |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 52 | #include "port.h" |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 53 | #include "core.h" |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 54 | #include "core_acl_flex_keys.h" |
| 55 | #include "core_acl_flex_actions.h" |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 56 | |
| 57 | #define MLXSW_SP_VFID_BASE VLAN_N_VID |
Nogah Frankel | 63fe813 | 2017-02-09 14:54:45 +0100 | [diff] [blame] | 58 | #define MLXSW_SP_VFID_MAX 1024 /* Bridged VLAN interfaces */ |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 59 | |
| 60 | #define MLXSW_SP_RFID_BASE 15360 |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 61 | |
Elad Raz | 53ae628 | 2016-01-10 21:06:26 +0100 | [diff] [blame] | 62 | #define MLXSW_SP_MID_MAX 7000 |
| 63 | |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 64 | #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4 |
| 65 | |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 66 | #define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */ |
| 67 | #define MLXSW_SP_LPM_TREE_MAX 22 |
| 68 | #define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN) |
| 69 | |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 70 | #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */ |
| 71 | |
Ido Schimmel | 1a19844 | 2016-04-06 17:10:02 +0200 | [diff] [blame] | 72 | #define MLXSW_SP_BYTES_PER_CELL 96 |
| 73 | |
| 74 | #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL) |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 75 | #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL) |
Ido Schimmel | 1a19844 | 2016-04-06 17:10:02 +0200 | [diff] [blame] | 76 | |
Jiri Pirko | c602242 | 2016-07-05 11:27:46 +0200 | [diff] [blame] | 77 | #define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */ |
Nogah Frankel | 403547d | 2016-09-20 11:16:52 +0200 | [diff] [blame] | 78 | #define MLXSW_SP_KVD_GRANULARITY 128 |
Jiri Pirko | c602242 | 2016-07-05 11:27:46 +0200 | [diff] [blame] | 79 | |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 80 | /* Maximum delay buffer needed in case of PAUSE frames, in cells. |
| 81 | * Assumes 100m cable and maximum MTU. |
| 82 | */ |
| 83 | #define MLXSW_SP_PAUSE_DELAY 612 |
| 84 | |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 85 | #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ |
| 86 | |
| 87 | static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay) |
| 88 | { |
| 89 | delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE)); |
| 90 | return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu); |
| 91 | } |
| 92 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 93 | struct mlxsw_sp_port; |
Ido Schimmel | 4724ba56 | 2017-03-10 08:53:39 +0100 | [diff] [blame] | 94 | struct mlxsw_sp_rif; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 95 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 96 | struct mlxsw_sp_upper { |
| 97 | struct net_device *dev; |
| 98 | unsigned int ref_count; |
| 99 | }; |
| 100 | |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 101 | struct mlxsw_sp_fid { |
Ido Schimmel | 1c80075 | 2016-06-20 23:04:20 +0200 | [diff] [blame] | 102 | void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport); |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 103 | struct list_head list; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 104 | unsigned int ref_count; |
| 105 | struct net_device *dev; |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 106 | struct mlxsw_sp_rif *r; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 107 | u16 fid; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 108 | }; |
| 109 | |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 110 | struct mlxsw_sp_mid { |
| 111 | struct list_head list; |
| 112 | unsigned char addr[ETH_ALEN]; |
Ido Schimmel | 46d0847 | 2016-10-30 10:09:22 +0100 | [diff] [blame] | 113 | u16 fid; |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 114 | u16 mid; |
| 115 | unsigned int ref_count; |
| 116 | }; |
| 117 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 118 | static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid) |
| 119 | { |
| 120 | return MLXSW_SP_VFID_BASE + vfid; |
| 121 | } |
| 122 | |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 123 | static inline u16 mlxsw_sp_fid_to_vfid(u16 fid) |
| 124 | { |
| 125 | return fid - MLXSW_SP_VFID_BASE; |
| 126 | } |
| 127 | |
| 128 | static inline bool mlxsw_sp_fid_is_vfid(u16 fid) |
| 129 | { |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 130 | return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE; |
| 131 | } |
| 132 | |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 133 | struct mlxsw_sp_sb_pr { |
| 134 | enum mlxsw_reg_sbpr_mode mode; |
| 135 | u32 size; |
| 136 | }; |
| 137 | |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 138 | struct mlxsw_cp_sb_occ { |
| 139 | u32 cur; |
| 140 | u32 max; |
| 141 | }; |
| 142 | |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 143 | struct mlxsw_sp_sb_cm { |
| 144 | u32 min_buff; |
| 145 | u32 max_buff; |
| 146 | u8 pool; |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 147 | struct mlxsw_cp_sb_occ occ; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 148 | }; |
| 149 | |
| 150 | struct mlxsw_sp_sb_pm { |
| 151 | u32 min_buff; |
| 152 | u32 max_buff; |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 153 | struct mlxsw_cp_sb_occ occ; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | #define MLXSW_SP_SB_POOL_COUNT 4 |
| 157 | #define MLXSW_SP_SB_TC_COUNT 8 |
| 158 | |
| 159 | struct mlxsw_sp_sb { |
| 160 | struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT]; |
| 161 | struct { |
| 162 | struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT]; |
| 163 | struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT]; |
| 164 | } ports[MLXSW_PORT_MAX_PORTS]; |
| 165 | }; |
| 166 | |
Jiri Pirko | 5e9c16c | 2016-07-04 08:23:04 +0200 | [diff] [blame] | 167 | #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE) |
| 168 | |
| 169 | struct mlxsw_sp_prefix_usage { |
| 170 | DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT); |
| 171 | }; |
| 172 | |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 173 | enum mlxsw_sp_l3proto { |
| 174 | MLXSW_SP_L3_PROTO_IPV4, |
| 175 | MLXSW_SP_L3_PROTO_IPV6, |
| 176 | }; |
| 177 | |
| 178 | struct mlxsw_sp_lpm_tree { |
| 179 | u8 id; /* tree ID */ |
| 180 | unsigned int ref_count; |
| 181 | enum mlxsw_sp_l3proto proto; |
| 182 | struct mlxsw_sp_prefix_usage prefix_usage; |
| 183 | }; |
| 184 | |
Jiri Pirko | 6b75c48 | 2016-07-04 08:23:09 +0200 | [diff] [blame] | 185 | struct mlxsw_sp_fib; |
| 186 | |
| 187 | struct mlxsw_sp_vr { |
| 188 | u16 id; /* virtual router ID */ |
Jiri Pirko | 6b75c48 | 2016-07-04 08:23:09 +0200 | [diff] [blame] | 189 | u32 tb_id; /* kernel fib table id */ |
Ido Schimmel | 6913229 | 2017-03-10 08:53:42 +0100 | [diff] [blame^] | 190 | unsigned int rif_count; |
Ido Schimmel | 76610eb | 2017-03-10 08:53:41 +0100 | [diff] [blame] | 191 | struct mlxsw_sp_fib *fib4; |
Jiri Pirko | 6b75c48 | 2016-07-04 08:23:09 +0200 | [diff] [blame] | 192 | }; |
| 193 | |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 194 | enum mlxsw_sp_span_type { |
| 195 | MLXSW_SP_SPAN_EGRESS, |
| 196 | MLXSW_SP_SPAN_INGRESS |
| 197 | }; |
| 198 | |
| 199 | struct mlxsw_sp_span_inspected_port { |
| 200 | struct list_head list; |
| 201 | enum mlxsw_sp_span_type type; |
| 202 | u8 local_port; |
| 203 | }; |
| 204 | |
| 205 | struct mlxsw_sp_span_entry { |
| 206 | u8 local_port; |
| 207 | bool used; |
| 208 | struct list_head bound_ports_list; |
| 209 | int ref_count; |
| 210 | int id; |
| 211 | }; |
| 212 | |
| 213 | enum mlxsw_sp_port_mall_action_type { |
| 214 | MLXSW_SP_PORT_MALL_MIRROR, |
Yotam Gigi | 98d0f7b | 2017-01-23 11:07:11 +0100 | [diff] [blame] | 215 | MLXSW_SP_PORT_MALL_SAMPLE, |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | struct mlxsw_sp_port_mall_mirror_tc_entry { |
| 219 | u8 to_local_port; |
| 220 | bool ingress; |
| 221 | }; |
| 222 | |
| 223 | struct mlxsw_sp_port_mall_tc_entry { |
| 224 | struct list_head list; |
| 225 | unsigned long cookie; |
| 226 | enum mlxsw_sp_port_mall_action_type type; |
| 227 | union { |
| 228 | struct mlxsw_sp_port_mall_mirror_tc_entry mirror; |
| 229 | }; |
| 230 | }; |
| 231 | |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 232 | struct mlxsw_sp_router { |
| 233 | struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT]; |
Nogah Frankel | 9497c04 | 2016-09-20 11:16:54 +0200 | [diff] [blame] | 234 | struct mlxsw_sp_vr *vrs; |
Jiri Pirko | 6cf3c97 | 2016-07-05 11:27:39 +0200 | [diff] [blame] | 235 | struct rhashtable neigh_ht; |
Ido Schimmel | e9ad5e7 | 2017-02-08 11:16:29 +0100 | [diff] [blame] | 236 | struct rhashtable nexthop_group_ht; |
Ido Schimmel | c53b8e1 | 2017-02-08 11:16:30 +0100 | [diff] [blame] | 237 | struct rhashtable nexthop_ht; |
Yotam Gigi | c723c735 | 2016-07-05 11:27:43 +0200 | [diff] [blame] | 238 | struct { |
| 239 | struct delayed_work dw; |
| 240 | unsigned long interval; /* ms */ |
| 241 | } neighs_update; |
Yotam Gigi | 0b2361d | 2016-07-05 11:27:52 +0200 | [diff] [blame] | 242 | struct delayed_work nexthop_probe_dw; |
| 243 | #define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */ |
Yotam Gigi | b215714 | 2016-07-05 11:27:51 +0200 | [diff] [blame] | 244 | struct list_head nexthop_neighs_list; |
Jiri Pirko | b45f64d | 2016-09-26 12:52:31 +0200 | [diff] [blame] | 245 | bool aborted; |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 246 | }; |
| 247 | |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 248 | struct mlxsw_sp_acl; |
| 249 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 250 | struct mlxsw_sp { |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 251 | struct { |
| 252 | struct list_head list; |
Ido Schimmel | 99724c1 | 2016-07-04 08:23:14 +0200 | [diff] [blame] | 253 | DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX); |
Ido Schimmel | 3ba2ebf | 2016-07-04 08:23:15 +0200 | [diff] [blame] | 254 | } vfids; |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 255 | struct { |
| 256 | struct list_head list; |
Ido Schimmel | d8651fd | 2016-06-20 23:04:07 +0200 | [diff] [blame] | 257 | DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX); |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 258 | } br_mids; |
Ido Schimmel | 14d3946 | 2016-06-20 23:04:15 +0200 | [diff] [blame] | 259 | struct list_head fids; /* VLAN-aware bridge FIDs */ |
Nogah Frankel | 8f8a62d | 2016-09-20 11:16:57 +0200 | [diff] [blame] | 260 | struct mlxsw_sp_rif **rifs; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 261 | struct mlxsw_sp_port **ports; |
| 262 | struct mlxsw_core *core; |
| 263 | const struct mlxsw_bus_info *bus_info; |
| 264 | unsigned char base_mac[ETH_ALEN]; |
| 265 | struct { |
| 266 | struct delayed_work dw; |
| 267 | #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100 |
| 268 | unsigned int interval; /* ms */ |
| 269 | } fdb_notify; |
Ido Schimmel | 869f63a | 2016-03-08 12:59:33 -0800 | [diff] [blame] | 270 | #define MLXSW_SP_MIN_AGEING_TIME 10 |
| 271 | #define MLXSW_SP_MAX_AGEING_TIME 1000000 |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 272 | #define MLXSW_SP_DEFAULT_AGEING_TIME 300 |
| 273 | u32 ageing_time; |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 274 | struct mlxsw_sp_upper master_bridge; |
Nogah Frankel | ce0bd2b | 2016-09-20 11:16:50 +0200 | [diff] [blame] | 275 | struct mlxsw_sp_upper *lags; |
Ido Schimmel | 558c2d5 | 2016-02-26 17:32:29 +0100 | [diff] [blame] | 276 | u8 port_to_module[MLXSW_PORT_MAX_PORTS]; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 277 | struct mlxsw_sp_sb sb; |
Jiri Pirko | 5334202 | 2016-07-04 08:23:08 +0200 | [diff] [blame] | 278 | struct mlxsw_sp_router router; |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 279 | struct mlxsw_sp_acl *acl; |
Jiri Pirko | b090ef0 | 2016-07-05 11:27:47 +0200 | [diff] [blame] | 280 | struct { |
| 281 | DECLARE_BITMAP(usage, MLXSW_SP_KVD_LINEAR_SIZE); |
| 282 | } kvdl; |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 283 | |
| 284 | struct { |
| 285 | struct mlxsw_sp_span_entry *entries; |
| 286 | int entries_count; |
| 287 | } span; |
Jiri Pirko | b45f64d | 2016-09-26 12:52:31 +0200 | [diff] [blame] | 288 | struct notifier_block fib_nb; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 289 | }; |
| 290 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 291 | static inline struct mlxsw_sp_upper * |
| 292 | mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id) |
| 293 | { |
| 294 | return &mlxsw_sp->lags[lag_id]; |
| 295 | } |
| 296 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 297 | struct mlxsw_sp_port_pcpu_stats { |
| 298 | u64 rx_packets; |
| 299 | u64 rx_bytes; |
| 300 | u64 tx_packets; |
| 301 | u64 tx_bytes; |
| 302 | struct u64_stats_sync syncp; |
| 303 | u32 tx_dropped; |
| 304 | }; |
| 305 | |
Yotam Gigi | 98d0f7b | 2017-01-23 11:07:11 +0100 | [diff] [blame] | 306 | struct mlxsw_sp_port_sample { |
| 307 | struct psample_group __rcu *psample_group; |
| 308 | u32 trunc_size; |
| 309 | u32 rate; |
| 310 | bool truncate; |
| 311 | }; |
| 312 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 313 | struct mlxsw_sp_port { |
| 314 | struct net_device *dev; |
| 315 | struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats; |
| 316 | struct mlxsw_sp *mlxsw_sp; |
| 317 | u8 local_port; |
| 318 | u8 stp_state; |
Nogah Frankel | 8ecd459 | 2017-02-09 14:54:47 +0100 | [diff] [blame] | 319 | u16 learning:1, |
Jiri Pirko | 0d9b970 | 2015-10-28 10:16:56 +0100 | [diff] [blame] | 320 | learning_sync:1, |
Ido Schimmel | 0293038 | 2015-10-28 10:16:58 +0100 | [diff] [blame] | 321 | uc_flood:1, |
Nogah Frankel | 71c365b | 2017-02-09 14:54:46 +0100 | [diff] [blame] | 322 | mc_flood:1, |
Nogah Frankel | 8ecd459 | 2017-02-09 14:54:47 +0100 | [diff] [blame] | 323 | mc_router:1, |
| 324 | mc_disabled:1, |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 325 | bridged:1, |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 326 | lagged:1, |
| 327 | split:1; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 328 | u16 pvid; |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 329 | u16 lag_id; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 330 | struct { |
| 331 | struct list_head list; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 332 | struct mlxsw_sp_fid *f; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 333 | u16 vid; |
| 334 | } vport; |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 335 | struct { |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 336 | u8 tx_pause:1, |
Ido Schimmel | 0c83f88 | 2016-09-12 13:26:23 +0200 | [diff] [blame] | 337 | rx_pause:1, |
| 338 | autoneg:1; |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 339 | } link; |
| 340 | struct { |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 341 | struct ieee_ets *ets; |
Ido Schimmel | cc7cf51 | 2016-04-06 17:10:11 +0200 | [diff] [blame] | 342 | struct ieee_maxrate *maxrate; |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 343 | struct ieee_pfc *pfc; |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 344 | } dcb; |
Ido Schimmel | d664b41 | 2016-06-09 09:51:40 +0200 | [diff] [blame] | 345 | struct { |
| 346 | u8 module; |
| 347 | u8 width; |
| 348 | u8 lane; |
| 349 | } mapping; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 350 | /* 802.1Q bridge VLANs */ |
Ido Schimmel | bd40e9d | 2015-12-15 16:03:36 +0100 | [diff] [blame] | 351 | unsigned long *active_vlans; |
Elad Raz | fc1273a | 2016-01-06 13:01:11 +0100 | [diff] [blame] | 352 | unsigned long *untagged_vlans; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 353 | /* VLAN interfaces */ |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 354 | struct list_head vports_list; |
Yotam Gigi | 763b4b7 | 2016-07-21 12:03:17 +0200 | [diff] [blame] | 355 | /* TC handles */ |
| 356 | struct list_head mall_tc_list; |
Nogah Frankel | fc1bbb0 | 2016-09-16 15:05:38 +0200 | [diff] [blame] | 357 | struct { |
| 358 | #define MLXSW_HW_STATS_UPDATE_TIME HZ |
| 359 | struct rtnl_link_stats64 *cache; |
| 360 | struct delayed_work update_dw; |
| 361 | } hw_stats; |
Yotam Gigi | 98d0f7b | 2017-01-23 11:07:11 +0100 | [diff] [blame] | 362 | struct mlxsw_sp_port_sample *sample; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 363 | }; |
| 364 | |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 365 | bool mlxsw_sp_port_dev_check(const struct net_device *dev); |
Ido Schimmel | 4724ba56 | 2017-03-10 08:53:39 +0100 | [diff] [blame] | 366 | struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev); |
Jiri Pirko | 7ce856a | 2016-07-04 08:23:12 +0200 | [diff] [blame] | 367 | struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev); |
| 368 | void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port); |
| 369 | |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 370 | static inline bool |
| 371 | mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port) |
| 372 | { |
| 373 | return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause; |
| 374 | } |
| 375 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 376 | static inline struct mlxsw_sp_port * |
| 377 | mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index) |
| 378 | { |
| 379 | struct mlxsw_sp_port *mlxsw_sp_port; |
| 380 | u8 local_port; |
| 381 | |
| 382 | local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core, |
| 383 | lag_id, port_index); |
| 384 | mlxsw_sp_port = mlxsw_sp->ports[local_port]; |
| 385 | return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL; |
| 386 | } |
| 387 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 388 | static inline u16 |
| 389 | mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
| 390 | { |
| 391 | return mlxsw_sp_vport->vport.vid; |
| 392 | } |
| 393 | |
Ido Schimmel | 6381b3a | 2016-06-20 23:04:16 +0200 | [diff] [blame] | 394 | static inline bool |
| 395 | mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port) |
| 396 | { |
| 397 | u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port); |
| 398 | |
| 399 | return vid != 0; |
| 400 | } |
| 401 | |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 402 | static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport, |
| 403 | struct mlxsw_sp_fid *f) |
| 404 | { |
| 405 | mlxsw_sp_vport->vport.f = f; |
| 406 | } |
| 407 | |
| 408 | static inline struct mlxsw_sp_fid * |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 409 | mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 410 | { |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 411 | return mlxsw_sp_vport->vport.f; |
| 412 | } |
| 413 | |
| 414 | static inline struct net_device * |
Ido Schimmel | 3ba2ebf | 2016-07-04 08:23:15 +0200 | [diff] [blame] | 415 | mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 416 | { |
| 417 | struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport); |
| 418 | |
Ido Schimmel | 56918b6 | 2016-06-20 23:04:18 +0200 | [diff] [blame] | 419 | return f ? f->dev : NULL; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | static inline struct mlxsw_sp_port * |
| 423 | mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) |
| 424 | { |
| 425 | struct mlxsw_sp_port *mlxsw_sp_vport; |
| 426 | |
| 427 | list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list, |
| 428 | vport.list) { |
| 429 | if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid) |
| 430 | return mlxsw_sp_vport; |
| 431 | } |
| 432 | |
| 433 | return NULL; |
| 434 | } |
| 435 | |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 436 | static inline struct mlxsw_sp_port * |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame] | 437 | mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port, |
| 438 | u16 fid) |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 439 | { |
| 440 | struct mlxsw_sp_port *mlxsw_sp_vport; |
| 441 | |
| 442 | list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list, |
| 443 | vport.list) { |
Ido Schimmel | 41b996c | 2016-06-20 23:04:17 +0200 | [diff] [blame] | 444 | struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport); |
| 445 | |
Ido Schimmel | 56918b6 | 2016-06-20 23:04:18 +0200 | [diff] [blame] | 446 | if (f && f->fid == fid) |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 447 | return mlxsw_sp_vport; |
| 448 | } |
| 449 | |
| 450 | return NULL; |
| 451 | } |
| 452 | |
Ido Schimmel | 701b186 | 2016-07-04 08:23:16 +0200 | [diff] [blame] | 453 | static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp, |
| 454 | u16 fid) |
| 455 | { |
| 456 | struct mlxsw_sp_fid *f; |
| 457 | |
| 458 | list_for_each_entry(f, &mlxsw_sp->fids, list) |
| 459 | if (f->fid == fid) |
| 460 | return f; |
| 461 | |
| 462 | return NULL; |
| 463 | } |
| 464 | |
| 465 | static inline struct mlxsw_sp_fid * |
| 466 | mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, |
| 467 | const struct net_device *br_dev) |
| 468 | { |
| 469 | struct mlxsw_sp_fid *f; |
| 470 | |
| 471 | list_for_each_entry(f, &mlxsw_sp->vfids.list, list) |
| 472 | if (f->dev == br_dev) |
| 473 | return f; |
| 474 | |
| 475 | return NULL; |
| 476 | } |
| 477 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 478 | enum mlxsw_sp_flood_table { |
| 479 | MLXSW_SP_FLOOD_TABLE_UC, |
Nogah Frankel | 71c365b | 2017-02-09 14:54:46 +0100 | [diff] [blame] | 480 | MLXSW_SP_FLOOD_TABLE_BC, |
| 481 | MLXSW_SP_FLOOD_TABLE_MC, |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 482 | }; |
| 483 | |
| 484 | int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 485 | void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 486 | int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port); |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 487 | int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core, |
| 488 | unsigned int sb_index, u16 pool_index, |
| 489 | struct devlink_sb_pool_info *pool_info); |
| 490 | int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core, |
| 491 | unsigned int sb_index, u16 pool_index, u32 size, |
| 492 | enum devlink_sb_threshold_type threshold_type); |
| 493 | int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, |
| 494 | unsigned int sb_index, u16 pool_index, |
| 495 | u32 *p_threshold); |
| 496 | int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port, |
| 497 | unsigned int sb_index, u16 pool_index, |
| 498 | u32 threshold); |
| 499 | int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port, |
| 500 | unsigned int sb_index, u16 tc_index, |
| 501 | enum devlink_sb_pool_type pool_type, |
| 502 | u16 *p_pool_index, u32 *p_threshold); |
| 503 | int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port, |
| 504 | unsigned int sb_index, u16 tc_index, |
| 505 | enum devlink_sb_pool_type pool_type, |
| 506 | u16 pool_index, u32 threshold); |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 507 | int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core, |
| 508 | unsigned int sb_index); |
| 509 | int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core, |
| 510 | unsigned int sb_index); |
| 511 | int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, |
| 512 | unsigned int sb_index, u16 pool_index, |
| 513 | u32 *p_cur, u32 *p_max); |
| 514 | int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port, |
| 515 | unsigned int sb_index, u16 tc_index, |
| 516 | enum devlink_sb_pool_type pool_type, |
| 517 | u32 *p_cur, u32 *p_max); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 518 | |
| 519 | int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp); |
| 520 | void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp); |
| 521 | int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 522 | void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 523 | void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port); |
| 524 | int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 525 | enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid, |
| 526 | u16 vid); |
| 527 | int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, |
| 528 | u16 vid_end, bool is_member, bool untagged); |
Ido Schimmel | e606002 | 2016-06-20 23:04:11 +0200 | [diff] [blame] | 529 | int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid, |
Ido Schimmel | 47a0a9e | 2016-06-20 23:04:08 +0200 | [diff] [blame] | 530 | bool set); |
Ido Schimmel | 4dc236c | 2016-01-27 15:20:16 +0100 | [diff] [blame] | 531 | void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port); |
Ido Schimmel | 28a01d2 | 2016-02-18 11:30:02 +0100 | [diff] [blame] | 532 | int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid); |
Ido Schimmel | fe3f6d1 | 2016-06-20 23:04:19 +0200 | [diff] [blame] | 533 | int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid); |
Ido Schimmel | 6e095fd | 2016-07-04 08:23:13 +0200 | [diff] [blame] | 534 | int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid, |
| 535 | bool adding); |
Ido Schimmel | 701b186 | 2016-07-04 08:23:16 +0200 | [diff] [blame] | 536 | struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid); |
| 537 | void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f); |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 538 | int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 539 | enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, |
| 540 | bool dwrr, u8 dwrr_weight); |
| 541 | int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 542 | u8 switch_prio, u8 tclass); |
| 543 | int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 544 | u8 *prio_tc, bool pause_en, |
| 545 | struct ieee_pfc *my_pfc); |
Ido Schimmel | cc7cf51 | 2016-04-06 17:10:11 +0200 | [diff] [blame] | 546 | int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 547 | enum mlxsw_reg_qeec_hr hr, u8 index, |
| 548 | u8 next_index, u32 maxrate); |
Ido Schimmel | 584d73d | 2016-08-24 12:00:26 +0200 | [diff] [blame] | 549 | int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 550 | u16 vid_begin, u16 vid_end, |
| 551 | bool learn_enable); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 552 | |
Ido Schimmel | f00817d | 2016-04-06 17:10:09 +0200 | [diff] [blame] | 553 | #ifdef CONFIG_MLXSW_SPECTRUM_DCB |
| 554 | |
| 555 | int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 556 | void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port); |
| 557 | |
| 558 | #else |
| 559 | |
| 560 | static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port) |
| 561 | { |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port) |
| 566 | {} |
| 567 | |
| 568 | #endif |
| 569 | |
Ido Schimmel | 464dce1 | 2016-07-02 11:00:15 +0200 | [diff] [blame] | 570 | int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp); |
| 571 | void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | e732263 | 2016-09-01 10:37:43 +0200 | [diff] [blame] | 572 | int mlxsw_sp_router_netevent_event(struct notifier_block *unused, |
| 573 | unsigned long event, void *ptr); |
Ido Schimmel | 4724ba56 | 2017-03-10 08:53:39 +0100 | [diff] [blame] | 574 | int mlxsw_sp_netdevice_router_port_event(struct net_device *dev); |
| 575 | int mlxsw_sp_inetaddr_event(struct notifier_block *unused, |
| 576 | unsigned long event, void *ptr); |
| 577 | void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp, |
| 578 | struct mlxsw_sp_rif *r); |
Ido Schimmel | 464dce1 | 2016-07-02 11:00:15 +0200 | [diff] [blame] | 579 | |
Jiri Pirko | b090ef0 | 2016-07-05 11:27:47 +0200 | [diff] [blame] | 580 | int mlxsw_sp_kvdl_alloc(struct mlxsw_sp *mlxsw_sp, unsigned int entry_count); |
| 581 | void mlxsw_sp_kvdl_free(struct mlxsw_sp *mlxsw_sp, int entry_index); |
| 582 | |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 583 | struct mlxsw_afk *mlxsw_sp_acl_afk(struct mlxsw_sp_acl *acl); |
| 584 | |
| 585 | struct mlxsw_sp_acl_rule_info { |
| 586 | unsigned int priority; |
| 587 | struct mlxsw_afk_element_values values; |
| 588 | struct mlxsw_afa_block *act_block; |
| 589 | }; |
| 590 | |
| 591 | enum mlxsw_sp_acl_profile { |
| 592 | MLXSW_SP_ACL_PROFILE_FLOWER, |
| 593 | }; |
| 594 | |
| 595 | struct mlxsw_sp_acl_profile_ops { |
| 596 | size_t ruleset_priv_size; |
| 597 | int (*ruleset_add)(struct mlxsw_sp *mlxsw_sp, |
| 598 | void *priv, void *ruleset_priv); |
| 599 | void (*ruleset_del)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv); |
| 600 | int (*ruleset_bind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv, |
| 601 | struct net_device *dev, bool ingress); |
| 602 | void (*ruleset_unbind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv); |
| 603 | size_t rule_priv_size; |
| 604 | int (*rule_add)(struct mlxsw_sp *mlxsw_sp, |
| 605 | void *ruleset_priv, void *rule_priv, |
| 606 | struct mlxsw_sp_acl_rule_info *rulei); |
| 607 | void (*rule_del)(struct mlxsw_sp *mlxsw_sp, void *rule_priv); |
| 608 | }; |
| 609 | |
| 610 | struct mlxsw_sp_acl_ops { |
| 611 | size_t priv_size; |
| 612 | int (*init)(struct mlxsw_sp *mlxsw_sp, void *priv); |
| 613 | void (*fini)(struct mlxsw_sp *mlxsw_sp, void *priv); |
| 614 | const struct mlxsw_sp_acl_profile_ops * |
| 615 | (*profile_ops)(struct mlxsw_sp *mlxsw_sp, |
| 616 | enum mlxsw_sp_acl_profile profile); |
| 617 | }; |
| 618 | |
| 619 | struct mlxsw_sp_acl_ruleset; |
| 620 | |
| 621 | struct mlxsw_sp_acl_ruleset * |
| 622 | mlxsw_sp_acl_ruleset_get(struct mlxsw_sp *mlxsw_sp, |
| 623 | struct net_device *dev, bool ingress, |
| 624 | enum mlxsw_sp_acl_profile profile); |
| 625 | void mlxsw_sp_acl_ruleset_put(struct mlxsw_sp *mlxsw_sp, |
| 626 | struct mlxsw_sp_acl_ruleset *ruleset); |
| 627 | |
| 628 | struct mlxsw_sp_acl_rule_info * |
| 629 | mlxsw_sp_acl_rulei_create(struct mlxsw_sp_acl *acl); |
| 630 | void mlxsw_sp_acl_rulei_destroy(struct mlxsw_sp_acl_rule_info *rulei); |
| 631 | int mlxsw_sp_acl_rulei_commit(struct mlxsw_sp_acl_rule_info *rulei); |
| 632 | void mlxsw_sp_acl_rulei_priority(struct mlxsw_sp_acl_rule_info *rulei, |
| 633 | unsigned int priority); |
| 634 | void mlxsw_sp_acl_rulei_keymask_u32(struct mlxsw_sp_acl_rule_info *rulei, |
| 635 | enum mlxsw_afk_element element, |
| 636 | u32 key_value, u32 mask_value); |
| 637 | void mlxsw_sp_acl_rulei_keymask_buf(struct mlxsw_sp_acl_rule_info *rulei, |
| 638 | enum mlxsw_afk_element element, |
| 639 | const char *key_value, |
| 640 | const char *mask_value, unsigned int len); |
| 641 | void mlxsw_sp_acl_rulei_act_continue(struct mlxsw_sp_acl_rule_info *rulei); |
| 642 | void mlxsw_sp_acl_rulei_act_jump(struct mlxsw_sp_acl_rule_info *rulei, |
| 643 | u16 group_id); |
| 644 | int mlxsw_sp_acl_rulei_act_drop(struct mlxsw_sp_acl_rule_info *rulei); |
| 645 | int mlxsw_sp_acl_rulei_act_fwd(struct mlxsw_sp *mlxsw_sp, |
| 646 | struct mlxsw_sp_acl_rule_info *rulei, |
| 647 | struct net_device *out_dev); |
Petr Machata | a150201 | 2017-03-09 09:25:19 +0100 | [diff] [blame] | 648 | int mlxsw_sp_acl_rulei_act_vlan(struct mlxsw_sp *mlxsw_sp, |
| 649 | struct mlxsw_sp_acl_rule_info *rulei, |
| 650 | u32 action, u16 vid, u16 proto, u8 prio); |
Jiri Pirko | 22a6776 | 2017-02-03 10:29:07 +0100 | [diff] [blame] | 651 | |
| 652 | struct mlxsw_sp_acl_rule; |
| 653 | |
| 654 | struct mlxsw_sp_acl_rule * |
| 655 | mlxsw_sp_acl_rule_create(struct mlxsw_sp *mlxsw_sp, |
| 656 | struct mlxsw_sp_acl_ruleset *ruleset, |
| 657 | unsigned long cookie); |
| 658 | void mlxsw_sp_acl_rule_destroy(struct mlxsw_sp *mlxsw_sp, |
| 659 | struct mlxsw_sp_acl_rule *rule); |
| 660 | int mlxsw_sp_acl_rule_add(struct mlxsw_sp *mlxsw_sp, |
| 661 | struct mlxsw_sp_acl_rule *rule); |
| 662 | void mlxsw_sp_acl_rule_del(struct mlxsw_sp *mlxsw_sp, |
| 663 | struct mlxsw_sp_acl_rule *rule); |
| 664 | struct mlxsw_sp_acl_rule * |
| 665 | mlxsw_sp_acl_rule_lookup(struct mlxsw_sp *mlxsw_sp, |
| 666 | struct mlxsw_sp_acl_ruleset *ruleset, |
| 667 | unsigned long cookie); |
| 668 | struct mlxsw_sp_acl_rule_info * |
| 669 | mlxsw_sp_acl_rule_rulei(struct mlxsw_sp_acl_rule *rule); |
| 670 | |
| 671 | int mlxsw_sp_acl_init(struct mlxsw_sp *mlxsw_sp); |
| 672 | void mlxsw_sp_acl_fini(struct mlxsw_sp *mlxsw_sp); |
| 673 | |
| 674 | extern const struct mlxsw_sp_acl_ops mlxsw_sp_acl_tcam_ops; |
| 675 | |
Jiri Pirko | 7aa0f5a | 2017-02-03 10:29:09 +0100 | [diff] [blame] | 676 | int mlxsw_sp_flower_replace(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress, |
| 677 | __be16 protocol, struct tc_cls_flower_offload *f); |
| 678 | void mlxsw_sp_flower_destroy(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress, |
| 679 | struct tc_cls_flower_offload *f); |
| 680 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 681 | #endif |