blob: 13ec85e7c392f8941ecf6441333d416ba4609f3a [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
Jiri Pirko6cf3c972016-07-05 11:27:39 +020042#include <linux/rhashtable.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020043#include <linux/bitops.h>
44#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010045#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020046#include <linux/dcbnl.h>
Jiri Pirko5e9c16c2016-07-04 08:23:04 +020047#include <linux/in6.h>
Jiri Pirkob45f64d2016-09-26 12:52:31 +020048#include <linux/notifier.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010049#include <net/psample.h>
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +010050#include <net/pkt_cls.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020051
Elad Raz3a49b4f2016-01-10 21:06:28 +010052#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020053#include "core.h"
Jiri Pirko22a67762017-02-03 10:29:07 +010054#include "core_acl_flex_keys.h"
55#include "core_acl_flex_actions.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056
57#define MLXSW_SP_VFID_BASE VLAN_N_VID
Nogah Frankel63fe8132017-02-09 14:54:45 +010058#define MLXSW_SP_VFID_MAX 1024 /* Bridged VLAN interfaces */
Ido Schimmel99724c12016-07-04 08:23:14 +020059
60#define MLXSW_SP_RFID_BASE 15360
Nogah Frankel8f8a62d2016-09-20 11:16:57 +020061#define MLXSW_SP_INVALID_RIF 0xffff
Ido Schimmel7f71eb42015-12-15 16:03:37 +010062
Elad Raz53ae6282016-01-10 21:06:26 +010063#define MLXSW_SP_MID_MAX 7000
64
Ido Schimmel18f1e702016-02-26 17:32:31 +010065#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
66
Jiri Pirko53342022016-07-04 08:23:08 +020067#define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
68#define MLXSW_SP_LPM_TREE_MAX 22
69#define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
70
Ido Schimmel18f1e702016-02-26 17:32:31 +010071#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
72
Ido Schimmel1a198442016-04-06 17:10:02 +020073#define MLXSW_SP_BYTES_PER_CELL 96
74
75#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
Jiri Pirko0f433fa2016-04-14 18:19:24 +020076#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
Ido Schimmel1a198442016-04-06 17:10:02 +020077
Jiri Pirkoc6022422016-07-05 11:27:46 +020078#define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */
Nogah Frankel403547d2016-09-20 11:16:52 +020079#define MLXSW_SP_KVD_GRANULARITY 128
Jiri Pirkoc6022422016-07-05 11:27:46 +020080
Ido Schimmel9f7ec052016-04-06 17:10:14 +020081/* Maximum delay buffer needed in case of PAUSE frames, in cells.
82 * Assumes 100m cable and maximum MTU.
83 */
84#define MLXSW_SP_PAUSE_DELAY 612
85
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020086#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
87
88static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
89{
90 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
91 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
92}
93
Jiri Pirko56ade8f2015-10-16 14:01:37 +020094struct mlxsw_sp_port;
95
Jiri Pirko0d65fc12015-12-03 12:12:28 +010096struct mlxsw_sp_upper {
97 struct net_device *dev;
98 unsigned int ref_count;
99};
100
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200101struct mlxsw_sp_fid {
Ido Schimmel1c800752016-06-20 23:04:20 +0200102 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100103 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200104 unsigned int ref_count;
105 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200106 struct mlxsw_sp_rif *r;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200107 u16 fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100108};
109
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200110struct mlxsw_sp_rif {
Ido Schimmel9665b742017-02-08 11:16:42 +0100111 struct list_head nexthop_list;
112 struct list_head neigh_list;
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200113 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200114 unsigned int ref_count;
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200115 struct mlxsw_sp_fid *f;
116 unsigned char addr[ETH_ALEN];
117 int mtu;
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200118 u16 rif;
119};
120
Elad Raz3a49b4f2016-01-10 21:06:28 +0100121struct mlxsw_sp_mid {
122 struct list_head list;
123 unsigned char addr[ETH_ALEN];
Ido Schimmel46d08472016-10-30 10:09:22 +0100124 u16 fid;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100125 u16 mid;
126 unsigned int ref_count;
127};
128
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100129static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
130{
131 return MLXSW_SP_VFID_BASE + vfid;
132}
133
Ido Schimmelaac78a42015-12-15 16:03:42 +0100134static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
135{
136 return fid - MLXSW_SP_VFID_BASE;
137}
138
139static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
140{
Ido Schimmel99724c12016-07-04 08:23:14 +0200141 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
142}
143
144static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
145{
146 return fid >= MLXSW_SP_RFID_BASE;
147}
148
149static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
150{
151 return MLXSW_SP_RFID_BASE + rif;
Ido Schimmelaac78a42015-12-15 16:03:42 +0100152}
153
Jiri Pirko078f9c72016-04-14 18:19:19 +0200154struct mlxsw_sp_sb_pr {
155 enum mlxsw_reg_sbpr_mode mode;
156 u32 size;
157};
158
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200159struct mlxsw_cp_sb_occ {
160 u32 cur;
161 u32 max;
162};
163
Jiri Pirko078f9c72016-04-14 18:19:19 +0200164struct mlxsw_sp_sb_cm {
165 u32 min_buff;
166 u32 max_buff;
167 u8 pool;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200168 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200169};
170
171struct mlxsw_sp_sb_pm {
172 u32 min_buff;
173 u32 max_buff;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200174 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200175};
176
177#define MLXSW_SP_SB_POOL_COUNT 4
178#define MLXSW_SP_SB_TC_COUNT 8
179
180struct mlxsw_sp_sb {
181 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
182 struct {
183 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
184 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
185 } ports[MLXSW_PORT_MAX_PORTS];
186};
187
Jiri Pirko5e9c16c2016-07-04 08:23:04 +0200188#define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
189
190struct mlxsw_sp_prefix_usage {
191 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
192};
193
Jiri Pirko53342022016-07-04 08:23:08 +0200194enum mlxsw_sp_l3proto {
195 MLXSW_SP_L3_PROTO_IPV4,
196 MLXSW_SP_L3_PROTO_IPV6,
197};
198
199struct mlxsw_sp_lpm_tree {
200 u8 id; /* tree ID */
201 unsigned int ref_count;
202 enum mlxsw_sp_l3proto proto;
203 struct mlxsw_sp_prefix_usage prefix_usage;
204};
205
Jiri Pirko6b75c482016-07-04 08:23:09 +0200206struct mlxsw_sp_fib;
207
208struct mlxsw_sp_vr {
209 u16 id; /* virtual router ID */
210 bool used;
211 enum mlxsw_sp_l3proto proto;
212 u32 tb_id; /* kernel fib table id */
213 struct mlxsw_sp_lpm_tree *lpm_tree;
214 struct mlxsw_sp_fib *fib;
215};
216
Yotam Gigi763b4b72016-07-21 12:03:17 +0200217enum mlxsw_sp_span_type {
218 MLXSW_SP_SPAN_EGRESS,
219 MLXSW_SP_SPAN_INGRESS
220};
221
222struct mlxsw_sp_span_inspected_port {
223 struct list_head list;
224 enum mlxsw_sp_span_type type;
225 u8 local_port;
226};
227
228struct mlxsw_sp_span_entry {
229 u8 local_port;
230 bool used;
231 struct list_head bound_ports_list;
232 int ref_count;
233 int id;
234};
235
236enum mlxsw_sp_port_mall_action_type {
237 MLXSW_SP_PORT_MALL_MIRROR,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100238 MLXSW_SP_PORT_MALL_SAMPLE,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200239};
240
241struct mlxsw_sp_port_mall_mirror_tc_entry {
242 u8 to_local_port;
243 bool ingress;
244};
245
246struct mlxsw_sp_port_mall_tc_entry {
247 struct list_head list;
248 unsigned long cookie;
249 enum mlxsw_sp_port_mall_action_type type;
250 union {
251 struct mlxsw_sp_port_mall_mirror_tc_entry mirror;
252 };
253};
254
Jiri Pirko53342022016-07-04 08:23:08 +0200255struct mlxsw_sp_router {
256 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
Nogah Frankel9497c042016-09-20 11:16:54 +0200257 struct mlxsw_sp_vr *vrs;
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200258 struct rhashtable neigh_ht;
Ido Schimmele9ad5e72017-02-08 11:16:29 +0100259 struct rhashtable nexthop_group_ht;
Ido Schimmelc53b8e12017-02-08 11:16:30 +0100260 struct rhashtable nexthop_ht;
Yotam Gigic723c7352016-07-05 11:27:43 +0200261 struct {
262 struct delayed_work dw;
263 unsigned long interval; /* ms */
264 } neighs_update;
Yotam Gigi0b2361d2016-07-05 11:27:52 +0200265 struct delayed_work nexthop_probe_dw;
266#define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */
Yotam Gigib2157142016-07-05 11:27:51 +0200267 struct list_head nexthop_neighs_list;
Jiri Pirkob45f64d2016-09-26 12:52:31 +0200268 bool aborted;
Jiri Pirko53342022016-07-04 08:23:08 +0200269};
270
Jiri Pirko22a67762017-02-03 10:29:07 +0100271struct mlxsw_sp_acl;
272
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200273struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100274 struct {
275 struct list_head list;
Ido Schimmel99724c12016-07-04 08:23:14 +0200276 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200277 } vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100278 struct {
279 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200280 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
Elad Raz3a49b4f2016-01-10 21:06:28 +0100281 } br_mids;
Ido Schimmel14d39462016-06-20 23:04:15 +0200282 struct list_head fids; /* VLAN-aware bridge FIDs */
Nogah Frankel8f8a62d2016-09-20 11:16:57 +0200283 struct mlxsw_sp_rif **rifs;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200284 struct mlxsw_sp_port **ports;
285 struct mlxsw_core *core;
286 const struct mlxsw_bus_info *bus_info;
287 unsigned char base_mac[ETH_ALEN];
288 struct {
289 struct delayed_work dw;
290#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
291 unsigned int interval; /* ms */
292 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800293#define MLXSW_SP_MIN_AGEING_TIME 10
294#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200295#define MLXSW_SP_DEFAULT_AGEING_TIME 300
296 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100297 struct mlxsw_sp_upper master_bridge;
Nogah Frankelce0bd2b2016-09-20 11:16:50 +0200298 struct mlxsw_sp_upper *lags;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100299 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200300 struct mlxsw_sp_sb sb;
Jiri Pirko53342022016-07-04 08:23:08 +0200301 struct mlxsw_sp_router router;
Jiri Pirko22a67762017-02-03 10:29:07 +0100302 struct mlxsw_sp_acl *acl;
Jiri Pirkob090ef02016-07-05 11:27:47 +0200303 struct {
304 DECLARE_BITMAP(usage, MLXSW_SP_KVD_LINEAR_SIZE);
305 } kvdl;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200306
307 struct {
308 struct mlxsw_sp_span_entry *entries;
309 int entries_count;
310 } span;
Jiri Pirkob45f64d2016-09-26 12:52:31 +0200311 struct notifier_block fib_nb;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200312};
313
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100314static inline struct mlxsw_sp_upper *
315mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
316{
317 return &mlxsw_sp->lags[lag_id];
318}
319
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200320struct mlxsw_sp_port_pcpu_stats {
321 u64 rx_packets;
322 u64 rx_bytes;
323 u64 tx_packets;
324 u64 tx_bytes;
325 struct u64_stats_sync syncp;
326 u32 tx_dropped;
327};
328
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100329struct mlxsw_sp_port_sample {
330 struct psample_group __rcu *psample_group;
331 u32 trunc_size;
332 u32 rate;
333 bool truncate;
334};
335
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200336struct mlxsw_sp_port {
337 struct net_device *dev;
338 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
339 struct mlxsw_sp *mlxsw_sp;
340 u8 local_port;
341 u8 stp_state;
Nogah Frankel8ecd4592017-02-09 14:54:47 +0100342 u16 learning:1,
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100343 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100344 uc_flood:1,
Nogah Frankel71c365b2017-02-09 14:54:46 +0100345 mc_flood:1,
Nogah Frankel8ecd4592017-02-09 14:54:47 +0100346 mc_router:1,
347 mc_disabled:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100348 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100349 lagged:1,
350 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200351 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100352 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100353 struct {
354 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200355 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100356 u16 vid;
357 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200358 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200359 u8 tx_pause:1,
Ido Schimmel0c83f882016-09-12 13:26:23 +0200360 rx_pause:1,
361 autoneg:1;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200362 } link;
363 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200364 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200365 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200366 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200367 } dcb;
Ido Schimmeld664b412016-06-09 09:51:40 +0200368 struct {
369 u8 module;
370 u8 width;
371 u8 lane;
372 } mapping;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200373 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100374 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100375 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200376 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100377 struct list_head vports_list;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200378 /* TC handles */
379 struct list_head mall_tc_list;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200380 struct {
381 #define MLXSW_HW_STATS_UPDATE_TIME HZ
382 struct rtnl_link_stats64 *cache;
383 struct delayed_work update_dw;
384 } hw_stats;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100385 struct mlxsw_sp_port_sample *sample;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200386};
387
Jiri Pirko22a67762017-02-03 10:29:07 +0100388bool mlxsw_sp_port_dev_check(const struct net_device *dev);
Jiri Pirko7ce856a2016-07-04 08:23:12 +0200389struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
390void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
391
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200392static inline bool
393mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
394{
395 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
396}
397
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100398static inline struct mlxsw_sp_port *
399mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
400{
401 struct mlxsw_sp_port *mlxsw_sp_port;
402 u8 local_port;
403
404 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
405 lag_id, port_index);
406 mlxsw_sp_port = mlxsw_sp->ports[local_port];
407 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
408}
409
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100410static inline u16
411mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
412{
413 return mlxsw_sp_vport->vport.vid;
414}
415
Ido Schimmel6381b3a2016-06-20 23:04:16 +0200416static inline bool
417mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
418{
419 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
420
421 return vid != 0;
422}
423
Ido Schimmel41b996c2016-06-20 23:04:17 +0200424static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
425 struct mlxsw_sp_fid *f)
426{
427 mlxsw_sp_vport->vport.f = f;
428}
429
430static inline struct mlxsw_sp_fid *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200431mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100432{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200433 return mlxsw_sp_vport->vport.f;
434}
435
436static inline struct net_device *
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200437mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel41b996c2016-06-20 23:04:17 +0200438{
439 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
440
Ido Schimmel56918b62016-06-20 23:04:18 +0200441 return f ? f->dev : NULL;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100442}
443
444static inline struct mlxsw_sp_port *
445mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
446{
447 struct mlxsw_sp_port *mlxsw_sp_vport;
448
449 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
450 vport.list) {
451 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
452 return mlxsw_sp_vport;
453 }
454
455 return NULL;
456}
457
Ido Schimmelaac78a42015-12-15 16:03:42 +0100458static inline struct mlxsw_sp_port *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200459mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
460 u16 fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100461{
462 struct mlxsw_sp_port *mlxsw_sp_vport;
463
464 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
465 vport.list) {
Ido Schimmel41b996c2016-06-20 23:04:17 +0200466 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
467
Ido Schimmel56918b62016-06-20 23:04:18 +0200468 if (f && f->fid == fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100469 return mlxsw_sp_vport;
470 }
471
472 return NULL;
473}
474
Ido Schimmel701b1862016-07-04 08:23:16 +0200475static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp,
476 u16 fid)
477{
478 struct mlxsw_sp_fid *f;
479
480 list_for_each_entry(f, &mlxsw_sp->fids, list)
481 if (f->fid == fid)
482 return f;
483
484 return NULL;
485}
486
487static inline struct mlxsw_sp_fid *
488mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp,
489 const struct net_device *br_dev)
490{
491 struct mlxsw_sp_fid *f;
492
493 list_for_each_entry(f, &mlxsw_sp->vfids.list, list)
494 if (f->dev == br_dev)
495 return f;
496
497 return NULL;
498}
499
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200500static inline struct mlxsw_sp_rif *
501mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
502 const struct net_device *dev)
503{
504 int i;
505
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200506 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200507 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
508 return mlxsw_sp->rifs[i];
509
510 return NULL;
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513enum mlxsw_sp_flood_table {
514 MLXSW_SP_FLOOD_TABLE_UC,
Nogah Frankel71c365b2017-02-09 14:54:46 +0100515 MLXSW_SP_FLOOD_TABLE_BC,
516 MLXSW_SP_FLOOD_TABLE_MC,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200517};
518
519int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200520void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200521int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200522int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
523 unsigned int sb_index, u16 pool_index,
524 struct devlink_sb_pool_info *pool_info);
525int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
526 unsigned int sb_index, u16 pool_index, u32 size,
527 enum devlink_sb_threshold_type threshold_type);
528int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
529 unsigned int sb_index, u16 pool_index,
530 u32 *p_threshold);
531int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
532 unsigned int sb_index, u16 pool_index,
533 u32 threshold);
534int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
535 unsigned int sb_index, u16 tc_index,
536 enum devlink_sb_pool_type pool_type,
537 u16 *p_pool_index, u32 *p_threshold);
538int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
539 unsigned int sb_index, u16 tc_index,
540 enum devlink_sb_pool_type pool_type,
541 u16 pool_index, u32 threshold);
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200542int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
543 unsigned int sb_index);
544int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
545 unsigned int sb_index);
546int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
547 unsigned int sb_index, u16 pool_index,
548 u32 *p_cur, u32 *p_max);
549int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
550 unsigned int sb_index, u16 tc_index,
551 enum devlink_sb_pool_type pool_type,
552 u32 *p_cur, u32 *p_max);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200553
554int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
555void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
556int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
557void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
558void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
559int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
560 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
561 u16 vid);
562int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
563 u16 vid_end, bool is_member, bool untagged);
Ido Schimmele6060022016-06-20 23:04:11 +0200564int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200565 bool set);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100566void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100567int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +0200568int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200569int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
570 bool adding);
Ido Schimmel701b1862016-07-04 08:23:16 +0200571struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid);
572void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +0200573void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
574 struct mlxsw_sp_rif *r);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200575int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
576 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
577 bool dwrr, u8 dwrr_weight);
578int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
579 u8 switch_prio, u8 tclass);
580int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200581 u8 *prio_tc, bool pause_en,
582 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200583int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
584 enum mlxsw_reg_qeec_hr hr, u8 index,
585 u8 next_index, u32 maxrate);
Ido Schimmel584d73d2016-08-24 12:00:26 +0200586int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
587 u16 vid_begin, u16 vid_end,
588 bool learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200589
Ido Schimmelf00817d2016-04-06 17:10:09 +0200590#ifdef CONFIG_MLXSW_SPECTRUM_DCB
591
592int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
593void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
594
595#else
596
597static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
598{
599 return 0;
600}
601
602static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
603{}
604
605#endif
606
Ido Schimmel464dce12016-07-02 11:00:15 +0200607int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
608void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirkoe7322632016-09-01 10:37:43 +0200609int mlxsw_sp_router_netevent_event(struct notifier_block *unused,
610 unsigned long event, void *ptr);
Ido Schimmel9665b742017-02-08 11:16:42 +0100611void mlxsw_sp_router_rif_gone_sync(struct mlxsw_sp *mlxsw_sp,
612 struct mlxsw_sp_rif *r);
Ido Schimmel464dce12016-07-02 11:00:15 +0200613
Jiri Pirkob090ef02016-07-05 11:27:47 +0200614int mlxsw_sp_kvdl_alloc(struct mlxsw_sp *mlxsw_sp, unsigned int entry_count);
615void mlxsw_sp_kvdl_free(struct mlxsw_sp *mlxsw_sp, int entry_index);
616
Jiri Pirko22a67762017-02-03 10:29:07 +0100617struct mlxsw_afk *mlxsw_sp_acl_afk(struct mlxsw_sp_acl *acl);
618
619struct mlxsw_sp_acl_rule_info {
620 unsigned int priority;
621 struct mlxsw_afk_element_values values;
622 struct mlxsw_afa_block *act_block;
623};
624
625enum mlxsw_sp_acl_profile {
626 MLXSW_SP_ACL_PROFILE_FLOWER,
627};
628
629struct mlxsw_sp_acl_profile_ops {
630 size_t ruleset_priv_size;
631 int (*ruleset_add)(struct mlxsw_sp *mlxsw_sp,
632 void *priv, void *ruleset_priv);
633 void (*ruleset_del)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv);
634 int (*ruleset_bind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv,
635 struct net_device *dev, bool ingress);
636 void (*ruleset_unbind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv);
637 size_t rule_priv_size;
638 int (*rule_add)(struct mlxsw_sp *mlxsw_sp,
639 void *ruleset_priv, void *rule_priv,
640 struct mlxsw_sp_acl_rule_info *rulei);
641 void (*rule_del)(struct mlxsw_sp *mlxsw_sp, void *rule_priv);
642};
643
644struct mlxsw_sp_acl_ops {
645 size_t priv_size;
646 int (*init)(struct mlxsw_sp *mlxsw_sp, void *priv);
647 void (*fini)(struct mlxsw_sp *mlxsw_sp, void *priv);
648 const struct mlxsw_sp_acl_profile_ops *
649 (*profile_ops)(struct mlxsw_sp *mlxsw_sp,
650 enum mlxsw_sp_acl_profile profile);
651};
652
653struct mlxsw_sp_acl_ruleset;
654
655struct mlxsw_sp_acl_ruleset *
656mlxsw_sp_acl_ruleset_get(struct mlxsw_sp *mlxsw_sp,
657 struct net_device *dev, bool ingress,
658 enum mlxsw_sp_acl_profile profile);
659void mlxsw_sp_acl_ruleset_put(struct mlxsw_sp *mlxsw_sp,
660 struct mlxsw_sp_acl_ruleset *ruleset);
661
662struct mlxsw_sp_acl_rule_info *
663mlxsw_sp_acl_rulei_create(struct mlxsw_sp_acl *acl);
664void mlxsw_sp_acl_rulei_destroy(struct mlxsw_sp_acl_rule_info *rulei);
665int mlxsw_sp_acl_rulei_commit(struct mlxsw_sp_acl_rule_info *rulei);
666void mlxsw_sp_acl_rulei_priority(struct mlxsw_sp_acl_rule_info *rulei,
667 unsigned int priority);
668void mlxsw_sp_acl_rulei_keymask_u32(struct mlxsw_sp_acl_rule_info *rulei,
669 enum mlxsw_afk_element element,
670 u32 key_value, u32 mask_value);
671void mlxsw_sp_acl_rulei_keymask_buf(struct mlxsw_sp_acl_rule_info *rulei,
672 enum mlxsw_afk_element element,
673 const char *key_value,
674 const char *mask_value, unsigned int len);
675void mlxsw_sp_acl_rulei_act_continue(struct mlxsw_sp_acl_rule_info *rulei);
676void mlxsw_sp_acl_rulei_act_jump(struct mlxsw_sp_acl_rule_info *rulei,
677 u16 group_id);
678int mlxsw_sp_acl_rulei_act_drop(struct mlxsw_sp_acl_rule_info *rulei);
679int mlxsw_sp_acl_rulei_act_fwd(struct mlxsw_sp *mlxsw_sp,
680 struct mlxsw_sp_acl_rule_info *rulei,
681 struct net_device *out_dev);
682
683struct mlxsw_sp_acl_rule;
684
685struct mlxsw_sp_acl_rule *
686mlxsw_sp_acl_rule_create(struct mlxsw_sp *mlxsw_sp,
687 struct mlxsw_sp_acl_ruleset *ruleset,
688 unsigned long cookie);
689void mlxsw_sp_acl_rule_destroy(struct mlxsw_sp *mlxsw_sp,
690 struct mlxsw_sp_acl_rule *rule);
691int mlxsw_sp_acl_rule_add(struct mlxsw_sp *mlxsw_sp,
692 struct mlxsw_sp_acl_rule *rule);
693void mlxsw_sp_acl_rule_del(struct mlxsw_sp *mlxsw_sp,
694 struct mlxsw_sp_acl_rule *rule);
695struct mlxsw_sp_acl_rule *
696mlxsw_sp_acl_rule_lookup(struct mlxsw_sp *mlxsw_sp,
697 struct mlxsw_sp_acl_ruleset *ruleset,
698 unsigned long cookie);
699struct mlxsw_sp_acl_rule_info *
700mlxsw_sp_acl_rule_rulei(struct mlxsw_sp_acl_rule *rule);
701
702int mlxsw_sp_acl_init(struct mlxsw_sp *mlxsw_sp);
703void mlxsw_sp_acl_fini(struct mlxsw_sp *mlxsw_sp);
704
705extern const struct mlxsw_sp_acl_ops mlxsw_sp_acl_tcam_ops;
706
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +0100707int mlxsw_sp_flower_replace(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress,
708 __be16 protocol, struct tc_cls_flower_offload *f);
709void mlxsw_sp_flower_destroy(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress,
710 struct tc_cls_flower_offload *f);
711
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200712#endif