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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
Jiri Pirko6cf3c972016-07-05 11:27:39 +020042#include <linux/rhashtable.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020043#include <linux/bitops.h>
44#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010045#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020046#include <linux/dcbnl.h>
Jiri Pirko5e9c16c2016-07-04 08:23:04 +020047#include <linux/in6.h>
Jiri Pirkob45f64d2016-09-26 12:52:31 +020048#include <linux/notifier.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010049#include <net/psample.h>
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +010050#include <net/pkt_cls.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020051
Elad Raz3a49b4f2016-01-10 21:06:28 +010052#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020053#include "core.h"
Jiri Pirko22a67762017-02-03 10:29:07 +010054#include "core_acl_flex_keys.h"
55#include "core_acl_flex_actions.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056
57#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel99724c12016-07-04 08:23:14 +020058#define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
59
60#define MLXSW_SP_RFID_BASE 15360
Nogah Frankel8f8a62d2016-09-20 11:16:57 +020061#define MLXSW_SP_INVALID_RIF 0xffff
Ido Schimmel7f71eb42015-12-15 16:03:37 +010062
Elad Raz53ae6282016-01-10 21:06:26 +010063#define MLXSW_SP_MID_MAX 7000
64
Ido Schimmel18f1e702016-02-26 17:32:31 +010065#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
66
Jiri Pirko53342022016-07-04 08:23:08 +020067#define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
68#define MLXSW_SP_LPM_TREE_MAX 22
69#define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
70
Ido Schimmel18f1e702016-02-26 17:32:31 +010071#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
72
Ido Schimmel1a198442016-04-06 17:10:02 +020073#define MLXSW_SP_BYTES_PER_CELL 96
74
75#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
Jiri Pirko0f433fa2016-04-14 18:19:24 +020076#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
Ido Schimmel1a198442016-04-06 17:10:02 +020077
Jiri Pirkoc6022422016-07-05 11:27:46 +020078#define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */
Nogah Frankel403547d2016-09-20 11:16:52 +020079#define MLXSW_SP_KVD_GRANULARITY 128
Jiri Pirkoc6022422016-07-05 11:27:46 +020080
Ido Schimmel9f7ec052016-04-06 17:10:14 +020081/* Maximum delay buffer needed in case of PAUSE frames, in cells.
82 * Assumes 100m cable and maximum MTU.
83 */
84#define MLXSW_SP_PAUSE_DELAY 612
85
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020086#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
87
88static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
89{
90 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
91 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
92}
93
Jiri Pirko56ade8f2015-10-16 14:01:37 +020094struct mlxsw_sp_port;
95
Jiri Pirko0d65fc12015-12-03 12:12:28 +010096struct mlxsw_sp_upper {
97 struct net_device *dev;
98 unsigned int ref_count;
99};
100
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200101struct mlxsw_sp_fid {
Ido Schimmel1c800752016-06-20 23:04:20 +0200102 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100103 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200104 unsigned int ref_count;
105 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200106 struct mlxsw_sp_rif *r;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200107 u16 fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100108};
109
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200110struct mlxsw_sp_rif {
111 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200112 unsigned int ref_count;
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200113 struct mlxsw_sp_fid *f;
114 unsigned char addr[ETH_ALEN];
115 int mtu;
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200116 u16 rif;
117};
118
Elad Raz3a49b4f2016-01-10 21:06:28 +0100119struct mlxsw_sp_mid {
120 struct list_head list;
121 unsigned char addr[ETH_ALEN];
Ido Schimmel46d08472016-10-30 10:09:22 +0100122 u16 fid;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100123 u16 mid;
124 unsigned int ref_count;
125};
126
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100127static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
128{
129 return MLXSW_SP_VFID_BASE + vfid;
130}
131
Ido Schimmelaac78a42015-12-15 16:03:42 +0100132static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
133{
134 return fid - MLXSW_SP_VFID_BASE;
135}
136
137static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
138{
Ido Schimmel99724c12016-07-04 08:23:14 +0200139 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
140}
141
142static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
143{
144 return fid >= MLXSW_SP_RFID_BASE;
145}
146
147static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
148{
149 return MLXSW_SP_RFID_BASE + rif;
Ido Schimmelaac78a42015-12-15 16:03:42 +0100150}
151
Jiri Pirko078f9c72016-04-14 18:19:19 +0200152struct mlxsw_sp_sb_pr {
153 enum mlxsw_reg_sbpr_mode mode;
154 u32 size;
155};
156
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200157struct mlxsw_cp_sb_occ {
158 u32 cur;
159 u32 max;
160};
161
Jiri Pirko078f9c72016-04-14 18:19:19 +0200162struct mlxsw_sp_sb_cm {
163 u32 min_buff;
164 u32 max_buff;
165 u8 pool;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200166 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200167};
168
169struct mlxsw_sp_sb_pm {
170 u32 min_buff;
171 u32 max_buff;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200172 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200173};
174
175#define MLXSW_SP_SB_POOL_COUNT 4
176#define MLXSW_SP_SB_TC_COUNT 8
177
178struct mlxsw_sp_sb {
179 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
180 struct {
181 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
182 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
183 } ports[MLXSW_PORT_MAX_PORTS];
184};
185
Jiri Pirko5e9c16c2016-07-04 08:23:04 +0200186#define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
187
188struct mlxsw_sp_prefix_usage {
189 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
190};
191
Jiri Pirko53342022016-07-04 08:23:08 +0200192enum mlxsw_sp_l3proto {
193 MLXSW_SP_L3_PROTO_IPV4,
194 MLXSW_SP_L3_PROTO_IPV6,
195};
196
197struct mlxsw_sp_lpm_tree {
198 u8 id; /* tree ID */
199 unsigned int ref_count;
200 enum mlxsw_sp_l3proto proto;
201 struct mlxsw_sp_prefix_usage prefix_usage;
202};
203
Jiri Pirko6b75c482016-07-04 08:23:09 +0200204struct mlxsw_sp_fib;
205
206struct mlxsw_sp_vr {
207 u16 id; /* virtual router ID */
208 bool used;
209 enum mlxsw_sp_l3proto proto;
210 u32 tb_id; /* kernel fib table id */
211 struct mlxsw_sp_lpm_tree *lpm_tree;
212 struct mlxsw_sp_fib *fib;
213};
214
Yotam Gigi763b4b72016-07-21 12:03:17 +0200215enum mlxsw_sp_span_type {
216 MLXSW_SP_SPAN_EGRESS,
217 MLXSW_SP_SPAN_INGRESS
218};
219
220struct mlxsw_sp_span_inspected_port {
221 struct list_head list;
222 enum mlxsw_sp_span_type type;
223 u8 local_port;
224};
225
226struct mlxsw_sp_span_entry {
227 u8 local_port;
228 bool used;
229 struct list_head bound_ports_list;
230 int ref_count;
231 int id;
232};
233
234enum mlxsw_sp_port_mall_action_type {
235 MLXSW_SP_PORT_MALL_MIRROR,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100236 MLXSW_SP_PORT_MALL_SAMPLE,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200237};
238
239struct mlxsw_sp_port_mall_mirror_tc_entry {
240 u8 to_local_port;
241 bool ingress;
242};
243
244struct mlxsw_sp_port_mall_tc_entry {
245 struct list_head list;
246 unsigned long cookie;
247 enum mlxsw_sp_port_mall_action_type type;
248 union {
249 struct mlxsw_sp_port_mall_mirror_tc_entry mirror;
250 };
251};
252
Jiri Pirko53342022016-07-04 08:23:08 +0200253struct mlxsw_sp_router {
254 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
Nogah Frankel9497c042016-09-20 11:16:54 +0200255 struct mlxsw_sp_vr *vrs;
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200256 struct rhashtable neigh_ht;
Yotam Gigic723c7352016-07-05 11:27:43 +0200257 struct {
258 struct delayed_work dw;
259 unsigned long interval; /* ms */
260 } neighs_update;
Yotam Gigi0b2361d2016-07-05 11:27:52 +0200261 struct delayed_work nexthop_probe_dw;
262#define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */
Jiri Pirkoa7ff87a2016-07-05 11:27:50 +0200263 struct list_head nexthop_group_list;
Yotam Gigib2157142016-07-05 11:27:51 +0200264 struct list_head nexthop_neighs_list;
Jiri Pirkob45f64d2016-09-26 12:52:31 +0200265 bool aborted;
Jiri Pirko53342022016-07-04 08:23:08 +0200266};
267
Jiri Pirko22a67762017-02-03 10:29:07 +0100268struct mlxsw_sp_acl;
269
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200270struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100271 struct {
272 struct list_head list;
Ido Schimmel99724c12016-07-04 08:23:14 +0200273 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200274 } vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100275 struct {
276 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200277 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
Elad Raz3a49b4f2016-01-10 21:06:28 +0100278 } br_mids;
Ido Schimmel14d39462016-06-20 23:04:15 +0200279 struct list_head fids; /* VLAN-aware bridge FIDs */
Nogah Frankel8f8a62d2016-09-20 11:16:57 +0200280 struct mlxsw_sp_rif **rifs;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200281 struct mlxsw_sp_port **ports;
282 struct mlxsw_core *core;
283 const struct mlxsw_bus_info *bus_info;
284 unsigned char base_mac[ETH_ALEN];
285 struct {
286 struct delayed_work dw;
287#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
288 unsigned int interval; /* ms */
289 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800290#define MLXSW_SP_MIN_AGEING_TIME 10
291#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200292#define MLXSW_SP_DEFAULT_AGEING_TIME 300
293 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100294 struct mlxsw_sp_upper master_bridge;
Nogah Frankelce0bd2b2016-09-20 11:16:50 +0200295 struct mlxsw_sp_upper *lags;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100296 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200297 struct mlxsw_sp_sb sb;
Jiri Pirko53342022016-07-04 08:23:08 +0200298 struct mlxsw_sp_router router;
Jiri Pirko22a67762017-02-03 10:29:07 +0100299 struct mlxsw_sp_acl *acl;
Jiri Pirkob090ef02016-07-05 11:27:47 +0200300 struct {
301 DECLARE_BITMAP(usage, MLXSW_SP_KVD_LINEAR_SIZE);
302 } kvdl;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200303
304 struct {
305 struct mlxsw_sp_span_entry *entries;
306 int entries_count;
307 } span;
Jiri Pirkob45f64d2016-09-26 12:52:31 +0200308 struct notifier_block fib_nb;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200309};
310
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100311static inline struct mlxsw_sp_upper *
312mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
313{
314 return &mlxsw_sp->lags[lag_id];
315}
316
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200317struct mlxsw_sp_port_pcpu_stats {
318 u64 rx_packets;
319 u64 rx_bytes;
320 u64 tx_packets;
321 u64 tx_bytes;
322 struct u64_stats_sync syncp;
323 u32 tx_dropped;
324};
325
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100326struct mlxsw_sp_port_sample {
327 struct psample_group __rcu *psample_group;
328 u32 trunc_size;
329 u32 rate;
330 bool truncate;
331};
332
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200333struct mlxsw_sp_port {
334 struct net_device *dev;
335 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
336 struct mlxsw_sp *mlxsw_sp;
337 u8 local_port;
338 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100339 u8 learning:1,
340 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100341 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100342 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100343 lagged:1,
344 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200345 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100346 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100347 struct {
348 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200349 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100350 u16 vid;
351 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200352 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200353 u8 tx_pause:1,
Ido Schimmel0c83f882016-09-12 13:26:23 +0200354 rx_pause:1,
355 autoneg:1;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200356 } link;
357 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200358 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200359 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200360 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200361 } dcb;
Ido Schimmeld664b412016-06-09 09:51:40 +0200362 struct {
363 u8 module;
364 u8 width;
365 u8 lane;
366 } mapping;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200367 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100368 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100369 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200370 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100371 struct list_head vports_list;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200372 /* TC handles */
373 struct list_head mall_tc_list;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200374 struct {
375 #define MLXSW_HW_STATS_UPDATE_TIME HZ
376 struct rtnl_link_stats64 *cache;
377 struct delayed_work update_dw;
378 } hw_stats;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100379 struct mlxsw_sp_port_sample *sample;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200380};
381
Jiri Pirko22a67762017-02-03 10:29:07 +0100382bool mlxsw_sp_port_dev_check(const struct net_device *dev);
Jiri Pirko7ce856a2016-07-04 08:23:12 +0200383struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
384void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
385
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200386static inline bool
387mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
388{
389 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
390}
391
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100392static inline struct mlxsw_sp_port *
393mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
394{
395 struct mlxsw_sp_port *mlxsw_sp_port;
396 u8 local_port;
397
398 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
399 lag_id, port_index);
400 mlxsw_sp_port = mlxsw_sp->ports[local_port];
401 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
402}
403
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100404static inline u16
405mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
406{
407 return mlxsw_sp_vport->vport.vid;
408}
409
Ido Schimmel6381b3a2016-06-20 23:04:16 +0200410static inline bool
411mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
412{
413 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
414
415 return vid != 0;
416}
417
Ido Schimmel41b996c2016-06-20 23:04:17 +0200418static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
419 struct mlxsw_sp_fid *f)
420{
421 mlxsw_sp_vport->vport.f = f;
422}
423
424static inline struct mlxsw_sp_fid *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200425mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100426{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200427 return mlxsw_sp_vport->vport.f;
428}
429
430static inline struct net_device *
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200431mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel41b996c2016-06-20 23:04:17 +0200432{
433 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
434
Ido Schimmel56918b62016-06-20 23:04:18 +0200435 return f ? f->dev : NULL;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100436}
437
438static inline struct mlxsw_sp_port *
439mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
440{
441 struct mlxsw_sp_port *mlxsw_sp_vport;
442
443 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
444 vport.list) {
445 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
446 return mlxsw_sp_vport;
447 }
448
449 return NULL;
450}
451
Ido Schimmelaac78a42015-12-15 16:03:42 +0100452static inline struct mlxsw_sp_port *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200453mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
454 u16 fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100455{
456 struct mlxsw_sp_port *mlxsw_sp_vport;
457
458 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
459 vport.list) {
Ido Schimmel41b996c2016-06-20 23:04:17 +0200460 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
461
Ido Schimmel56918b62016-06-20 23:04:18 +0200462 if (f && f->fid == fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100463 return mlxsw_sp_vport;
464 }
465
466 return NULL;
467}
468
Ido Schimmel701b1862016-07-04 08:23:16 +0200469static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp,
470 u16 fid)
471{
472 struct mlxsw_sp_fid *f;
473
474 list_for_each_entry(f, &mlxsw_sp->fids, list)
475 if (f->fid == fid)
476 return f;
477
478 return NULL;
479}
480
481static inline struct mlxsw_sp_fid *
482mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp,
483 const struct net_device *br_dev)
484{
485 struct mlxsw_sp_fid *f;
486
487 list_for_each_entry(f, &mlxsw_sp->vfids.list, list)
488 if (f->dev == br_dev)
489 return f;
490
491 return NULL;
492}
493
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200494static inline struct mlxsw_sp_rif *
495mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
496 const struct net_device *dev)
497{
498 int i;
499
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200500 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200501 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
502 return mlxsw_sp->rifs[i];
503
504 return NULL;
505}
506
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200507enum mlxsw_sp_flood_table {
508 MLXSW_SP_FLOOD_TABLE_UC,
509 MLXSW_SP_FLOOD_TABLE_BM,
510};
511
512int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200513void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200514int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200515int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
516 unsigned int sb_index, u16 pool_index,
517 struct devlink_sb_pool_info *pool_info);
518int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
519 unsigned int sb_index, u16 pool_index, u32 size,
520 enum devlink_sb_threshold_type threshold_type);
521int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
522 unsigned int sb_index, u16 pool_index,
523 u32 *p_threshold);
524int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
525 unsigned int sb_index, u16 pool_index,
526 u32 threshold);
527int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
528 unsigned int sb_index, u16 tc_index,
529 enum devlink_sb_pool_type pool_type,
530 u16 *p_pool_index, u32 *p_threshold);
531int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
532 unsigned int sb_index, u16 tc_index,
533 enum devlink_sb_pool_type pool_type,
534 u16 pool_index, u32 threshold);
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200535int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
536 unsigned int sb_index);
537int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
538 unsigned int sb_index);
539int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
540 unsigned int sb_index, u16 pool_index,
541 u32 *p_cur, u32 *p_max);
542int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
543 unsigned int sb_index, u16 tc_index,
544 enum devlink_sb_pool_type pool_type,
545 u32 *p_cur, u32 *p_max);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200546
547int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
548void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
549int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
550void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
551void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
552int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
553 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
554 u16 vid);
555int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
556 u16 vid_end, bool is_member, bool untagged);
Ido Schimmele6060022016-06-20 23:04:11 +0200557int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200558 bool set);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100559void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100560int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +0200561int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200562int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
563 bool adding);
Ido Schimmel701b1862016-07-04 08:23:16 +0200564struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid);
565void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +0200566void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
567 struct mlxsw_sp_rif *r);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200568int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
569 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
570 bool dwrr, u8 dwrr_weight);
571int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
572 u8 switch_prio, u8 tclass);
573int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200574 u8 *prio_tc, bool pause_en,
575 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200576int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
577 enum mlxsw_reg_qeec_hr hr, u8 index,
578 u8 next_index, u32 maxrate);
Ido Schimmel584d73d2016-08-24 12:00:26 +0200579int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
580 u16 vid_begin, u16 vid_end,
581 bool learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200582
Ido Schimmelf00817d2016-04-06 17:10:09 +0200583#ifdef CONFIG_MLXSW_SPECTRUM_DCB
584
585int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
586void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
587
588#else
589
590static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
591{
592 return 0;
593}
594
595static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
596{}
597
598#endif
599
Ido Schimmel464dce12016-07-02 11:00:15 +0200600int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
601void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200602int mlxsw_sp_router_neigh_construct(struct net_device *dev,
603 struct neighbour *n);
604void mlxsw_sp_router_neigh_destroy(struct net_device *dev,
605 struct neighbour *n);
Jiri Pirkoe7322632016-09-01 10:37:43 +0200606int mlxsw_sp_router_netevent_event(struct notifier_block *unused,
607 unsigned long event, void *ptr);
Ido Schimmel464dce12016-07-02 11:00:15 +0200608
Jiri Pirkob090ef02016-07-05 11:27:47 +0200609int mlxsw_sp_kvdl_alloc(struct mlxsw_sp *mlxsw_sp, unsigned int entry_count);
610void mlxsw_sp_kvdl_free(struct mlxsw_sp *mlxsw_sp, int entry_index);
611
Jiri Pirko22a67762017-02-03 10:29:07 +0100612struct mlxsw_afk *mlxsw_sp_acl_afk(struct mlxsw_sp_acl *acl);
613
614struct mlxsw_sp_acl_rule_info {
615 unsigned int priority;
616 struct mlxsw_afk_element_values values;
617 struct mlxsw_afa_block *act_block;
618};
619
620enum mlxsw_sp_acl_profile {
621 MLXSW_SP_ACL_PROFILE_FLOWER,
622};
623
624struct mlxsw_sp_acl_profile_ops {
625 size_t ruleset_priv_size;
626 int (*ruleset_add)(struct mlxsw_sp *mlxsw_sp,
627 void *priv, void *ruleset_priv);
628 void (*ruleset_del)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv);
629 int (*ruleset_bind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv,
630 struct net_device *dev, bool ingress);
631 void (*ruleset_unbind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv);
632 size_t rule_priv_size;
633 int (*rule_add)(struct mlxsw_sp *mlxsw_sp,
634 void *ruleset_priv, void *rule_priv,
635 struct mlxsw_sp_acl_rule_info *rulei);
636 void (*rule_del)(struct mlxsw_sp *mlxsw_sp, void *rule_priv);
637};
638
639struct mlxsw_sp_acl_ops {
640 size_t priv_size;
641 int (*init)(struct mlxsw_sp *mlxsw_sp, void *priv);
642 void (*fini)(struct mlxsw_sp *mlxsw_sp, void *priv);
643 const struct mlxsw_sp_acl_profile_ops *
644 (*profile_ops)(struct mlxsw_sp *mlxsw_sp,
645 enum mlxsw_sp_acl_profile profile);
646};
647
648struct mlxsw_sp_acl_ruleset;
649
650struct mlxsw_sp_acl_ruleset *
651mlxsw_sp_acl_ruleset_get(struct mlxsw_sp *mlxsw_sp,
652 struct net_device *dev, bool ingress,
653 enum mlxsw_sp_acl_profile profile);
654void mlxsw_sp_acl_ruleset_put(struct mlxsw_sp *mlxsw_sp,
655 struct mlxsw_sp_acl_ruleset *ruleset);
656
657struct mlxsw_sp_acl_rule_info *
658mlxsw_sp_acl_rulei_create(struct mlxsw_sp_acl *acl);
659void mlxsw_sp_acl_rulei_destroy(struct mlxsw_sp_acl_rule_info *rulei);
660int mlxsw_sp_acl_rulei_commit(struct mlxsw_sp_acl_rule_info *rulei);
661void mlxsw_sp_acl_rulei_priority(struct mlxsw_sp_acl_rule_info *rulei,
662 unsigned int priority);
663void mlxsw_sp_acl_rulei_keymask_u32(struct mlxsw_sp_acl_rule_info *rulei,
664 enum mlxsw_afk_element element,
665 u32 key_value, u32 mask_value);
666void mlxsw_sp_acl_rulei_keymask_buf(struct mlxsw_sp_acl_rule_info *rulei,
667 enum mlxsw_afk_element element,
668 const char *key_value,
669 const char *mask_value, unsigned int len);
670void mlxsw_sp_acl_rulei_act_continue(struct mlxsw_sp_acl_rule_info *rulei);
671void mlxsw_sp_acl_rulei_act_jump(struct mlxsw_sp_acl_rule_info *rulei,
672 u16 group_id);
673int mlxsw_sp_acl_rulei_act_drop(struct mlxsw_sp_acl_rule_info *rulei);
674int mlxsw_sp_acl_rulei_act_fwd(struct mlxsw_sp *mlxsw_sp,
675 struct mlxsw_sp_acl_rule_info *rulei,
676 struct net_device *out_dev);
677
678struct mlxsw_sp_acl_rule;
679
680struct mlxsw_sp_acl_rule *
681mlxsw_sp_acl_rule_create(struct mlxsw_sp *mlxsw_sp,
682 struct mlxsw_sp_acl_ruleset *ruleset,
683 unsigned long cookie);
684void mlxsw_sp_acl_rule_destroy(struct mlxsw_sp *mlxsw_sp,
685 struct mlxsw_sp_acl_rule *rule);
686int mlxsw_sp_acl_rule_add(struct mlxsw_sp *mlxsw_sp,
687 struct mlxsw_sp_acl_rule *rule);
688void mlxsw_sp_acl_rule_del(struct mlxsw_sp *mlxsw_sp,
689 struct mlxsw_sp_acl_rule *rule);
690struct mlxsw_sp_acl_rule *
691mlxsw_sp_acl_rule_lookup(struct mlxsw_sp *mlxsw_sp,
692 struct mlxsw_sp_acl_ruleset *ruleset,
693 unsigned long cookie);
694struct mlxsw_sp_acl_rule_info *
695mlxsw_sp_acl_rule_rulei(struct mlxsw_sp_acl_rule *rule);
696
697int mlxsw_sp_acl_init(struct mlxsw_sp *mlxsw_sp);
698void mlxsw_sp_acl_fini(struct mlxsw_sp *mlxsw_sp);
699
700extern const struct mlxsw_sp_acl_ops mlxsw_sp_acl_tcam_ops;
701
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +0100702int mlxsw_sp_flower_replace(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress,
703 __be16 protocol, struct tc_cls_flower_offload *f);
704void mlxsw_sp_flower_destroy(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress,
705 struct tc_cls_flower_offload *f);
706
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200707#endif