blob: 4c3bdff092bdfe27b2b5b57c7bf4044db1997bb8 [file] [log] [blame]
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
Shreyas NC6277e832016-08-12 12:29:51 +053024#include <uapi/sound/snd_sst_tokens.h>
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010025#include "skl-sst-dsp.h"
26#include "skl-sst-ipc.h"
27#include "skl-topology.h"
28#include "skl.h"
29#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053030#include "../common/sst-dsp.h"
31#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010032
Jeeja KPf7590d42015-10-07 11:31:53 +010033#define SKL_CH_FIXUP_MASK (1 << 0)
34#define SKL_RATE_FIXUP_MASK (1 << 1)
35#define SKL_FMT_FIXUP_MASK (1 << 2)
Shreyas NC6277e832016-08-12 12:29:51 +053036#define SKL_IN_DIR_BIT_MASK BIT(0)
37#define SKL_PIN_COUNT_MASK GENMASK(7, 4)
Jeeja KPf7590d42015-10-07 11:31:53 +010038
Vinod Koula83e3b42016-11-03 17:07:20 +053039void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps)
40{
41 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
42
43 switch (caps) {
44 case SKL_D0I3_NONE:
45 d0i3->non_d0i3++;
46 break;
47
48 case SKL_D0I3_STREAMING:
49 d0i3->streaming++;
50 break;
51
52 case SKL_D0I3_NON_STREAMING:
53 d0i3->non_streaming++;
54 break;
55 }
56}
57
58void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps)
59{
60 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
61
62 switch (caps) {
63 case SKL_D0I3_NONE:
64 d0i3->non_d0i3--;
65 break;
66
67 case SKL_D0I3_STREAMING:
68 d0i3->streaming--;
69 break;
70
71 case SKL_D0I3_NON_STREAMING:
72 d0i3->non_streaming--;
73 break;
74 }
75}
76
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010077/*
78 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
79 * ignore. This helpers checks if the SKL driver handles this widget type
80 */
81static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
82{
83 switch (w->id) {
84 case snd_soc_dapm_dai_link:
85 case snd_soc_dapm_dai_in:
86 case snd_soc_dapm_aif_in:
87 case snd_soc_dapm_aif_out:
88 case snd_soc_dapm_dai_out:
89 case snd_soc_dapm_switch:
90 return false;
91 default:
92 return true;
93 }
94}
95
96/*
97 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053098 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530100static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100101 struct skl_module_cfg *mconfig)
102{
103 struct skl_sst *ctx = skl->skl_sst;
104
105 if (skl->resource.mem + mconfig->pipe->memory_pages >
106 skl->resource.max_mem) {
107 dev_err(ctx->dev,
108 "%s: module_id %d instance %d\n", __func__,
109 mconfig->id.module_id,
110 mconfig->id.instance_id);
111 dev_err(ctx->dev,
112 "exceeds ppl memory available %d mem %d\n",
113 skl->resource.max_mem, skl->resource.mem);
114 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530115 } else {
116 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100117 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530118}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530120/*
121 * Add the mem to the mem pool. This is freed when pipe is deleted.
122 * Note: DSP does actual memory management we only keep track for complete
123 * pool
124 */
125static void skl_tplg_alloc_pipe_mem(struct skl *skl,
126 struct skl_module_cfg *mconfig)
127{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100128 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100129}
130
131/*
132 * Pipeline needs needs DSP CPU resources for computation, this is
133 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
134 *
135 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530136 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100137 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530138
139static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100140 struct skl_module_cfg *mconfig)
141{
142 struct skl_sst *ctx = skl->skl_sst;
143
144 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
145 dev_err(ctx->dev,
146 "%s: module_id %d instance %d\n", __func__,
147 mconfig->id.module_id, mconfig->id.instance_id);
148 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530149 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100150 skl->resource.max_mcps, skl->resource.mcps);
151 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530152 } else {
153 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100154 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530155}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100156
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530157static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
158 struct skl_module_cfg *mconfig)
159{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100160 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100161}
162
163/*
164 * Free the mcps when tearing down
165 */
166static void
167skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
168{
169 skl->resource.mcps -= mconfig->mcps;
170}
171
172/*
173 * Free the memory when tearing down
174 */
175static void
176skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
177{
178 skl->resource.mem -= mconfig->pipe->memory_pages;
179}
180
Jeeja KPf7590d42015-10-07 11:31:53 +0100181
182static void skl_dump_mconfig(struct skl_sst *ctx,
183 struct skl_module_cfg *mcfg)
184{
185 dev_dbg(ctx->dev, "Dumping config\n");
186 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900187 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
188 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
189 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
190 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100191 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900192 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
193 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
194 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
195 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100196}
197
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530198static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
199{
200 int slot_map = 0xFFFFFFFF;
201 int start_slot = 0;
202 int i;
203
204 for (i = 0; i < chs; i++) {
205 /*
206 * For 2 channels with starting slot as 0, slot map will
207 * look like 0xFFFFFF10.
208 */
209 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
210 start_slot++;
211 }
212 fmt->ch_map = slot_map;
213}
214
Jeeja KPf7590d42015-10-07 11:31:53 +0100215static void skl_tplg_update_params(struct skl_module_fmt *fmt,
216 struct skl_pipe_params *params, int fixup)
217{
218 if (fixup & SKL_RATE_FIXUP_MASK)
219 fmt->s_freq = params->s_freq;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530220 if (fixup & SKL_CH_FIXUP_MASK) {
Jeeja KPf7590d42015-10-07 11:31:53 +0100221 fmt->channels = params->ch;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530222 skl_tplg_update_chmap(fmt, fmt->channels);
223 }
Jeeja KP98256f82015-11-23 22:26:25 +0530224 if (fixup & SKL_FMT_FIXUP_MASK) {
225 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
226
227 /*
228 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
229 * container so update bit depth accordingly
230 */
231 switch (fmt->valid_bit_depth) {
232 case SKL_DEPTH_16BIT:
233 fmt->bit_depth = fmt->valid_bit_depth;
234 break;
235
236 default:
237 fmt->bit_depth = SKL_DEPTH_32BIT;
238 break;
239 }
240 }
241
Jeeja KPf7590d42015-10-07 11:31:53 +0100242}
243
244/*
245 * A pipeline may have modules which impact the pcm parameters, like SRC,
246 * channel converter, format converter.
247 * We need to calculate the output params by applying the 'fixup'
248 * Topology will tell driver which type of fixup is to be applied by
249 * supplying the fixup mask, so based on that we calculate the output
250 *
251 * Now In FE the pcm hw_params is source/target format. Same is applicable
252 * for BE with its hw_params invoked.
253 * here based on FE, BE pipeline and direction we calculate the input and
254 * outfix and then apply that for a module
255 */
256static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
257 struct skl_pipe_params *params, bool is_fe)
258{
259 int in_fixup, out_fixup;
260 struct skl_module_fmt *in_fmt, *out_fmt;
261
Hardik T Shah4cd98992015-10-27 09:22:55 +0900262 /* Fixups will be applied to pin 0 only */
263 in_fmt = &m_cfg->in_fmt[0];
264 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100265
266 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
267 if (is_fe) {
268 in_fixup = m_cfg->params_fixup;
269 out_fixup = (~m_cfg->converter) &
270 m_cfg->params_fixup;
271 } else {
272 out_fixup = m_cfg->params_fixup;
273 in_fixup = (~m_cfg->converter) &
274 m_cfg->params_fixup;
275 }
276 } else {
277 if (is_fe) {
278 out_fixup = m_cfg->params_fixup;
279 in_fixup = (~m_cfg->converter) &
280 m_cfg->params_fixup;
281 } else {
282 in_fixup = m_cfg->params_fixup;
283 out_fixup = (~m_cfg->converter) &
284 m_cfg->params_fixup;
285 }
286 }
287
288 skl_tplg_update_params(in_fmt, params, in_fixup);
289 skl_tplg_update_params(out_fmt, params, out_fixup);
290}
291
292/*
293 * A module needs input and output buffers, which are dependent upon pcm
294 * params, so once we have calculate params, we need buffer calculation as
295 * well.
296 */
297static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
298 struct skl_module_cfg *mcfg)
299{
300 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900301 struct skl_module_fmt *in_fmt, *out_fmt;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900302
303 /* Since fixups is applied to pin 0 only, ibs, obs needs
304 * change for pin 0 only
305 */
306 in_fmt = &mcfg->in_fmt[0];
307 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100308
309 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
310 multiplier = 5;
Jeeja KPf7590d42015-10-07 11:31:53 +0100311
Takashi Sakamoto8e15e762017-03-06 16:12:22 +0900312 mcfg->ibs = DIV_ROUND_UP(in_fmt->s_freq, 1000) *
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900313 in_fmt->channels * (in_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530314 multiplier;
315
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900316 mcfg->obs = DIV_ROUND_UP(out_fmt->s_freq, 1000) *
317 out_fmt->channels * (out_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530318 multiplier;
Jeeja KPf7590d42015-10-07 11:31:53 +0100319}
320
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530321static u8 skl_tplg_be_dev_type(int dev_type)
322{
323 int ret;
324
325 switch (dev_type) {
326 case SKL_DEVICE_BT:
327 ret = NHLT_DEVICE_BT;
328 break;
329
330 case SKL_DEVICE_DMIC:
331 ret = NHLT_DEVICE_DMIC;
332 break;
333
334 case SKL_DEVICE_I2S:
335 ret = NHLT_DEVICE_I2S;
336 break;
337
338 default:
339 ret = NHLT_DEVICE_INVALID;
340 break;
341 }
342
343 return ret;
344}
345
Jeeja KP2d1419a2016-02-05 12:19:10 +0530346static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
347 struct skl_sst *ctx)
348{
349 struct skl_module_cfg *m_cfg = w->priv;
350 int link_type, dir;
351 u32 ch, s_freq, s_fmt;
352 struct nhlt_specific_cfg *cfg;
353 struct skl *skl = get_skl_ctx(ctx->dev);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530354 u8 dev_type = skl_tplg_be_dev_type(m_cfg->dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530355
356 /* check if we already have blob */
357 if (m_cfg->formats_config.caps_size > 0)
358 return 0;
359
Jeeja KPc7c6c732016-03-01 07:59:10 +0530360 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530361 switch (m_cfg->dev_type) {
362 case SKL_DEVICE_DMIC:
363 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530364 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530365 s_freq = m_cfg->in_fmt[0].s_freq;
366 s_fmt = m_cfg->in_fmt[0].bit_depth;
367 ch = m_cfg->in_fmt[0].channels;
368 break;
369
370 case SKL_DEVICE_I2S:
371 link_type = NHLT_LINK_SSP;
372 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530373 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530374 s_freq = m_cfg->out_fmt[0].s_freq;
375 s_fmt = m_cfg->out_fmt[0].bit_depth;
376 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530377 } else {
378 dir = SNDRV_PCM_STREAM_CAPTURE;
379 s_freq = m_cfg->in_fmt[0].s_freq;
380 s_fmt = m_cfg->in_fmt[0].bit_depth;
381 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530382 }
383 break;
384
385 default:
386 return -EINVAL;
387 }
388
389 /* update the blob based on virtual bus_id and default params */
390 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530391 s_fmt, ch, s_freq, dir, dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530392 if (cfg) {
393 m_cfg->formats_config.caps_size = cfg->size;
394 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
395 } else {
396 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
397 m_cfg->vbus_id, link_type, dir);
398 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
399 ch, s_freq, s_fmt);
400 return -EIO;
401 }
402
403 return 0;
404}
405
Jeeja KPf7590d42015-10-07 11:31:53 +0100406static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
407 struct skl_sst *ctx)
408{
409 struct skl_module_cfg *m_cfg = w->priv;
410 struct skl_pipe_params *params = m_cfg->pipe->p_params;
411 int p_conn_type = m_cfg->pipe->conn_type;
412 bool is_fe;
413
414 if (!m_cfg->params_fixup)
415 return;
416
417 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
418 w->name);
419
420 skl_dump_mconfig(ctx, m_cfg);
421
422 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
423 is_fe = true;
424 else
425 is_fe = false;
426
427 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
428 skl_tplg_update_buffer_size(ctx, m_cfg);
429
430 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
431 w->name);
432
433 skl_dump_mconfig(ctx, m_cfg);
434}
435
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100436/*
Jeeja KPabb74002015-11-28 15:01:49 +0530437 * some modules can have multiple params set from user control and
438 * need to be set after module is initialized. If set_param flag is
439 * set module params will be done after module is initialised.
440 */
441static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
442 struct skl_sst *ctx)
443{
444 int i, ret;
445 struct skl_module_cfg *mconfig = w->priv;
446 const struct snd_kcontrol_new *k;
447 struct soc_bytes_ext *sb;
448 struct skl_algo_data *bc;
449 struct skl_specific_cfg *sp_cfg;
450
451 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530452 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530453 sp_cfg = &mconfig->formats_config;
454 ret = skl_set_module_params(ctx, sp_cfg->caps,
455 sp_cfg->caps_size,
456 sp_cfg->param_id, mconfig);
457 if (ret < 0)
458 return ret;
459 }
460
461 for (i = 0; i < w->num_kcontrols; i++) {
462 k = &w->kcontrol_news[i];
463 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
464 sb = (void *) k->private_value;
465 bc = (struct skl_algo_data *)sb->dobj.private;
466
Jeeja KP4ced1822015-12-03 23:29:53 +0530467 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530468 ret = skl_set_module_params(ctx,
Dharageswari R0d682102016-07-08 18:15:03 +0530469 (u32 *)bc->params, bc->size,
Jeeja KPabb74002015-11-28 15:01:49 +0530470 bc->param_id, mconfig);
471 if (ret < 0)
472 return ret;
473 }
474 }
475 }
476
477 return 0;
478}
479
480/*
481 * some module param can set from user control and this is required as
482 * when module is initailzed. if module param is required in init it is
483 * identifed by set_param flag. if set_param flag is not set, then this
484 * parameter needs to set as part of module init.
485 */
486static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
487{
488 const struct snd_kcontrol_new *k;
489 struct soc_bytes_ext *sb;
490 struct skl_algo_data *bc;
491 struct skl_module_cfg *mconfig = w->priv;
492 int i;
493
494 for (i = 0; i < w->num_kcontrols; i++) {
495 k = &w->kcontrol_news[i];
496 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
497 sb = (struct soc_bytes_ext *)k->private_value;
498 bc = (struct skl_algo_data *)sb->dobj.private;
499
Jeeja KP4ced1822015-12-03 23:29:53 +0530500 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530501 continue;
502
Takashi Sakamotod1a6fe42017-02-24 11:48:41 +0900503 mconfig->formats_config.caps = (u32 *)bc->params;
Dharageswari R0d682102016-07-08 18:15:03 +0530504 mconfig->formats_config.caps_size = bc->size;
Jeeja KPabb74002015-11-28 15:01:49 +0530505
506 break;
507 }
508 }
509
510 return 0;
511}
512
Jeeja KPbb704a732016-12-08 13:41:14 +0530513static int skl_tplg_module_prepare(struct skl_sst *ctx, struct skl_pipe *pipe,
514 struct snd_soc_dapm_widget *w, struct skl_module_cfg *mcfg)
515{
516 switch (mcfg->dev_type) {
517 case SKL_DEVICE_HDAHOST:
518 return skl_pcm_host_dma_prepare(ctx->dev, pipe->p_params);
519
520 case SKL_DEVICE_HDALINK:
521 return skl_pcm_link_dma_prepare(ctx->dev, pipe->p_params);
522 }
523
524 return 0;
525}
526
Jeeja KPabb74002015-11-28 15:01:49 +0530527/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100528 * Inside a pipe instance, we can have various modules. These modules need
529 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
530 * skl_init_module() routine, so invoke that for all modules in a pipeline
531 */
532static int
533skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
534{
535 struct skl_pipe_module *w_module;
536 struct snd_soc_dapm_widget *w;
537 struct skl_module_cfg *mconfig;
538 struct skl_sst *ctx = skl->skl_sst;
539 int ret = 0;
540
541 list_for_each_entry(w_module, &pipe->w_list, node) {
Jeeja KPb26199e2017-03-24 23:10:31 +0530542 uuid_le *uuid_mod;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100543 w = w_module->w;
544 mconfig = w->priv;
545
Vinod Koulb7c50552016-07-26 18:06:40 +0530546 /* check if module ids are populated */
547 if (mconfig->id.module_id < 0) {
Vinod Koula657ae72016-08-10 09:40:50 +0530548 dev_err(skl->skl_sst->dev,
549 "module %pUL id not populated\n",
550 (uuid_le *)mconfig->guid);
551 return -EIO;
Vinod Koulb7c50552016-07-26 18:06:40 +0530552 }
553
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100554 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530555 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100556 return -ENOMEM;
557
Dharageswari R6c5768b2015-12-03 23:29:50 +0530558 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
559 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
560 mconfig->id.module_id, mconfig->guid);
561 if (ret < 0)
562 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530563
564 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530565 }
566
Jeeja KPbb704a732016-12-08 13:41:14 +0530567 /* prepare the DMA if the module is gateway cpr */
568 ret = skl_tplg_module_prepare(ctx, pipe, w, mconfig);
569 if (ret < 0)
570 return ret;
571
Jeeja KP2d1419a2016-02-05 12:19:10 +0530572 /* update blob if blob is null for be with default value */
573 skl_tplg_update_be_blob(w, ctx);
574
Jeeja KPf7590d42015-10-07 11:31:53 +0100575 /*
576 * apply fix/conversion to module params based on
577 * FE/BE params
578 */
579 skl_tplg_update_module_params(w, ctx);
Jeeja KPb26199e2017-03-24 23:10:31 +0530580 uuid_mod = (uuid_le *)mconfig->guid;
581 mconfig->id.pvt_id = skl_get_pvt_id(ctx, uuid_mod,
582 mconfig->id.instance_id);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530583 if (mconfig->id.pvt_id < 0)
584 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530585 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530586 ret = skl_init_module(ctx, mconfig);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530587 if (ret < 0) {
Jeeja KPb26199e2017-03-24 23:10:31 +0530588 skl_put_pvt_id(ctx, uuid_mod, &mconfig->id.pvt_id);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100589 return ret;
Dharageswari Ref2a3522016-09-22 14:00:38 +0530590 }
Dharageswari R260eb732016-06-03 18:29:38 +0530591 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPabb74002015-11-28 15:01:49 +0530592 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100593 if (ret < 0)
594 return ret;
595 }
596
597 return 0;
598}
Vinod Kould93f8e52015-10-07 11:31:54 +0100599
Dharageswari R6c5768b2015-12-03 23:29:50 +0530600static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
601 struct skl_pipe *pipe)
602{
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530603 int ret;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530604 struct skl_pipe_module *w_module = NULL;
605 struct skl_module_cfg *mconfig = NULL;
606
607 list_for_each_entry(w_module, &pipe->w_list, node) {
Jeeja KPb26199e2017-03-24 23:10:31 +0530608 uuid_le *uuid_mod;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530609 mconfig = w_module->w->priv;
Jeeja KPb26199e2017-03-24 23:10:31 +0530610 uuid_mod = (uuid_le *)mconfig->guid;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530611
Jeeja KPd6436782016-03-28 22:11:30 +0530612 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530613 mconfig->m_state > SKL_MODULE_UNINIT) {
614 ret = ctx->dsp->fw_ops.unload_mod(ctx->dsp,
Dharageswari R6c5768b2015-12-03 23:29:50 +0530615 mconfig->id.module_id);
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530616 if (ret < 0)
617 return -EIO;
618 }
Jeeja KPb26199e2017-03-24 23:10:31 +0530619 skl_put_pvt_id(ctx, uuid_mod, &mconfig->id.pvt_id);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530620 }
621
622 /* no modules to unload in this path, so return */
623 return 0;
624}
625
Vinod Kould93f8e52015-10-07 11:31:54 +0100626/*
627 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
628 * need create the pipeline. So we do following:
629 * - check the resources
630 * - Create the pipeline
631 * - Initialize the modules in pipeline
632 * - finally bind all modules together
633 */
634static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
635 struct skl *skl)
636{
637 int ret;
638 struct skl_module_cfg *mconfig = w->priv;
639 struct skl_pipe_module *w_module;
640 struct skl_pipe *s_pipe = mconfig->pipe;
Jeeja KPb8c722d2017-03-24 23:10:34 +0530641 struct skl_module_cfg *src_module = NULL, *dst_module, *module;
Vinod Kould93f8e52015-10-07 11:31:54 +0100642 struct skl_sst *ctx = skl->skl_sst;
Jeeja KPb8c722d2017-03-24 23:10:34 +0530643 struct skl_module_deferred_bind *modules;
Vinod Kould93f8e52015-10-07 11:31:54 +0100644
645 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530646 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100647 return -EBUSY;
648
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530649 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100650 return -ENOMEM;
651
652 /*
653 * Create a list of modules for pipe.
654 * This list contains modules from source to sink
655 */
656 ret = skl_create_pipeline(ctx, mconfig->pipe);
657 if (ret < 0)
658 return ret;
659
Dharageswari R260eb732016-06-03 18:29:38 +0530660 skl_tplg_alloc_pipe_mem(skl, mconfig);
661 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100662
663 /* Init all pipe modules from source to sink */
664 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
665 if (ret < 0)
666 return ret;
667
668 /* Bind modules from source to sink */
669 list_for_each_entry(w_module, &s_pipe->w_list, node) {
670 dst_module = w_module->w->priv;
671
672 if (src_module == NULL) {
673 src_module = dst_module;
674 continue;
675 }
676
677 ret = skl_bind_modules(ctx, src_module, dst_module);
678 if (ret < 0)
679 return ret;
680
681 src_module = dst_module;
682 }
683
Jeeja KPb8c722d2017-03-24 23:10:34 +0530684 /*
685 * When the destination module is initialized, check for these modules
686 * in deferred bind list. If found, bind them.
687 */
688 list_for_each_entry(w_module, &s_pipe->w_list, node) {
689 if (list_empty(&skl->bind_list))
690 break;
691
692 list_for_each_entry(modules, &skl->bind_list, node) {
693 module = w_module->w->priv;
694 if (modules->dst == module)
695 skl_bind_modules(ctx, modules->src,
696 modules->dst);
697 }
698 }
699
Vinod Kould93f8e52015-10-07 11:31:54 +0100700 return 0;
701}
702
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530703static int skl_fill_sink_instance_id(struct skl_sst *ctx, u32 *params,
704 int size, struct skl_module_cfg *mcfg)
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530705{
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530706 int i, pvt_id;
707
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530708 if (mcfg->m_type == SKL_MODULE_TYPE_KPB) {
709 struct skl_kpb_params *kpb_params =
710 (struct skl_kpb_params *)params;
711 struct skl_mod_inst_map *inst = kpb_params->map;
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530712
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530713 for (i = 0; i < kpb_params->num_modules; i++) {
714 pvt_id = skl_get_pvt_instance_id_map(ctx, inst->mod_id,
715 inst->inst_id);
716 if (pvt_id < 0)
717 return -EINVAL;
718
719 inst->inst_id = pvt_id;
720 inst++;
721 }
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530722 }
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530723
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530724 return 0;
725}
Jeeja KPcc6a4042016-02-05 12:19:08 +0530726/*
727 * Some modules require params to be set after the module is bound to
728 * all pins connected.
729 *
730 * The module provider initializes set_param flag for such modules and we
731 * send params after binding
732 */
733static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
734 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
735{
736 int i, ret;
737 struct skl_module_cfg *mconfig = w->priv;
738 const struct snd_kcontrol_new *k;
739 struct soc_bytes_ext *sb;
740 struct skl_algo_data *bc;
741 struct skl_specific_cfg *sp_cfg;
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530742 u32 *params;
Jeeja KPcc6a4042016-02-05 12:19:08 +0530743
744 /*
745 * check all out/in pins are in bind state.
746 * if so set the module param
747 */
748 for (i = 0; i < mcfg->max_out_queue; i++) {
749 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
750 return 0;
751 }
752
753 for (i = 0; i < mcfg->max_in_queue; i++) {
754 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
755 return 0;
756 }
757
758 if (mconfig->formats_config.caps_size > 0 &&
759 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
760 sp_cfg = &mconfig->formats_config;
761 ret = skl_set_module_params(ctx, sp_cfg->caps,
762 sp_cfg->caps_size,
763 sp_cfg->param_id, mconfig);
764 if (ret < 0)
765 return ret;
766 }
767
768 for (i = 0; i < w->num_kcontrols; i++) {
769 k = &w->kcontrol_news[i];
770 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
771 sb = (void *) k->private_value;
772 bc = (struct skl_algo_data *)sb->dobj.private;
773
774 if (bc->set_params == SKL_PARAM_BIND) {
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530775 params = kzalloc(bc->max, GFP_KERNEL);
776 if (!params)
777 return -ENOMEM;
778
779 memcpy(params, bc->params, bc->max);
780 skl_fill_sink_instance_id(ctx, params, bc->max,
781 mconfig);
782
783 ret = skl_set_module_params(ctx, params,
784 bc->max, bc->param_id, mconfig);
785 kfree(params);
786
Jeeja KPcc6a4042016-02-05 12:19:08 +0530787 if (ret < 0)
788 return ret;
789 }
790 }
791 }
792
793 return 0;
794}
795
Jeeja KPb8c722d2017-03-24 23:10:34 +0530796
797static int skl_tplg_module_add_deferred_bind(struct skl *skl,
798 struct skl_module_cfg *src, struct skl_module_cfg *dst)
799{
800 struct skl_module_deferred_bind *m_list, *modules;
801 int i;
802
803 /* only supported for module with static pin connection */
804 for (i = 0; i < dst->max_in_queue; i++) {
805 struct skl_module_pin *pin = &dst->m_in_pin[i];
806
807 if (pin->is_dynamic)
808 continue;
809
810 if ((pin->id.module_id == src->id.module_id) &&
811 (pin->id.instance_id == src->id.instance_id)) {
812
813 if (!list_empty(&skl->bind_list)) {
814 list_for_each_entry(modules, &skl->bind_list, node) {
815 if (modules->src == src && modules->dst == dst)
816 return 0;
817 }
818 }
819
820 m_list = kzalloc(sizeof(*m_list), GFP_KERNEL);
821 if (!m_list)
822 return -ENOMEM;
823
824 m_list->src = src;
825 m_list->dst = dst;
826
827 list_add(&m_list->node, &skl->bind_list);
828 }
829 }
830
831 return 0;
832}
833
Jeeja KP8724ff12015-10-27 09:22:52 +0900834static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
835 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530836 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900837 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100838{
839 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530840 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900841 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100842 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900843 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100844
Jeeja KP8724ff12015-10-27 09:22:52 +0900845 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100846 if (!p->connect)
847 continue;
848
849 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
850 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
851
Jeeja KP0ed95d72015-11-13 19:22:11 +0530852 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530853
854 if (!is_skl_dsp_widget_type(p->sink))
855 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
856
Vinod Kould93f8e52015-10-07 11:31:54 +0100857 /*
858 * here we will check widgets in sink pipelines, so that
859 * can be any widgets type and we are only interested if
860 * they are ones used for SKL so check that first
861 */
862 if ((p->sink->priv != NULL) &&
863 is_skl_dsp_widget_type(p->sink)) {
864
865 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100866 sink_mconfig = sink->priv;
867
Jeeja KPb8c722d2017-03-24 23:10:34 +0530868 /*
869 * Modules other than PGA leaf can be connected
870 * directly or via switch to a module in another
871 * pipeline. EX: reference path
872 * when the path is enabled, the dst module that needs
873 * to be bound may not be initialized. if the module is
874 * not initialized, add these modules in the deferred
875 * bind list and when the dst module is initialised,
876 * bind this module to the dst_module in deferred list.
877 */
878 if (((src_mconfig->m_state == SKL_MODULE_INIT_DONE)
879 && (sink_mconfig->m_state == SKL_MODULE_UNINIT))) {
880
881 ret = skl_tplg_module_add_deferred_bind(skl,
882 src_mconfig, sink_mconfig);
883
884 if (ret < 0)
885 return ret;
886
887 }
888
889
Jeeja KPcc6a4042016-02-05 12:19:08 +0530890 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
891 sink_mconfig->m_state == SKL_MODULE_UNINIT)
892 continue;
893
Vinod Kould93f8e52015-10-07 11:31:54 +0100894 /* Bind source to sink, mixin is always source */
895 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
896 if (ret)
897 return ret;
898
Jeeja KPcc6a4042016-02-05 12:19:08 +0530899 /* set module params after bind */
900 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
901 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
902
Vinod Kould93f8e52015-10-07 11:31:54 +0100903 /* Start sinks pipe first */
904 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900905 if (sink_mconfig->pipe->conn_type !=
906 SKL_PIPE_CONN_TYPE_FE)
907 ret = skl_run_pipe(ctx,
908 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100909 if (ret)
910 return ret;
911 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100912 }
913 }
914
Jeeja KP8724ff12015-10-27 09:22:52 +0900915 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530916 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900917
918 return 0;
919}
920
Vinod Kould93f8e52015-10-07 11:31:54 +0100921/*
922 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
923 * we need to do following:
924 * - Bind to sink pipeline
925 * Since the sink pipes can be running and we don't get mixer event on
926 * connect for already running mixer, we need to find the sink pipes
927 * here and bind to them. This way dynamic connect works.
928 * - Start sink pipeline, if not running
929 * - Then run current pipe
930 */
931static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900932 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100933{
Jeeja KP8724ff12015-10-27 09:22:52 +0900934 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100935 struct skl_sst *ctx = skl->skl_sst;
936 int ret = 0;
937
Jeeja KP8724ff12015-10-27 09:22:52 +0900938 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100939
940 /*
941 * find which sink it is connected to, bind with the sink,
942 * if sink is not started, start sink pipe first, then start
943 * this pipe
944 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530945 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100946 if (ret)
947 return ret;
948
Vinod Kould93f8e52015-10-07 11:31:54 +0100949 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900950 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
951 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100952
953 return 0;
954}
955
Jeeja KP8724ff12015-10-27 09:22:52 +0900956static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
957 struct snd_soc_dapm_widget *w, struct skl *skl)
958{
959 struct snd_soc_dapm_path *p;
960 struct snd_soc_dapm_widget *src_w = NULL;
961 struct skl_sst *ctx = skl->skl_sst;
962
963 snd_soc_dapm_widget_for_each_source_path(w, p) {
964 src_w = p->source;
965 if (!p->connect)
966 continue;
967
968 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
969 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
970
971 /*
972 * here we will check widgets in sink pipelines, so that can
973 * be any widgets type and we are only interested if they are
974 * ones used for SKL so check that first
975 */
976 if ((p->source->priv != NULL) &&
977 is_skl_dsp_widget_type(p->source)) {
978 return p->source;
979 }
980 }
981
982 if (src_w != NULL)
983 return skl_get_src_dsp_widget(src_w, skl);
984
985 return NULL;
986}
987
Vinod Kould93f8e52015-10-07 11:31:54 +0100988/*
989 * in the Post-PMU event of mixer we need to do following:
990 * - Check if this pipe is running
991 * - if not, then
992 * - bind this pipeline to its source pipeline
993 * if source pipe is already running, this means it is a dynamic
994 * connection and we need to bind only to that pipe
995 * - start this pipeline
996 */
997static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
998 struct skl *skl)
999{
1000 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +01001001 struct snd_soc_dapm_widget *source, *sink;
1002 struct skl_module_cfg *src_mconfig, *sink_mconfig;
1003 struct skl_sst *ctx = skl->skl_sst;
1004 int src_pipe_started = 0;
1005
1006 sink = w;
1007 sink_mconfig = sink->priv;
1008
1009 /*
1010 * If source pipe is already started, that means source is driving
1011 * one more sink before this sink got connected, Since source is
1012 * started, bind this sink to source and start this pipe.
1013 */
Jeeja KP8724ff12015-10-27 09:22:52 +09001014 source = skl_get_src_dsp_widget(w, skl);
1015 if (source != NULL) {
1016 src_mconfig = source->priv;
1017 sink_mconfig = sink->priv;
1018 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +01001019
1020 /*
Jeeja KP8724ff12015-10-27 09:22:52 +09001021 * check pipe state, then no need to bind or start the
1022 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +01001023 */
Jeeja KP8724ff12015-10-27 09:22:52 +09001024 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
1025 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +01001026 }
1027
1028 if (src_pipe_started) {
1029 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
1030 if (ret)
1031 return ret;
1032
Jeeja KPcc6a4042016-02-05 12:19:08 +05301033 /* set module params after bind */
1034 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
1035 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
1036
Jeeja KPd1730c32015-10-27 09:22:53 +09001037 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
1038 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001039 }
1040
1041 return ret;
1042}
1043
1044/*
1045 * in the Pre-PMD event of mixer we need to do following:
1046 * - Stop the pipe
1047 * - find the source connections and remove that from dapm_path_list
1048 * - unbind with source pipelines if still connected
1049 */
1050static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
1051 struct skl *skl)
1052{
Vinod Kould93f8e52015-10-07 11:31:54 +01001053 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +09001054 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +01001055 struct skl_sst *ctx = skl->skl_sst;
1056
Jeeja KPce1b5552015-10-27 09:22:51 +09001057 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +01001058
1059 /* Stop the pipe */
1060 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
1061 if (ret)
1062 return ret;
1063
Jeeja KPce1b5552015-10-27 09:22:51 +09001064 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
1065 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
1066 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
1067 if (!src_mconfig)
1068 continue;
Vinod Kould93f8e52015-10-07 11:31:54 +01001069
Jeeja KPce1b5552015-10-27 09:22:51 +09001070 ret = skl_unbind_modules(ctx,
1071 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001072 }
1073 }
1074
Vinod Kould93f8e52015-10-07 11:31:54 +01001075 return ret;
1076}
1077
1078/*
1079 * in the Post-PMD event of mixer we need to do following:
1080 * - Free the mcps used
1081 * - Free the mem used
1082 * - Unbind the modules within the pipeline
1083 * - Delete the pipeline (modules are not required to be explicitly
1084 * deleted, pipeline delete is enough here
1085 */
1086static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1087 struct skl *skl)
1088{
1089 struct skl_module_cfg *mconfig = w->priv;
1090 struct skl_pipe_module *w_module;
1091 struct skl_module_cfg *src_module = NULL, *dst_module;
1092 struct skl_sst *ctx = skl->skl_sst;
1093 struct skl_pipe *s_pipe = mconfig->pipe;
Dan Carpenter550b3492017-04-14 22:11:20 +03001094 struct skl_module_deferred_bind *modules, *tmp;
Vinod Kould93f8e52015-10-07 11:31:54 +01001095
Dharageswari R260eb732016-06-03 18:29:38 +05301096 if (s_pipe->state == SKL_PIPE_INVALID)
1097 return -EINVAL;
1098
Vinod Kould93f8e52015-10-07 11:31:54 +01001099 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +05301100 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001101
1102 list_for_each_entry(w_module, &s_pipe->w_list, node) {
Jeeja KPb8c722d2017-03-24 23:10:34 +05301103 if (list_empty(&skl->bind_list))
1104 break;
1105
1106 src_module = w_module->w->priv;
1107
Dan Carpenter550b3492017-04-14 22:11:20 +03001108 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
Jeeja KPb8c722d2017-03-24 23:10:34 +05301109 /*
1110 * When the destination module is deleted, Unbind the
1111 * modules from deferred bind list.
1112 */
1113 if (modules->dst == src_module) {
1114 skl_unbind_modules(ctx, modules->src,
1115 modules->dst);
1116 }
1117
1118 /*
1119 * When the source module is deleted, remove this entry
1120 * from the deferred bind list.
1121 */
1122 if (modules->src == src_module) {
1123 list_del(&modules->node);
1124 modules->src = NULL;
1125 modules->dst = NULL;
1126 kfree(modules);
1127 }
1128 }
1129 }
1130
1131 list_for_each_entry(w_module, &s_pipe->w_list, node) {
Vinod Kould93f8e52015-10-07 11:31:54 +01001132 dst_module = w_module->w->priv;
1133
Dharageswari R260eb732016-06-03 18:29:38 +05301134 if (mconfig->m_state >= SKL_MODULE_INIT_DONE)
1135 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001136 if (src_module == NULL) {
1137 src_module = dst_module;
1138 continue;
1139 }
1140
Guneshwor Singh7ca42f52016-02-03 17:59:46 +05301141 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001142 src_module = dst_module;
1143 }
1144
Vinod Koul547cafa2016-12-08 23:01:24 +05301145 skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001146
Jeeja KP473a4d52017-03-24 23:10:33 +05301147 list_for_each_entry(w_module, &s_pipe->w_list, node) {
1148 src_module = w_module->w->priv;
1149 src_module->m_state = SKL_MODULE_UNINIT;
1150 }
1151
Dharageswari R6c5768b2015-12-03 23:29:50 +05301152 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001153}
1154
1155/*
1156 * in the Post-PMD event of PGA we need to do following:
1157 * - Free the mcps used
1158 * - Stop the pipeline
1159 * - In source pipe is connected, unbind with source pipelines
1160 */
1161static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1162 struct skl *skl)
1163{
Vinod Kould93f8e52015-10-07 11:31:54 +01001164 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +09001165 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +01001166 struct skl_sst *ctx = skl->skl_sst;
1167
Jeeja KPce1b5552015-10-27 09:22:51 +09001168 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +01001169
Vinod Kould93f8e52015-10-07 11:31:54 +01001170 /* Stop the pipe since this is a mixin module */
1171 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
1172 if (ret)
1173 return ret;
1174
Jeeja KPce1b5552015-10-27 09:22:51 +09001175 for (i = 0; i < src_mconfig->max_out_queue; i++) {
1176 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
1177 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
1178 if (!sink_mconfig)
1179 continue;
1180 /*
1181 * This is a connecter and if path is found that means
1182 * unbind between source and sink has not happened yet
1183 */
Jeeja KPce1b5552015-10-27 09:22:51 +09001184 ret = skl_unbind_modules(ctx, src_mconfig,
1185 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001186 }
1187 }
1188
Vinod Kould93f8e52015-10-07 11:31:54 +01001189 return ret;
1190}
1191
1192/*
Vinod Kould93f8e52015-10-07 11:31:54 +01001193 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1194 * second one is required that is created as another pipe entity.
1195 * The mixer is responsible for pipe management and represent a pipeline
1196 * instance
1197 */
1198static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1199 struct snd_kcontrol *k, int event)
1200{
1201 struct snd_soc_dapm_context *dapm = w->dapm;
1202 struct skl *skl = get_skl_ctx(dapm->dev);
1203
1204 switch (event) {
1205 case SND_SOC_DAPM_PRE_PMU:
1206 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1207
1208 case SND_SOC_DAPM_POST_PMU:
1209 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1210
1211 case SND_SOC_DAPM_PRE_PMD:
1212 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1213
1214 case SND_SOC_DAPM_POST_PMD:
1215 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1216 }
1217
1218 return 0;
1219}
1220
1221/*
1222 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1223 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1224 * the sink when it is running (two FE to one BE or one FE to two BE)
1225 * scenarios
1226 */
1227static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1228 struct snd_kcontrol *k, int event)
1229
1230{
1231 struct snd_soc_dapm_context *dapm = w->dapm;
1232 struct skl *skl = get_skl_ctx(dapm->dev);
1233
1234 switch (event) {
1235 case SND_SOC_DAPM_PRE_PMU:
1236 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1237
1238 case SND_SOC_DAPM_POST_PMD:
1239 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1240 }
1241
1242 return 0;
1243}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001244
Jeeja KP140adfb2015-11-28 15:01:50 +05301245static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1246 unsigned int __user *data, unsigned int size)
1247{
1248 struct soc_bytes_ext *sb =
1249 (struct soc_bytes_ext *)kcontrol->private_value;
1250 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301251 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1252 struct skl_module_cfg *mconfig = w->priv;
1253 struct skl *skl = get_skl_ctx(w->dapm->dev);
1254
1255 if (w->power)
1256 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
Dharageswari R0d682102016-07-08 18:15:03 +05301257 bc->size, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301258
Vinod Koul41556f62016-02-03 17:59:44 +05301259 /* decrement size for TLV header */
1260 size -= 2 * sizeof(u32);
1261
1262 /* check size as we don't want to send kernel data */
1263 if (size > bc->max)
1264 size = bc->max;
1265
Jeeja KP140adfb2015-11-28 15:01:50 +05301266 if (bc->params) {
1267 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1268 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001269 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301270 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001271 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301272 return -EFAULT;
1273 }
1274
1275 return 0;
1276}
1277
1278#define SKL_PARAM_VENDOR_ID 0xff
1279
1280static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1281 const unsigned int __user *data, unsigned int size)
1282{
1283 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1284 struct skl_module_cfg *mconfig = w->priv;
1285 struct soc_bytes_ext *sb =
1286 (struct soc_bytes_ext *)kcontrol->private_value;
1287 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1288 struct skl *skl = get_skl_ctx(w->dapm->dev);
1289
1290 if (ac->params) {
Dharageswari R0d682102016-07-08 18:15:03 +05301291 if (size > ac->max)
1292 return -EINVAL;
1293
1294 ac->size = size;
Jeeja KP140adfb2015-11-28 15:01:50 +05301295 /*
1296 * if the param_is is of type Vendor, firmware expects actual
1297 * parameter id and size from the control.
1298 */
1299 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1300 if (copy_from_user(ac->params, data, size))
1301 return -EFAULT;
1302 } else {
1303 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301304 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301305 return -EFAULT;
1306 }
1307
1308 if (w->power)
1309 return skl_set_module_params(skl->skl_sst,
Dharageswari R0d682102016-07-08 18:15:03 +05301310 (u32 *)ac->params, ac->size,
Jeeja KP140adfb2015-11-28 15:01:50 +05301311 ac->param_id, mconfig);
1312 }
1313
1314 return 0;
1315}
1316
Vinod Koulcfb0a872015-10-07 11:31:55 +01001317/*
Jeeja KP8871dcb2016-06-03 18:29:42 +05301318 * Fill the dma id for host and link. In case of passthrough
1319 * pipeline, this will both host and link in the same
1320 * pipeline, so need to copy the link and host based on dev_type
1321 */
1322static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
1323 struct skl_pipe_params *params)
1324{
1325 struct skl_pipe *pipe = mcfg->pipe;
1326
1327 if (pipe->passthru) {
1328 switch (mcfg->dev_type) {
1329 case SKL_DEVICE_HDALINK:
1330 pipe->p_params->link_dma_id = params->link_dma_id;
Jeeja KP12c3be02016-12-08 13:41:12 +05301331 pipe->p_params->link_index = params->link_index;
Jeeja KP7f975a32017-03-24 23:10:25 +05301332 pipe->p_params->link_bps = params->link_bps;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301333 break;
1334
1335 case SKL_DEVICE_HDAHOST:
1336 pipe->p_params->host_dma_id = params->host_dma_id;
Jeeja KP7f975a32017-03-24 23:10:25 +05301337 pipe->p_params->host_bps = params->host_bps;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301338 break;
1339
1340 default:
1341 break;
1342 }
1343 pipe->p_params->s_fmt = params->s_fmt;
1344 pipe->p_params->ch = params->ch;
1345 pipe->p_params->s_freq = params->s_freq;
1346 pipe->p_params->stream = params->stream;
Jeeja KP12c3be02016-12-08 13:41:12 +05301347 pipe->p_params->format = params->format;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301348
1349 } else {
1350 memcpy(pipe->p_params, params, sizeof(*params));
1351 }
1352}
1353
1354/*
Vinod Koulcfb0a872015-10-07 11:31:55 +01001355 * The FE params are passed by hw_params of the DAI.
1356 * On hw_params, the params are stored in Gateway module of the FE and we
1357 * need to calculate the format in DSP module configuration, that
1358 * conversion is done here
1359 */
1360int skl_tplg_update_pipe_params(struct device *dev,
1361 struct skl_module_cfg *mconfig,
1362 struct skl_pipe_params *params)
1363{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001364 struct skl_module_fmt *format = NULL;
1365
Jeeja KP8871dcb2016-06-03 18:29:42 +05301366 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001367
1368 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001369 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001370 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001371 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001372
1373 /* set the hw_params */
1374 format->s_freq = params->s_freq;
1375 format->channels = params->ch;
1376 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1377
1378 /*
1379 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1380 * container so update bit depth accordingly
1381 */
1382 switch (format->valid_bit_depth) {
1383 case SKL_DEPTH_16BIT:
1384 format->bit_depth = format->valid_bit_depth;
1385 break;
1386
1387 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001388 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001389 format->bit_depth = SKL_DEPTH_32BIT;
1390 break;
1391
1392 default:
1393 dev_err(dev, "Invalid bit depth %x for pipe\n",
1394 format->valid_bit_depth);
1395 return -EINVAL;
1396 }
1397
1398 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1399 mconfig->ibs = (format->s_freq / 1000) *
1400 (format->channels) *
1401 (format->bit_depth >> 3);
1402 } else {
1403 mconfig->obs = (format->s_freq / 1000) *
1404 (format->channels) *
1405 (format->bit_depth >> 3);
1406 }
1407
1408 return 0;
1409}
1410
1411/*
1412 * Query the module config for the FE DAI
1413 * This is used to find the hw_params set for that DAI and apply to FE
1414 * pipeline
1415 */
1416struct skl_module_cfg *
1417skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1418{
1419 struct snd_soc_dapm_widget *w;
1420 struct snd_soc_dapm_path *p = NULL;
1421
1422 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1423 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301424 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001425 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001426 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001427 continue;
1428
1429 if (p->sink->priv) {
1430 dev_dbg(dai->dev, "set params for %s\n",
1431 p->sink->name);
1432 return p->sink->priv;
1433 }
1434 }
1435 } else {
1436 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301437 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001438 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001439 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001440 continue;
1441
1442 if (p->source->priv) {
1443 dev_dbg(dai->dev, "set params for %s\n",
1444 p->source->name);
1445 return p->source->priv;
1446 }
1447 }
1448 }
1449
1450 return NULL;
1451}
1452
Dharageswari.R718a42b2016-02-05 12:19:06 +05301453static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1454 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1455{
1456 struct snd_soc_dapm_path *p;
1457 struct skl_module_cfg *mconfig = NULL;
1458
1459 snd_soc_dapm_widget_for_each_source_path(w, p) {
1460 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1461 if (p->connect &&
1462 (p->sink->id == snd_soc_dapm_aif_out) &&
1463 p->source->priv) {
1464 mconfig = p->source->priv;
1465 return mconfig;
1466 }
1467 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1468 if (mconfig)
1469 return mconfig;
1470 }
1471 }
1472 return mconfig;
1473}
1474
1475static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1476 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1477{
1478 struct snd_soc_dapm_path *p;
1479 struct skl_module_cfg *mconfig = NULL;
1480
1481 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1482 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1483 if (p->connect &&
1484 (p->source->id == snd_soc_dapm_aif_in) &&
1485 p->sink->priv) {
1486 mconfig = p->sink->priv;
1487 return mconfig;
1488 }
1489 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1490 if (mconfig)
1491 return mconfig;
1492 }
1493 }
1494 return mconfig;
1495}
1496
1497struct skl_module_cfg *
1498skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1499{
1500 struct snd_soc_dapm_widget *w;
1501 struct skl_module_cfg *mconfig;
1502
1503 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1504 w = dai->playback_widget;
1505 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1506 } else {
1507 w = dai->capture_widget;
1508 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1509 }
1510 return mconfig;
1511}
1512
Vinod Koulcfb0a872015-10-07 11:31:55 +01001513static u8 skl_tplg_be_link_type(int dev_type)
1514{
1515 int ret;
1516
1517 switch (dev_type) {
1518 case SKL_DEVICE_BT:
1519 ret = NHLT_LINK_SSP;
1520 break;
1521
1522 case SKL_DEVICE_DMIC:
1523 ret = NHLT_LINK_DMIC;
1524 break;
1525
1526 case SKL_DEVICE_I2S:
1527 ret = NHLT_LINK_SSP;
1528 break;
1529
1530 case SKL_DEVICE_HDALINK:
1531 ret = NHLT_LINK_HDA;
1532 break;
1533
1534 default:
1535 ret = NHLT_LINK_INVALID;
1536 break;
1537 }
1538
1539 return ret;
1540}
1541
1542/*
1543 * Fill the BE gateway parameters
1544 * The BE gateway expects a blob of parameters which are kept in the ACPI
1545 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1546 * The port can have multiple settings so pick based on the PCM
1547 * parameters
1548 */
1549static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1550 struct skl_module_cfg *mconfig,
1551 struct skl_pipe_params *params)
1552{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001553 struct nhlt_specific_cfg *cfg;
1554 struct skl *skl = get_skl_ctx(dai->dev);
1555 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301556 u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001557
Jeeja KP8871dcb2016-06-03 18:29:42 +05301558 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001559
Jeeja KPb30c2752015-10-27 09:22:48 +09001560 if (link_type == NHLT_LINK_HDA)
1561 return 0;
1562
Vinod Koulcfb0a872015-10-07 11:31:55 +01001563 /* update the blob based on virtual bus_id*/
1564 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1565 params->s_fmt, params->ch,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301566 params->s_freq, params->stream,
1567 dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001568 if (cfg) {
1569 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301570 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001571 } else {
1572 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1573 mconfig->vbus_id, link_type,
1574 params->stream);
1575 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1576 params->ch, params->s_freq, params->s_fmt);
1577 return -EINVAL;
1578 }
1579
1580 return 0;
1581}
1582
1583static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1584 struct snd_soc_dapm_widget *w,
1585 struct skl_pipe_params *params)
1586{
1587 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301588 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001589
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301590 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001591 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1592 p->source->priv) {
1593
Jeeja KP9a03cb42015-10-27 09:22:54 +09001594 ret = skl_tplg_be_fill_pipe_params(dai,
1595 p->source->priv, params);
1596 if (ret < 0)
1597 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001598 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001599 ret = skl_tplg_be_set_src_pipe_params(dai,
1600 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301601 if (ret < 0)
1602 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001603 }
1604 }
1605
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301606 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001607}
1608
1609static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1610 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1611{
1612 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301613 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001614
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301615 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001616 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1617 p->sink->priv) {
1618
Jeeja KP9a03cb42015-10-27 09:22:54 +09001619 ret = skl_tplg_be_fill_pipe_params(dai,
1620 p->sink->priv, params);
1621 if (ret < 0)
1622 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001623 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301624 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001625 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301626 if (ret < 0)
1627 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001628 }
1629 }
1630
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301631 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001632}
1633
1634/*
1635 * BE hw_params can be a source parameters (capture) or sink parameters
1636 * (playback). Based on sink and source we need to either find the source
1637 * list or the sink list and set the pipeline parameters
1638 */
1639int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1640 struct skl_pipe_params *params)
1641{
1642 struct snd_soc_dapm_widget *w;
1643
1644 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1645 w = dai->playback_widget;
1646
1647 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1648
1649 } else {
1650 w = dai->capture_widget;
1651
1652 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1653 }
1654
1655 return 0;
1656}
Vinod Koul3af36702015-10-07 11:31:56 +01001657
1658static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1659 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
Vinod Koul9a1e3502017-03-24 23:10:29 +05301660 {SKL_VMIXER_EVENT, skl_tplg_mixer_event},
Vinod Koul3af36702015-10-07 11:31:56 +01001661 {SKL_PGA_EVENT, skl_tplg_pga_event},
1662};
1663
Jeeja KP140adfb2015-11-28 15:01:50 +05301664static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1665 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1666 skl_tplg_tlv_control_set},
1667};
1668
Shreyas NC6277e832016-08-12 12:29:51 +05301669static int skl_tplg_fill_pipe_tkn(struct device *dev,
1670 struct skl_pipe *pipe, u32 tkn,
1671 u32 tkn_val)
Vinod Koul3af36702015-10-07 11:31:56 +01001672{
Vinod Koul3af36702015-10-07 11:31:56 +01001673
Shreyas NC6277e832016-08-12 12:29:51 +05301674 switch (tkn) {
1675 case SKL_TKN_U32_PIPE_CONN_TYPE:
1676 pipe->conn_type = tkn_val;
1677 break;
1678
1679 case SKL_TKN_U32_PIPE_PRIORITY:
1680 pipe->pipe_priority = tkn_val;
1681 break;
1682
1683 case SKL_TKN_U32_PIPE_MEM_PGS:
1684 pipe->memory_pages = tkn_val;
1685 break;
1686
Vinod Koul8a0cb232016-11-03 17:07:18 +05301687 case SKL_TKN_U32_PMODE:
1688 pipe->lp_mode = tkn_val;
1689 break;
1690
Shreyas NC6277e832016-08-12 12:29:51 +05301691 default:
1692 dev_err(dev, "Token not handled %d\n", tkn);
1693 return -EINVAL;
Vinod Koul3af36702015-10-07 11:31:56 +01001694 }
Shreyas NC6277e832016-08-12 12:29:51 +05301695
1696 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001697}
1698
1699/*
Shreyas NC6277e832016-08-12 12:29:51 +05301700 * Add pipeline by parsing the relevant tokens
1701 * Return an existing pipe if the pipe already exists.
Vinod Koul3af36702015-10-07 11:31:56 +01001702 */
Shreyas NC6277e832016-08-12 12:29:51 +05301703static int skl_tplg_add_pipe(struct device *dev,
1704 struct skl_module_cfg *mconfig, struct skl *skl,
1705 struct snd_soc_tplg_vendor_value_elem *tkn_elem)
Vinod Koul3af36702015-10-07 11:31:56 +01001706{
1707 struct skl_pipeline *ppl;
1708 struct skl_pipe *pipe;
1709 struct skl_pipe_params *params;
1710
1711 list_for_each_entry(ppl, &skl->ppl_list, node) {
Shreyas NC6277e832016-08-12 12:29:51 +05301712 if (ppl->pipe->ppl_id == tkn_elem->value) {
1713 mconfig->pipe = ppl->pipe;
Guneshwor Singh081dc8a2017-04-27 12:21:22 +05301714 return -EEXIST;
Shreyas NC6277e832016-08-12 12:29:51 +05301715 }
Vinod Koul3af36702015-10-07 11:31:56 +01001716 }
1717
1718 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1719 if (!ppl)
Shreyas NC6277e832016-08-12 12:29:51 +05301720 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001721
1722 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1723 if (!pipe)
Shreyas NC6277e832016-08-12 12:29:51 +05301724 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001725
1726 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1727 if (!params)
Shreyas NC6277e832016-08-12 12:29:51 +05301728 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001729
Vinod Koul3af36702015-10-07 11:31:56 +01001730 pipe->p_params = params;
Shreyas NC6277e832016-08-12 12:29:51 +05301731 pipe->ppl_id = tkn_elem->value;
Vinod Koul3af36702015-10-07 11:31:56 +01001732 INIT_LIST_HEAD(&pipe->w_list);
1733
1734 ppl->pipe = pipe;
1735 list_add(&ppl->node, &skl->ppl_list);
1736
Shreyas NC6277e832016-08-12 12:29:51 +05301737 mconfig->pipe = pipe;
1738 mconfig->pipe->state = SKL_PIPE_INVALID;
1739
1740 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001741}
1742
Shreyas NC6277e832016-08-12 12:29:51 +05301743static int skl_tplg_fill_pin(struct device *dev, u32 tkn,
1744 struct skl_module_pin *m_pin,
1745 int pin_index, u32 value)
1746{
1747 switch (tkn) {
1748 case SKL_TKN_U32_PIN_MOD_ID:
1749 m_pin[pin_index].id.module_id = value;
1750 break;
1751
1752 case SKL_TKN_U32_PIN_INST_ID:
1753 m_pin[pin_index].id.instance_id = value;
1754 break;
1755
1756 default:
1757 dev_err(dev, "%d Not a pin token\n", value);
1758 return -EINVAL;
1759 }
1760
1761 return 0;
1762}
1763
1764/*
1765 * Parse for pin config specific tokens to fill up the
1766 * module private data
1767 */
1768static int skl_tplg_fill_pins_info(struct device *dev,
1769 struct skl_module_cfg *mconfig,
1770 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1771 int dir, int pin_count)
1772{
1773 int ret;
1774 struct skl_module_pin *m_pin;
1775
1776 switch (dir) {
1777 case SKL_DIR_IN:
1778 m_pin = mconfig->m_in_pin;
1779 break;
1780
1781 case SKL_DIR_OUT:
1782 m_pin = mconfig->m_out_pin;
1783 break;
1784
1785 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001786 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301787 return -EINVAL;
1788 }
1789
1790 ret = skl_tplg_fill_pin(dev, tkn_elem->token,
1791 m_pin, pin_count, tkn_elem->value);
1792
1793 if (ret < 0)
1794 return ret;
1795
1796 m_pin[pin_count].in_use = false;
1797 m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
1798
1799 return 0;
1800}
1801
1802/*
1803 * Fill up input/output module config format based
1804 * on the direction
1805 */
1806static int skl_tplg_fill_fmt(struct device *dev,
1807 struct skl_module_cfg *mconfig, u32 tkn,
1808 u32 value, u32 dir, u32 pin_count)
1809{
1810 struct skl_module_fmt *dst_fmt;
1811
1812 switch (dir) {
1813 case SKL_DIR_IN:
1814 dst_fmt = mconfig->in_fmt;
1815 dst_fmt += pin_count;
1816 break;
1817
1818 case SKL_DIR_OUT:
1819 dst_fmt = mconfig->out_fmt;
1820 dst_fmt += pin_count;
1821 break;
1822
1823 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001824 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301825 return -EINVAL;
1826 }
1827
1828 switch (tkn) {
1829 case SKL_TKN_U32_FMT_CH:
1830 dst_fmt->channels = value;
1831 break;
1832
1833 case SKL_TKN_U32_FMT_FREQ:
1834 dst_fmt->s_freq = value;
1835 break;
1836
1837 case SKL_TKN_U32_FMT_BIT_DEPTH:
1838 dst_fmt->bit_depth = value;
1839 break;
1840
1841 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1842 dst_fmt->valid_bit_depth = value;
1843 break;
1844
1845 case SKL_TKN_U32_FMT_CH_CONFIG:
1846 dst_fmt->ch_cfg = value;
1847 break;
1848
1849 case SKL_TKN_U32_FMT_INTERLEAVE:
1850 dst_fmt->interleaving_style = value;
1851 break;
1852
1853 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1854 dst_fmt->sample_type = value;
1855 break;
1856
1857 case SKL_TKN_U32_FMT_CH_MAP:
1858 dst_fmt->ch_map = value;
1859 break;
1860
1861 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001862 dev_err(dev, "Invalid token %d\n", tkn);
Shreyas NC6277e832016-08-12 12:29:51 +05301863 return -EINVAL;
1864 }
1865
1866 return 0;
1867}
1868
1869static int skl_tplg_get_uuid(struct device *dev, struct skl_module_cfg *mconfig,
1870 struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
1871{
1872 if (uuid_tkn->token == SKL_TKN_UUID)
1873 memcpy(&mconfig->guid, &uuid_tkn->uuid, 16);
1874 else {
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001875 dev_err(dev, "Not an UUID token tkn %d\n", uuid_tkn->token);
Shreyas NC6277e832016-08-12 12:29:51 +05301876 return -EINVAL;
1877 }
1878
1879 return 0;
1880}
1881
1882static void skl_tplg_fill_pin_dynamic_val(
1883 struct skl_module_pin *mpin, u32 pin_count, u32 value)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001884{
1885 int i;
1886
Shreyas NC6277e832016-08-12 12:29:51 +05301887 for (i = 0; i < pin_count; i++)
1888 mpin[i].is_dynamic = value;
1889}
1890
1891/*
1892 * Parse tokens to fill up the module private data
1893 */
1894static int skl_tplg_get_token(struct device *dev,
1895 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1896 struct skl *skl, struct skl_module_cfg *mconfig)
1897{
1898 int tkn_count = 0;
1899 int ret;
1900 static int is_pipe_exists;
1901 static int pin_index, dir;
1902
1903 if (tkn_elem->token > SKL_TKN_MAX)
1904 return -EINVAL;
1905
1906 switch (tkn_elem->token) {
1907 case SKL_TKN_U8_IN_QUEUE_COUNT:
1908 mconfig->max_in_queue = tkn_elem->value;
1909 mconfig->m_in_pin = devm_kzalloc(dev, mconfig->max_in_queue *
1910 sizeof(*mconfig->m_in_pin),
1911 GFP_KERNEL);
1912 if (!mconfig->m_in_pin)
1913 return -ENOMEM;
1914
1915 break;
1916
1917 case SKL_TKN_U8_OUT_QUEUE_COUNT:
1918 mconfig->max_out_queue = tkn_elem->value;
1919 mconfig->m_out_pin = devm_kzalloc(dev, mconfig->max_out_queue *
1920 sizeof(*mconfig->m_out_pin),
1921 GFP_KERNEL);
1922
1923 if (!mconfig->m_out_pin)
1924 return -ENOMEM;
1925
1926 break;
1927
1928 case SKL_TKN_U8_DYN_IN_PIN:
1929 if (!mconfig->m_in_pin)
1930 return -ENOMEM;
1931
1932 skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin,
1933 mconfig->max_in_queue, tkn_elem->value);
1934
1935 break;
1936
1937 case SKL_TKN_U8_DYN_OUT_PIN:
1938 if (!mconfig->m_out_pin)
1939 return -ENOMEM;
1940
1941 skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin,
1942 mconfig->max_out_queue, tkn_elem->value);
1943
1944 break;
1945
1946 case SKL_TKN_U8_TIME_SLOT:
1947 mconfig->time_slot = tkn_elem->value;
1948 break;
1949
1950 case SKL_TKN_U8_CORE_ID:
1951 mconfig->core_id = tkn_elem->value;
1952
1953 case SKL_TKN_U8_MOD_TYPE:
1954 mconfig->m_type = tkn_elem->value;
1955 break;
1956
1957 case SKL_TKN_U8_DEV_TYPE:
1958 mconfig->dev_type = tkn_elem->value;
1959 break;
1960
1961 case SKL_TKN_U8_HW_CONN_TYPE:
1962 mconfig->hw_conn_type = tkn_elem->value;
1963 break;
1964
1965 case SKL_TKN_U16_MOD_INST_ID:
1966 mconfig->id.instance_id =
1967 tkn_elem->value;
1968 break;
1969
1970 case SKL_TKN_U32_MEM_PAGES:
1971 mconfig->mem_pages = tkn_elem->value;
1972 break;
1973
1974 case SKL_TKN_U32_MAX_MCPS:
1975 mconfig->mcps = tkn_elem->value;
1976 break;
1977
1978 case SKL_TKN_U32_OBS:
1979 mconfig->obs = tkn_elem->value;
1980 break;
1981
1982 case SKL_TKN_U32_IBS:
1983 mconfig->ibs = tkn_elem->value;
1984 break;
1985
1986 case SKL_TKN_U32_VBUS_ID:
1987 mconfig->vbus_id = tkn_elem->value;
1988 break;
1989
1990 case SKL_TKN_U32_PARAMS_FIXUP:
1991 mconfig->params_fixup = tkn_elem->value;
1992 break;
1993
1994 case SKL_TKN_U32_CONVERTER:
1995 mconfig->converter = tkn_elem->value;
1996 break;
1997
Subhransu S. Prustyc0116be2017-05-04 14:09:11 +05301998 case SKL_TKN_U32_D0I3_CAPS:
Vinod Koul6bd9dcf2016-11-03 17:07:19 +05301999 mconfig->d0i3_caps = tkn_elem->value;
2000 break;
2001
Shreyas NC6277e832016-08-12 12:29:51 +05302002 case SKL_TKN_U32_PIPE_ID:
2003 ret = skl_tplg_add_pipe(dev,
2004 mconfig, skl, tkn_elem);
2005
Guneshwor Singh081dc8a2017-04-27 12:21:22 +05302006 if (ret < 0) {
2007 if (ret == -EEXIST) {
2008 is_pipe_exists = 1;
2009 break;
2010 }
Shreyas NC6277e832016-08-12 12:29:51 +05302011 return is_pipe_exists;
Guneshwor Singh081dc8a2017-04-27 12:21:22 +05302012 }
Shreyas NC6277e832016-08-12 12:29:51 +05302013
2014 break;
2015
2016 case SKL_TKN_U32_PIPE_CONN_TYPE:
2017 case SKL_TKN_U32_PIPE_PRIORITY:
2018 case SKL_TKN_U32_PIPE_MEM_PGS:
Vinod Koul8a0cb232016-11-03 17:07:18 +05302019 case SKL_TKN_U32_PMODE:
Shreyas NC6277e832016-08-12 12:29:51 +05302020 if (is_pipe_exists) {
2021 ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
2022 tkn_elem->token, tkn_elem->value);
2023 if (ret < 0)
2024 return ret;
2025 }
2026
2027 break;
2028
2029 /*
2030 * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
2031 * direction and the pin count. The first four bits represent
2032 * direction and next four the pin count.
2033 */
2034 case SKL_TKN_U32_DIR_PIN_COUNT:
2035 dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
2036 pin_index = (tkn_elem->value &
2037 SKL_PIN_COUNT_MASK) >> 4;
2038
2039 break;
2040
2041 case SKL_TKN_U32_FMT_CH:
2042 case SKL_TKN_U32_FMT_FREQ:
2043 case SKL_TKN_U32_FMT_BIT_DEPTH:
2044 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
2045 case SKL_TKN_U32_FMT_CH_CONFIG:
2046 case SKL_TKN_U32_FMT_INTERLEAVE:
2047 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
2048 case SKL_TKN_U32_FMT_CH_MAP:
2049 ret = skl_tplg_fill_fmt(dev, mconfig, tkn_elem->token,
2050 tkn_elem->value, dir, pin_index);
2051
2052 if (ret < 0)
2053 return ret;
2054
2055 break;
2056
2057 case SKL_TKN_U32_PIN_MOD_ID:
2058 case SKL_TKN_U32_PIN_INST_ID:
2059 ret = skl_tplg_fill_pins_info(dev,
2060 mconfig, tkn_elem, dir,
2061 pin_index);
2062 if (ret < 0)
2063 return ret;
2064
2065 break;
2066
2067 case SKL_TKN_U32_CAPS_SIZE:
2068 mconfig->formats_config.caps_size =
2069 tkn_elem->value;
2070
2071 break;
2072
Shreyas NC133e6e52017-05-15 19:44:31 +05302073 case SKL_TKN_U32_CAPS_SET_PARAMS:
2074 mconfig->formats_config.set_params =
2075 tkn_elem->value;
2076 break;
2077
2078 case SKL_TKN_U32_CAPS_PARAMS_ID:
2079 mconfig->formats_config.param_id =
2080 tkn_elem->value;
2081 break;
2082
Shreyas NC6277e832016-08-12 12:29:51 +05302083 case SKL_TKN_U32_PROC_DOMAIN:
2084 mconfig->domain =
2085 tkn_elem->value;
2086
2087 break;
2088
2089 case SKL_TKN_U8_IN_PIN_TYPE:
2090 case SKL_TKN_U8_OUT_PIN_TYPE:
2091 case SKL_TKN_U8_CONN_TYPE:
2092 break;
2093
2094 default:
2095 dev_err(dev, "Token %d not handled\n",
2096 tkn_elem->token);
2097 return -EINVAL;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002098 }
Shreyas NC6277e832016-08-12 12:29:51 +05302099
2100 tkn_count++;
2101
2102 return tkn_count;
2103}
2104
2105/*
2106 * Parse the vendor array for specific tokens to construct
2107 * module private data
2108 */
2109static int skl_tplg_get_tokens(struct device *dev,
2110 char *pvt_data, struct skl *skl,
2111 struct skl_module_cfg *mconfig, int block_size)
2112{
2113 struct snd_soc_tplg_vendor_array *array;
2114 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2115 int tkn_count = 0, ret;
2116 int off = 0, tuple_size = 0;
2117
2118 if (block_size <= 0)
2119 return -EINVAL;
2120
2121 while (tuple_size < block_size) {
2122 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2123
2124 off += array->size;
2125
2126 switch (array->type) {
2127 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002128 dev_warn(dev, "no string tokens expected for skl tplg\n");
Shreyas NC6277e832016-08-12 12:29:51 +05302129 continue;
2130
2131 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
2132 ret = skl_tplg_get_uuid(dev, mconfig, array->uuid);
2133 if (ret < 0)
2134 return ret;
2135
2136 tuple_size += sizeof(*array->uuid);
2137
2138 continue;
2139
2140 default:
2141 tkn_elem = array->value;
2142 tkn_count = 0;
2143 break;
2144 }
2145
2146 while (tkn_count <= (array->num_elems - 1)) {
2147 ret = skl_tplg_get_token(dev, tkn_elem,
2148 skl, mconfig);
2149
2150 if (ret < 0)
2151 return ret;
2152
2153 tkn_count = tkn_count + ret;
2154 tkn_elem++;
2155 }
2156
2157 tuple_size += tkn_count * sizeof(*tkn_elem);
2158 }
2159
Shreyas NC133e6e52017-05-15 19:44:31 +05302160 return off;
Shreyas NC6277e832016-08-12 12:29:51 +05302161}
2162
2163/*
2164 * Every data block is preceded by a descriptor to read the number
2165 * of data blocks, they type of the block and it's size
2166 */
2167static int skl_tplg_get_desc_blocks(struct device *dev,
2168 struct snd_soc_tplg_vendor_array *array)
2169{
2170 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2171
2172 tkn_elem = array->value;
2173
2174 switch (tkn_elem->token) {
2175 case SKL_TKN_U8_NUM_BLOCKS:
2176 case SKL_TKN_U8_BLOCK_TYPE:
2177 case SKL_TKN_U16_BLOCK_SIZE:
2178 return tkn_elem->value;
2179
2180 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002181 dev_err(dev, "Invalid descriptor token %d\n", tkn_elem->token);
Shreyas NC6277e832016-08-12 12:29:51 +05302182 break;
2183 }
2184
2185 return -EINVAL;
2186}
2187
2188/*
2189 * Parse the private data for the token and corresponding value.
2190 * The private data can have multiple data blocks. So, a data block
2191 * is preceded by a descriptor for number of blocks and a descriptor
2192 * for the type and size of the suceeding data block.
2193 */
2194static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
2195 struct skl *skl, struct device *dev,
2196 struct skl_module_cfg *mconfig)
2197{
2198 struct snd_soc_tplg_vendor_array *array;
2199 int num_blocks, block_size = 0, block_type, off = 0;
2200 char *data;
2201 int ret;
2202
2203 /* Read the NUM_DATA_BLOCKS descriptor */
2204 array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
2205 ret = skl_tplg_get_desc_blocks(dev, array);
2206 if (ret < 0)
2207 return ret;
2208 num_blocks = ret;
2209
2210 off += array->size;
Shreyas NC6277e832016-08-12 12:29:51 +05302211 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2212 while (num_blocks > 0) {
Shreyas NC133e6e52017-05-15 19:44:31 +05302213 array = (struct snd_soc_tplg_vendor_array *)
2214 (tplg_w->priv.data + off);
2215
Shreyas NC6277e832016-08-12 12:29:51 +05302216 ret = skl_tplg_get_desc_blocks(dev, array);
2217
2218 if (ret < 0)
2219 return ret;
2220 block_type = ret;
2221 off += array->size;
2222
2223 array = (struct snd_soc_tplg_vendor_array *)
2224 (tplg_w->priv.data + off);
2225
2226 ret = skl_tplg_get_desc_blocks(dev, array);
2227
2228 if (ret < 0)
2229 return ret;
2230 block_size = ret;
2231 off += array->size;
2232
2233 array = (struct snd_soc_tplg_vendor_array *)
2234 (tplg_w->priv.data + off);
2235
2236 data = (tplg_w->priv.data + off);
2237
2238 if (block_type == SKL_TYPE_TUPLE) {
2239 ret = skl_tplg_get_tokens(dev, data,
2240 skl, mconfig, block_size);
2241
2242 if (ret < 0)
2243 return ret;
2244
2245 --num_blocks;
2246 } else {
2247 if (mconfig->formats_config.caps_size > 0)
2248 memcpy(mconfig->formats_config.caps, data,
2249 mconfig->formats_config.caps_size);
2250 --num_blocks;
Shreyas NC133e6e52017-05-15 19:44:31 +05302251 ret = mconfig->formats_config.caps_size;
Shreyas NC6277e832016-08-12 12:29:51 +05302252 }
Shreyas NC133e6e52017-05-15 19:44:31 +05302253 off += ret;
Shreyas NC6277e832016-08-12 12:29:51 +05302254 }
2255
2256 return 0;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002257}
2258
Dharageswari Rfe3f4442016-06-03 18:29:39 +05302259static void skl_clear_pin_config(struct snd_soc_platform *platform,
2260 struct snd_soc_dapm_widget *w)
2261{
2262 int i;
2263 struct skl_module_cfg *mconfig;
2264 struct skl_pipe *pipe;
2265
2266 if (!strncmp(w->dapm->component->name, platform->component.name,
2267 strlen(platform->component.name))) {
2268 mconfig = w->priv;
2269 pipe = mconfig->pipe;
2270 for (i = 0; i < mconfig->max_in_queue; i++) {
2271 mconfig->m_in_pin[i].in_use = false;
2272 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
2273 }
2274 for (i = 0; i < mconfig->max_out_queue; i++) {
2275 mconfig->m_out_pin[i].in_use = false;
2276 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
2277 }
2278 pipe->state = SKL_PIPE_INVALID;
2279 mconfig->m_state = SKL_MODULE_UNINIT;
2280 }
2281}
2282
2283void skl_cleanup_resources(struct skl *skl)
2284{
2285 struct skl_sst *ctx = skl->skl_sst;
2286 struct snd_soc_platform *soc_platform = skl->platform;
2287 struct snd_soc_dapm_widget *w;
2288 struct snd_soc_card *card;
2289
2290 if (soc_platform == NULL)
2291 return;
2292
2293 card = soc_platform->component.card;
2294 if (!card || !card->instantiated)
2295 return;
2296
2297 skl->resource.mem = 0;
2298 skl->resource.mcps = 0;
2299
2300 list_for_each_entry(w, &card->widgets, list) {
2301 if (is_skl_dsp_widget_type(w) && (w->priv != NULL))
2302 skl_clear_pin_config(soc_platform, w);
2303 }
2304
2305 skl_clear_module_cnt(ctx->dsp);
2306}
2307
Vinod Koul3af36702015-10-07 11:31:56 +01002308/*
2309 * Topology core widget load callback
2310 *
2311 * This is used to save the private data for each widget which gives
2312 * information to the driver about module and pipeline parameters which DSP
2313 * FW expects like ids, resource values, formats etc
2314 */
2315static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002316 struct snd_soc_dapm_widget *w,
2317 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01002318{
2319 int ret;
2320 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2321 struct skl *skl = ebus_to_skl(ebus);
2322 struct hdac_bus *bus = ebus_to_hbus(ebus);
2323 struct skl_module_cfg *mconfig;
Vinod Koul3af36702015-10-07 11:31:56 +01002324
2325 if (!tplg_w->priv.size)
2326 goto bind_event;
2327
2328 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
2329
2330 if (!mconfig)
2331 return -ENOMEM;
2332
2333 w->priv = mconfig;
Shreyas NC09305da2016-04-21 11:45:22 +05302334
Vinod Koulb7c50552016-07-26 18:06:40 +05302335 /*
2336 * module binary can be loaded later, so set it to query when
2337 * module is load for a use case
2338 */
2339 mconfig->id.module_id = -1;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002340
Shreyas NC6277e832016-08-12 12:29:51 +05302341 /* Parse private data for tuples */
2342 ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
2343 if (ret < 0)
2344 return ret;
Vinod Koul3af36702015-10-07 11:31:56 +01002345bind_event:
2346 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01002347 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01002348 return 0;
2349 }
2350
2351 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002352 ARRAY_SIZE(skl_tplg_widget_ops),
2353 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01002354
2355 if (ret) {
2356 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
2357 __func__, tplg_w->event_type);
2358 return -EINVAL;
2359 }
2360
2361 return 0;
2362}
2363
Jeeja KP140adfb2015-11-28 15:01:50 +05302364static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
2365 struct snd_soc_tplg_bytes_control *bc)
2366{
2367 struct skl_algo_data *ac;
2368 struct skl_dfw_algo_data *dfw_ac =
2369 (struct skl_dfw_algo_data *)bc->priv.data;
2370
2371 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
2372 if (!ac)
2373 return -ENOMEM;
2374
2375 /* Fill private data */
2376 ac->max = dfw_ac->max;
2377 ac->param_id = dfw_ac->param_id;
2378 ac->set_params = dfw_ac->set_params;
Dharageswari R0d682102016-07-08 18:15:03 +05302379 ac->size = dfw_ac->max;
Jeeja KP140adfb2015-11-28 15:01:50 +05302380
2381 if (ac->max) {
2382 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
2383 if (!ac->params)
2384 return -ENOMEM;
2385
Alan Coxedd7ea22016-02-22 09:37:27 +05302386 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05302387 }
2388
2389 be->dobj.private = ac;
2390 return 0;
2391}
2392
2393static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
2394 struct snd_kcontrol_new *kctl,
2395 struct snd_soc_tplg_ctl_hdr *hdr)
2396{
2397 struct soc_bytes_ext *sb;
2398 struct snd_soc_tplg_bytes_control *tplg_bc;
2399 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2400 struct hdac_bus *bus = ebus_to_hbus(ebus);
2401
2402 switch (hdr->ops.info) {
2403 case SND_SOC_TPLG_CTL_BYTES:
2404 tplg_bc = container_of(hdr,
2405 struct snd_soc_tplg_bytes_control, hdr);
2406 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
2407 sb = (struct soc_bytes_ext *)kctl->private_value;
2408 if (tplg_bc->priv.size)
2409 return skl_init_algo_data(
2410 bus->dev, sb, tplg_bc);
2411 }
2412 break;
2413
2414 default:
2415 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
2416 hdr->ops.get, hdr->ops.put, hdr->ops.info);
2417 break;
2418 }
2419
2420 return 0;
2421}
2422
Shreyas NC541070c2016-08-23 09:31:03 +05302423static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
2424 struct snd_soc_tplg_vendor_string_elem *str_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302425 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302426{
2427 int tkn_count = 0;
2428 static int ref_count;
2429
2430 switch (str_elem->token) {
2431 case SKL_TKN_STR_LIB_NAME:
Jeeja KPeee0e162017-01-02 09:50:04 +05302432 if (ref_count > skl->skl_sst->lib_count - 1) {
Shreyas NC541070c2016-08-23 09:31:03 +05302433 ref_count = 0;
2434 return -EINVAL;
2435 }
2436
Jeeja KPeee0e162017-01-02 09:50:04 +05302437 strncpy(skl->skl_sst->lib_info[ref_count].name,
2438 str_elem->string,
2439 ARRAY_SIZE(skl->skl_sst->lib_info[ref_count].name));
Shreyas NC541070c2016-08-23 09:31:03 +05302440 ref_count++;
2441 tkn_count++;
2442 break;
2443
2444 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002445 dev_err(dev, "Not a string token %d\n", str_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302446 break;
2447 }
2448
2449 return tkn_count;
2450}
2451
2452static int skl_tplg_get_str_tkn(struct device *dev,
2453 struct snd_soc_tplg_vendor_array *array,
Jeeja KPeee0e162017-01-02 09:50:04 +05302454 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302455{
2456 int tkn_count = 0, ret;
2457 struct snd_soc_tplg_vendor_string_elem *str_elem;
2458
2459 str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
2460 while (tkn_count < array->num_elems) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302461 ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302462 str_elem++;
2463
2464 if (ret < 0)
2465 return ret;
2466
2467 tkn_count = tkn_count + ret;
2468 }
2469
2470 return tkn_count;
2471}
2472
2473static int skl_tplg_get_int_tkn(struct device *dev,
2474 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302475 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302476{
2477 int tkn_count = 0;
2478
2479 switch (tkn_elem->token) {
2480 case SKL_TKN_U32_LIB_COUNT:
Jeeja KPeee0e162017-01-02 09:50:04 +05302481 skl->skl_sst->lib_count = tkn_elem->value;
Shreyas NC541070c2016-08-23 09:31:03 +05302482 tkn_count++;
2483 break;
2484
2485 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002486 dev_err(dev, "Not a manifest token %d\n", tkn_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302487 return -EINVAL;
2488 }
2489
2490 return tkn_count;
2491}
2492
2493/*
2494 * Fill the manifest structure by parsing the tokens based on the
2495 * type.
2496 */
2497static int skl_tplg_get_manifest_tkn(struct device *dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302498 char *pvt_data, struct skl *skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302499 int block_size)
2500{
2501 int tkn_count = 0, ret;
2502 int off = 0, tuple_size = 0;
2503 struct snd_soc_tplg_vendor_array *array;
2504 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2505
2506 if (block_size <= 0)
2507 return -EINVAL;
2508
2509 while (tuple_size < block_size) {
2510 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2511 off += array->size;
2512 switch (array->type) {
2513 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Jeeja KPeee0e162017-01-02 09:50:04 +05302514 ret = skl_tplg_get_str_tkn(dev, array, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302515
2516 if (ret < 0)
2517 return ret;
2518 tkn_count += ret;
2519
2520 tuple_size += tkn_count *
2521 sizeof(struct snd_soc_tplg_vendor_string_elem);
2522 continue;
2523
2524 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002525 dev_warn(dev, "no uuid tokens for skl tplf manifest\n");
Shreyas NC541070c2016-08-23 09:31:03 +05302526 continue;
2527
2528 default:
2529 tkn_elem = array->value;
2530 tkn_count = 0;
2531 break;
2532 }
2533
2534 while (tkn_count <= array->num_elems - 1) {
2535 ret = skl_tplg_get_int_tkn(dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302536 tkn_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302537 if (ret < 0)
2538 return ret;
2539
2540 tkn_count = tkn_count + ret;
2541 tkn_elem++;
2542 tuple_size += tkn_count *
2543 sizeof(struct snd_soc_tplg_vendor_value_elem);
2544 break;
2545 }
2546 tkn_count = 0;
2547 }
2548
2549 return 0;
2550}
2551
2552/*
2553 * Parse manifest private data for tokens. The private data block is
2554 * preceded by descriptors for type and size of data block.
2555 */
2556static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
Jeeja KPeee0e162017-01-02 09:50:04 +05302557 struct device *dev, struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302558{
2559 struct snd_soc_tplg_vendor_array *array;
2560 int num_blocks, block_size = 0, block_type, off = 0;
2561 char *data;
2562 int ret;
2563
2564 /* Read the NUM_DATA_BLOCKS descriptor */
2565 array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
2566 ret = skl_tplg_get_desc_blocks(dev, array);
2567 if (ret < 0)
2568 return ret;
2569 num_blocks = ret;
2570
2571 off += array->size;
2572 array = (struct snd_soc_tplg_vendor_array *)
2573 (manifest->priv.data + off);
2574
2575 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2576 while (num_blocks > 0) {
2577 ret = skl_tplg_get_desc_blocks(dev, array);
2578
2579 if (ret < 0)
2580 return ret;
2581 block_type = ret;
2582 off += array->size;
2583
2584 array = (struct snd_soc_tplg_vendor_array *)
2585 (manifest->priv.data + off);
2586
2587 ret = skl_tplg_get_desc_blocks(dev, array);
2588
2589 if (ret < 0)
2590 return ret;
2591 block_size = ret;
2592 off += array->size;
2593
2594 array = (struct snd_soc_tplg_vendor_array *)
2595 (manifest->priv.data + off);
2596
2597 data = (manifest->priv.data + off);
2598
2599 if (block_type == SKL_TYPE_TUPLE) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302600 ret = skl_tplg_get_manifest_tkn(dev, data, skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302601 block_size);
2602
2603 if (ret < 0)
2604 return ret;
2605
2606 --num_blocks;
2607 } else {
2608 return -EINVAL;
2609 }
2610 }
2611
2612 return 0;
2613}
2614
Kranthi G15ecaba92016-07-26 18:06:43 +05302615static int skl_manifest_load(struct snd_soc_component *cmpnt,
2616 struct snd_soc_tplg_manifest *manifest)
2617{
Kranthi G15ecaba92016-07-26 18:06:43 +05302618 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2619 struct hdac_bus *bus = ebus_to_hbus(ebus);
2620 struct skl *skl = ebus_to_skl(ebus);
Kranthi G15ecaba92016-07-26 18:06:43 +05302621
Vinod Koulc15ad602016-08-24 18:03:13 +05302622 /* proceed only if we have private data defined */
2623 if (manifest->priv.size == 0)
2624 return 0;
2625
Jeeja KPeee0e162017-01-02 09:50:04 +05302626 skl_tplg_get_manifest_data(manifest, bus->dev, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302627
Jeeja KPeee0e162017-01-02 09:50:04 +05302628 if (skl->skl_sst->lib_count > SKL_MAX_LIB) {
Kranthi G15ecaba92016-07-26 18:06:43 +05302629 dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
Jeeja KPeee0e162017-01-02 09:50:04 +05302630 skl->skl_sst->lib_count);
2631 return -EINVAL;
Kranthi G15ecaba92016-07-26 18:06:43 +05302632 }
2633
Jeeja KPeee0e162017-01-02 09:50:04 +05302634 return 0;
Kranthi G15ecaba92016-07-26 18:06:43 +05302635}
2636
Vinod Koul3af36702015-10-07 11:31:56 +01002637static struct snd_soc_tplg_ops skl_tplg_ops = {
2638 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05302639 .control_load = skl_tplg_control_load,
2640 .bytes_ext_ops = skl_tlv_ops,
2641 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Kranthi G15ecaba92016-07-26 18:06:43 +05302642 .manifest = skl_manifest_load,
Vinod Koul3af36702015-10-07 11:31:56 +01002643};
2644
Jeeja KP287af4f2016-06-03 18:29:40 +05302645/*
2646 * A pipe can have multiple modules, each of them will be a DAPM widget as
2647 * well. While managing a pipeline we need to get the list of all the
2648 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
2649 * helps to get the SKL type widgets in that pipeline
2650 */
2651static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform)
2652{
2653 struct snd_soc_dapm_widget *w;
2654 struct skl_module_cfg *mcfg = NULL;
2655 struct skl_pipe_module *p_module = NULL;
2656 struct skl_pipe *pipe;
2657
2658 list_for_each_entry(w, &platform->component.card->widgets, list) {
2659 if (is_skl_dsp_widget_type(w) && w->priv != NULL) {
2660 mcfg = w->priv;
2661 pipe = mcfg->pipe;
2662
2663 p_module = devm_kzalloc(platform->dev,
2664 sizeof(*p_module), GFP_KERNEL);
2665 if (!p_module)
2666 return -ENOMEM;
2667
2668 p_module->w = w;
2669 list_add_tail(&p_module->node, &pipe->w_list);
2670 }
2671 }
2672
2673 return 0;
2674}
2675
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302676static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe)
2677{
2678 struct skl_pipe_module *w_module;
2679 struct snd_soc_dapm_widget *w;
2680 struct skl_module_cfg *mconfig;
2681 bool host_found = false, link_found = false;
2682
2683 list_for_each_entry(w_module, &pipe->w_list, node) {
2684 w = w_module->w;
2685 mconfig = w->priv;
2686
2687 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
2688 host_found = true;
2689 else if (mconfig->dev_type != SKL_DEVICE_NONE)
2690 link_found = true;
2691 }
2692
2693 if (host_found && link_found)
2694 pipe->passthru = true;
2695 else
2696 pipe->passthru = false;
2697}
2698
Vinod Koul3af36702015-10-07 11:31:56 +01002699/* This will be read from topology manifest, currently defined here */
2700#define SKL_MAX_MCPS 30000000
2701#define SKL_FW_MAX_MEM 1000000
2702
2703/*
2704 * SKL topology init routine
2705 */
2706int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
2707{
2708 int ret;
2709 const struct firmware *fw;
2710 struct hdac_bus *bus = ebus_to_hbus(ebus);
2711 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302712 struct skl_pipeline *ppl;
Vinod Koul3af36702015-10-07 11:31:56 +01002713
Vinod Koul4b235c42016-02-19 11:42:34 +05302714 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01002715 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01002716 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05302717 skl->tplg_name, ret);
2718 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
2719 if (ret < 0) {
2720 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
2721 "dfw_sst.bin", ret);
2722 return ret;
2723 }
Vinod Koul3af36702015-10-07 11:31:56 +01002724 }
2725
2726 /*
2727 * The complete tplg for SKL is loaded as index 0, we don't use
2728 * any other index
2729 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01002730 ret = snd_soc_tplg_component_load(&platform->component,
2731 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01002732 if (ret < 0) {
2733 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05302734 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01002735 return -EINVAL;
2736 }
2737
2738 skl->resource.max_mcps = SKL_MAX_MCPS;
2739 skl->resource.max_mem = SKL_FW_MAX_MEM;
2740
Vinod Kould8018362016-01-05 17:16:04 +05302741 skl->tplg = fw;
Jeeja KP287af4f2016-06-03 18:29:40 +05302742 ret = skl_tplg_create_pipe_widget_list(platform);
2743 if (ret < 0)
2744 return ret;
Vinod Kould8018362016-01-05 17:16:04 +05302745
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302746 list_for_each_entry(ppl, &skl->ppl_list, node)
2747 skl_tplg_set_pipe_type(skl, ppl->pipe);
Vinod Koul3af36702015-10-07 11:31:56 +01002748
2749 return 0;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01002750}