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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
Shreyas NC6277e832016-08-12 12:29:51 +053024#include <uapi/sound/snd_sst_tokens.h>
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010025#include "skl-sst-dsp.h"
26#include "skl-sst-ipc.h"
27#include "skl-topology.h"
28#include "skl.h"
29#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053030#include "../common/sst-dsp.h"
31#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010032
Jeeja KPf7590d42015-10-07 11:31:53 +010033#define SKL_CH_FIXUP_MASK (1 << 0)
34#define SKL_RATE_FIXUP_MASK (1 << 1)
35#define SKL_FMT_FIXUP_MASK (1 << 2)
Shreyas NC6277e832016-08-12 12:29:51 +053036#define SKL_IN_DIR_BIT_MASK BIT(0)
37#define SKL_PIN_COUNT_MASK GENMASK(7, 4)
Jeeja KPf7590d42015-10-07 11:31:53 +010038
Vinod Koula83e3b42016-11-03 17:07:20 +053039void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps)
40{
41 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
42
43 switch (caps) {
44 case SKL_D0I3_NONE:
45 d0i3->non_d0i3++;
46 break;
47
48 case SKL_D0I3_STREAMING:
49 d0i3->streaming++;
50 break;
51
52 case SKL_D0I3_NON_STREAMING:
53 d0i3->non_streaming++;
54 break;
55 }
56}
57
58void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps)
59{
60 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
61
62 switch (caps) {
63 case SKL_D0I3_NONE:
64 d0i3->non_d0i3--;
65 break;
66
67 case SKL_D0I3_STREAMING:
68 d0i3->streaming--;
69 break;
70
71 case SKL_D0I3_NON_STREAMING:
72 d0i3->non_streaming--;
73 break;
74 }
75}
76
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010077/*
78 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
79 * ignore. This helpers checks if the SKL driver handles this widget type
80 */
81static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
82{
83 switch (w->id) {
84 case snd_soc_dapm_dai_link:
85 case snd_soc_dapm_dai_in:
86 case snd_soc_dapm_aif_in:
87 case snd_soc_dapm_aif_out:
88 case snd_soc_dapm_dai_out:
89 case snd_soc_dapm_switch:
90 return false;
91 default:
92 return true;
93 }
94}
95
96/*
97 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053098 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530100static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100101 struct skl_module_cfg *mconfig)
102{
103 struct skl_sst *ctx = skl->skl_sst;
104
105 if (skl->resource.mem + mconfig->pipe->memory_pages >
106 skl->resource.max_mem) {
107 dev_err(ctx->dev,
108 "%s: module_id %d instance %d\n", __func__,
109 mconfig->id.module_id,
110 mconfig->id.instance_id);
111 dev_err(ctx->dev,
112 "exceeds ppl memory available %d mem %d\n",
113 skl->resource.max_mem, skl->resource.mem);
114 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530115 } else {
116 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100117 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530118}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530120/*
121 * Add the mem to the mem pool. This is freed when pipe is deleted.
122 * Note: DSP does actual memory management we only keep track for complete
123 * pool
124 */
125static void skl_tplg_alloc_pipe_mem(struct skl *skl,
126 struct skl_module_cfg *mconfig)
127{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100128 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100129}
130
131/*
132 * Pipeline needs needs DSP CPU resources for computation, this is
133 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
134 *
135 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530136 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100137 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530138
139static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100140 struct skl_module_cfg *mconfig)
141{
142 struct skl_sst *ctx = skl->skl_sst;
143
144 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
145 dev_err(ctx->dev,
146 "%s: module_id %d instance %d\n", __func__,
147 mconfig->id.module_id, mconfig->id.instance_id);
148 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530149 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100150 skl->resource.max_mcps, skl->resource.mcps);
151 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530152 } else {
153 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100154 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530155}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100156
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530157static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
158 struct skl_module_cfg *mconfig)
159{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100160 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100161}
162
163/*
164 * Free the mcps when tearing down
165 */
166static void
167skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
168{
169 skl->resource.mcps -= mconfig->mcps;
170}
171
172/*
173 * Free the memory when tearing down
174 */
175static void
176skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
177{
178 skl->resource.mem -= mconfig->pipe->memory_pages;
179}
180
Jeeja KPf7590d42015-10-07 11:31:53 +0100181
182static void skl_dump_mconfig(struct skl_sst *ctx,
183 struct skl_module_cfg *mcfg)
184{
185 dev_dbg(ctx->dev, "Dumping config\n");
186 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900187 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
188 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
189 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
190 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100191 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900192 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
193 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
194 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
195 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100196}
197
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530198static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
199{
200 int slot_map = 0xFFFFFFFF;
201 int start_slot = 0;
202 int i;
203
204 for (i = 0; i < chs; i++) {
205 /*
206 * For 2 channels with starting slot as 0, slot map will
207 * look like 0xFFFFFF10.
208 */
209 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
210 start_slot++;
211 }
212 fmt->ch_map = slot_map;
213}
214
Jeeja KPf7590d42015-10-07 11:31:53 +0100215static void skl_tplg_update_params(struct skl_module_fmt *fmt,
216 struct skl_pipe_params *params, int fixup)
217{
218 if (fixup & SKL_RATE_FIXUP_MASK)
219 fmt->s_freq = params->s_freq;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530220 if (fixup & SKL_CH_FIXUP_MASK) {
Jeeja KPf7590d42015-10-07 11:31:53 +0100221 fmt->channels = params->ch;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530222 skl_tplg_update_chmap(fmt, fmt->channels);
223 }
Jeeja KP98256f82015-11-23 22:26:25 +0530224 if (fixup & SKL_FMT_FIXUP_MASK) {
225 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
226
227 /*
228 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
229 * container so update bit depth accordingly
230 */
231 switch (fmt->valid_bit_depth) {
232 case SKL_DEPTH_16BIT:
233 fmt->bit_depth = fmt->valid_bit_depth;
234 break;
235
236 default:
237 fmt->bit_depth = SKL_DEPTH_32BIT;
238 break;
239 }
240 }
241
Jeeja KPf7590d42015-10-07 11:31:53 +0100242}
243
244/*
245 * A pipeline may have modules which impact the pcm parameters, like SRC,
246 * channel converter, format converter.
247 * We need to calculate the output params by applying the 'fixup'
248 * Topology will tell driver which type of fixup is to be applied by
249 * supplying the fixup mask, so based on that we calculate the output
250 *
251 * Now In FE the pcm hw_params is source/target format. Same is applicable
252 * for BE with its hw_params invoked.
253 * here based on FE, BE pipeline and direction we calculate the input and
254 * outfix and then apply that for a module
255 */
256static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
257 struct skl_pipe_params *params, bool is_fe)
258{
259 int in_fixup, out_fixup;
260 struct skl_module_fmt *in_fmt, *out_fmt;
261
Hardik T Shah4cd98992015-10-27 09:22:55 +0900262 /* Fixups will be applied to pin 0 only */
263 in_fmt = &m_cfg->in_fmt[0];
264 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100265
266 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
267 if (is_fe) {
268 in_fixup = m_cfg->params_fixup;
269 out_fixup = (~m_cfg->converter) &
270 m_cfg->params_fixup;
271 } else {
272 out_fixup = m_cfg->params_fixup;
273 in_fixup = (~m_cfg->converter) &
274 m_cfg->params_fixup;
275 }
276 } else {
277 if (is_fe) {
278 out_fixup = m_cfg->params_fixup;
279 in_fixup = (~m_cfg->converter) &
280 m_cfg->params_fixup;
281 } else {
282 in_fixup = m_cfg->params_fixup;
283 out_fixup = (~m_cfg->converter) &
284 m_cfg->params_fixup;
285 }
286 }
287
288 skl_tplg_update_params(in_fmt, params, in_fixup);
289 skl_tplg_update_params(out_fmt, params, out_fixup);
290}
291
292/*
293 * A module needs input and output buffers, which are dependent upon pcm
294 * params, so once we have calculate params, we need buffer calculation as
295 * well.
296 */
297static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
298 struct skl_module_cfg *mcfg)
299{
300 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900301 struct skl_module_fmt *in_fmt, *out_fmt;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900302
303 /* Since fixups is applied to pin 0 only, ibs, obs needs
304 * change for pin 0 only
305 */
306 in_fmt = &mcfg->in_fmt[0];
307 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100308
309 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
310 multiplier = 5;
Jeeja KPf7590d42015-10-07 11:31:53 +0100311
Takashi Sakamoto8e15e762017-03-06 16:12:22 +0900312 mcfg->ibs = DIV_ROUND_UP(in_fmt->s_freq, 1000) *
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900313 in_fmt->channels * (in_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530314 multiplier;
315
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900316 mcfg->obs = DIV_ROUND_UP(out_fmt->s_freq, 1000) *
317 out_fmt->channels * (out_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530318 multiplier;
Jeeja KPf7590d42015-10-07 11:31:53 +0100319}
320
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530321static u8 skl_tplg_be_dev_type(int dev_type)
322{
323 int ret;
324
325 switch (dev_type) {
326 case SKL_DEVICE_BT:
327 ret = NHLT_DEVICE_BT;
328 break;
329
330 case SKL_DEVICE_DMIC:
331 ret = NHLT_DEVICE_DMIC;
332 break;
333
334 case SKL_DEVICE_I2S:
335 ret = NHLT_DEVICE_I2S;
336 break;
337
338 default:
339 ret = NHLT_DEVICE_INVALID;
340 break;
341 }
342
343 return ret;
344}
345
Jeeja KP2d1419a2016-02-05 12:19:10 +0530346static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
347 struct skl_sst *ctx)
348{
349 struct skl_module_cfg *m_cfg = w->priv;
350 int link_type, dir;
351 u32 ch, s_freq, s_fmt;
352 struct nhlt_specific_cfg *cfg;
353 struct skl *skl = get_skl_ctx(ctx->dev);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530354 u8 dev_type = skl_tplg_be_dev_type(m_cfg->dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530355
356 /* check if we already have blob */
357 if (m_cfg->formats_config.caps_size > 0)
358 return 0;
359
Jeeja KPc7c6c732016-03-01 07:59:10 +0530360 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530361 switch (m_cfg->dev_type) {
362 case SKL_DEVICE_DMIC:
363 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530364 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530365 s_freq = m_cfg->in_fmt[0].s_freq;
366 s_fmt = m_cfg->in_fmt[0].bit_depth;
367 ch = m_cfg->in_fmt[0].channels;
368 break;
369
370 case SKL_DEVICE_I2S:
371 link_type = NHLT_LINK_SSP;
372 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530373 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530374 s_freq = m_cfg->out_fmt[0].s_freq;
375 s_fmt = m_cfg->out_fmt[0].bit_depth;
376 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530377 } else {
378 dir = SNDRV_PCM_STREAM_CAPTURE;
379 s_freq = m_cfg->in_fmt[0].s_freq;
380 s_fmt = m_cfg->in_fmt[0].bit_depth;
381 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530382 }
383 break;
384
385 default:
386 return -EINVAL;
387 }
388
389 /* update the blob based on virtual bus_id and default params */
390 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530391 s_fmt, ch, s_freq, dir, dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530392 if (cfg) {
393 m_cfg->formats_config.caps_size = cfg->size;
394 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
395 } else {
396 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
397 m_cfg->vbus_id, link_type, dir);
398 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
399 ch, s_freq, s_fmt);
400 return -EIO;
401 }
402
403 return 0;
404}
405
Jeeja KPf7590d42015-10-07 11:31:53 +0100406static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
407 struct skl_sst *ctx)
408{
409 struct skl_module_cfg *m_cfg = w->priv;
410 struct skl_pipe_params *params = m_cfg->pipe->p_params;
411 int p_conn_type = m_cfg->pipe->conn_type;
412 bool is_fe;
413
414 if (!m_cfg->params_fixup)
415 return;
416
417 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
418 w->name);
419
420 skl_dump_mconfig(ctx, m_cfg);
421
422 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
423 is_fe = true;
424 else
425 is_fe = false;
426
427 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
428 skl_tplg_update_buffer_size(ctx, m_cfg);
429
430 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
431 w->name);
432
433 skl_dump_mconfig(ctx, m_cfg);
434}
435
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100436/*
Jeeja KPabb74002015-11-28 15:01:49 +0530437 * some modules can have multiple params set from user control and
438 * need to be set after module is initialized. If set_param flag is
439 * set module params will be done after module is initialised.
440 */
441static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
442 struct skl_sst *ctx)
443{
444 int i, ret;
445 struct skl_module_cfg *mconfig = w->priv;
446 const struct snd_kcontrol_new *k;
447 struct soc_bytes_ext *sb;
448 struct skl_algo_data *bc;
449 struct skl_specific_cfg *sp_cfg;
450
451 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530452 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530453 sp_cfg = &mconfig->formats_config;
454 ret = skl_set_module_params(ctx, sp_cfg->caps,
455 sp_cfg->caps_size,
456 sp_cfg->param_id, mconfig);
457 if (ret < 0)
458 return ret;
459 }
460
461 for (i = 0; i < w->num_kcontrols; i++) {
462 k = &w->kcontrol_news[i];
463 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
464 sb = (void *) k->private_value;
465 bc = (struct skl_algo_data *)sb->dobj.private;
466
Jeeja KP4ced1822015-12-03 23:29:53 +0530467 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530468 ret = skl_set_module_params(ctx,
Dharageswari R0d682102016-07-08 18:15:03 +0530469 (u32 *)bc->params, bc->size,
Jeeja KPabb74002015-11-28 15:01:49 +0530470 bc->param_id, mconfig);
471 if (ret < 0)
472 return ret;
473 }
474 }
475 }
476
477 return 0;
478}
479
480/*
481 * some module param can set from user control and this is required as
482 * when module is initailzed. if module param is required in init it is
483 * identifed by set_param flag. if set_param flag is not set, then this
484 * parameter needs to set as part of module init.
485 */
486static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
487{
488 const struct snd_kcontrol_new *k;
489 struct soc_bytes_ext *sb;
490 struct skl_algo_data *bc;
491 struct skl_module_cfg *mconfig = w->priv;
492 int i;
493
494 for (i = 0; i < w->num_kcontrols; i++) {
495 k = &w->kcontrol_news[i];
496 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
497 sb = (struct soc_bytes_ext *)k->private_value;
498 bc = (struct skl_algo_data *)sb->dobj.private;
499
Jeeja KP4ced1822015-12-03 23:29:53 +0530500 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530501 continue;
502
503 mconfig->formats_config.caps = (u32 *)&bc->params;
Dharageswari R0d682102016-07-08 18:15:03 +0530504 mconfig->formats_config.caps_size = bc->size;
Jeeja KPabb74002015-11-28 15:01:49 +0530505
506 break;
507 }
508 }
509
510 return 0;
511}
512
Jeeja KPbb704a732016-12-08 13:41:14 +0530513static int skl_tplg_module_prepare(struct skl_sst *ctx, struct skl_pipe *pipe,
514 struct snd_soc_dapm_widget *w, struct skl_module_cfg *mcfg)
515{
516 switch (mcfg->dev_type) {
517 case SKL_DEVICE_HDAHOST:
518 return skl_pcm_host_dma_prepare(ctx->dev, pipe->p_params);
519
520 case SKL_DEVICE_HDALINK:
521 return skl_pcm_link_dma_prepare(ctx->dev, pipe->p_params);
522 }
523
524 return 0;
525}
526
Jeeja KPabb74002015-11-28 15:01:49 +0530527/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100528 * Inside a pipe instance, we can have various modules. These modules need
529 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
530 * skl_init_module() routine, so invoke that for all modules in a pipeline
531 */
532static int
533skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
534{
535 struct skl_pipe_module *w_module;
536 struct snd_soc_dapm_widget *w;
537 struct skl_module_cfg *mconfig;
538 struct skl_sst *ctx = skl->skl_sst;
539 int ret = 0;
540
541 list_for_each_entry(w_module, &pipe->w_list, node) {
542 w = w_module->w;
543 mconfig = w->priv;
544
Vinod Koulb7c50552016-07-26 18:06:40 +0530545 /* check if module ids are populated */
546 if (mconfig->id.module_id < 0) {
Vinod Koula657ae72016-08-10 09:40:50 +0530547 dev_err(skl->skl_sst->dev,
548 "module %pUL id not populated\n",
549 (uuid_le *)mconfig->guid);
550 return -EIO;
Vinod Koulb7c50552016-07-26 18:06:40 +0530551 }
552
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100553 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530554 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100555 return -ENOMEM;
556
Dharageswari R6c5768b2015-12-03 23:29:50 +0530557 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
558 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
559 mconfig->id.module_id, mconfig->guid);
560 if (ret < 0)
561 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530562
563 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530564 }
565
Jeeja KPbb704a732016-12-08 13:41:14 +0530566 /* prepare the DMA if the module is gateway cpr */
567 ret = skl_tplg_module_prepare(ctx, pipe, w, mconfig);
568 if (ret < 0)
569 return ret;
570
Jeeja KP2d1419a2016-02-05 12:19:10 +0530571 /* update blob if blob is null for be with default value */
572 skl_tplg_update_be_blob(w, ctx);
573
Jeeja KPf7590d42015-10-07 11:31:53 +0100574 /*
575 * apply fix/conversion to module params based on
576 * FE/BE params
577 */
578 skl_tplg_update_module_params(w, ctx);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530579 mconfig->id.pvt_id = skl_get_pvt_id(ctx, mconfig);
580 if (mconfig->id.pvt_id < 0)
581 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530582 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530583 ret = skl_init_module(ctx, mconfig);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530584 if (ret < 0) {
585 skl_put_pvt_id(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100586 return ret;
Dharageswari Ref2a3522016-09-22 14:00:38 +0530587 }
Dharageswari R260eb732016-06-03 18:29:38 +0530588 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPabb74002015-11-28 15:01:49 +0530589 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100590 if (ret < 0)
591 return ret;
592 }
593
594 return 0;
595}
Vinod Kould93f8e52015-10-07 11:31:54 +0100596
Dharageswari R6c5768b2015-12-03 23:29:50 +0530597static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
598 struct skl_pipe *pipe)
599{
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530600 int ret;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530601 struct skl_pipe_module *w_module = NULL;
602 struct skl_module_cfg *mconfig = NULL;
603
604 list_for_each_entry(w_module, &pipe->w_list, node) {
605 mconfig = w_module->w->priv;
606
Jeeja KPd6436782016-03-28 22:11:30 +0530607 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530608 mconfig->m_state > SKL_MODULE_UNINIT) {
609 ret = ctx->dsp->fw_ops.unload_mod(ctx->dsp,
Dharageswari R6c5768b2015-12-03 23:29:50 +0530610 mconfig->id.module_id);
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530611 if (ret < 0)
612 return -EIO;
613 }
Dharageswari Ref2a3522016-09-22 14:00:38 +0530614 skl_put_pvt_id(ctx, mconfig);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530615 }
616
617 /* no modules to unload in this path, so return */
618 return 0;
619}
620
Vinod Kould93f8e52015-10-07 11:31:54 +0100621/*
622 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
623 * need create the pipeline. So we do following:
624 * - check the resources
625 * - Create the pipeline
626 * - Initialize the modules in pipeline
627 * - finally bind all modules together
628 */
629static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
630 struct skl *skl)
631{
632 int ret;
633 struct skl_module_cfg *mconfig = w->priv;
634 struct skl_pipe_module *w_module;
635 struct skl_pipe *s_pipe = mconfig->pipe;
636 struct skl_module_cfg *src_module = NULL, *dst_module;
637 struct skl_sst *ctx = skl->skl_sst;
638
639 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530640 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100641 return -EBUSY;
642
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530643 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100644 return -ENOMEM;
645
646 /*
647 * Create a list of modules for pipe.
648 * This list contains modules from source to sink
649 */
650 ret = skl_create_pipeline(ctx, mconfig->pipe);
651 if (ret < 0)
652 return ret;
653
Dharageswari R260eb732016-06-03 18:29:38 +0530654 skl_tplg_alloc_pipe_mem(skl, mconfig);
655 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100656
657 /* Init all pipe modules from source to sink */
658 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
659 if (ret < 0)
660 return ret;
661
662 /* Bind modules from source to sink */
663 list_for_each_entry(w_module, &s_pipe->w_list, node) {
664 dst_module = w_module->w->priv;
665
666 if (src_module == NULL) {
667 src_module = dst_module;
668 continue;
669 }
670
671 ret = skl_bind_modules(ctx, src_module, dst_module);
672 if (ret < 0)
673 return ret;
674
675 src_module = dst_module;
676 }
677
678 return 0;
679}
680
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530681static int skl_fill_sink_instance_id(struct skl_sst *ctx,
682 struct skl_algo_data *alg_data)
683{
684 struct skl_kpb_params *params = (struct skl_kpb_params *)alg_data->params;
685 struct skl_mod_inst_map *inst;
686 int i, pvt_id;
687
688 inst = params->map;
689
690 for (i = 0; i < params->num_modules; i++) {
691 pvt_id = skl_get_pvt_instance_id_map(ctx,
692 inst->mod_id, inst->inst_id);
693 if (pvt_id < 0)
694 return -EINVAL;
695 inst->inst_id = pvt_id;
696 inst++;
697 }
698 return 0;
699}
700
Jeeja KPcc6a4042016-02-05 12:19:08 +0530701/*
702 * Some modules require params to be set after the module is bound to
703 * all pins connected.
704 *
705 * The module provider initializes set_param flag for such modules and we
706 * send params after binding
707 */
708static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
709 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
710{
711 int i, ret;
712 struct skl_module_cfg *mconfig = w->priv;
713 const struct snd_kcontrol_new *k;
714 struct soc_bytes_ext *sb;
715 struct skl_algo_data *bc;
716 struct skl_specific_cfg *sp_cfg;
717
718 /*
719 * check all out/in pins are in bind state.
720 * if so set the module param
721 */
722 for (i = 0; i < mcfg->max_out_queue; i++) {
723 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
724 return 0;
725 }
726
727 for (i = 0; i < mcfg->max_in_queue; i++) {
728 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
729 return 0;
730 }
731
732 if (mconfig->formats_config.caps_size > 0 &&
733 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
734 sp_cfg = &mconfig->formats_config;
735 ret = skl_set_module_params(ctx, sp_cfg->caps,
736 sp_cfg->caps_size,
737 sp_cfg->param_id, mconfig);
738 if (ret < 0)
739 return ret;
740 }
741
742 for (i = 0; i < w->num_kcontrols; i++) {
743 k = &w->kcontrol_news[i];
744 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
745 sb = (void *) k->private_value;
746 bc = (struct skl_algo_data *)sb->dobj.private;
747
748 if (bc->set_params == SKL_PARAM_BIND) {
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530749 if (mconfig->m_type == SKL_MODULE_TYPE_KPB)
750 skl_fill_sink_instance_id(ctx, bc);
Jeeja KPcc6a4042016-02-05 12:19:08 +0530751 ret = skl_set_module_params(ctx,
752 (u32 *)bc->params, bc->max,
753 bc->param_id, mconfig);
754 if (ret < 0)
755 return ret;
756 }
757 }
758 }
759
760 return 0;
761}
762
Jeeja KP8724ff12015-10-27 09:22:52 +0900763static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
764 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530765 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900766 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100767{
768 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530769 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900770 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100771 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900772 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100773
Jeeja KP8724ff12015-10-27 09:22:52 +0900774 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100775 if (!p->connect)
776 continue;
777
778 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
779 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
780
Jeeja KP0ed95d72015-11-13 19:22:11 +0530781 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530782
783 if (!is_skl_dsp_widget_type(p->sink))
784 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
785
Vinod Kould93f8e52015-10-07 11:31:54 +0100786 /*
787 * here we will check widgets in sink pipelines, so that
788 * can be any widgets type and we are only interested if
789 * they are ones used for SKL so check that first
790 */
791 if ((p->sink->priv != NULL) &&
792 is_skl_dsp_widget_type(p->sink)) {
793
794 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100795 sink_mconfig = sink->priv;
796
Jeeja KPcc6a4042016-02-05 12:19:08 +0530797 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
798 sink_mconfig->m_state == SKL_MODULE_UNINIT)
799 continue;
800
Vinod Kould93f8e52015-10-07 11:31:54 +0100801 /* Bind source to sink, mixin is always source */
802 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
803 if (ret)
804 return ret;
805
Jeeja KPcc6a4042016-02-05 12:19:08 +0530806 /* set module params after bind */
807 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
808 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
809
Vinod Kould93f8e52015-10-07 11:31:54 +0100810 /* Start sinks pipe first */
811 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900812 if (sink_mconfig->pipe->conn_type !=
813 SKL_PIPE_CONN_TYPE_FE)
814 ret = skl_run_pipe(ctx,
815 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100816 if (ret)
817 return ret;
818 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100819 }
820 }
821
Jeeja KP8724ff12015-10-27 09:22:52 +0900822 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530823 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900824
825 return 0;
826}
827
Vinod Kould93f8e52015-10-07 11:31:54 +0100828/*
829 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
830 * we need to do following:
831 * - Bind to sink pipeline
832 * Since the sink pipes can be running and we don't get mixer event on
833 * connect for already running mixer, we need to find the sink pipes
834 * here and bind to them. This way dynamic connect works.
835 * - Start sink pipeline, if not running
836 * - Then run current pipe
837 */
838static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900839 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100840{
Jeeja KP8724ff12015-10-27 09:22:52 +0900841 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100842 struct skl_sst *ctx = skl->skl_sst;
843 int ret = 0;
844
Jeeja KP8724ff12015-10-27 09:22:52 +0900845 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100846
847 /*
848 * find which sink it is connected to, bind with the sink,
849 * if sink is not started, start sink pipe first, then start
850 * this pipe
851 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530852 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100853 if (ret)
854 return ret;
855
Vinod Kould93f8e52015-10-07 11:31:54 +0100856 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900857 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
858 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100859
860 return 0;
861}
862
Jeeja KP8724ff12015-10-27 09:22:52 +0900863static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
864 struct snd_soc_dapm_widget *w, struct skl *skl)
865{
866 struct snd_soc_dapm_path *p;
867 struct snd_soc_dapm_widget *src_w = NULL;
868 struct skl_sst *ctx = skl->skl_sst;
869
870 snd_soc_dapm_widget_for_each_source_path(w, p) {
871 src_w = p->source;
872 if (!p->connect)
873 continue;
874
875 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
876 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
877
878 /*
879 * here we will check widgets in sink pipelines, so that can
880 * be any widgets type and we are only interested if they are
881 * ones used for SKL so check that first
882 */
883 if ((p->source->priv != NULL) &&
884 is_skl_dsp_widget_type(p->source)) {
885 return p->source;
886 }
887 }
888
889 if (src_w != NULL)
890 return skl_get_src_dsp_widget(src_w, skl);
891
892 return NULL;
893}
894
Vinod Kould93f8e52015-10-07 11:31:54 +0100895/*
896 * in the Post-PMU event of mixer we need to do following:
897 * - Check if this pipe is running
898 * - if not, then
899 * - bind this pipeline to its source pipeline
900 * if source pipe is already running, this means it is a dynamic
901 * connection and we need to bind only to that pipe
902 * - start this pipeline
903 */
904static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
905 struct skl *skl)
906{
907 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100908 struct snd_soc_dapm_widget *source, *sink;
909 struct skl_module_cfg *src_mconfig, *sink_mconfig;
910 struct skl_sst *ctx = skl->skl_sst;
911 int src_pipe_started = 0;
912
913 sink = w;
914 sink_mconfig = sink->priv;
915
916 /*
917 * If source pipe is already started, that means source is driving
918 * one more sink before this sink got connected, Since source is
919 * started, bind this sink to source and start this pipe.
920 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900921 source = skl_get_src_dsp_widget(w, skl);
922 if (source != NULL) {
923 src_mconfig = source->priv;
924 sink_mconfig = sink->priv;
925 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100926
927 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900928 * check pipe state, then no need to bind or start the
929 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100930 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900931 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
932 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100933 }
934
935 if (src_pipe_started) {
936 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
937 if (ret)
938 return ret;
939
Jeeja KPcc6a4042016-02-05 12:19:08 +0530940 /* set module params after bind */
941 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
942 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
943
Jeeja KPd1730c32015-10-27 09:22:53 +0900944 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
945 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100946 }
947
948 return ret;
949}
950
951/*
952 * in the Pre-PMD event of mixer we need to do following:
953 * - Stop the pipe
954 * - find the source connections and remove that from dapm_path_list
955 * - unbind with source pipelines if still connected
956 */
957static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
958 struct skl *skl)
959{
Vinod Kould93f8e52015-10-07 11:31:54 +0100960 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900961 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100962 struct skl_sst *ctx = skl->skl_sst;
963
Jeeja KPce1b5552015-10-27 09:22:51 +0900964 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100965
966 /* Stop the pipe */
967 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
968 if (ret)
969 return ret;
970
Jeeja KPce1b5552015-10-27 09:22:51 +0900971 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
972 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
973 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
974 if (!src_mconfig)
975 continue;
976 /*
977 * If path_found == 1, that means pmd for source
978 * pipe has not occurred, source is connected to
979 * some other sink. so its responsibility of sink
980 * to unbind itself from source.
981 */
982 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
983 if (ret < 0)
984 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100985
Jeeja KPce1b5552015-10-27 09:22:51 +0900986 ret = skl_unbind_modules(ctx,
987 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100988 }
989 }
990
Vinod Kould93f8e52015-10-07 11:31:54 +0100991 return ret;
992}
993
994/*
995 * in the Post-PMD event of mixer we need to do following:
996 * - Free the mcps used
997 * - Free the mem used
998 * - Unbind the modules within the pipeline
999 * - Delete the pipeline (modules are not required to be explicitly
1000 * deleted, pipeline delete is enough here
1001 */
1002static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1003 struct skl *skl)
1004{
1005 struct skl_module_cfg *mconfig = w->priv;
1006 struct skl_pipe_module *w_module;
1007 struct skl_module_cfg *src_module = NULL, *dst_module;
1008 struct skl_sst *ctx = skl->skl_sst;
1009 struct skl_pipe *s_pipe = mconfig->pipe;
Vinod Kould93f8e52015-10-07 11:31:54 +01001010
Dharageswari R260eb732016-06-03 18:29:38 +05301011 if (s_pipe->state == SKL_PIPE_INVALID)
1012 return -EINVAL;
1013
Vinod Kould93f8e52015-10-07 11:31:54 +01001014 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +05301015 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001016
1017 list_for_each_entry(w_module, &s_pipe->w_list, node) {
1018 dst_module = w_module->w->priv;
1019
Dharageswari R260eb732016-06-03 18:29:38 +05301020 if (mconfig->m_state >= SKL_MODULE_INIT_DONE)
1021 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001022 if (src_module == NULL) {
1023 src_module = dst_module;
1024 continue;
1025 }
1026
Guneshwor Singh7ca42f52016-02-03 17:59:46 +05301027 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001028 src_module = dst_module;
1029 }
1030
Vinod Koul547cafa2016-12-08 23:01:24 +05301031 skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001032
Dharageswari R6c5768b2015-12-03 23:29:50 +05301033 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001034}
1035
1036/*
1037 * in the Post-PMD event of PGA we need to do following:
1038 * - Free the mcps used
1039 * - Stop the pipeline
1040 * - In source pipe is connected, unbind with source pipelines
1041 */
1042static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1043 struct skl *skl)
1044{
Vinod Kould93f8e52015-10-07 11:31:54 +01001045 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +09001046 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +01001047 struct skl_sst *ctx = skl->skl_sst;
1048
Jeeja KPce1b5552015-10-27 09:22:51 +09001049 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +01001050
Vinod Kould93f8e52015-10-07 11:31:54 +01001051 /* Stop the pipe since this is a mixin module */
1052 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
1053 if (ret)
1054 return ret;
1055
Jeeja KPce1b5552015-10-27 09:22:51 +09001056 for (i = 0; i < src_mconfig->max_out_queue; i++) {
1057 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
1058 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
1059 if (!sink_mconfig)
1060 continue;
1061 /*
1062 * This is a connecter and if path is found that means
1063 * unbind between source and sink has not happened yet
1064 */
Jeeja KPce1b5552015-10-27 09:22:51 +09001065 ret = skl_unbind_modules(ctx, src_mconfig,
1066 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001067 }
1068 }
1069
Vinod Kould93f8e52015-10-07 11:31:54 +01001070 return ret;
1071}
1072
1073/*
1074 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
1075 * mixer is not required then it is treated as static mixer aka vmixer with
1076 * a hard path to source module
1077 * So we don't need to check if source is started or not as hard path puts
1078 * dependency on each other
1079 */
1080static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
1081 struct snd_kcontrol *k, int event)
1082{
1083 struct snd_soc_dapm_context *dapm = w->dapm;
1084 struct skl *skl = get_skl_ctx(dapm->dev);
1085
1086 switch (event) {
1087 case SND_SOC_DAPM_PRE_PMU:
1088 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1089
Jeeja KPde1fedf2016-02-03 17:59:52 +05301090 case SND_SOC_DAPM_POST_PMU:
1091 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1092
1093 case SND_SOC_DAPM_PRE_PMD:
1094 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1095
Vinod Kould93f8e52015-10-07 11:31:54 +01001096 case SND_SOC_DAPM_POST_PMD:
1097 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1098 }
1099
1100 return 0;
1101}
1102
1103/*
1104 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1105 * second one is required that is created as another pipe entity.
1106 * The mixer is responsible for pipe management and represent a pipeline
1107 * instance
1108 */
1109static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1110 struct snd_kcontrol *k, int event)
1111{
1112 struct snd_soc_dapm_context *dapm = w->dapm;
1113 struct skl *skl = get_skl_ctx(dapm->dev);
1114
1115 switch (event) {
1116 case SND_SOC_DAPM_PRE_PMU:
1117 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1118
1119 case SND_SOC_DAPM_POST_PMU:
1120 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1121
1122 case SND_SOC_DAPM_PRE_PMD:
1123 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1124
1125 case SND_SOC_DAPM_POST_PMD:
1126 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1127 }
1128
1129 return 0;
1130}
1131
1132/*
1133 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1134 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1135 * the sink when it is running (two FE to one BE or one FE to two BE)
1136 * scenarios
1137 */
1138static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1139 struct snd_kcontrol *k, int event)
1140
1141{
1142 struct snd_soc_dapm_context *dapm = w->dapm;
1143 struct skl *skl = get_skl_ctx(dapm->dev);
1144
1145 switch (event) {
1146 case SND_SOC_DAPM_PRE_PMU:
1147 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1148
1149 case SND_SOC_DAPM_POST_PMD:
1150 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1151 }
1152
1153 return 0;
1154}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001155
Jeeja KP140adfb2015-11-28 15:01:50 +05301156static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1157 unsigned int __user *data, unsigned int size)
1158{
1159 struct soc_bytes_ext *sb =
1160 (struct soc_bytes_ext *)kcontrol->private_value;
1161 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301162 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1163 struct skl_module_cfg *mconfig = w->priv;
1164 struct skl *skl = get_skl_ctx(w->dapm->dev);
1165
1166 if (w->power)
1167 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
Dharageswari R0d682102016-07-08 18:15:03 +05301168 bc->size, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301169
Vinod Koul41556f62016-02-03 17:59:44 +05301170 /* decrement size for TLV header */
1171 size -= 2 * sizeof(u32);
1172
1173 /* check size as we don't want to send kernel data */
1174 if (size > bc->max)
1175 size = bc->max;
1176
Jeeja KP140adfb2015-11-28 15:01:50 +05301177 if (bc->params) {
1178 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1179 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001180 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301181 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001182 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301183 return -EFAULT;
1184 }
1185
1186 return 0;
1187}
1188
1189#define SKL_PARAM_VENDOR_ID 0xff
1190
1191static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1192 const unsigned int __user *data, unsigned int size)
1193{
1194 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1195 struct skl_module_cfg *mconfig = w->priv;
1196 struct soc_bytes_ext *sb =
1197 (struct soc_bytes_ext *)kcontrol->private_value;
1198 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1199 struct skl *skl = get_skl_ctx(w->dapm->dev);
1200
1201 if (ac->params) {
Dharageswari R0d682102016-07-08 18:15:03 +05301202 if (size > ac->max)
1203 return -EINVAL;
1204
1205 ac->size = size;
Jeeja KP140adfb2015-11-28 15:01:50 +05301206 /*
1207 * if the param_is is of type Vendor, firmware expects actual
1208 * parameter id and size from the control.
1209 */
1210 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1211 if (copy_from_user(ac->params, data, size))
1212 return -EFAULT;
1213 } else {
1214 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301215 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301216 return -EFAULT;
1217 }
1218
1219 if (w->power)
1220 return skl_set_module_params(skl->skl_sst,
Dharageswari R0d682102016-07-08 18:15:03 +05301221 (u32 *)ac->params, ac->size,
Jeeja KP140adfb2015-11-28 15:01:50 +05301222 ac->param_id, mconfig);
1223 }
1224
1225 return 0;
1226}
1227
Vinod Koulcfb0a872015-10-07 11:31:55 +01001228/*
Jeeja KP8871dcb2016-06-03 18:29:42 +05301229 * Fill the dma id for host and link. In case of passthrough
1230 * pipeline, this will both host and link in the same
1231 * pipeline, so need to copy the link and host based on dev_type
1232 */
1233static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
1234 struct skl_pipe_params *params)
1235{
1236 struct skl_pipe *pipe = mcfg->pipe;
1237
1238 if (pipe->passthru) {
1239 switch (mcfg->dev_type) {
1240 case SKL_DEVICE_HDALINK:
1241 pipe->p_params->link_dma_id = params->link_dma_id;
Jeeja KP12c3be02016-12-08 13:41:12 +05301242 pipe->p_params->link_index = params->link_index;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301243 break;
1244
1245 case SKL_DEVICE_HDAHOST:
1246 pipe->p_params->host_dma_id = params->host_dma_id;
1247 break;
1248
1249 default:
1250 break;
1251 }
1252 pipe->p_params->s_fmt = params->s_fmt;
1253 pipe->p_params->ch = params->ch;
1254 pipe->p_params->s_freq = params->s_freq;
1255 pipe->p_params->stream = params->stream;
Jeeja KP12c3be02016-12-08 13:41:12 +05301256 pipe->p_params->format = params->format;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301257
1258 } else {
1259 memcpy(pipe->p_params, params, sizeof(*params));
1260 }
1261}
1262
1263/*
Vinod Koulcfb0a872015-10-07 11:31:55 +01001264 * The FE params are passed by hw_params of the DAI.
1265 * On hw_params, the params are stored in Gateway module of the FE and we
1266 * need to calculate the format in DSP module configuration, that
1267 * conversion is done here
1268 */
1269int skl_tplg_update_pipe_params(struct device *dev,
1270 struct skl_module_cfg *mconfig,
1271 struct skl_pipe_params *params)
1272{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001273 struct skl_module_fmt *format = NULL;
1274
Jeeja KP8871dcb2016-06-03 18:29:42 +05301275 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001276
1277 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001278 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001279 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001280 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001281
1282 /* set the hw_params */
1283 format->s_freq = params->s_freq;
1284 format->channels = params->ch;
1285 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1286
1287 /*
1288 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1289 * container so update bit depth accordingly
1290 */
1291 switch (format->valid_bit_depth) {
1292 case SKL_DEPTH_16BIT:
1293 format->bit_depth = format->valid_bit_depth;
1294 break;
1295
1296 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001297 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001298 format->bit_depth = SKL_DEPTH_32BIT;
1299 break;
1300
1301 default:
1302 dev_err(dev, "Invalid bit depth %x for pipe\n",
1303 format->valid_bit_depth);
1304 return -EINVAL;
1305 }
1306
1307 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1308 mconfig->ibs = (format->s_freq / 1000) *
1309 (format->channels) *
1310 (format->bit_depth >> 3);
1311 } else {
1312 mconfig->obs = (format->s_freq / 1000) *
1313 (format->channels) *
1314 (format->bit_depth >> 3);
1315 }
1316
1317 return 0;
1318}
1319
1320/*
1321 * Query the module config for the FE DAI
1322 * This is used to find the hw_params set for that DAI and apply to FE
1323 * pipeline
1324 */
1325struct skl_module_cfg *
1326skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1327{
1328 struct snd_soc_dapm_widget *w;
1329 struct snd_soc_dapm_path *p = NULL;
1330
1331 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1332 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301333 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001334 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001335 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001336 continue;
1337
1338 if (p->sink->priv) {
1339 dev_dbg(dai->dev, "set params for %s\n",
1340 p->sink->name);
1341 return p->sink->priv;
1342 }
1343 }
1344 } else {
1345 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301346 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001347 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001348 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001349 continue;
1350
1351 if (p->source->priv) {
1352 dev_dbg(dai->dev, "set params for %s\n",
1353 p->source->name);
1354 return p->source->priv;
1355 }
1356 }
1357 }
1358
1359 return NULL;
1360}
1361
Dharageswari.R718a42b2016-02-05 12:19:06 +05301362static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1363 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1364{
1365 struct snd_soc_dapm_path *p;
1366 struct skl_module_cfg *mconfig = NULL;
1367
1368 snd_soc_dapm_widget_for_each_source_path(w, p) {
1369 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1370 if (p->connect &&
1371 (p->sink->id == snd_soc_dapm_aif_out) &&
1372 p->source->priv) {
1373 mconfig = p->source->priv;
1374 return mconfig;
1375 }
1376 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1377 if (mconfig)
1378 return mconfig;
1379 }
1380 }
1381 return mconfig;
1382}
1383
1384static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1385 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1386{
1387 struct snd_soc_dapm_path *p;
1388 struct skl_module_cfg *mconfig = NULL;
1389
1390 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1391 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1392 if (p->connect &&
1393 (p->source->id == snd_soc_dapm_aif_in) &&
1394 p->sink->priv) {
1395 mconfig = p->sink->priv;
1396 return mconfig;
1397 }
1398 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1399 if (mconfig)
1400 return mconfig;
1401 }
1402 }
1403 return mconfig;
1404}
1405
1406struct skl_module_cfg *
1407skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1408{
1409 struct snd_soc_dapm_widget *w;
1410 struct skl_module_cfg *mconfig;
1411
1412 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1413 w = dai->playback_widget;
1414 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1415 } else {
1416 w = dai->capture_widget;
1417 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1418 }
1419 return mconfig;
1420}
1421
Vinod Koulcfb0a872015-10-07 11:31:55 +01001422static u8 skl_tplg_be_link_type(int dev_type)
1423{
1424 int ret;
1425
1426 switch (dev_type) {
1427 case SKL_DEVICE_BT:
1428 ret = NHLT_LINK_SSP;
1429 break;
1430
1431 case SKL_DEVICE_DMIC:
1432 ret = NHLT_LINK_DMIC;
1433 break;
1434
1435 case SKL_DEVICE_I2S:
1436 ret = NHLT_LINK_SSP;
1437 break;
1438
1439 case SKL_DEVICE_HDALINK:
1440 ret = NHLT_LINK_HDA;
1441 break;
1442
1443 default:
1444 ret = NHLT_LINK_INVALID;
1445 break;
1446 }
1447
1448 return ret;
1449}
1450
1451/*
1452 * Fill the BE gateway parameters
1453 * The BE gateway expects a blob of parameters which are kept in the ACPI
1454 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1455 * The port can have multiple settings so pick based on the PCM
1456 * parameters
1457 */
1458static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1459 struct skl_module_cfg *mconfig,
1460 struct skl_pipe_params *params)
1461{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001462 struct nhlt_specific_cfg *cfg;
1463 struct skl *skl = get_skl_ctx(dai->dev);
1464 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301465 u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001466
Jeeja KP8871dcb2016-06-03 18:29:42 +05301467 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001468
Jeeja KPb30c2752015-10-27 09:22:48 +09001469 if (link_type == NHLT_LINK_HDA)
1470 return 0;
1471
Vinod Koulcfb0a872015-10-07 11:31:55 +01001472 /* update the blob based on virtual bus_id*/
1473 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1474 params->s_fmt, params->ch,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301475 params->s_freq, params->stream,
1476 dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001477 if (cfg) {
1478 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301479 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001480 } else {
1481 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1482 mconfig->vbus_id, link_type,
1483 params->stream);
1484 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1485 params->ch, params->s_freq, params->s_fmt);
1486 return -EINVAL;
1487 }
1488
1489 return 0;
1490}
1491
1492static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1493 struct snd_soc_dapm_widget *w,
1494 struct skl_pipe_params *params)
1495{
1496 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301497 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001498
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301499 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001500 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1501 p->source->priv) {
1502
Jeeja KP9a03cb42015-10-27 09:22:54 +09001503 ret = skl_tplg_be_fill_pipe_params(dai,
1504 p->source->priv, params);
1505 if (ret < 0)
1506 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001507 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001508 ret = skl_tplg_be_set_src_pipe_params(dai,
1509 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301510 if (ret < 0)
1511 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001512 }
1513 }
1514
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301515 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001516}
1517
1518static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1519 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1520{
1521 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301522 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001523
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301524 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001525 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1526 p->sink->priv) {
1527
Jeeja KP9a03cb42015-10-27 09:22:54 +09001528 ret = skl_tplg_be_fill_pipe_params(dai,
1529 p->sink->priv, params);
1530 if (ret < 0)
1531 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001532 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301533 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001534 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301535 if (ret < 0)
1536 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001537 }
1538 }
1539
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301540 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001541}
1542
1543/*
1544 * BE hw_params can be a source parameters (capture) or sink parameters
1545 * (playback). Based on sink and source we need to either find the source
1546 * list or the sink list and set the pipeline parameters
1547 */
1548int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1549 struct skl_pipe_params *params)
1550{
1551 struct snd_soc_dapm_widget *w;
1552
1553 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1554 w = dai->playback_widget;
1555
1556 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1557
1558 } else {
1559 w = dai->capture_widget;
1560
1561 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1562 }
1563
1564 return 0;
1565}
Vinod Koul3af36702015-10-07 11:31:56 +01001566
1567static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1568 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1569 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1570 {SKL_PGA_EVENT, skl_tplg_pga_event},
1571};
1572
Jeeja KP140adfb2015-11-28 15:01:50 +05301573static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1574 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1575 skl_tplg_tlv_control_set},
1576};
1577
Shreyas NC6277e832016-08-12 12:29:51 +05301578static int skl_tplg_fill_pipe_tkn(struct device *dev,
1579 struct skl_pipe *pipe, u32 tkn,
1580 u32 tkn_val)
Vinod Koul3af36702015-10-07 11:31:56 +01001581{
Vinod Koul3af36702015-10-07 11:31:56 +01001582
Shreyas NC6277e832016-08-12 12:29:51 +05301583 switch (tkn) {
1584 case SKL_TKN_U32_PIPE_CONN_TYPE:
1585 pipe->conn_type = tkn_val;
1586 break;
1587
1588 case SKL_TKN_U32_PIPE_PRIORITY:
1589 pipe->pipe_priority = tkn_val;
1590 break;
1591
1592 case SKL_TKN_U32_PIPE_MEM_PGS:
1593 pipe->memory_pages = tkn_val;
1594 break;
1595
Vinod Koul8a0cb232016-11-03 17:07:18 +05301596 case SKL_TKN_U32_PMODE:
1597 pipe->lp_mode = tkn_val;
1598 break;
1599
Shreyas NC6277e832016-08-12 12:29:51 +05301600 default:
1601 dev_err(dev, "Token not handled %d\n", tkn);
1602 return -EINVAL;
Vinod Koul3af36702015-10-07 11:31:56 +01001603 }
Shreyas NC6277e832016-08-12 12:29:51 +05301604
1605 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001606}
1607
1608/*
Shreyas NC6277e832016-08-12 12:29:51 +05301609 * Add pipeline by parsing the relevant tokens
1610 * Return an existing pipe if the pipe already exists.
Vinod Koul3af36702015-10-07 11:31:56 +01001611 */
Shreyas NC6277e832016-08-12 12:29:51 +05301612static int skl_tplg_add_pipe(struct device *dev,
1613 struct skl_module_cfg *mconfig, struct skl *skl,
1614 struct snd_soc_tplg_vendor_value_elem *tkn_elem)
Vinod Koul3af36702015-10-07 11:31:56 +01001615{
1616 struct skl_pipeline *ppl;
1617 struct skl_pipe *pipe;
1618 struct skl_pipe_params *params;
1619
1620 list_for_each_entry(ppl, &skl->ppl_list, node) {
Shreyas NC6277e832016-08-12 12:29:51 +05301621 if (ppl->pipe->ppl_id == tkn_elem->value) {
1622 mconfig->pipe = ppl->pipe;
1623 return EEXIST;
1624 }
Vinod Koul3af36702015-10-07 11:31:56 +01001625 }
1626
1627 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1628 if (!ppl)
Shreyas NC6277e832016-08-12 12:29:51 +05301629 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001630
1631 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1632 if (!pipe)
Shreyas NC6277e832016-08-12 12:29:51 +05301633 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001634
1635 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1636 if (!params)
Shreyas NC6277e832016-08-12 12:29:51 +05301637 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001638
Vinod Koul3af36702015-10-07 11:31:56 +01001639 pipe->p_params = params;
Shreyas NC6277e832016-08-12 12:29:51 +05301640 pipe->ppl_id = tkn_elem->value;
Vinod Koul3af36702015-10-07 11:31:56 +01001641 INIT_LIST_HEAD(&pipe->w_list);
1642
1643 ppl->pipe = pipe;
1644 list_add(&ppl->node, &skl->ppl_list);
1645
Shreyas NC6277e832016-08-12 12:29:51 +05301646 mconfig->pipe = pipe;
1647 mconfig->pipe->state = SKL_PIPE_INVALID;
1648
1649 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001650}
1651
Shreyas NC6277e832016-08-12 12:29:51 +05301652static int skl_tplg_fill_pin(struct device *dev, u32 tkn,
1653 struct skl_module_pin *m_pin,
1654 int pin_index, u32 value)
1655{
1656 switch (tkn) {
1657 case SKL_TKN_U32_PIN_MOD_ID:
1658 m_pin[pin_index].id.module_id = value;
1659 break;
1660
1661 case SKL_TKN_U32_PIN_INST_ID:
1662 m_pin[pin_index].id.instance_id = value;
1663 break;
1664
1665 default:
1666 dev_err(dev, "%d Not a pin token\n", value);
1667 return -EINVAL;
1668 }
1669
1670 return 0;
1671}
1672
1673/*
1674 * Parse for pin config specific tokens to fill up the
1675 * module private data
1676 */
1677static int skl_tplg_fill_pins_info(struct device *dev,
1678 struct skl_module_cfg *mconfig,
1679 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1680 int dir, int pin_count)
1681{
1682 int ret;
1683 struct skl_module_pin *m_pin;
1684
1685 switch (dir) {
1686 case SKL_DIR_IN:
1687 m_pin = mconfig->m_in_pin;
1688 break;
1689
1690 case SKL_DIR_OUT:
1691 m_pin = mconfig->m_out_pin;
1692 break;
1693
1694 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001695 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301696 return -EINVAL;
1697 }
1698
1699 ret = skl_tplg_fill_pin(dev, tkn_elem->token,
1700 m_pin, pin_count, tkn_elem->value);
1701
1702 if (ret < 0)
1703 return ret;
1704
1705 m_pin[pin_count].in_use = false;
1706 m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
1707
1708 return 0;
1709}
1710
1711/*
1712 * Fill up input/output module config format based
1713 * on the direction
1714 */
1715static int skl_tplg_fill_fmt(struct device *dev,
1716 struct skl_module_cfg *mconfig, u32 tkn,
1717 u32 value, u32 dir, u32 pin_count)
1718{
1719 struct skl_module_fmt *dst_fmt;
1720
1721 switch (dir) {
1722 case SKL_DIR_IN:
1723 dst_fmt = mconfig->in_fmt;
1724 dst_fmt += pin_count;
1725 break;
1726
1727 case SKL_DIR_OUT:
1728 dst_fmt = mconfig->out_fmt;
1729 dst_fmt += pin_count;
1730 break;
1731
1732 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001733 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301734 return -EINVAL;
1735 }
1736
1737 switch (tkn) {
1738 case SKL_TKN_U32_FMT_CH:
1739 dst_fmt->channels = value;
1740 break;
1741
1742 case SKL_TKN_U32_FMT_FREQ:
1743 dst_fmt->s_freq = value;
1744 break;
1745
1746 case SKL_TKN_U32_FMT_BIT_DEPTH:
1747 dst_fmt->bit_depth = value;
1748 break;
1749
1750 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1751 dst_fmt->valid_bit_depth = value;
1752 break;
1753
1754 case SKL_TKN_U32_FMT_CH_CONFIG:
1755 dst_fmt->ch_cfg = value;
1756 break;
1757
1758 case SKL_TKN_U32_FMT_INTERLEAVE:
1759 dst_fmt->interleaving_style = value;
1760 break;
1761
1762 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1763 dst_fmt->sample_type = value;
1764 break;
1765
1766 case SKL_TKN_U32_FMT_CH_MAP:
1767 dst_fmt->ch_map = value;
1768 break;
1769
1770 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001771 dev_err(dev, "Invalid token %d\n", tkn);
Shreyas NC6277e832016-08-12 12:29:51 +05301772 return -EINVAL;
1773 }
1774
1775 return 0;
1776}
1777
1778static int skl_tplg_get_uuid(struct device *dev, struct skl_module_cfg *mconfig,
1779 struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
1780{
1781 if (uuid_tkn->token == SKL_TKN_UUID)
1782 memcpy(&mconfig->guid, &uuid_tkn->uuid, 16);
1783 else {
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001784 dev_err(dev, "Not an UUID token tkn %d\n", uuid_tkn->token);
Shreyas NC6277e832016-08-12 12:29:51 +05301785 return -EINVAL;
1786 }
1787
1788 return 0;
1789}
1790
1791static void skl_tplg_fill_pin_dynamic_val(
1792 struct skl_module_pin *mpin, u32 pin_count, u32 value)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001793{
1794 int i;
1795
Shreyas NC6277e832016-08-12 12:29:51 +05301796 for (i = 0; i < pin_count; i++)
1797 mpin[i].is_dynamic = value;
1798}
1799
1800/*
1801 * Parse tokens to fill up the module private data
1802 */
1803static int skl_tplg_get_token(struct device *dev,
1804 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1805 struct skl *skl, struct skl_module_cfg *mconfig)
1806{
1807 int tkn_count = 0;
1808 int ret;
1809 static int is_pipe_exists;
1810 static int pin_index, dir;
1811
1812 if (tkn_elem->token > SKL_TKN_MAX)
1813 return -EINVAL;
1814
1815 switch (tkn_elem->token) {
1816 case SKL_TKN_U8_IN_QUEUE_COUNT:
1817 mconfig->max_in_queue = tkn_elem->value;
1818 mconfig->m_in_pin = devm_kzalloc(dev, mconfig->max_in_queue *
1819 sizeof(*mconfig->m_in_pin),
1820 GFP_KERNEL);
1821 if (!mconfig->m_in_pin)
1822 return -ENOMEM;
1823
1824 break;
1825
1826 case SKL_TKN_U8_OUT_QUEUE_COUNT:
1827 mconfig->max_out_queue = tkn_elem->value;
1828 mconfig->m_out_pin = devm_kzalloc(dev, mconfig->max_out_queue *
1829 sizeof(*mconfig->m_out_pin),
1830 GFP_KERNEL);
1831
1832 if (!mconfig->m_out_pin)
1833 return -ENOMEM;
1834
1835 break;
1836
1837 case SKL_TKN_U8_DYN_IN_PIN:
1838 if (!mconfig->m_in_pin)
1839 return -ENOMEM;
1840
1841 skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin,
1842 mconfig->max_in_queue, tkn_elem->value);
1843
1844 break;
1845
1846 case SKL_TKN_U8_DYN_OUT_PIN:
1847 if (!mconfig->m_out_pin)
1848 return -ENOMEM;
1849
1850 skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin,
1851 mconfig->max_out_queue, tkn_elem->value);
1852
1853 break;
1854
1855 case SKL_TKN_U8_TIME_SLOT:
1856 mconfig->time_slot = tkn_elem->value;
1857 break;
1858
1859 case SKL_TKN_U8_CORE_ID:
1860 mconfig->core_id = tkn_elem->value;
1861
1862 case SKL_TKN_U8_MOD_TYPE:
1863 mconfig->m_type = tkn_elem->value;
1864 break;
1865
1866 case SKL_TKN_U8_DEV_TYPE:
1867 mconfig->dev_type = tkn_elem->value;
1868 break;
1869
1870 case SKL_TKN_U8_HW_CONN_TYPE:
1871 mconfig->hw_conn_type = tkn_elem->value;
1872 break;
1873
1874 case SKL_TKN_U16_MOD_INST_ID:
1875 mconfig->id.instance_id =
1876 tkn_elem->value;
1877 break;
1878
1879 case SKL_TKN_U32_MEM_PAGES:
1880 mconfig->mem_pages = tkn_elem->value;
1881 break;
1882
1883 case SKL_TKN_U32_MAX_MCPS:
1884 mconfig->mcps = tkn_elem->value;
1885 break;
1886
1887 case SKL_TKN_U32_OBS:
1888 mconfig->obs = tkn_elem->value;
1889 break;
1890
1891 case SKL_TKN_U32_IBS:
1892 mconfig->ibs = tkn_elem->value;
1893 break;
1894
1895 case SKL_TKN_U32_VBUS_ID:
1896 mconfig->vbus_id = tkn_elem->value;
1897 break;
1898
1899 case SKL_TKN_U32_PARAMS_FIXUP:
1900 mconfig->params_fixup = tkn_elem->value;
1901 break;
1902
1903 case SKL_TKN_U32_CONVERTER:
1904 mconfig->converter = tkn_elem->value;
1905 break;
1906
Vinod Koul6bd9dcf2016-11-03 17:07:19 +05301907 case SKL_TKL_U32_D0I3_CAPS:
1908 mconfig->d0i3_caps = tkn_elem->value;
1909 break;
1910
Shreyas NC6277e832016-08-12 12:29:51 +05301911 case SKL_TKN_U32_PIPE_ID:
1912 ret = skl_tplg_add_pipe(dev,
1913 mconfig, skl, tkn_elem);
1914
1915 if (ret < 0)
1916 return is_pipe_exists;
1917
1918 if (ret == EEXIST)
1919 is_pipe_exists = 1;
1920
1921 break;
1922
1923 case SKL_TKN_U32_PIPE_CONN_TYPE:
1924 case SKL_TKN_U32_PIPE_PRIORITY:
1925 case SKL_TKN_U32_PIPE_MEM_PGS:
Vinod Koul8a0cb232016-11-03 17:07:18 +05301926 case SKL_TKN_U32_PMODE:
Shreyas NC6277e832016-08-12 12:29:51 +05301927 if (is_pipe_exists) {
1928 ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
1929 tkn_elem->token, tkn_elem->value);
1930 if (ret < 0)
1931 return ret;
1932 }
1933
1934 break;
1935
1936 /*
1937 * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
1938 * direction and the pin count. The first four bits represent
1939 * direction and next four the pin count.
1940 */
1941 case SKL_TKN_U32_DIR_PIN_COUNT:
1942 dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
1943 pin_index = (tkn_elem->value &
1944 SKL_PIN_COUNT_MASK) >> 4;
1945
1946 break;
1947
1948 case SKL_TKN_U32_FMT_CH:
1949 case SKL_TKN_U32_FMT_FREQ:
1950 case SKL_TKN_U32_FMT_BIT_DEPTH:
1951 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1952 case SKL_TKN_U32_FMT_CH_CONFIG:
1953 case SKL_TKN_U32_FMT_INTERLEAVE:
1954 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1955 case SKL_TKN_U32_FMT_CH_MAP:
1956 ret = skl_tplg_fill_fmt(dev, mconfig, tkn_elem->token,
1957 tkn_elem->value, dir, pin_index);
1958
1959 if (ret < 0)
1960 return ret;
1961
1962 break;
1963
1964 case SKL_TKN_U32_PIN_MOD_ID:
1965 case SKL_TKN_U32_PIN_INST_ID:
1966 ret = skl_tplg_fill_pins_info(dev,
1967 mconfig, tkn_elem, dir,
1968 pin_index);
1969 if (ret < 0)
1970 return ret;
1971
1972 break;
1973
1974 case SKL_TKN_U32_CAPS_SIZE:
1975 mconfig->formats_config.caps_size =
1976 tkn_elem->value;
1977
1978 break;
1979
1980 case SKL_TKN_U32_PROC_DOMAIN:
1981 mconfig->domain =
1982 tkn_elem->value;
1983
1984 break;
1985
1986 case SKL_TKN_U8_IN_PIN_TYPE:
1987 case SKL_TKN_U8_OUT_PIN_TYPE:
1988 case SKL_TKN_U8_CONN_TYPE:
1989 break;
1990
1991 default:
1992 dev_err(dev, "Token %d not handled\n",
1993 tkn_elem->token);
1994 return -EINVAL;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001995 }
Shreyas NC6277e832016-08-12 12:29:51 +05301996
1997 tkn_count++;
1998
1999 return tkn_count;
2000}
2001
2002/*
2003 * Parse the vendor array for specific tokens to construct
2004 * module private data
2005 */
2006static int skl_tplg_get_tokens(struct device *dev,
2007 char *pvt_data, struct skl *skl,
2008 struct skl_module_cfg *mconfig, int block_size)
2009{
2010 struct snd_soc_tplg_vendor_array *array;
2011 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2012 int tkn_count = 0, ret;
2013 int off = 0, tuple_size = 0;
2014
2015 if (block_size <= 0)
2016 return -EINVAL;
2017
2018 while (tuple_size < block_size) {
2019 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2020
2021 off += array->size;
2022
2023 switch (array->type) {
2024 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002025 dev_warn(dev, "no string tokens expected for skl tplg\n");
Shreyas NC6277e832016-08-12 12:29:51 +05302026 continue;
2027
2028 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
2029 ret = skl_tplg_get_uuid(dev, mconfig, array->uuid);
2030 if (ret < 0)
2031 return ret;
2032
2033 tuple_size += sizeof(*array->uuid);
2034
2035 continue;
2036
2037 default:
2038 tkn_elem = array->value;
2039 tkn_count = 0;
2040 break;
2041 }
2042
2043 while (tkn_count <= (array->num_elems - 1)) {
2044 ret = skl_tplg_get_token(dev, tkn_elem,
2045 skl, mconfig);
2046
2047 if (ret < 0)
2048 return ret;
2049
2050 tkn_count = tkn_count + ret;
2051 tkn_elem++;
2052 }
2053
2054 tuple_size += tkn_count * sizeof(*tkn_elem);
2055 }
2056
2057 return 0;
2058}
2059
2060/*
2061 * Every data block is preceded by a descriptor to read the number
2062 * of data blocks, they type of the block and it's size
2063 */
2064static int skl_tplg_get_desc_blocks(struct device *dev,
2065 struct snd_soc_tplg_vendor_array *array)
2066{
2067 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2068
2069 tkn_elem = array->value;
2070
2071 switch (tkn_elem->token) {
2072 case SKL_TKN_U8_NUM_BLOCKS:
2073 case SKL_TKN_U8_BLOCK_TYPE:
2074 case SKL_TKN_U16_BLOCK_SIZE:
2075 return tkn_elem->value;
2076
2077 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002078 dev_err(dev, "Invalid descriptor token %d\n", tkn_elem->token);
Shreyas NC6277e832016-08-12 12:29:51 +05302079 break;
2080 }
2081
2082 return -EINVAL;
2083}
2084
2085/*
2086 * Parse the private data for the token and corresponding value.
2087 * The private data can have multiple data blocks. So, a data block
2088 * is preceded by a descriptor for number of blocks and a descriptor
2089 * for the type and size of the suceeding data block.
2090 */
2091static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
2092 struct skl *skl, struct device *dev,
2093 struct skl_module_cfg *mconfig)
2094{
2095 struct snd_soc_tplg_vendor_array *array;
2096 int num_blocks, block_size = 0, block_type, off = 0;
2097 char *data;
2098 int ret;
2099
2100 /* Read the NUM_DATA_BLOCKS descriptor */
2101 array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
2102 ret = skl_tplg_get_desc_blocks(dev, array);
2103 if (ret < 0)
2104 return ret;
2105 num_blocks = ret;
2106
2107 off += array->size;
2108 array = (struct snd_soc_tplg_vendor_array *)(tplg_w->priv.data + off);
2109
2110 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2111 while (num_blocks > 0) {
2112 ret = skl_tplg_get_desc_blocks(dev, array);
2113
2114 if (ret < 0)
2115 return ret;
2116 block_type = ret;
2117 off += array->size;
2118
2119 array = (struct snd_soc_tplg_vendor_array *)
2120 (tplg_w->priv.data + off);
2121
2122 ret = skl_tplg_get_desc_blocks(dev, array);
2123
2124 if (ret < 0)
2125 return ret;
2126 block_size = ret;
2127 off += array->size;
2128
2129 array = (struct snd_soc_tplg_vendor_array *)
2130 (tplg_w->priv.data + off);
2131
2132 data = (tplg_w->priv.data + off);
2133
2134 if (block_type == SKL_TYPE_TUPLE) {
2135 ret = skl_tplg_get_tokens(dev, data,
2136 skl, mconfig, block_size);
2137
2138 if (ret < 0)
2139 return ret;
2140
2141 --num_blocks;
2142 } else {
2143 if (mconfig->formats_config.caps_size > 0)
2144 memcpy(mconfig->formats_config.caps, data,
2145 mconfig->formats_config.caps_size);
2146 --num_blocks;
2147 }
2148 }
2149
2150 return 0;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002151}
2152
Dharageswari Rfe3f4442016-06-03 18:29:39 +05302153static void skl_clear_pin_config(struct snd_soc_platform *platform,
2154 struct snd_soc_dapm_widget *w)
2155{
2156 int i;
2157 struct skl_module_cfg *mconfig;
2158 struct skl_pipe *pipe;
2159
2160 if (!strncmp(w->dapm->component->name, platform->component.name,
2161 strlen(platform->component.name))) {
2162 mconfig = w->priv;
2163 pipe = mconfig->pipe;
2164 for (i = 0; i < mconfig->max_in_queue; i++) {
2165 mconfig->m_in_pin[i].in_use = false;
2166 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
2167 }
2168 for (i = 0; i < mconfig->max_out_queue; i++) {
2169 mconfig->m_out_pin[i].in_use = false;
2170 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
2171 }
2172 pipe->state = SKL_PIPE_INVALID;
2173 mconfig->m_state = SKL_MODULE_UNINIT;
2174 }
2175}
2176
2177void skl_cleanup_resources(struct skl *skl)
2178{
2179 struct skl_sst *ctx = skl->skl_sst;
2180 struct snd_soc_platform *soc_platform = skl->platform;
2181 struct snd_soc_dapm_widget *w;
2182 struct snd_soc_card *card;
2183
2184 if (soc_platform == NULL)
2185 return;
2186
2187 card = soc_platform->component.card;
2188 if (!card || !card->instantiated)
2189 return;
2190
2191 skl->resource.mem = 0;
2192 skl->resource.mcps = 0;
2193
2194 list_for_each_entry(w, &card->widgets, list) {
2195 if (is_skl_dsp_widget_type(w) && (w->priv != NULL))
2196 skl_clear_pin_config(soc_platform, w);
2197 }
2198
2199 skl_clear_module_cnt(ctx->dsp);
2200}
2201
Vinod Koul3af36702015-10-07 11:31:56 +01002202/*
2203 * Topology core widget load callback
2204 *
2205 * This is used to save the private data for each widget which gives
2206 * information to the driver about module and pipeline parameters which DSP
2207 * FW expects like ids, resource values, formats etc
2208 */
2209static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002210 struct snd_soc_dapm_widget *w,
2211 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01002212{
2213 int ret;
2214 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2215 struct skl *skl = ebus_to_skl(ebus);
2216 struct hdac_bus *bus = ebus_to_hbus(ebus);
2217 struct skl_module_cfg *mconfig;
Vinod Koul3af36702015-10-07 11:31:56 +01002218
2219 if (!tplg_w->priv.size)
2220 goto bind_event;
2221
2222 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
2223
2224 if (!mconfig)
2225 return -ENOMEM;
2226
2227 w->priv = mconfig;
Shreyas NC09305da2016-04-21 11:45:22 +05302228
Vinod Koulb7c50552016-07-26 18:06:40 +05302229 /*
2230 * module binary can be loaded later, so set it to query when
2231 * module is load for a use case
2232 */
2233 mconfig->id.module_id = -1;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002234
Shreyas NC6277e832016-08-12 12:29:51 +05302235 /* Parse private data for tuples */
2236 ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
2237 if (ret < 0)
2238 return ret;
Vinod Koul3af36702015-10-07 11:31:56 +01002239bind_event:
2240 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01002241 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01002242 return 0;
2243 }
2244
2245 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002246 ARRAY_SIZE(skl_tplg_widget_ops),
2247 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01002248
2249 if (ret) {
2250 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
2251 __func__, tplg_w->event_type);
2252 return -EINVAL;
2253 }
2254
2255 return 0;
2256}
2257
Jeeja KP140adfb2015-11-28 15:01:50 +05302258static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
2259 struct snd_soc_tplg_bytes_control *bc)
2260{
2261 struct skl_algo_data *ac;
2262 struct skl_dfw_algo_data *dfw_ac =
2263 (struct skl_dfw_algo_data *)bc->priv.data;
2264
2265 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
2266 if (!ac)
2267 return -ENOMEM;
2268
2269 /* Fill private data */
2270 ac->max = dfw_ac->max;
2271 ac->param_id = dfw_ac->param_id;
2272 ac->set_params = dfw_ac->set_params;
Dharageswari R0d682102016-07-08 18:15:03 +05302273 ac->size = dfw_ac->max;
Jeeja KP140adfb2015-11-28 15:01:50 +05302274
2275 if (ac->max) {
2276 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
2277 if (!ac->params)
2278 return -ENOMEM;
2279
Alan Coxedd7ea22016-02-22 09:37:27 +05302280 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05302281 }
2282
2283 be->dobj.private = ac;
2284 return 0;
2285}
2286
2287static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
2288 struct snd_kcontrol_new *kctl,
2289 struct snd_soc_tplg_ctl_hdr *hdr)
2290{
2291 struct soc_bytes_ext *sb;
2292 struct snd_soc_tplg_bytes_control *tplg_bc;
2293 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2294 struct hdac_bus *bus = ebus_to_hbus(ebus);
2295
2296 switch (hdr->ops.info) {
2297 case SND_SOC_TPLG_CTL_BYTES:
2298 tplg_bc = container_of(hdr,
2299 struct snd_soc_tplg_bytes_control, hdr);
2300 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
2301 sb = (struct soc_bytes_ext *)kctl->private_value;
2302 if (tplg_bc->priv.size)
2303 return skl_init_algo_data(
2304 bus->dev, sb, tplg_bc);
2305 }
2306 break;
2307
2308 default:
2309 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
2310 hdr->ops.get, hdr->ops.put, hdr->ops.info);
2311 break;
2312 }
2313
2314 return 0;
2315}
2316
Shreyas NC541070c2016-08-23 09:31:03 +05302317static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
2318 struct snd_soc_tplg_vendor_string_elem *str_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302319 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302320{
2321 int tkn_count = 0;
2322 static int ref_count;
2323
2324 switch (str_elem->token) {
2325 case SKL_TKN_STR_LIB_NAME:
Jeeja KPeee0e162017-01-02 09:50:04 +05302326 if (ref_count > skl->skl_sst->lib_count - 1) {
Shreyas NC541070c2016-08-23 09:31:03 +05302327 ref_count = 0;
2328 return -EINVAL;
2329 }
2330
Jeeja KPeee0e162017-01-02 09:50:04 +05302331 strncpy(skl->skl_sst->lib_info[ref_count].name,
2332 str_elem->string,
2333 ARRAY_SIZE(skl->skl_sst->lib_info[ref_count].name));
Shreyas NC541070c2016-08-23 09:31:03 +05302334 ref_count++;
2335 tkn_count++;
2336 break;
2337
2338 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002339 dev_err(dev, "Not a string token %d\n", str_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302340 break;
2341 }
2342
2343 return tkn_count;
2344}
2345
2346static int skl_tplg_get_str_tkn(struct device *dev,
2347 struct snd_soc_tplg_vendor_array *array,
Jeeja KPeee0e162017-01-02 09:50:04 +05302348 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302349{
2350 int tkn_count = 0, ret;
2351 struct snd_soc_tplg_vendor_string_elem *str_elem;
2352
2353 str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
2354 while (tkn_count < array->num_elems) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302355 ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302356 str_elem++;
2357
2358 if (ret < 0)
2359 return ret;
2360
2361 tkn_count = tkn_count + ret;
2362 }
2363
2364 return tkn_count;
2365}
2366
2367static int skl_tplg_get_int_tkn(struct device *dev,
2368 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302369 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302370{
2371 int tkn_count = 0;
2372
2373 switch (tkn_elem->token) {
2374 case SKL_TKN_U32_LIB_COUNT:
Jeeja KPeee0e162017-01-02 09:50:04 +05302375 skl->skl_sst->lib_count = tkn_elem->value;
Shreyas NC541070c2016-08-23 09:31:03 +05302376 tkn_count++;
2377 break;
2378
2379 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002380 dev_err(dev, "Not a manifest token %d\n", tkn_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302381 return -EINVAL;
2382 }
2383
2384 return tkn_count;
2385}
2386
2387/*
2388 * Fill the manifest structure by parsing the tokens based on the
2389 * type.
2390 */
2391static int skl_tplg_get_manifest_tkn(struct device *dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302392 char *pvt_data, struct skl *skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302393 int block_size)
2394{
2395 int tkn_count = 0, ret;
2396 int off = 0, tuple_size = 0;
2397 struct snd_soc_tplg_vendor_array *array;
2398 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2399
2400 if (block_size <= 0)
2401 return -EINVAL;
2402
2403 while (tuple_size < block_size) {
2404 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2405 off += array->size;
2406 switch (array->type) {
2407 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Jeeja KPeee0e162017-01-02 09:50:04 +05302408 ret = skl_tplg_get_str_tkn(dev, array, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302409
2410 if (ret < 0)
2411 return ret;
2412 tkn_count += ret;
2413
2414 tuple_size += tkn_count *
2415 sizeof(struct snd_soc_tplg_vendor_string_elem);
2416 continue;
2417
2418 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002419 dev_warn(dev, "no uuid tokens for skl tplf manifest\n");
Shreyas NC541070c2016-08-23 09:31:03 +05302420 continue;
2421
2422 default:
2423 tkn_elem = array->value;
2424 tkn_count = 0;
2425 break;
2426 }
2427
2428 while (tkn_count <= array->num_elems - 1) {
2429 ret = skl_tplg_get_int_tkn(dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302430 tkn_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302431 if (ret < 0)
2432 return ret;
2433
2434 tkn_count = tkn_count + ret;
2435 tkn_elem++;
2436 tuple_size += tkn_count *
2437 sizeof(struct snd_soc_tplg_vendor_value_elem);
2438 break;
2439 }
2440 tkn_count = 0;
2441 }
2442
2443 return 0;
2444}
2445
2446/*
2447 * Parse manifest private data for tokens. The private data block is
2448 * preceded by descriptors for type and size of data block.
2449 */
2450static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
Jeeja KPeee0e162017-01-02 09:50:04 +05302451 struct device *dev, struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302452{
2453 struct snd_soc_tplg_vendor_array *array;
2454 int num_blocks, block_size = 0, block_type, off = 0;
2455 char *data;
2456 int ret;
2457
2458 /* Read the NUM_DATA_BLOCKS descriptor */
2459 array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
2460 ret = skl_tplg_get_desc_blocks(dev, array);
2461 if (ret < 0)
2462 return ret;
2463 num_blocks = ret;
2464
2465 off += array->size;
2466 array = (struct snd_soc_tplg_vendor_array *)
2467 (manifest->priv.data + off);
2468
2469 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2470 while (num_blocks > 0) {
2471 ret = skl_tplg_get_desc_blocks(dev, array);
2472
2473 if (ret < 0)
2474 return ret;
2475 block_type = ret;
2476 off += array->size;
2477
2478 array = (struct snd_soc_tplg_vendor_array *)
2479 (manifest->priv.data + off);
2480
2481 ret = skl_tplg_get_desc_blocks(dev, array);
2482
2483 if (ret < 0)
2484 return ret;
2485 block_size = ret;
2486 off += array->size;
2487
2488 array = (struct snd_soc_tplg_vendor_array *)
2489 (manifest->priv.data + off);
2490
2491 data = (manifest->priv.data + off);
2492
2493 if (block_type == SKL_TYPE_TUPLE) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302494 ret = skl_tplg_get_manifest_tkn(dev, data, skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302495 block_size);
2496
2497 if (ret < 0)
2498 return ret;
2499
2500 --num_blocks;
2501 } else {
2502 return -EINVAL;
2503 }
2504 }
2505
2506 return 0;
2507}
2508
Kranthi G15ecaba92016-07-26 18:06:43 +05302509static int skl_manifest_load(struct snd_soc_component *cmpnt,
2510 struct snd_soc_tplg_manifest *manifest)
2511{
Kranthi G15ecaba92016-07-26 18:06:43 +05302512 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2513 struct hdac_bus *bus = ebus_to_hbus(ebus);
2514 struct skl *skl = ebus_to_skl(ebus);
Kranthi G15ecaba92016-07-26 18:06:43 +05302515
Vinod Koulc15ad602016-08-24 18:03:13 +05302516 /* proceed only if we have private data defined */
2517 if (manifest->priv.size == 0)
2518 return 0;
2519
Jeeja KPeee0e162017-01-02 09:50:04 +05302520 skl_tplg_get_manifest_data(manifest, bus->dev, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302521
Jeeja KPeee0e162017-01-02 09:50:04 +05302522 if (skl->skl_sst->lib_count > SKL_MAX_LIB) {
Kranthi G15ecaba92016-07-26 18:06:43 +05302523 dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
Jeeja KPeee0e162017-01-02 09:50:04 +05302524 skl->skl_sst->lib_count);
2525 return -EINVAL;
Kranthi G15ecaba92016-07-26 18:06:43 +05302526 }
2527
Jeeja KPeee0e162017-01-02 09:50:04 +05302528 return 0;
Kranthi G15ecaba92016-07-26 18:06:43 +05302529}
2530
Vinod Koul3af36702015-10-07 11:31:56 +01002531static struct snd_soc_tplg_ops skl_tplg_ops = {
2532 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05302533 .control_load = skl_tplg_control_load,
2534 .bytes_ext_ops = skl_tlv_ops,
2535 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Kranthi G15ecaba92016-07-26 18:06:43 +05302536 .manifest = skl_manifest_load,
Vinod Koul3af36702015-10-07 11:31:56 +01002537};
2538
Jeeja KP287af4f2016-06-03 18:29:40 +05302539/*
2540 * A pipe can have multiple modules, each of them will be a DAPM widget as
2541 * well. While managing a pipeline we need to get the list of all the
2542 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
2543 * helps to get the SKL type widgets in that pipeline
2544 */
2545static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform)
2546{
2547 struct snd_soc_dapm_widget *w;
2548 struct skl_module_cfg *mcfg = NULL;
2549 struct skl_pipe_module *p_module = NULL;
2550 struct skl_pipe *pipe;
2551
2552 list_for_each_entry(w, &platform->component.card->widgets, list) {
2553 if (is_skl_dsp_widget_type(w) && w->priv != NULL) {
2554 mcfg = w->priv;
2555 pipe = mcfg->pipe;
2556
2557 p_module = devm_kzalloc(platform->dev,
2558 sizeof(*p_module), GFP_KERNEL);
2559 if (!p_module)
2560 return -ENOMEM;
2561
2562 p_module->w = w;
2563 list_add_tail(&p_module->node, &pipe->w_list);
2564 }
2565 }
2566
2567 return 0;
2568}
2569
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302570static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe)
2571{
2572 struct skl_pipe_module *w_module;
2573 struct snd_soc_dapm_widget *w;
2574 struct skl_module_cfg *mconfig;
2575 bool host_found = false, link_found = false;
2576
2577 list_for_each_entry(w_module, &pipe->w_list, node) {
2578 w = w_module->w;
2579 mconfig = w->priv;
2580
2581 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
2582 host_found = true;
2583 else if (mconfig->dev_type != SKL_DEVICE_NONE)
2584 link_found = true;
2585 }
2586
2587 if (host_found && link_found)
2588 pipe->passthru = true;
2589 else
2590 pipe->passthru = false;
2591}
2592
Vinod Koul3af36702015-10-07 11:31:56 +01002593/* This will be read from topology manifest, currently defined here */
2594#define SKL_MAX_MCPS 30000000
2595#define SKL_FW_MAX_MEM 1000000
2596
2597/*
2598 * SKL topology init routine
2599 */
2600int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
2601{
2602 int ret;
2603 const struct firmware *fw;
2604 struct hdac_bus *bus = ebus_to_hbus(ebus);
2605 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302606 struct skl_pipeline *ppl;
Vinod Koul3af36702015-10-07 11:31:56 +01002607
Vinod Koul4b235c42016-02-19 11:42:34 +05302608 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01002609 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01002610 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05302611 skl->tplg_name, ret);
2612 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
2613 if (ret < 0) {
2614 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
2615 "dfw_sst.bin", ret);
2616 return ret;
2617 }
Vinod Koul3af36702015-10-07 11:31:56 +01002618 }
2619
2620 /*
2621 * The complete tplg for SKL is loaded as index 0, we don't use
2622 * any other index
2623 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01002624 ret = snd_soc_tplg_component_load(&platform->component,
2625 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01002626 if (ret < 0) {
2627 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05302628 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01002629 return -EINVAL;
2630 }
2631
2632 skl->resource.max_mcps = SKL_MAX_MCPS;
2633 skl->resource.max_mem = SKL_FW_MAX_MEM;
2634
Vinod Kould8018362016-01-05 17:16:04 +05302635 skl->tplg = fw;
Jeeja KP287af4f2016-06-03 18:29:40 +05302636 ret = skl_tplg_create_pipe_widget_list(platform);
2637 if (ret < 0)
2638 return ret;
Vinod Kould8018362016-01-05 17:16:04 +05302639
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302640 list_for_each_entry(ppl, &skl->ppl_list, node)
2641 skl_tplg_set_pipe_type(skl, ppl->pipe);
Vinod Koul3af36702015-10-07 11:31:56 +01002642
2643 return 0;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01002644}