Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 1 | /* |
Sean Wang | a63e3d2 | 2018-04-11 16:53:59 +0800 | [diff] [blame^] | 2 | * Copyright 2017-2018 Sean Wang <sean.wang@mediatek.com> |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include <dt-bindings/input/input.h> |
| 9 | #include "mt7623.dtsi" |
| 10 | #include "mt6323.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "Bananapi BPI-R2"; |
| 14 | compatible = "bananapi,bpi-r2", "mediatek,mt7623"; |
| 15 | |
| 16 | aliases { |
| 17 | serial2 = &uart2; |
| 18 | }; |
| 19 | |
| 20 | chosen { |
| 21 | stdout-path = "serial2:115200n8"; |
| 22 | }; |
| 23 | |
| 24 | cpus { |
| 25 | cpu@0 { |
| 26 | proc-supply = <&mt6323_vproc_reg>; |
| 27 | }; |
| 28 | |
| 29 | cpu@1 { |
| 30 | proc-supply = <&mt6323_vproc_reg>; |
| 31 | }; |
| 32 | |
| 33 | cpu@2 { |
| 34 | proc-supply = <&mt6323_vproc_reg>; |
| 35 | }; |
| 36 | |
| 37 | cpu@3 { |
| 38 | proc-supply = <&mt6323_vproc_reg>; |
| 39 | }; |
| 40 | }; |
| 41 | |
Sean Wang | 528a97e | 2018-02-23 18:16:27 +0800 | [diff] [blame] | 42 | reg_1p8v: regulator-1p8v { |
| 43 | compatible = "regulator-fixed"; |
| 44 | regulator-name = "fixed-1.8V"; |
| 45 | regulator-min-microvolt = <1800000>; |
| 46 | regulator-max-microvolt = <1800000>; |
| 47 | regulator-boot-on; |
| 48 | regulator-always-on; |
| 49 | }; |
| 50 | |
Sean Wang | 0629a01 | 2018-02-23 18:16:26 +0800 | [diff] [blame] | 51 | reg_3p3v: regulator-3p3v { |
| 52 | compatible = "regulator-fixed"; |
| 53 | regulator-name = "fixed-3.3V"; |
| 54 | regulator-min-microvolt = <3300000>; |
| 55 | regulator-max-microvolt = <3300000>; |
| 56 | regulator-boot-on; |
| 57 | regulator-always-on; |
| 58 | }; |
| 59 | |
| 60 | reg_5v: regulator-5v { |
| 61 | compatible = "regulator-fixed"; |
| 62 | regulator-name = "fixed-5V"; |
| 63 | regulator-min-microvolt = <5000000>; |
| 64 | regulator-max-microvolt = <5000000>; |
| 65 | regulator-boot-on; |
| 66 | regulator-always-on; |
| 67 | }; |
| 68 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 69 | gpio-keys { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 70 | compatible = "gpio-keys"; |
| 71 | pinctrl-names = "default"; |
| 72 | pinctrl-0 = <&key_pins_a>; |
| 73 | |
| 74 | factory { |
| 75 | label = "factory"; |
| 76 | linux,code = <BTN_0>; |
| 77 | gpios = <&pio 256 GPIO_ACTIVE_LOW>; |
| 78 | }; |
| 79 | |
| 80 | wps { |
| 81 | label = "wps"; |
| 82 | linux,code = <KEY_WPS_BUTTON>; |
| 83 | gpios = <&pio 257 GPIO_ACTIVE_HIGH>; |
| 84 | }; |
| 85 | }; |
| 86 | |
| 87 | leds { |
| 88 | compatible = "gpio-leds"; |
| 89 | pinctrl-names = "default"; |
| 90 | pinctrl-0 = <&led_pins_a>; |
| 91 | |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 92 | blue { |
| 93 | label = "bpi-r2:pio:blue"; |
| 94 | gpios = <&pio 241 GPIO_ACTIVE_HIGH>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 95 | default-state = "off"; |
| 96 | }; |
| 97 | |
| 98 | green { |
| 99 | label = "bpi-r2:pio:green"; |
| 100 | gpios = <&pio 240 GPIO_ACTIVE_HIGH>; |
| 101 | default-state = "off"; |
| 102 | }; |
| 103 | |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 104 | red { |
| 105 | label = "bpi-r2:pio:red"; |
| 106 | gpios = <&pio 239 GPIO_ACTIVE_HIGH>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 107 | default-state = "off"; |
| 108 | }; |
| 109 | }; |
| 110 | |
| 111 | memory@80000000 { |
Sean Wang | c0b0d54 | 2018-04-11 16:53:56 +0800 | [diff] [blame] | 112 | device_type = "memory"; |
Sean Wang | acf0996 | 2018-04-11 16:53:57 +0800 | [diff] [blame] | 113 | reg = <0 0x80000000 0 0x80000000>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 114 | }; |
| 115 | }; |
| 116 | |
Sean Wang | a63e3d2 | 2018-04-11 16:53:59 +0800 | [diff] [blame^] | 117 | &btif { |
| 118 | status = "okay"; |
| 119 | }; |
| 120 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 121 | &cir { |
| 122 | pinctrl-names = "default"; |
| 123 | pinctrl-0 = <&cir_pins_a>; |
| 124 | status = "okay"; |
| 125 | }; |
| 126 | |
| 127 | &crypto { |
| 128 | status = "okay"; |
| 129 | }; |
| 130 | |
| 131 | ð { |
| 132 | status = "okay"; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 133 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 134 | gmac0: mac@0 { |
| 135 | compatible = "mediatek,eth-mac"; |
| 136 | reg = <0>; |
| 137 | phy-mode = "trgmii"; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 138 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 139 | fixed-link { |
| 140 | speed = <1000>; |
| 141 | full-duplex; |
| 142 | pause; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | mdio: mdio-bus { |
| 147 | #address-cells = <1>; |
| 148 | #size-cells = <0>; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 149 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 150 | switch@0 { |
| 151 | compatible = "mediatek,mt7530"; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 152 | reg = <0>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 153 | reset-gpios = <&pio 33 0>; |
| 154 | core-supply = <&mt6323_vpa_reg>; |
| 155 | io-supply = <&mt6323_vemc3v3_reg>; |
| 156 | |
| 157 | ports { |
| 158 | #address-cells = <1>; |
| 159 | #size-cells = <0>; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 160 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 161 | port@0 { |
| 162 | reg = <0>; |
| 163 | label = "wan"; |
| 164 | }; |
| 165 | |
| 166 | port@1 { |
| 167 | reg = <1>; |
| 168 | label = "lan0"; |
| 169 | }; |
| 170 | |
| 171 | port@2 { |
| 172 | reg = <2>; |
| 173 | label = "lan1"; |
| 174 | }; |
| 175 | |
| 176 | port@3 { |
| 177 | reg = <3>; |
| 178 | label = "lan2"; |
| 179 | }; |
| 180 | |
| 181 | port@4 { |
| 182 | reg = <4>; |
| 183 | label = "lan3"; |
| 184 | }; |
| 185 | |
| 186 | port@6 { |
| 187 | reg = <6>; |
| 188 | label = "cpu"; |
| 189 | ethernet = <&gmac0>; |
| 190 | phy-mode = "trgmii"; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 191 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 192 | fixed-link { |
| 193 | speed = <1000>; |
| 194 | full-duplex; |
| 195 | }; |
| 196 | }; |
| 197 | }; |
| 198 | }; |
| 199 | }; |
| 200 | }; |
| 201 | |
| 202 | &i2c0 { |
| 203 | pinctrl-names = "default"; |
| 204 | pinctrl-0 = <&i2c0_pins_a>; |
| 205 | status = "okay"; |
| 206 | }; |
| 207 | |
| 208 | &i2c1 { |
| 209 | pinctrl-names = "default"; |
| 210 | pinctrl-0 = <&i2c1_pins_a>; |
| 211 | status = "okay"; |
| 212 | }; |
| 213 | |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 214 | &mmc0 { |
| 215 | pinctrl-names = "default", "state_uhs"; |
| 216 | pinctrl-0 = <&mmc0_pins_default>; |
| 217 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 218 | status = "okay"; |
| 219 | bus-width = <8>; |
| 220 | max-frequency = <50000000>; |
| 221 | cap-mmc-highspeed; |
Sean Wang | 528a97e | 2018-02-23 18:16:27 +0800 | [diff] [blame] | 222 | vmmc-supply = <®_3p3v>; |
| 223 | vqmmc-supply = <®_1p8v>; |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 224 | non-removable; |
| 225 | }; |
| 226 | |
| 227 | &mmc1 { |
| 228 | pinctrl-names = "default", "state_uhs"; |
| 229 | pinctrl-0 = <&mmc1_pins_default>; |
| 230 | pinctrl-1 = <&mmc1_pins_uhs>; |
| 231 | status = "okay"; |
| 232 | bus-width = <4>; |
| 233 | max-frequency = <50000000>; |
| 234 | cap-sd-highspeed; |
Sean Wang | b96a696 | 2017-12-07 14:43:24 +0800 | [diff] [blame] | 235 | cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; |
Sean Wang | 528a97e | 2018-02-23 18:16:27 +0800 | [diff] [blame] | 236 | vmmc-supply = <®_3p3v>; |
| 237 | vqmmc-supply = <®_3p3v>; |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 238 | }; |
| 239 | |
Ryder Lee | c10a98c | 2018-02-14 11:27:34 +0800 | [diff] [blame] | 240 | &pcie { |
| 241 | pinctrl-names = "default"; |
| 242 | pinctrl-0 = <&pcie_default>; |
| 243 | status = "okay"; |
| 244 | |
| 245 | pcie@0,0 { |
| 246 | status = "okay"; |
| 247 | }; |
| 248 | |
| 249 | pcie@1,0 { |
| 250 | status = "okay"; |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | &pcie0_phy { |
| 255 | status = "okay"; |
| 256 | }; |
| 257 | |
| 258 | &pcie1_phy { |
| 259 | status = "okay"; |
| 260 | }; |
| 261 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 262 | &pio { |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 263 | cir_pins_a:cir-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 264 | pins-cir { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 265 | pinmux = <MT7623_PIN_46_IR_FUNC_IR>; |
| 266 | bias-disable; |
| 267 | }; |
| 268 | }; |
| 269 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 270 | i2c0_pins_a: i2c0-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 271 | pins-i2c0 { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 272 | pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, |
| 273 | <MT7623_PIN_76_SCL0_FUNC_SCL0>; |
| 274 | bias-disable; |
| 275 | }; |
| 276 | }; |
| 277 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 278 | i2c1_pins_a: i2c1-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 279 | pin-i2c1 { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 280 | pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, |
| 281 | <MT7623_PIN_58_SCL1_FUNC_SCL1>; |
| 282 | bias-disable; |
| 283 | }; |
| 284 | }; |
| 285 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 286 | i2s0_pins_a: i2s0-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 287 | pin-i2s0 { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 288 | pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, |
| 289 | <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, |
| 290 | <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, |
| 291 | <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, |
| 292 | <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; |
| 293 | drive-strength = <MTK_DRIVE_12mA>; |
| 294 | bias-pull-down; |
| 295 | }; |
| 296 | }; |
| 297 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 298 | i2s1_pins_a: i2s1-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 299 | pin-i2s1 { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 300 | pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, |
| 301 | <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, |
| 302 | <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, |
| 303 | <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, |
| 304 | <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; |
| 305 | drive-strength = <MTK_DRIVE_12mA>; |
| 306 | bias-pull-down; |
| 307 | }; |
| 308 | }; |
| 309 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 310 | key_pins_a: keys-alt { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 311 | pins-keys { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 312 | pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, |
| 313 | <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; |
| 314 | input-enable; |
| 315 | }; |
| 316 | }; |
| 317 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 318 | led_pins_a: leds-alt { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 319 | pins-leds { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 320 | pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, |
| 321 | <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, |
| 322 | <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>; |
| 323 | }; |
| 324 | }; |
| 325 | |
| 326 | mmc0_pins_default: mmc0default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 327 | pins-cmd-dat { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 328 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
| 329 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
| 330 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
| 331 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
| 332 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
| 333 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
| 334 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
| 335 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
| 336 | <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
| 337 | input-enable; |
| 338 | bias-pull-up; |
| 339 | }; |
| 340 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 341 | pins-clk { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 342 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
| 343 | bias-pull-down; |
| 344 | }; |
| 345 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 346 | pins-rst { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 347 | pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
| 348 | bias-pull-up; |
| 349 | }; |
| 350 | }; |
| 351 | |
| 352 | mmc0_pins_uhs: mmc0 { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 353 | pins-cmd-dat { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 354 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
| 355 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
| 356 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
| 357 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
| 358 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
| 359 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
| 360 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
| 361 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
| 362 | <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
| 363 | input-enable; |
| 364 | drive-strength = <MTK_DRIVE_2mA>; |
| 365 | bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| 366 | }; |
| 367 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 368 | pins-clk { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 369 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
| 370 | drive-strength = <MTK_DRIVE_2mA>; |
| 371 | bias-pull-down = <MTK_PUPD_SET_R1R0_01>; |
| 372 | }; |
| 373 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 374 | pins-rst { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 375 | pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
| 376 | bias-pull-up; |
| 377 | }; |
| 378 | }; |
| 379 | |
| 380 | mmc1_pins_default: mmc1default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 381 | pins-cmd-dat { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 382 | pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
| 383 | <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
| 384 | <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
| 385 | <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
| 386 | <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
| 387 | input-enable; |
| 388 | drive-strength = <MTK_DRIVE_4mA>; |
| 389 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| 390 | }; |
| 391 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 392 | pins-clk { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 393 | pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
| 394 | bias-pull-down; |
| 395 | drive-strength = <MTK_DRIVE_4mA>; |
| 396 | }; |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 397 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 398 | pins-wp { |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 399 | pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; |
| 400 | input-enable; |
| 401 | bias-pull-up; |
| 402 | }; |
| 403 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 404 | pins-insert { |
Sean Wang | 0eed8d0 | 2017-08-04 11:59:34 +0800 | [diff] [blame] | 405 | pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; |
| 406 | bias-pull-up; |
| 407 | }; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 408 | }; |
| 409 | |
| 410 | mmc1_pins_uhs: mmc1 { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 411 | pins-cmd-dat { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 412 | pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
| 413 | <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
| 414 | <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
| 415 | <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
| 416 | <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
| 417 | input-enable; |
| 418 | drive-strength = <MTK_DRIVE_4mA>; |
| 419 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| 420 | }; |
| 421 | |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 422 | pins-clk { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 423 | pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
| 424 | drive-strength = <MTK_DRIVE_4mA>; |
| 425 | bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| 426 | }; |
| 427 | }; |
| 428 | |
Ryder Lee | c10a98c | 2018-02-14 11:27:34 +0800 | [diff] [blame] | 429 | pcie_default: pcie_pin_default { |
| 430 | pins_cmd_dat { |
| 431 | pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, |
| 432 | <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; |
| 433 | bias-disable; |
| 434 | }; |
| 435 | }; |
| 436 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 437 | pwm_pins_a: pwm-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 438 | pins-pwm { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 439 | pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, |
| 440 | <MT7623_PIN_204_PWM1_FUNC_PWM1>, |
| 441 | <MT7623_PIN_205_PWM2_FUNC_PWM2>, |
| 442 | <MT7623_PIN_206_PWM3_FUNC_PWM3>, |
| 443 | <MT7623_PIN_207_PWM4_FUNC_PWM4>; |
| 444 | }; |
| 445 | }; |
| 446 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 447 | spi0_pins_a: spi0-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 448 | pins-spi { |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 449 | pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, |
| 450 | <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, |
| 451 | <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, |
| 452 | <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; |
| 453 | bias-disable; |
| 454 | }; |
| 455 | }; |
| 456 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 457 | uart0_pins_a: uart0-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 458 | pins-dat { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 459 | pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, |
| 460 | <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; |
| 461 | }; |
| 462 | }; |
| 463 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 464 | uart1_pins_a: uart1-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 465 | pins-dat { |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 466 | pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, |
| 467 | <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; |
| 468 | }; |
| 469 | }; |
Sean Wang | cc2f652 | 2018-02-23 18:16:28 +0800 | [diff] [blame] | 470 | |
Sean Wang | 1c8fadd | 2018-04-11 16:53:58 +0800 | [diff] [blame] | 471 | uart2_pins_a: uart2-default { |
Sean Wang | 58b3696 | 2018-02-23 18:16:31 +0800 | [diff] [blame] | 472 | pins-dat { |
Sean Wang | cc2f652 | 2018-02-23 18:16:28 +0800 | [diff] [blame] | 473 | pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>, |
| 474 | <MT7623_PIN_15_GPIO15_FUNC_UTXD2>; |
| 475 | }; |
| 476 | }; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 477 | }; |
| 478 | |
| 479 | &pwm { |
| 480 | pinctrl-names = "default"; |
| 481 | pinctrl-0 = <&pwm_pins_a>; |
| 482 | status = "okay"; |
| 483 | }; |
| 484 | |
| 485 | &pwrap { |
| 486 | mt6323 { |
| 487 | mt6323led: led { |
| 488 | compatible = "mediatek,mt6323-led"; |
| 489 | #address-cells = <1>; |
| 490 | #size-cells = <0>; |
| 491 | |
| 492 | led@0 { |
| 493 | reg = <0>; |
| 494 | label = "bpi-r2:isink:green"; |
| 495 | default-state = "off"; |
| 496 | }; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 497 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 498 | led@1 { |
| 499 | reg = <1>; |
| 500 | label = "bpi-r2:isink:red"; |
| 501 | default-state = "off"; |
| 502 | }; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 503 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 504 | led@2 { |
| 505 | reg = <2>; |
| 506 | label = "bpi-r2:isink:blue"; |
| 507 | default-state = "off"; |
| 508 | }; |
| 509 | }; |
| 510 | }; |
| 511 | }; |
| 512 | |
| 513 | &spi0 { |
| 514 | pinctrl-names = "default"; |
| 515 | pinctrl-0 = <&spi0_pins_a>; |
| 516 | status = "okay"; |
| 517 | }; |
| 518 | |
| 519 | &uart0 { |
| 520 | pinctrl-names = "default"; |
| 521 | pinctrl-0 = <&uart0_pins_a>; |
Sean Wang | cc2f652 | 2018-02-23 18:16:28 +0800 | [diff] [blame] | 522 | status = "okay"; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 523 | }; |
| 524 | |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 525 | &uart1 { |
| 526 | pinctrl-names = "default"; |
| 527 | pinctrl-0 = <&uart1_pins_a>; |
Sean Wang | cc2f652 | 2018-02-23 18:16:28 +0800 | [diff] [blame] | 528 | status = "okay"; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 529 | }; |
| 530 | |
| 531 | &uart2 { |
Sean Wang | cc2f652 | 2018-02-23 18:16:28 +0800 | [diff] [blame] | 532 | pinctrl-names = "default"; |
| 533 | pinctrl-0 = <&uart2_pins_a>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 534 | status = "okay"; |
| 535 | }; |
| 536 | |
| 537 | &usb1 { |
Sean Wang | 0629a01 | 2018-02-23 18:16:26 +0800 | [diff] [blame] | 538 | vusb33-supply = <®_3p3v>; |
| 539 | vbus-supply = <®_5v>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 540 | status = "okay"; |
| 541 | }; |
| 542 | |
| 543 | &usb2 { |
Sean Wang | 0629a01 | 2018-02-23 18:16:26 +0800 | [diff] [blame] | 544 | vusb33-supply = <®_3p3v>; |
| 545 | vbus-supply = <®_5v>; |
Sean Wang | f4ff257 | 2017-07-31 15:36:42 +0800 | [diff] [blame] | 546 | status = "okay"; |
| 547 | }; |
Ryder Lee | dfff569 | 2017-08-04 11:59:35 +0800 | [diff] [blame] | 548 | |
| 549 | &u3phy1 { |
| 550 | status = "okay"; |
| 551 | }; |
| 552 | |
| 553 | &u3phy2 { |
| 554 | status = "okay"; |
| 555 | }; |
| 556 | |