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gerrit-public.fairphone.software / kernel / msm-5.4 / ad0acf782d0ecedfbae2ae8f5f6c25bb3b6e97b6 / . / arch / arm / boot / dts / tegra20-harmony.dts
blob: f45aad688d9b5296239795860231de5d3340eab1 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]3#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]4#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]5
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +0000[diff] [blame]7 model = "NVIDIA Tegra20 Harmony evaluation board";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]8 compatible = "nvidia,harmony", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]16 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]17 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]19 host1x@50000000 {
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]28 hdmi@54280000 {
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]29 status = "okay";
30
Thierry Redingad0acf72014-04-25 17:44:48 +0200[diff] [blame^]31 hdmi-supply = <&vdd_5v0_hdmi>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]32 vdd-supply = <&hdmi_vdd_reg>;
33 pll-supply = <&hdmi_pll_reg>;
34
35 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]36 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
37 GPIO_ACTIVE_HIGH>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]38 };
39 };
40
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]41 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]42 pinctrl-names = "default";
43 pinctrl-0 = <&state_default>;
44
45 state_default: pinmux {
46 ata {
47 nvidia,pins = "ata";
48 nvidia,function = "ide";
49 };
50 atb {
51 nvidia,pins = "atb", "gma", "gme";
52 nvidia,function = "sdio4";
53 };
54 atc {
55 nvidia,pins = "atc";
56 nvidia,function = "nand";
57 };
58 atd {
59 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
60 "spia", "spib", "spic";
61 nvidia,function = "gmi";
62 };
63 cdev1 {
64 nvidia,pins = "cdev1";
65 nvidia,function = "plla_out";
66 };
67 cdev2 {
68 nvidia,pins = "cdev2";
69 nvidia,function = "pllp_out4";
70 };
71 crtp {
72 nvidia,pins = "crtp";
73 nvidia,function = "crt";
74 };
75 csus {
76 nvidia,pins = "csus";
77 nvidia,function = "vi_sensor_clk";
78 };
79 dap1 {
80 nvidia,pins = "dap1";
81 nvidia,function = "dap1";
82 };
83 dap2 {
84 nvidia,pins = "dap2";
85 nvidia,function = "dap2";
86 };
87 dap3 {
88 nvidia,pins = "dap3";
89 nvidia,function = "dap3";
90 };
91 dap4 {
92 nvidia,pins = "dap4";
93 nvidia,function = "dap4";
94 };
95 ddc {
96 nvidia,pins = "ddc";
97 nvidia,function = "i2c2";
98 };
99 dta {
100 nvidia,pins = "dta", "dtd";
101 nvidia,function = "sdio2";
102 };
103 dtb {
104 nvidia,pins = "dtb", "dtc", "dte";
105 nvidia,function = "rsvd1";
106 };
107 dtf {
108 nvidia,pins = "dtf";
109 nvidia,function = "i2c3";
110 };
111 gmc {
112 nvidia,pins = "gmc";
113 nvidia,function = "uartd";
114 };
115 gpu7 {
116 nvidia,pins = "gpu7";
117 nvidia,function = "rtck";
118 };
119 gpv {
120 nvidia,pins = "gpv", "slxa", "slxk";
121 nvidia,function = "pcie";
122 };
123 hdint {
124 nvidia,pins = "hdint", "pta";
125 nvidia,function = "hdmi";
126 };
127 i2cp {
128 nvidia,pins = "i2cp";
129 nvidia,function = "i2cp";
130 };
131 irrx {
132 nvidia,pins = "irrx", "irtx";
133 nvidia,function = "uarta";
134 };
135 kbca {
136 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
137 "kbce", "kbcf";
138 nvidia,function = "kbc";
139 };
140 lcsn {
141 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
142 "ld3", "ld4", "ld5", "ld6", "ld7",
143 "ld8", "ld9", "ld10", "ld11", "ld12",
144 "ld13", "ld14", "ld15", "ld16", "ld17",
145 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
146 "lhs", "lm0", "lm1", "lpp", "lpw0",
147 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
148 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
149 "lvs";
150 nvidia,function = "displaya";
151 };
152 owc {
153 nvidia,pins = "owc", "spdi", "spdo", "uac";
154 nvidia,function = "rsvd2";
155 };
156 pmc {
157 nvidia,pins = "pmc";
158 nvidia,function = "pwr_on";
159 };
160 rm {
161 nvidia,pins = "rm";
162 nvidia,function = "i2c1";
163 };
164 sdb {
165 nvidia,pins = "sdb", "sdc", "sdd";
166 nvidia,function = "pwm";
167 };
168 sdio1 {
169 nvidia,pins = "sdio1";
170 nvidia,function = "sdio1";
171 };
172 slxc {
173 nvidia,pins = "slxc", "slxd";
174 nvidia,function = "spdif";
175 };
176 spid {
177 nvidia,pins = "spid", "spie", "spif";
178 nvidia,function = "spi1";
179 };
180 spig {
181 nvidia,pins = "spig", "spih";
182 nvidia,function = "spi2_alt";
183 };
184 uaa {
185 nvidia,pins = "uaa", "uab", "uda";
186 nvidia,function = "ulpi";
187 };
188 uad {
189 nvidia,pins = "uad";
190 nvidia,function = "irda";
191 };
192 uca {
193 nvidia,pins = "uca", "ucb";
194 nvidia,function = "uartc";
195 };
196 conf_ata {
197 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]198 "cdev1", "cdev2", "dap1", "dtb", "gma",
199 "gmb", "gmc", "gmd", "gme", "gpu7",
200 "gpv", "i2cp", "pta", "rm", "slxa",
201 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]204 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]205 conf_ck32 {
206 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
207 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]209 };
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]210 conf_csus {
211 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]212 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
213 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]214 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]215 conf_crtp {
216 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
217 "dtc", "dte", "dtf", "gpu", "sdio1",
218 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]219 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]222 };
223 conf_ddc {
224 nvidia,pins = "ddc", "dta", "dtd", "kbca",
225 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
226 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]229 };
230 conf_hdint {
231 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
232 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
233 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]234 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]235 };
236 conf_irrx {
237 nvidia,pins = "irrx", "irtx", "sdd", "spic",
238 "spie", "spih", "uaa", "uab", "uad",
239 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]240 nvidia,pull = <TEGRA_PIN_PULL_UP>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]242 };
243 conf_lc {
244 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]246 };
247 conf_ld0 {
248 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
249 "ld5", "ld6", "ld7", "ld8", "ld9",
250 "ld10", "ld11", "ld12", "ld13", "ld14",
251 "ld15", "ld16", "ld17", "ldi", "lhp0",
252 "lhp1", "lhp2", "lhs", "lm0", "lpp",
253 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
254 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]256 };
257 conf_ld17_0 {
258 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
259 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]260 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]261 };
262 };
263 };
264
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]265 i2s@70002800 {
266 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]267 };
268
269 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]270 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]271 };
272
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]273 pwm: pwm@7000a000 {
274 status = "okay";
275 };
276
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]277 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]278 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]279 clock-frequency = <400000>;
280
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]281 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]282 compatible = "wlf,wm8903";
283 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]284 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]285 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]286
287 gpio-controller;
288 #gpio-cells = <2>;
289
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]290 micdet-cfg = <0>;
291 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]292 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]293 };
294 };
295
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]296 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]297 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]298 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]299 };
300
301 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]302 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]303 clock-frequency = <400000>;
304 };
305
306 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]307 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]308 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]309
310 pmic: tps6586x@34 {
311 compatible = "ti,tps6586x";
312 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]313 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]314
Stephen Warrenbe972c32012-09-11 11:40:04 -0600[diff] [blame]315 ti,system-power-controller;
316
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]317 #gpio-cells = <2>;
318 gpio-controller;
319
320 sys-supply = <&vdd_5v0_reg>;
321 vin-sm0-supply = <&sys_reg>;
322 vin-sm1-supply = <&sys_reg>;
323 vin-sm2-supply = <&sys_reg>;
324 vinldo01-supply = <&sm2_reg>;
325 vinldo23-supply = <&sm2_reg>;
326 vinldo4-supply = <&sm2_reg>;
327 vinldo678-supply = <&sm2_reg>;
328 vinldo9-supply = <&sm2_reg>;
329
330 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]331 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]332 regulator-name = "vdd_sys";
333 regulator-always-on;
334 };
335
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]336 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]337 regulator-name = "vdd_sm0,vdd_core";
338 regulator-min-microvolt = <1200000>;
339 regulator-max-microvolt = <1200000>;
340 regulator-always-on;
341 };
342
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]343 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]344 regulator-name = "vdd_sm1,vdd_cpu";
345 regulator-min-microvolt = <1000000>;
346 regulator-max-microvolt = <1000000>;
347 regulator-always-on;
348 };
349
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]350 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]351 regulator-name = "vdd_sm2,vin_ldo*";
352 regulator-min-microvolt = <3700000>;
353 regulator-max-microvolt = <3700000>;
354 regulator-always-on;
355 };
356
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]357 pci_clk_reg: ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]358 regulator-name = "vdd_ldo0,vddio_pex_clk";
359 regulator-min-microvolt = <3300000>;
360 regulator-max-microvolt = <3300000>;
361 };
362
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]363 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]364 regulator-name = "vdd_ldo1,avdd_pll*";
365 regulator-min-microvolt = <1100000>;
366 regulator-max-microvolt = <1100000>;
367 regulator-always-on;
368 };
369
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]370 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]371 regulator-name = "vdd_ldo2,vdd_rtc";
372 regulator-min-microvolt = <1200000>;
373 regulator-max-microvolt = <1200000>;
374 };
375
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]376 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]377 regulator-name = "vdd_ldo3,avdd_usb*";
378 regulator-min-microvolt = <3300000>;
379 regulator-max-microvolt = <3300000>;
380 regulator-always-on;
381 };
382
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]383 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]384 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <1800000>;
387 regulator-always-on;
388 };
389
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]390 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]391 regulator-name = "vdd_ldo5,vcore_mmc";
392 regulator-min-microvolt = <2850000>;
393 regulator-max-microvolt = <2850000>;
394 regulator-always-on;
395 };
396
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]397 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]398 regulator-name = "vdd_ldo6,avdd_vdac";
399 regulator-min-microvolt = <1800000>;
400 regulator-max-microvolt = <1800000>;
401 };
402
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]403 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600[diff] [blame]404 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]405 regulator-min-microvolt = <3300000>;
406 regulator-max-microvolt = <3300000>;
407 };
408
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]409 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]410 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
411 regulator-min-microvolt = <1800000>;
412 regulator-max-microvolt = <1800000>;
413 };
414
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]415 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]416 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
417 regulator-min-microvolt = <2850000>;
418 regulator-max-microvolt = <2850000>;
419 regulator-always-on;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]422 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]423 regulator-name = "vdd_rtc_out,vdd_cell";
424 regulator-min-microvolt = <3300000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-always-on;
427 };
428 };
429 };
Thierry Reding42d25342012-11-09 22:58:43 +0100[diff] [blame]430
431 temperature-sensor@4c {
432 compatible = "adi,adt7461";
433 reg = <0x4c>;
434 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]435 };
436
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]437 kbc@7000e200 {
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]438 status = "okay";
439 nvidia,debounce-delay-ms = <2>;
440 nvidia,repeat-delay-ms = <160>;
441 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
442 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]443 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
444 MATRIX_KEY(0x00, 0x03, KEY_S)
445 MATRIX_KEY(0x00, 0x04, KEY_A)
446 MATRIX_KEY(0x00, 0x05, KEY_Z)
447 MATRIX_KEY(0x00, 0x07, KEY_FN)
448 MATRIX_KEY(0x01, 0x07, KEY_MENU)
449 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
450 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
451 MATRIX_KEY(0x03, 0x00, KEY_5)
452 MATRIX_KEY(0x03, 0x01, KEY_4)
453 MATRIX_KEY(0x03, 0x02, KEY_R)
454 MATRIX_KEY(0x03, 0x03, KEY_E)
455 MATRIX_KEY(0x03, 0x04, KEY_F)
456 MATRIX_KEY(0x03, 0x05, KEY_D)
457 MATRIX_KEY(0x03, 0x06, KEY_X)
458 MATRIX_KEY(0x04, 0x00, KEY_7)
459 MATRIX_KEY(0x04, 0x01, KEY_6)
460 MATRIX_KEY(0x04, 0x02, KEY_T)
461 MATRIX_KEY(0x04, 0x03, KEY_H)
462 MATRIX_KEY(0x04, 0x04, KEY_G)
463 MATRIX_KEY(0x04, 0x05, KEY_V)
464 MATRIX_KEY(0x04, 0x06, KEY_C)
465 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
466 MATRIX_KEY(0x05, 0x00, KEY_9)
467 MATRIX_KEY(0x05, 0x01, KEY_8)
468 MATRIX_KEY(0x05, 0x02, KEY_U)
469 MATRIX_KEY(0x05, 0x03, KEY_Y)
470 MATRIX_KEY(0x05, 0x04, KEY_J)
471 MATRIX_KEY(0x05, 0x05, KEY_N)
472 MATRIX_KEY(0x05, 0x06, KEY_B)
473 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
474 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
475 MATRIX_KEY(0x06, 0x01, KEY_0)
476 MATRIX_KEY(0x06, 0x02, KEY_O)
477 MATRIX_KEY(0x06, 0x03, KEY_I)
478 MATRIX_KEY(0x06, 0x04, KEY_L)
479 MATRIX_KEY(0x06, 0x05, KEY_K)
480 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
481 MATRIX_KEY(0x06, 0x07, KEY_M)
482 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
483 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
484 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
485 MATRIX_KEY(0x07, 0x07, KEY_MENU)
486 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
487 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
488 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
489 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
490 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
491 MATRIX_KEY(0x0B, 0x01, KEY_P)
492 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
493 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
494 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
495 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
496 MATRIX_KEY(0x0C, 0x00, KEY_F10)
497 MATRIX_KEY(0x0C, 0x01, KEY_F9)
498 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
499 MATRIX_KEY(0x0C, 0x03, KEY_3)
500 MATRIX_KEY(0x0C, 0x04, KEY_2)
501 MATRIX_KEY(0x0C, 0x05, KEY_UP)
502 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
503 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
504 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
505 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
506 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
507 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
508 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
509 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
510 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
511 MATRIX_KEY(0x0E, 0x00, KEY_F11)
512 MATRIX_KEY(0x0E, 0x01, KEY_F12)
513 MATRIX_KEY(0x0E, 0x02, KEY_F8)
514 MATRIX_KEY(0x0E, 0x03, KEY_Q)
515 MATRIX_KEY(0x0E, 0x04, KEY_F4)
516 MATRIX_KEY(0x0E, 0x05, KEY_F3)
517 MATRIX_KEY(0x0E, 0x06, KEY_1)
518 MATRIX_KEY(0x0E, 0x07, KEY_F7)
519 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
520 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
521 MATRIX_KEY(0x0F, 0x02, KEY_F5)
522 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
523 MATRIX_KEY(0x0F, 0x04, KEY_F1)
524 MATRIX_KEY(0x0F, 0x05, KEY_F2)
525 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
526 MATRIX_KEY(0x0F, 0x07, KEY_F6)
527 MATRIX_KEY(0x14, 0x00, KEY_KP7)
528 MATRIX_KEY(0x15, 0x00, KEY_KP9)
529 MATRIX_KEY(0x15, 0x01, KEY_KP8)
530 MATRIX_KEY(0x15, 0x02, KEY_KP4)
531 MATRIX_KEY(0x15, 0x04, KEY_KP1)
532 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
533 MATRIX_KEY(0x16, 0x02, KEY_KP6)
534 MATRIX_KEY(0x16, 0x03, KEY_KP5)
535 MATRIX_KEY(0x16, 0x04, KEY_KP3)
536 MATRIX_KEY(0x16, 0x05, KEY_KP2)
537 MATRIX_KEY(0x16, 0x07, KEY_KP0)
538 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
539 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
540 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
541 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
542 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
543 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
544 MATRIX_KEY(0x1D, 0x04, KEY_END)
545 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
546 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
547 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
548 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
549 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
550 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
551 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]552 };
553
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]554 pmc@7000e400 {
555 nvidia,invert-interrupt;
556 nvidia,suspend-mode = <1>;
557 nvidia,cpu-pwr-good-time = <5000>;
558 nvidia,cpu-pwr-off-time = <5000>;
559 nvidia,core-pwr-good-time = <3845 3845>;
560 nvidia,core-pwr-off-time = <3875>;
561 nvidia,sys-clock-req-active-high;
562 };
563
564 pcie-controller@80003000 {
565 pex-clk-supply = <&pci_clk_reg>;
566 vdd-supply = <&pci_vdd_reg>;
567 status = "okay";
568
569 pci@1,0 {
570 status = "okay";
571 };
572
573 pci@2,0 {
574 status = "okay";
575 };
576 };
577
578 usb@c5000000 {
579 status = "okay";
580 };
581
582 usb-phy@c5000000 {
583 status = "okay";
584 };
585
586 usb@c5004000 {
587 status = "okay";
588 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
589 GPIO_ACTIVE_LOW>;
590 };
591
592 usb-phy@c5004000 {
593 status = "okay";
594 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
595 GPIO_ACTIVE_LOW>;
596 };
597
598 usb@c5008000 {
599 status = "okay";
600 };
601
602 usb-phy@c5008000 {
603 status = "okay";
604 };
605
606 sdhci@c8000200 {
607 status = "okay";
608 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
609 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
610 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
611 bus-width = <4>;
612 };
613
614 sdhci@c8000600 {
615 status = "okay";
616 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
617 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
618 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
619 bus-width = <8>;
620 };
621
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]622 backlight: backlight {
623 compatible = "pwm-backlight";
624
625 enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
626 power-supply = <&vdd_bl_reg>;
627 pwms = <&pwm 0 5000000>;
628
629 brightness-levels = <0 4 8 16 32 64 128 255>;
630 default-brightness-level = <6>;
631 };
632
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]633 clocks {
634 compatible = "simple-bus";
635 #address-cells = <1>;
636 #size-cells = <0>;
637
638 clk32k_in: clock@0 {
639 compatible = "fixed-clock";
640 reg=<0>;
641 #clock-cells = <0>;
642 clock-frequency = <32768>;
643 };
644 };
645
646 gpio-keys {
647 compatible = "gpio-keys";
648
649 power {
650 label = "Power";
651 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]652 linux,code = <KEY_POWER>;
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]653 gpio-key,wakeup;
654 };
655 };
656
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]657 panel: panel {
658 compatible = "auo,b101aw03", "simple-panel";
659
660 power-supply = <&vdd_pnl_reg>;
661 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
662
663 backlight = <&backlight>;
664 };
665
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]666 regulators {
667 compatible = "simple-bus";
668 #address-cells = <1>;
669 #size-cells = <0>;
670
671 vdd_5v0_reg: regulator@0 {
672 compatible = "regulator-fixed";
673 reg = <0>;
674 regulator-name = "vdd_5v0";
675 regulator-min-microvolt = <5000000>;
676 regulator-max-microvolt = <5000000>;
677 regulator-always-on;
678 };
679
680 regulator@1 {
681 compatible = "regulator-fixed";
682 reg = <1>;
683 regulator-name = "vdd_1v5";
684 regulator-min-microvolt = <1500000>;
685 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]686 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]687 };
688
689 regulator@2 {
690 compatible = "regulator-fixed";
691 reg = <2>;
692 regulator-name = "vdd_1v2";
693 regulator-min-microvolt = <1200000>;
694 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]695 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]696 enable-active-high;
697 };
698
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]699 pci_vdd_reg: regulator@3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]700 compatible = "regulator-fixed";
701 reg = <3>;
702 regulator-name = "vdd_1v05";
703 regulator-min-microvolt = <1050000>;
704 regulator-max-microvolt = <1050000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]705 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]706 enable-active-high;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]707 };
708
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]709 vdd_pnl_reg: regulator@4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]710 compatible = "regulator-fixed";
711 reg = <4>;
712 regulator-name = "vdd_pnl";
713 regulator-min-microvolt = <2800000>;
714 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]715 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]716 enable-active-high;
717 };
718
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]719 vdd_bl_reg: regulator@5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]720 compatible = "regulator-fixed";
721 reg = <5>;
722 regulator-name = "vdd_bl";
723 regulator-min-microvolt = <2800000>;
724 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]725 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]726 enable-active-high;
727 };
Thierry Redingad0acf72014-04-25 17:44:48 +0200[diff] [blame^]728
729 vdd_5v0_hdmi: regulator@6 {
730 compatible = "regulator-fixed";
731 reg = <6>;
732 regulator-name = "VDDIO_HDMI";
733 regulator-min-microvolt = <5000000>;
734 regulator-max-microvolt = <5000000>;
735 gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
736 enable-active-high;
737 vin-supply = <&vdd_5v0_reg>;
738 };
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]739 };
740
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]741 sound {
742 compatible = "nvidia,tegra-audio-wm8903-harmony",
743 "nvidia,tegra-audio-wm8903";
744 nvidia,model = "NVIDIA Tegra Harmony";
745
746 nvidia,audio-routing =
747 "Headphone Jack", "HPOUTR",
748 "Headphone Jack", "HPOUTL",
749 "Int Spk", "ROP",
750 "Int Spk", "RON",
751 "Int Spk", "LOP",
752 "Int Spk", "LON",
753 "Mic Jack", "MICBIAS",
754 "IN1L", "Mic Jack";
755
756 nvidia,i2s-controller = <&tegra_i2s1>;
757 nvidia,audio-codec = <&wm8903>;
758
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]759 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
760 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
761 GPIO_ACTIVE_HIGH>;
762 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
763 GPIO_ACTIVE_HIGH>;
764 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
765 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]766
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]767 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
768 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
769 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]770 clock-names = "pll_a", "pll_a_out0", "mclk";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]771 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]772};