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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
Shreyas NC6277e832016-08-12 12:29:51 +053024#include <uapi/sound/snd_sst_tokens.h>
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010025#include "skl-sst-dsp.h"
26#include "skl-sst-ipc.h"
27#include "skl-topology.h"
28#include "skl.h"
29#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053030#include "../common/sst-dsp.h"
31#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010032
Jeeja KPf7590d42015-10-07 11:31:53 +010033#define SKL_CH_FIXUP_MASK (1 << 0)
34#define SKL_RATE_FIXUP_MASK (1 << 1)
35#define SKL_FMT_FIXUP_MASK (1 << 2)
Shreyas NC6277e832016-08-12 12:29:51 +053036#define SKL_IN_DIR_BIT_MASK BIT(0)
37#define SKL_PIN_COUNT_MASK GENMASK(7, 4)
Jeeja KPf7590d42015-10-07 11:31:53 +010038
Vinod Koula83e3b42016-11-03 17:07:20 +053039void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps)
40{
41 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
42
43 switch (caps) {
44 case SKL_D0I3_NONE:
45 d0i3->non_d0i3++;
46 break;
47
48 case SKL_D0I3_STREAMING:
49 d0i3->streaming++;
50 break;
51
52 case SKL_D0I3_NON_STREAMING:
53 d0i3->non_streaming++;
54 break;
55 }
56}
57
58void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps)
59{
60 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
61
62 switch (caps) {
63 case SKL_D0I3_NONE:
64 d0i3->non_d0i3--;
65 break;
66
67 case SKL_D0I3_STREAMING:
68 d0i3->streaming--;
69 break;
70
71 case SKL_D0I3_NON_STREAMING:
72 d0i3->non_streaming--;
73 break;
74 }
75}
76
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010077/*
78 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
79 * ignore. This helpers checks if the SKL driver handles this widget type
80 */
81static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
82{
83 switch (w->id) {
84 case snd_soc_dapm_dai_link:
85 case snd_soc_dapm_dai_in:
86 case snd_soc_dapm_aif_in:
87 case snd_soc_dapm_aif_out:
88 case snd_soc_dapm_dai_out:
89 case snd_soc_dapm_switch:
90 return false;
91 default:
92 return true;
93 }
94}
95
96/*
97 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053098 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530100static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100101 struct skl_module_cfg *mconfig)
102{
103 struct skl_sst *ctx = skl->skl_sst;
104
105 if (skl->resource.mem + mconfig->pipe->memory_pages >
106 skl->resource.max_mem) {
107 dev_err(ctx->dev,
108 "%s: module_id %d instance %d\n", __func__,
109 mconfig->id.module_id,
110 mconfig->id.instance_id);
111 dev_err(ctx->dev,
112 "exceeds ppl memory available %d mem %d\n",
113 skl->resource.max_mem, skl->resource.mem);
114 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530115 } else {
116 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100117 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530118}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530120/*
121 * Add the mem to the mem pool. This is freed when pipe is deleted.
122 * Note: DSP does actual memory management we only keep track for complete
123 * pool
124 */
125static void skl_tplg_alloc_pipe_mem(struct skl *skl,
126 struct skl_module_cfg *mconfig)
127{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100128 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100129}
130
131/*
132 * Pipeline needs needs DSP CPU resources for computation, this is
133 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
134 *
135 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530136 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100137 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530138
139static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100140 struct skl_module_cfg *mconfig)
141{
142 struct skl_sst *ctx = skl->skl_sst;
143
144 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
145 dev_err(ctx->dev,
146 "%s: module_id %d instance %d\n", __func__,
147 mconfig->id.module_id, mconfig->id.instance_id);
148 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530149 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100150 skl->resource.max_mcps, skl->resource.mcps);
151 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530152 } else {
153 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100154 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530155}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100156
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530157static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
158 struct skl_module_cfg *mconfig)
159{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100160 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100161}
162
163/*
164 * Free the mcps when tearing down
165 */
166static void
167skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
168{
169 skl->resource.mcps -= mconfig->mcps;
170}
171
172/*
173 * Free the memory when tearing down
174 */
175static void
176skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
177{
178 skl->resource.mem -= mconfig->pipe->memory_pages;
179}
180
Jeeja KPf7590d42015-10-07 11:31:53 +0100181
182static void skl_dump_mconfig(struct skl_sst *ctx,
183 struct skl_module_cfg *mcfg)
184{
185 dev_dbg(ctx->dev, "Dumping config\n");
186 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900187 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
188 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
189 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
190 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100191 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900192 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
193 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
194 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
195 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100196}
197
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530198static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
199{
200 int slot_map = 0xFFFFFFFF;
201 int start_slot = 0;
202 int i;
203
204 for (i = 0; i < chs; i++) {
205 /*
206 * For 2 channels with starting slot as 0, slot map will
207 * look like 0xFFFFFF10.
208 */
209 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
210 start_slot++;
211 }
212 fmt->ch_map = slot_map;
213}
214
Jeeja KPf7590d42015-10-07 11:31:53 +0100215static void skl_tplg_update_params(struct skl_module_fmt *fmt,
216 struct skl_pipe_params *params, int fixup)
217{
218 if (fixup & SKL_RATE_FIXUP_MASK)
219 fmt->s_freq = params->s_freq;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530220 if (fixup & SKL_CH_FIXUP_MASK) {
Jeeja KPf7590d42015-10-07 11:31:53 +0100221 fmt->channels = params->ch;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530222 skl_tplg_update_chmap(fmt, fmt->channels);
223 }
Jeeja KP98256f82015-11-23 22:26:25 +0530224 if (fixup & SKL_FMT_FIXUP_MASK) {
225 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
226
227 /*
228 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
229 * container so update bit depth accordingly
230 */
231 switch (fmt->valid_bit_depth) {
232 case SKL_DEPTH_16BIT:
233 fmt->bit_depth = fmt->valid_bit_depth;
234 break;
235
236 default:
237 fmt->bit_depth = SKL_DEPTH_32BIT;
238 break;
239 }
240 }
241
Jeeja KPf7590d42015-10-07 11:31:53 +0100242}
243
244/*
245 * A pipeline may have modules which impact the pcm parameters, like SRC,
246 * channel converter, format converter.
247 * We need to calculate the output params by applying the 'fixup'
248 * Topology will tell driver which type of fixup is to be applied by
249 * supplying the fixup mask, so based on that we calculate the output
250 *
251 * Now In FE the pcm hw_params is source/target format. Same is applicable
252 * for BE with its hw_params invoked.
253 * here based on FE, BE pipeline and direction we calculate the input and
254 * outfix and then apply that for a module
255 */
256static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
257 struct skl_pipe_params *params, bool is_fe)
258{
259 int in_fixup, out_fixup;
260 struct skl_module_fmt *in_fmt, *out_fmt;
261
Hardik T Shah4cd98992015-10-27 09:22:55 +0900262 /* Fixups will be applied to pin 0 only */
263 in_fmt = &m_cfg->in_fmt[0];
264 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100265
266 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
267 if (is_fe) {
268 in_fixup = m_cfg->params_fixup;
269 out_fixup = (~m_cfg->converter) &
270 m_cfg->params_fixup;
271 } else {
272 out_fixup = m_cfg->params_fixup;
273 in_fixup = (~m_cfg->converter) &
274 m_cfg->params_fixup;
275 }
276 } else {
277 if (is_fe) {
278 out_fixup = m_cfg->params_fixup;
279 in_fixup = (~m_cfg->converter) &
280 m_cfg->params_fixup;
281 } else {
282 in_fixup = m_cfg->params_fixup;
283 out_fixup = (~m_cfg->converter) &
284 m_cfg->params_fixup;
285 }
286 }
287
288 skl_tplg_update_params(in_fmt, params, in_fixup);
289 skl_tplg_update_params(out_fmt, params, out_fixup);
290}
291
292/*
293 * A module needs input and output buffers, which are dependent upon pcm
294 * params, so once we have calculate params, we need buffer calculation as
295 * well.
296 */
297static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
298 struct skl_module_cfg *mcfg)
299{
300 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900301 struct skl_module_fmt *in_fmt, *out_fmt;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900302
303 /* Since fixups is applied to pin 0 only, ibs, obs needs
304 * change for pin 0 only
305 */
306 in_fmt = &mcfg->in_fmt[0];
307 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100308
309 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
310 multiplier = 5;
Jeeja KPf7590d42015-10-07 11:31:53 +0100311
Takashi Sakamoto8e15e762017-03-06 16:12:22 +0900312 mcfg->ibs = DIV_ROUND_UP(in_fmt->s_freq, 1000) *
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900313 in_fmt->channels * (in_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530314 multiplier;
315
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900316 mcfg->obs = DIV_ROUND_UP(out_fmt->s_freq, 1000) *
317 out_fmt->channels * (out_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530318 multiplier;
Jeeja KPf7590d42015-10-07 11:31:53 +0100319}
320
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530321static u8 skl_tplg_be_dev_type(int dev_type)
322{
323 int ret;
324
325 switch (dev_type) {
326 case SKL_DEVICE_BT:
327 ret = NHLT_DEVICE_BT;
328 break;
329
330 case SKL_DEVICE_DMIC:
331 ret = NHLT_DEVICE_DMIC;
332 break;
333
334 case SKL_DEVICE_I2S:
335 ret = NHLT_DEVICE_I2S;
336 break;
337
338 default:
339 ret = NHLT_DEVICE_INVALID;
340 break;
341 }
342
343 return ret;
344}
345
Jeeja KP2d1419a2016-02-05 12:19:10 +0530346static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
347 struct skl_sst *ctx)
348{
349 struct skl_module_cfg *m_cfg = w->priv;
350 int link_type, dir;
351 u32 ch, s_freq, s_fmt;
352 struct nhlt_specific_cfg *cfg;
353 struct skl *skl = get_skl_ctx(ctx->dev);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530354 u8 dev_type = skl_tplg_be_dev_type(m_cfg->dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530355
356 /* check if we already have blob */
357 if (m_cfg->formats_config.caps_size > 0)
358 return 0;
359
Jeeja KPc7c6c732016-03-01 07:59:10 +0530360 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530361 switch (m_cfg->dev_type) {
362 case SKL_DEVICE_DMIC:
363 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530364 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530365 s_freq = m_cfg->in_fmt[0].s_freq;
366 s_fmt = m_cfg->in_fmt[0].bit_depth;
367 ch = m_cfg->in_fmt[0].channels;
368 break;
369
370 case SKL_DEVICE_I2S:
371 link_type = NHLT_LINK_SSP;
372 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530373 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530374 s_freq = m_cfg->out_fmt[0].s_freq;
375 s_fmt = m_cfg->out_fmt[0].bit_depth;
376 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530377 } else {
378 dir = SNDRV_PCM_STREAM_CAPTURE;
379 s_freq = m_cfg->in_fmt[0].s_freq;
380 s_fmt = m_cfg->in_fmt[0].bit_depth;
381 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530382 }
383 break;
384
385 default:
386 return -EINVAL;
387 }
388
389 /* update the blob based on virtual bus_id and default params */
390 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530391 s_fmt, ch, s_freq, dir, dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530392 if (cfg) {
393 m_cfg->formats_config.caps_size = cfg->size;
394 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
395 } else {
396 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
397 m_cfg->vbus_id, link_type, dir);
398 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
399 ch, s_freq, s_fmt);
400 return -EIO;
401 }
402
403 return 0;
404}
405
Jeeja KPf7590d42015-10-07 11:31:53 +0100406static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
407 struct skl_sst *ctx)
408{
409 struct skl_module_cfg *m_cfg = w->priv;
410 struct skl_pipe_params *params = m_cfg->pipe->p_params;
411 int p_conn_type = m_cfg->pipe->conn_type;
412 bool is_fe;
413
414 if (!m_cfg->params_fixup)
415 return;
416
417 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
418 w->name);
419
420 skl_dump_mconfig(ctx, m_cfg);
421
422 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
423 is_fe = true;
424 else
425 is_fe = false;
426
427 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
428 skl_tplg_update_buffer_size(ctx, m_cfg);
429
430 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
431 w->name);
432
433 skl_dump_mconfig(ctx, m_cfg);
434}
435
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100436/*
Jeeja KPabb74002015-11-28 15:01:49 +0530437 * some modules can have multiple params set from user control and
438 * need to be set after module is initialized. If set_param flag is
439 * set module params will be done after module is initialised.
440 */
441static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
442 struct skl_sst *ctx)
443{
444 int i, ret;
445 struct skl_module_cfg *mconfig = w->priv;
446 const struct snd_kcontrol_new *k;
447 struct soc_bytes_ext *sb;
448 struct skl_algo_data *bc;
449 struct skl_specific_cfg *sp_cfg;
450
451 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530452 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530453 sp_cfg = &mconfig->formats_config;
454 ret = skl_set_module_params(ctx, sp_cfg->caps,
455 sp_cfg->caps_size,
456 sp_cfg->param_id, mconfig);
457 if (ret < 0)
458 return ret;
459 }
460
461 for (i = 0; i < w->num_kcontrols; i++) {
462 k = &w->kcontrol_news[i];
463 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
464 sb = (void *) k->private_value;
465 bc = (struct skl_algo_data *)sb->dobj.private;
466
Jeeja KP4ced1822015-12-03 23:29:53 +0530467 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530468 ret = skl_set_module_params(ctx,
Dharageswari R0d682102016-07-08 18:15:03 +0530469 (u32 *)bc->params, bc->size,
Jeeja KPabb74002015-11-28 15:01:49 +0530470 bc->param_id, mconfig);
471 if (ret < 0)
472 return ret;
473 }
474 }
475 }
476
477 return 0;
478}
479
480/*
481 * some module param can set from user control and this is required as
482 * when module is initailzed. if module param is required in init it is
483 * identifed by set_param flag. if set_param flag is not set, then this
484 * parameter needs to set as part of module init.
485 */
486static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
487{
488 const struct snd_kcontrol_new *k;
489 struct soc_bytes_ext *sb;
490 struct skl_algo_data *bc;
491 struct skl_module_cfg *mconfig = w->priv;
492 int i;
493
494 for (i = 0; i < w->num_kcontrols; i++) {
495 k = &w->kcontrol_news[i];
496 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
497 sb = (struct soc_bytes_ext *)k->private_value;
498 bc = (struct skl_algo_data *)sb->dobj.private;
499
Jeeja KP4ced1822015-12-03 23:29:53 +0530500 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530501 continue;
502
503 mconfig->formats_config.caps = (u32 *)&bc->params;
Dharageswari R0d682102016-07-08 18:15:03 +0530504 mconfig->formats_config.caps_size = bc->size;
Jeeja KPabb74002015-11-28 15:01:49 +0530505
506 break;
507 }
508 }
509
510 return 0;
511}
512
Jeeja KPbb704a732016-12-08 13:41:14 +0530513static int skl_tplg_module_prepare(struct skl_sst *ctx, struct skl_pipe *pipe,
514 struct snd_soc_dapm_widget *w, struct skl_module_cfg *mcfg)
515{
516 switch (mcfg->dev_type) {
517 case SKL_DEVICE_HDAHOST:
518 return skl_pcm_host_dma_prepare(ctx->dev, pipe->p_params);
519
520 case SKL_DEVICE_HDALINK:
521 return skl_pcm_link_dma_prepare(ctx->dev, pipe->p_params);
522 }
523
524 return 0;
525}
526
Jeeja KPabb74002015-11-28 15:01:49 +0530527/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100528 * Inside a pipe instance, we can have various modules. These modules need
529 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
530 * skl_init_module() routine, so invoke that for all modules in a pipeline
531 */
532static int
533skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
534{
535 struct skl_pipe_module *w_module;
536 struct snd_soc_dapm_widget *w;
537 struct skl_module_cfg *mconfig;
538 struct skl_sst *ctx = skl->skl_sst;
539 int ret = 0;
540
541 list_for_each_entry(w_module, &pipe->w_list, node) {
542 w = w_module->w;
543 mconfig = w->priv;
544
Vinod Koulb7c50552016-07-26 18:06:40 +0530545 /* check if module ids are populated */
546 if (mconfig->id.module_id < 0) {
Vinod Koula657ae72016-08-10 09:40:50 +0530547 dev_err(skl->skl_sst->dev,
548 "module %pUL id not populated\n",
549 (uuid_le *)mconfig->guid);
550 return -EIO;
Vinod Koulb7c50552016-07-26 18:06:40 +0530551 }
552
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100553 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530554 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100555 return -ENOMEM;
556
Dharageswari R6c5768b2015-12-03 23:29:50 +0530557 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
558 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
559 mconfig->id.module_id, mconfig->guid);
560 if (ret < 0)
561 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530562
563 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530564 }
565
Jeeja KPbb704a732016-12-08 13:41:14 +0530566 /* prepare the DMA if the module is gateway cpr */
567 ret = skl_tplg_module_prepare(ctx, pipe, w, mconfig);
568 if (ret < 0)
569 return ret;
570
Jeeja KP2d1419a2016-02-05 12:19:10 +0530571 /* update blob if blob is null for be with default value */
572 skl_tplg_update_be_blob(w, ctx);
573
Jeeja KPf7590d42015-10-07 11:31:53 +0100574 /*
575 * apply fix/conversion to module params based on
576 * FE/BE params
577 */
578 skl_tplg_update_module_params(w, ctx);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530579 mconfig->id.pvt_id = skl_get_pvt_id(ctx, mconfig);
580 if (mconfig->id.pvt_id < 0)
581 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530582 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530583 ret = skl_init_module(ctx, mconfig);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530584 if (ret < 0) {
585 skl_put_pvt_id(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100586 return ret;
Dharageswari Ref2a3522016-09-22 14:00:38 +0530587 }
Dharageswari R260eb732016-06-03 18:29:38 +0530588 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPabb74002015-11-28 15:01:49 +0530589 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100590 if (ret < 0)
591 return ret;
592 }
593
594 return 0;
595}
Vinod Kould93f8e52015-10-07 11:31:54 +0100596
Dharageswari R6c5768b2015-12-03 23:29:50 +0530597static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
598 struct skl_pipe *pipe)
599{
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530600 int ret;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530601 struct skl_pipe_module *w_module = NULL;
602 struct skl_module_cfg *mconfig = NULL;
603
604 list_for_each_entry(w_module, &pipe->w_list, node) {
605 mconfig = w_module->w->priv;
606
Jeeja KPd6436782016-03-28 22:11:30 +0530607 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530608 mconfig->m_state > SKL_MODULE_UNINIT) {
609 ret = ctx->dsp->fw_ops.unload_mod(ctx->dsp,
Dharageswari R6c5768b2015-12-03 23:29:50 +0530610 mconfig->id.module_id);
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530611 if (ret < 0)
612 return -EIO;
613 }
Dharageswari Ref2a3522016-09-22 14:00:38 +0530614 skl_put_pvt_id(ctx, mconfig);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530615 }
616
617 /* no modules to unload in this path, so return */
618 return 0;
619}
620
Vinod Kould93f8e52015-10-07 11:31:54 +0100621/*
622 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
623 * need create the pipeline. So we do following:
624 * - check the resources
625 * - Create the pipeline
626 * - Initialize the modules in pipeline
627 * - finally bind all modules together
628 */
629static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
630 struct skl *skl)
631{
632 int ret;
633 struct skl_module_cfg *mconfig = w->priv;
634 struct skl_pipe_module *w_module;
635 struct skl_pipe *s_pipe = mconfig->pipe;
636 struct skl_module_cfg *src_module = NULL, *dst_module;
637 struct skl_sst *ctx = skl->skl_sst;
638
639 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530640 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100641 return -EBUSY;
642
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530643 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100644 return -ENOMEM;
645
646 /*
647 * Create a list of modules for pipe.
648 * This list contains modules from source to sink
649 */
650 ret = skl_create_pipeline(ctx, mconfig->pipe);
651 if (ret < 0)
652 return ret;
653
Dharageswari R260eb732016-06-03 18:29:38 +0530654 skl_tplg_alloc_pipe_mem(skl, mconfig);
655 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100656
657 /* Init all pipe modules from source to sink */
658 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
659 if (ret < 0)
660 return ret;
661
662 /* Bind modules from source to sink */
663 list_for_each_entry(w_module, &s_pipe->w_list, node) {
664 dst_module = w_module->w->priv;
665
666 if (src_module == NULL) {
667 src_module = dst_module;
668 continue;
669 }
670
671 ret = skl_bind_modules(ctx, src_module, dst_module);
672 if (ret < 0)
673 return ret;
674
675 src_module = dst_module;
676 }
677
678 return 0;
679}
680
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530681static int skl_fill_sink_instance_id(struct skl_sst *ctx,
682 struct skl_algo_data *alg_data)
683{
684 struct skl_kpb_params *params = (struct skl_kpb_params *)alg_data->params;
685 struct skl_mod_inst_map *inst;
686 int i, pvt_id;
687
688 inst = params->map;
689
690 for (i = 0; i < params->num_modules; i++) {
691 pvt_id = skl_get_pvt_instance_id_map(ctx,
692 inst->mod_id, inst->inst_id);
693 if (pvt_id < 0)
694 return -EINVAL;
695 inst->inst_id = pvt_id;
696 inst++;
697 }
698 return 0;
699}
700
Jeeja KPcc6a4042016-02-05 12:19:08 +0530701/*
702 * Some modules require params to be set after the module is bound to
703 * all pins connected.
704 *
705 * The module provider initializes set_param flag for such modules and we
706 * send params after binding
707 */
708static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
709 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
710{
711 int i, ret;
712 struct skl_module_cfg *mconfig = w->priv;
713 const struct snd_kcontrol_new *k;
714 struct soc_bytes_ext *sb;
715 struct skl_algo_data *bc;
716 struct skl_specific_cfg *sp_cfg;
717
718 /*
719 * check all out/in pins are in bind state.
720 * if so set the module param
721 */
722 for (i = 0; i < mcfg->max_out_queue; i++) {
723 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
724 return 0;
725 }
726
727 for (i = 0; i < mcfg->max_in_queue; i++) {
728 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
729 return 0;
730 }
731
732 if (mconfig->formats_config.caps_size > 0 &&
733 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
734 sp_cfg = &mconfig->formats_config;
735 ret = skl_set_module_params(ctx, sp_cfg->caps,
736 sp_cfg->caps_size,
737 sp_cfg->param_id, mconfig);
738 if (ret < 0)
739 return ret;
740 }
741
742 for (i = 0; i < w->num_kcontrols; i++) {
743 k = &w->kcontrol_news[i];
744 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
745 sb = (void *) k->private_value;
746 bc = (struct skl_algo_data *)sb->dobj.private;
747
748 if (bc->set_params == SKL_PARAM_BIND) {
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530749 if (mconfig->m_type == SKL_MODULE_TYPE_KPB)
750 skl_fill_sink_instance_id(ctx, bc);
Jeeja KPcc6a4042016-02-05 12:19:08 +0530751 ret = skl_set_module_params(ctx,
752 (u32 *)bc->params, bc->max,
753 bc->param_id, mconfig);
754 if (ret < 0)
755 return ret;
756 }
757 }
758 }
759
760 return 0;
761}
762
Jeeja KP8724ff12015-10-27 09:22:52 +0900763static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
764 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530765 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900766 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100767{
768 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530769 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900770 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100771 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900772 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100773
Jeeja KP8724ff12015-10-27 09:22:52 +0900774 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100775 if (!p->connect)
776 continue;
777
778 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
779 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
780
Jeeja KP0ed95d72015-11-13 19:22:11 +0530781 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530782
783 if (!is_skl_dsp_widget_type(p->sink))
784 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
785
Vinod Kould93f8e52015-10-07 11:31:54 +0100786 /*
787 * here we will check widgets in sink pipelines, so that
788 * can be any widgets type and we are only interested if
789 * they are ones used for SKL so check that first
790 */
791 if ((p->sink->priv != NULL) &&
792 is_skl_dsp_widget_type(p->sink)) {
793
794 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100795 sink_mconfig = sink->priv;
796
Jeeja KPcc6a4042016-02-05 12:19:08 +0530797 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
798 sink_mconfig->m_state == SKL_MODULE_UNINIT)
799 continue;
800
Vinod Kould93f8e52015-10-07 11:31:54 +0100801 /* Bind source to sink, mixin is always source */
802 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
803 if (ret)
804 return ret;
805
Jeeja KPcc6a4042016-02-05 12:19:08 +0530806 /* set module params after bind */
807 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
808 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
809
Vinod Kould93f8e52015-10-07 11:31:54 +0100810 /* Start sinks pipe first */
811 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900812 if (sink_mconfig->pipe->conn_type !=
813 SKL_PIPE_CONN_TYPE_FE)
814 ret = skl_run_pipe(ctx,
815 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100816 if (ret)
817 return ret;
818 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100819 }
820 }
821
Jeeja KP8724ff12015-10-27 09:22:52 +0900822 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530823 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900824
825 return 0;
826}
827
Vinod Kould93f8e52015-10-07 11:31:54 +0100828/*
829 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
830 * we need to do following:
831 * - Bind to sink pipeline
832 * Since the sink pipes can be running and we don't get mixer event on
833 * connect for already running mixer, we need to find the sink pipes
834 * here and bind to them. This way dynamic connect works.
835 * - Start sink pipeline, if not running
836 * - Then run current pipe
837 */
838static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900839 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100840{
Jeeja KP8724ff12015-10-27 09:22:52 +0900841 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100842 struct skl_sst *ctx = skl->skl_sst;
843 int ret = 0;
844
Jeeja KP8724ff12015-10-27 09:22:52 +0900845 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100846
847 /*
848 * find which sink it is connected to, bind with the sink,
849 * if sink is not started, start sink pipe first, then start
850 * this pipe
851 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530852 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100853 if (ret)
854 return ret;
855
Vinod Kould93f8e52015-10-07 11:31:54 +0100856 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900857 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
858 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100859
860 return 0;
861}
862
Jeeja KP8724ff12015-10-27 09:22:52 +0900863static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
864 struct snd_soc_dapm_widget *w, struct skl *skl)
865{
866 struct snd_soc_dapm_path *p;
867 struct snd_soc_dapm_widget *src_w = NULL;
868 struct skl_sst *ctx = skl->skl_sst;
869
870 snd_soc_dapm_widget_for_each_source_path(w, p) {
871 src_w = p->source;
872 if (!p->connect)
873 continue;
874
875 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
876 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
877
878 /*
879 * here we will check widgets in sink pipelines, so that can
880 * be any widgets type and we are only interested if they are
881 * ones used for SKL so check that first
882 */
883 if ((p->source->priv != NULL) &&
884 is_skl_dsp_widget_type(p->source)) {
885 return p->source;
886 }
887 }
888
889 if (src_w != NULL)
890 return skl_get_src_dsp_widget(src_w, skl);
891
892 return NULL;
893}
894
Vinod Kould93f8e52015-10-07 11:31:54 +0100895/*
896 * in the Post-PMU event of mixer we need to do following:
897 * - Check if this pipe is running
898 * - if not, then
899 * - bind this pipeline to its source pipeline
900 * if source pipe is already running, this means it is a dynamic
901 * connection and we need to bind only to that pipe
902 * - start this pipeline
903 */
904static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
905 struct skl *skl)
906{
907 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100908 struct snd_soc_dapm_widget *source, *sink;
909 struct skl_module_cfg *src_mconfig, *sink_mconfig;
910 struct skl_sst *ctx = skl->skl_sst;
911 int src_pipe_started = 0;
912
913 sink = w;
914 sink_mconfig = sink->priv;
915
916 /*
917 * If source pipe is already started, that means source is driving
918 * one more sink before this sink got connected, Since source is
919 * started, bind this sink to source and start this pipe.
920 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900921 source = skl_get_src_dsp_widget(w, skl);
922 if (source != NULL) {
923 src_mconfig = source->priv;
924 sink_mconfig = sink->priv;
925 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100926
927 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900928 * check pipe state, then no need to bind or start the
929 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100930 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900931 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
932 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100933 }
934
935 if (src_pipe_started) {
936 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
937 if (ret)
938 return ret;
939
Jeeja KPcc6a4042016-02-05 12:19:08 +0530940 /* set module params after bind */
941 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
942 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
943
Jeeja KPd1730c32015-10-27 09:22:53 +0900944 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
945 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100946 }
947
948 return ret;
949}
950
951/*
952 * in the Pre-PMD event of mixer we need to do following:
953 * - Stop the pipe
954 * - find the source connections and remove that from dapm_path_list
955 * - unbind with source pipelines if still connected
956 */
957static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
958 struct skl *skl)
959{
Vinod Kould93f8e52015-10-07 11:31:54 +0100960 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900961 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100962 struct skl_sst *ctx = skl->skl_sst;
963
Jeeja KPce1b5552015-10-27 09:22:51 +0900964 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100965
966 /* Stop the pipe */
967 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
968 if (ret)
969 return ret;
970
Jeeja KPce1b5552015-10-27 09:22:51 +0900971 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
972 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
973 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
974 if (!src_mconfig)
975 continue;
Vinod Kould93f8e52015-10-07 11:31:54 +0100976
Jeeja KPce1b5552015-10-27 09:22:51 +0900977 ret = skl_unbind_modules(ctx,
978 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100979 }
980 }
981
Vinod Kould93f8e52015-10-07 11:31:54 +0100982 return ret;
983}
984
985/*
986 * in the Post-PMD event of mixer we need to do following:
987 * - Free the mcps used
988 * - Free the mem used
989 * - Unbind the modules within the pipeline
990 * - Delete the pipeline (modules are not required to be explicitly
991 * deleted, pipeline delete is enough here
992 */
993static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
994 struct skl *skl)
995{
996 struct skl_module_cfg *mconfig = w->priv;
997 struct skl_pipe_module *w_module;
998 struct skl_module_cfg *src_module = NULL, *dst_module;
999 struct skl_sst *ctx = skl->skl_sst;
1000 struct skl_pipe *s_pipe = mconfig->pipe;
Vinod Kould93f8e52015-10-07 11:31:54 +01001001
Dharageswari R260eb732016-06-03 18:29:38 +05301002 if (s_pipe->state == SKL_PIPE_INVALID)
1003 return -EINVAL;
1004
Vinod Kould93f8e52015-10-07 11:31:54 +01001005 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +05301006 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001007
1008 list_for_each_entry(w_module, &s_pipe->w_list, node) {
1009 dst_module = w_module->w->priv;
1010
Dharageswari R260eb732016-06-03 18:29:38 +05301011 if (mconfig->m_state >= SKL_MODULE_INIT_DONE)
1012 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001013 if (src_module == NULL) {
1014 src_module = dst_module;
1015 continue;
1016 }
1017
Guneshwor Singh7ca42f52016-02-03 17:59:46 +05301018 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001019 src_module = dst_module;
1020 }
1021
Vinod Koul547cafa2016-12-08 23:01:24 +05301022 skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001023
Dharageswari R6c5768b2015-12-03 23:29:50 +05301024 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001025}
1026
1027/*
1028 * in the Post-PMD event of PGA we need to do following:
1029 * - Free the mcps used
1030 * - Stop the pipeline
1031 * - In source pipe is connected, unbind with source pipelines
1032 */
1033static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1034 struct skl *skl)
1035{
Vinod Kould93f8e52015-10-07 11:31:54 +01001036 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +09001037 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +01001038 struct skl_sst *ctx = skl->skl_sst;
1039
Jeeja KPce1b5552015-10-27 09:22:51 +09001040 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +01001041
Vinod Kould93f8e52015-10-07 11:31:54 +01001042 /* Stop the pipe since this is a mixin module */
1043 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
1044 if (ret)
1045 return ret;
1046
Jeeja KPce1b5552015-10-27 09:22:51 +09001047 for (i = 0; i < src_mconfig->max_out_queue; i++) {
1048 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
1049 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
1050 if (!sink_mconfig)
1051 continue;
1052 /*
1053 * This is a connecter and if path is found that means
1054 * unbind between source and sink has not happened yet
1055 */
Jeeja KPce1b5552015-10-27 09:22:51 +09001056 ret = skl_unbind_modules(ctx, src_mconfig,
1057 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001058 }
1059 }
1060
Vinod Kould93f8e52015-10-07 11:31:54 +01001061 return ret;
1062}
1063
1064/*
1065 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
1066 * mixer is not required then it is treated as static mixer aka vmixer with
1067 * a hard path to source module
1068 * So we don't need to check if source is started or not as hard path puts
1069 * dependency on each other
1070 */
1071static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
1072 struct snd_kcontrol *k, int event)
1073{
1074 struct snd_soc_dapm_context *dapm = w->dapm;
1075 struct skl *skl = get_skl_ctx(dapm->dev);
1076
1077 switch (event) {
1078 case SND_SOC_DAPM_PRE_PMU:
1079 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1080
Jeeja KPde1fedf2016-02-03 17:59:52 +05301081 case SND_SOC_DAPM_POST_PMU:
1082 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1083
1084 case SND_SOC_DAPM_PRE_PMD:
1085 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1086
Vinod Kould93f8e52015-10-07 11:31:54 +01001087 case SND_SOC_DAPM_POST_PMD:
1088 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1089 }
1090
1091 return 0;
1092}
1093
1094/*
1095 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1096 * second one is required that is created as another pipe entity.
1097 * The mixer is responsible for pipe management and represent a pipeline
1098 * instance
1099 */
1100static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1101 struct snd_kcontrol *k, int event)
1102{
1103 struct snd_soc_dapm_context *dapm = w->dapm;
1104 struct skl *skl = get_skl_ctx(dapm->dev);
1105
1106 switch (event) {
1107 case SND_SOC_DAPM_PRE_PMU:
1108 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1109
1110 case SND_SOC_DAPM_POST_PMU:
1111 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1112
1113 case SND_SOC_DAPM_PRE_PMD:
1114 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1115
1116 case SND_SOC_DAPM_POST_PMD:
1117 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1118 }
1119
1120 return 0;
1121}
1122
1123/*
1124 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1125 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1126 * the sink when it is running (two FE to one BE or one FE to two BE)
1127 * scenarios
1128 */
1129static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1130 struct snd_kcontrol *k, int event)
1131
1132{
1133 struct snd_soc_dapm_context *dapm = w->dapm;
1134 struct skl *skl = get_skl_ctx(dapm->dev);
1135
1136 switch (event) {
1137 case SND_SOC_DAPM_PRE_PMU:
1138 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1139
1140 case SND_SOC_DAPM_POST_PMD:
1141 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1142 }
1143
1144 return 0;
1145}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001146
Jeeja KP140adfb2015-11-28 15:01:50 +05301147static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1148 unsigned int __user *data, unsigned int size)
1149{
1150 struct soc_bytes_ext *sb =
1151 (struct soc_bytes_ext *)kcontrol->private_value;
1152 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301153 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1154 struct skl_module_cfg *mconfig = w->priv;
1155 struct skl *skl = get_skl_ctx(w->dapm->dev);
1156
1157 if (w->power)
1158 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
Dharageswari R0d682102016-07-08 18:15:03 +05301159 bc->size, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301160
Vinod Koul41556f62016-02-03 17:59:44 +05301161 /* decrement size for TLV header */
1162 size -= 2 * sizeof(u32);
1163
1164 /* check size as we don't want to send kernel data */
1165 if (size > bc->max)
1166 size = bc->max;
1167
Jeeja KP140adfb2015-11-28 15:01:50 +05301168 if (bc->params) {
1169 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1170 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001171 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301172 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001173 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301174 return -EFAULT;
1175 }
1176
1177 return 0;
1178}
1179
1180#define SKL_PARAM_VENDOR_ID 0xff
1181
1182static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1183 const unsigned int __user *data, unsigned int size)
1184{
1185 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1186 struct skl_module_cfg *mconfig = w->priv;
1187 struct soc_bytes_ext *sb =
1188 (struct soc_bytes_ext *)kcontrol->private_value;
1189 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1190 struct skl *skl = get_skl_ctx(w->dapm->dev);
1191
1192 if (ac->params) {
Dharageswari R0d682102016-07-08 18:15:03 +05301193 if (size > ac->max)
1194 return -EINVAL;
1195
1196 ac->size = size;
Jeeja KP140adfb2015-11-28 15:01:50 +05301197 /*
1198 * if the param_is is of type Vendor, firmware expects actual
1199 * parameter id and size from the control.
1200 */
1201 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1202 if (copy_from_user(ac->params, data, size))
1203 return -EFAULT;
1204 } else {
1205 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301206 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301207 return -EFAULT;
1208 }
1209
1210 if (w->power)
1211 return skl_set_module_params(skl->skl_sst,
Dharageswari R0d682102016-07-08 18:15:03 +05301212 (u32 *)ac->params, ac->size,
Jeeja KP140adfb2015-11-28 15:01:50 +05301213 ac->param_id, mconfig);
1214 }
1215
1216 return 0;
1217}
1218
Vinod Koulcfb0a872015-10-07 11:31:55 +01001219/*
Jeeja KP8871dcb2016-06-03 18:29:42 +05301220 * Fill the dma id for host and link. In case of passthrough
1221 * pipeline, this will both host and link in the same
1222 * pipeline, so need to copy the link and host based on dev_type
1223 */
1224static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
1225 struct skl_pipe_params *params)
1226{
1227 struct skl_pipe *pipe = mcfg->pipe;
1228
1229 if (pipe->passthru) {
1230 switch (mcfg->dev_type) {
1231 case SKL_DEVICE_HDALINK:
1232 pipe->p_params->link_dma_id = params->link_dma_id;
Jeeja KP12c3be02016-12-08 13:41:12 +05301233 pipe->p_params->link_index = params->link_index;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301234 break;
1235
1236 case SKL_DEVICE_HDAHOST:
1237 pipe->p_params->host_dma_id = params->host_dma_id;
1238 break;
1239
1240 default:
1241 break;
1242 }
1243 pipe->p_params->s_fmt = params->s_fmt;
1244 pipe->p_params->ch = params->ch;
1245 pipe->p_params->s_freq = params->s_freq;
1246 pipe->p_params->stream = params->stream;
Jeeja KP12c3be02016-12-08 13:41:12 +05301247 pipe->p_params->format = params->format;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301248
1249 } else {
1250 memcpy(pipe->p_params, params, sizeof(*params));
1251 }
1252}
1253
1254/*
Vinod Koulcfb0a872015-10-07 11:31:55 +01001255 * The FE params are passed by hw_params of the DAI.
1256 * On hw_params, the params are stored in Gateway module of the FE and we
1257 * need to calculate the format in DSP module configuration, that
1258 * conversion is done here
1259 */
1260int skl_tplg_update_pipe_params(struct device *dev,
1261 struct skl_module_cfg *mconfig,
1262 struct skl_pipe_params *params)
1263{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001264 struct skl_module_fmt *format = NULL;
1265
Jeeja KP8871dcb2016-06-03 18:29:42 +05301266 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001267
1268 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001269 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001270 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001271 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001272
1273 /* set the hw_params */
1274 format->s_freq = params->s_freq;
1275 format->channels = params->ch;
1276 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1277
1278 /*
1279 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1280 * container so update bit depth accordingly
1281 */
1282 switch (format->valid_bit_depth) {
1283 case SKL_DEPTH_16BIT:
1284 format->bit_depth = format->valid_bit_depth;
1285 break;
1286
1287 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001288 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001289 format->bit_depth = SKL_DEPTH_32BIT;
1290 break;
1291
1292 default:
1293 dev_err(dev, "Invalid bit depth %x for pipe\n",
1294 format->valid_bit_depth);
1295 return -EINVAL;
1296 }
1297
1298 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1299 mconfig->ibs = (format->s_freq / 1000) *
1300 (format->channels) *
1301 (format->bit_depth >> 3);
1302 } else {
1303 mconfig->obs = (format->s_freq / 1000) *
1304 (format->channels) *
1305 (format->bit_depth >> 3);
1306 }
1307
1308 return 0;
1309}
1310
1311/*
1312 * Query the module config for the FE DAI
1313 * This is used to find the hw_params set for that DAI and apply to FE
1314 * pipeline
1315 */
1316struct skl_module_cfg *
1317skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1318{
1319 struct snd_soc_dapm_widget *w;
1320 struct snd_soc_dapm_path *p = NULL;
1321
1322 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1323 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301324 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001325 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001326 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001327 continue;
1328
1329 if (p->sink->priv) {
1330 dev_dbg(dai->dev, "set params for %s\n",
1331 p->sink->name);
1332 return p->sink->priv;
1333 }
1334 }
1335 } else {
1336 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301337 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001338 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001339 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001340 continue;
1341
1342 if (p->source->priv) {
1343 dev_dbg(dai->dev, "set params for %s\n",
1344 p->source->name);
1345 return p->source->priv;
1346 }
1347 }
1348 }
1349
1350 return NULL;
1351}
1352
Dharageswari.R718a42b2016-02-05 12:19:06 +05301353static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1354 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1355{
1356 struct snd_soc_dapm_path *p;
1357 struct skl_module_cfg *mconfig = NULL;
1358
1359 snd_soc_dapm_widget_for_each_source_path(w, p) {
1360 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1361 if (p->connect &&
1362 (p->sink->id == snd_soc_dapm_aif_out) &&
1363 p->source->priv) {
1364 mconfig = p->source->priv;
1365 return mconfig;
1366 }
1367 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1368 if (mconfig)
1369 return mconfig;
1370 }
1371 }
1372 return mconfig;
1373}
1374
1375static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1376 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1377{
1378 struct snd_soc_dapm_path *p;
1379 struct skl_module_cfg *mconfig = NULL;
1380
1381 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1382 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1383 if (p->connect &&
1384 (p->source->id == snd_soc_dapm_aif_in) &&
1385 p->sink->priv) {
1386 mconfig = p->sink->priv;
1387 return mconfig;
1388 }
1389 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1390 if (mconfig)
1391 return mconfig;
1392 }
1393 }
1394 return mconfig;
1395}
1396
1397struct skl_module_cfg *
1398skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1399{
1400 struct snd_soc_dapm_widget *w;
1401 struct skl_module_cfg *mconfig;
1402
1403 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1404 w = dai->playback_widget;
1405 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1406 } else {
1407 w = dai->capture_widget;
1408 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1409 }
1410 return mconfig;
1411}
1412
Vinod Koulcfb0a872015-10-07 11:31:55 +01001413static u8 skl_tplg_be_link_type(int dev_type)
1414{
1415 int ret;
1416
1417 switch (dev_type) {
1418 case SKL_DEVICE_BT:
1419 ret = NHLT_LINK_SSP;
1420 break;
1421
1422 case SKL_DEVICE_DMIC:
1423 ret = NHLT_LINK_DMIC;
1424 break;
1425
1426 case SKL_DEVICE_I2S:
1427 ret = NHLT_LINK_SSP;
1428 break;
1429
1430 case SKL_DEVICE_HDALINK:
1431 ret = NHLT_LINK_HDA;
1432 break;
1433
1434 default:
1435 ret = NHLT_LINK_INVALID;
1436 break;
1437 }
1438
1439 return ret;
1440}
1441
1442/*
1443 * Fill the BE gateway parameters
1444 * The BE gateway expects a blob of parameters which are kept in the ACPI
1445 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1446 * The port can have multiple settings so pick based on the PCM
1447 * parameters
1448 */
1449static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1450 struct skl_module_cfg *mconfig,
1451 struct skl_pipe_params *params)
1452{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001453 struct nhlt_specific_cfg *cfg;
1454 struct skl *skl = get_skl_ctx(dai->dev);
1455 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301456 u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001457
Jeeja KP8871dcb2016-06-03 18:29:42 +05301458 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001459
Jeeja KPb30c2752015-10-27 09:22:48 +09001460 if (link_type == NHLT_LINK_HDA)
1461 return 0;
1462
Vinod Koulcfb0a872015-10-07 11:31:55 +01001463 /* update the blob based on virtual bus_id*/
1464 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1465 params->s_fmt, params->ch,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301466 params->s_freq, params->stream,
1467 dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001468 if (cfg) {
1469 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301470 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001471 } else {
1472 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1473 mconfig->vbus_id, link_type,
1474 params->stream);
1475 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1476 params->ch, params->s_freq, params->s_fmt);
1477 return -EINVAL;
1478 }
1479
1480 return 0;
1481}
1482
1483static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1484 struct snd_soc_dapm_widget *w,
1485 struct skl_pipe_params *params)
1486{
1487 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301488 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001489
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301490 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001491 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1492 p->source->priv) {
1493
Jeeja KP9a03cb42015-10-27 09:22:54 +09001494 ret = skl_tplg_be_fill_pipe_params(dai,
1495 p->source->priv, params);
1496 if (ret < 0)
1497 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001498 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001499 ret = skl_tplg_be_set_src_pipe_params(dai,
1500 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301501 if (ret < 0)
1502 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001503 }
1504 }
1505
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301506 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001507}
1508
1509static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1510 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1511{
1512 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301513 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001514
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301515 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001516 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1517 p->sink->priv) {
1518
Jeeja KP9a03cb42015-10-27 09:22:54 +09001519 ret = skl_tplg_be_fill_pipe_params(dai,
1520 p->sink->priv, params);
1521 if (ret < 0)
1522 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001523 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301524 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001525 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301526 if (ret < 0)
1527 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001528 }
1529 }
1530
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301531 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001532}
1533
1534/*
1535 * BE hw_params can be a source parameters (capture) or sink parameters
1536 * (playback). Based on sink and source we need to either find the source
1537 * list or the sink list and set the pipeline parameters
1538 */
1539int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1540 struct skl_pipe_params *params)
1541{
1542 struct snd_soc_dapm_widget *w;
1543
1544 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1545 w = dai->playback_widget;
1546
1547 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1548
1549 } else {
1550 w = dai->capture_widget;
1551
1552 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1553 }
1554
1555 return 0;
1556}
Vinod Koul3af36702015-10-07 11:31:56 +01001557
1558static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1559 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1560 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1561 {SKL_PGA_EVENT, skl_tplg_pga_event},
1562};
1563
Jeeja KP140adfb2015-11-28 15:01:50 +05301564static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1565 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1566 skl_tplg_tlv_control_set},
1567};
1568
Shreyas NC6277e832016-08-12 12:29:51 +05301569static int skl_tplg_fill_pipe_tkn(struct device *dev,
1570 struct skl_pipe *pipe, u32 tkn,
1571 u32 tkn_val)
Vinod Koul3af36702015-10-07 11:31:56 +01001572{
Vinod Koul3af36702015-10-07 11:31:56 +01001573
Shreyas NC6277e832016-08-12 12:29:51 +05301574 switch (tkn) {
1575 case SKL_TKN_U32_PIPE_CONN_TYPE:
1576 pipe->conn_type = tkn_val;
1577 break;
1578
1579 case SKL_TKN_U32_PIPE_PRIORITY:
1580 pipe->pipe_priority = tkn_val;
1581 break;
1582
1583 case SKL_TKN_U32_PIPE_MEM_PGS:
1584 pipe->memory_pages = tkn_val;
1585 break;
1586
Vinod Koul8a0cb232016-11-03 17:07:18 +05301587 case SKL_TKN_U32_PMODE:
1588 pipe->lp_mode = tkn_val;
1589 break;
1590
Shreyas NC6277e832016-08-12 12:29:51 +05301591 default:
1592 dev_err(dev, "Token not handled %d\n", tkn);
1593 return -EINVAL;
Vinod Koul3af36702015-10-07 11:31:56 +01001594 }
Shreyas NC6277e832016-08-12 12:29:51 +05301595
1596 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001597}
1598
1599/*
Shreyas NC6277e832016-08-12 12:29:51 +05301600 * Add pipeline by parsing the relevant tokens
1601 * Return an existing pipe if the pipe already exists.
Vinod Koul3af36702015-10-07 11:31:56 +01001602 */
Shreyas NC6277e832016-08-12 12:29:51 +05301603static int skl_tplg_add_pipe(struct device *dev,
1604 struct skl_module_cfg *mconfig, struct skl *skl,
1605 struct snd_soc_tplg_vendor_value_elem *tkn_elem)
Vinod Koul3af36702015-10-07 11:31:56 +01001606{
1607 struct skl_pipeline *ppl;
1608 struct skl_pipe *pipe;
1609 struct skl_pipe_params *params;
1610
1611 list_for_each_entry(ppl, &skl->ppl_list, node) {
Shreyas NC6277e832016-08-12 12:29:51 +05301612 if (ppl->pipe->ppl_id == tkn_elem->value) {
1613 mconfig->pipe = ppl->pipe;
1614 return EEXIST;
1615 }
Vinod Koul3af36702015-10-07 11:31:56 +01001616 }
1617
1618 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1619 if (!ppl)
Shreyas NC6277e832016-08-12 12:29:51 +05301620 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001621
1622 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1623 if (!pipe)
Shreyas NC6277e832016-08-12 12:29:51 +05301624 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001625
1626 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1627 if (!params)
Shreyas NC6277e832016-08-12 12:29:51 +05301628 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001629
Vinod Koul3af36702015-10-07 11:31:56 +01001630 pipe->p_params = params;
Shreyas NC6277e832016-08-12 12:29:51 +05301631 pipe->ppl_id = tkn_elem->value;
Vinod Koul3af36702015-10-07 11:31:56 +01001632 INIT_LIST_HEAD(&pipe->w_list);
1633
1634 ppl->pipe = pipe;
1635 list_add(&ppl->node, &skl->ppl_list);
1636
Shreyas NC6277e832016-08-12 12:29:51 +05301637 mconfig->pipe = pipe;
1638 mconfig->pipe->state = SKL_PIPE_INVALID;
1639
1640 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001641}
1642
Shreyas NC6277e832016-08-12 12:29:51 +05301643static int skl_tplg_fill_pin(struct device *dev, u32 tkn,
1644 struct skl_module_pin *m_pin,
1645 int pin_index, u32 value)
1646{
1647 switch (tkn) {
1648 case SKL_TKN_U32_PIN_MOD_ID:
1649 m_pin[pin_index].id.module_id = value;
1650 break;
1651
1652 case SKL_TKN_U32_PIN_INST_ID:
1653 m_pin[pin_index].id.instance_id = value;
1654 break;
1655
1656 default:
1657 dev_err(dev, "%d Not a pin token\n", value);
1658 return -EINVAL;
1659 }
1660
1661 return 0;
1662}
1663
1664/*
1665 * Parse for pin config specific tokens to fill up the
1666 * module private data
1667 */
1668static int skl_tplg_fill_pins_info(struct device *dev,
1669 struct skl_module_cfg *mconfig,
1670 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1671 int dir, int pin_count)
1672{
1673 int ret;
1674 struct skl_module_pin *m_pin;
1675
1676 switch (dir) {
1677 case SKL_DIR_IN:
1678 m_pin = mconfig->m_in_pin;
1679 break;
1680
1681 case SKL_DIR_OUT:
1682 m_pin = mconfig->m_out_pin;
1683 break;
1684
1685 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001686 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301687 return -EINVAL;
1688 }
1689
1690 ret = skl_tplg_fill_pin(dev, tkn_elem->token,
1691 m_pin, pin_count, tkn_elem->value);
1692
1693 if (ret < 0)
1694 return ret;
1695
1696 m_pin[pin_count].in_use = false;
1697 m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
1698
1699 return 0;
1700}
1701
1702/*
1703 * Fill up input/output module config format based
1704 * on the direction
1705 */
1706static int skl_tplg_fill_fmt(struct device *dev,
1707 struct skl_module_cfg *mconfig, u32 tkn,
1708 u32 value, u32 dir, u32 pin_count)
1709{
1710 struct skl_module_fmt *dst_fmt;
1711
1712 switch (dir) {
1713 case SKL_DIR_IN:
1714 dst_fmt = mconfig->in_fmt;
1715 dst_fmt += pin_count;
1716 break;
1717
1718 case SKL_DIR_OUT:
1719 dst_fmt = mconfig->out_fmt;
1720 dst_fmt += pin_count;
1721 break;
1722
1723 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001724 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301725 return -EINVAL;
1726 }
1727
1728 switch (tkn) {
1729 case SKL_TKN_U32_FMT_CH:
1730 dst_fmt->channels = value;
1731 break;
1732
1733 case SKL_TKN_U32_FMT_FREQ:
1734 dst_fmt->s_freq = value;
1735 break;
1736
1737 case SKL_TKN_U32_FMT_BIT_DEPTH:
1738 dst_fmt->bit_depth = value;
1739 break;
1740
1741 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1742 dst_fmt->valid_bit_depth = value;
1743 break;
1744
1745 case SKL_TKN_U32_FMT_CH_CONFIG:
1746 dst_fmt->ch_cfg = value;
1747 break;
1748
1749 case SKL_TKN_U32_FMT_INTERLEAVE:
1750 dst_fmt->interleaving_style = value;
1751 break;
1752
1753 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1754 dst_fmt->sample_type = value;
1755 break;
1756
1757 case SKL_TKN_U32_FMT_CH_MAP:
1758 dst_fmt->ch_map = value;
1759 break;
1760
1761 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001762 dev_err(dev, "Invalid token %d\n", tkn);
Shreyas NC6277e832016-08-12 12:29:51 +05301763 return -EINVAL;
1764 }
1765
1766 return 0;
1767}
1768
1769static int skl_tplg_get_uuid(struct device *dev, struct skl_module_cfg *mconfig,
1770 struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
1771{
1772 if (uuid_tkn->token == SKL_TKN_UUID)
1773 memcpy(&mconfig->guid, &uuid_tkn->uuid, 16);
1774 else {
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001775 dev_err(dev, "Not an UUID token tkn %d\n", uuid_tkn->token);
Shreyas NC6277e832016-08-12 12:29:51 +05301776 return -EINVAL;
1777 }
1778
1779 return 0;
1780}
1781
1782static void skl_tplg_fill_pin_dynamic_val(
1783 struct skl_module_pin *mpin, u32 pin_count, u32 value)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001784{
1785 int i;
1786
Shreyas NC6277e832016-08-12 12:29:51 +05301787 for (i = 0; i < pin_count; i++)
1788 mpin[i].is_dynamic = value;
1789}
1790
1791/*
1792 * Parse tokens to fill up the module private data
1793 */
1794static int skl_tplg_get_token(struct device *dev,
1795 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1796 struct skl *skl, struct skl_module_cfg *mconfig)
1797{
1798 int tkn_count = 0;
1799 int ret;
1800 static int is_pipe_exists;
1801 static int pin_index, dir;
1802
1803 if (tkn_elem->token > SKL_TKN_MAX)
1804 return -EINVAL;
1805
1806 switch (tkn_elem->token) {
1807 case SKL_TKN_U8_IN_QUEUE_COUNT:
1808 mconfig->max_in_queue = tkn_elem->value;
1809 mconfig->m_in_pin = devm_kzalloc(dev, mconfig->max_in_queue *
1810 sizeof(*mconfig->m_in_pin),
1811 GFP_KERNEL);
1812 if (!mconfig->m_in_pin)
1813 return -ENOMEM;
1814
1815 break;
1816
1817 case SKL_TKN_U8_OUT_QUEUE_COUNT:
1818 mconfig->max_out_queue = tkn_elem->value;
1819 mconfig->m_out_pin = devm_kzalloc(dev, mconfig->max_out_queue *
1820 sizeof(*mconfig->m_out_pin),
1821 GFP_KERNEL);
1822
1823 if (!mconfig->m_out_pin)
1824 return -ENOMEM;
1825
1826 break;
1827
1828 case SKL_TKN_U8_DYN_IN_PIN:
1829 if (!mconfig->m_in_pin)
1830 return -ENOMEM;
1831
1832 skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin,
1833 mconfig->max_in_queue, tkn_elem->value);
1834
1835 break;
1836
1837 case SKL_TKN_U8_DYN_OUT_PIN:
1838 if (!mconfig->m_out_pin)
1839 return -ENOMEM;
1840
1841 skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin,
1842 mconfig->max_out_queue, tkn_elem->value);
1843
1844 break;
1845
1846 case SKL_TKN_U8_TIME_SLOT:
1847 mconfig->time_slot = tkn_elem->value;
1848 break;
1849
1850 case SKL_TKN_U8_CORE_ID:
1851 mconfig->core_id = tkn_elem->value;
1852
1853 case SKL_TKN_U8_MOD_TYPE:
1854 mconfig->m_type = tkn_elem->value;
1855 break;
1856
1857 case SKL_TKN_U8_DEV_TYPE:
1858 mconfig->dev_type = tkn_elem->value;
1859 break;
1860
1861 case SKL_TKN_U8_HW_CONN_TYPE:
1862 mconfig->hw_conn_type = tkn_elem->value;
1863 break;
1864
1865 case SKL_TKN_U16_MOD_INST_ID:
1866 mconfig->id.instance_id =
1867 tkn_elem->value;
1868 break;
1869
1870 case SKL_TKN_U32_MEM_PAGES:
1871 mconfig->mem_pages = tkn_elem->value;
1872 break;
1873
1874 case SKL_TKN_U32_MAX_MCPS:
1875 mconfig->mcps = tkn_elem->value;
1876 break;
1877
1878 case SKL_TKN_U32_OBS:
1879 mconfig->obs = tkn_elem->value;
1880 break;
1881
1882 case SKL_TKN_U32_IBS:
1883 mconfig->ibs = tkn_elem->value;
1884 break;
1885
1886 case SKL_TKN_U32_VBUS_ID:
1887 mconfig->vbus_id = tkn_elem->value;
1888 break;
1889
1890 case SKL_TKN_U32_PARAMS_FIXUP:
1891 mconfig->params_fixup = tkn_elem->value;
1892 break;
1893
1894 case SKL_TKN_U32_CONVERTER:
1895 mconfig->converter = tkn_elem->value;
1896 break;
1897
Vinod Koul6bd9dcf2016-11-03 17:07:19 +05301898 case SKL_TKL_U32_D0I3_CAPS:
1899 mconfig->d0i3_caps = tkn_elem->value;
1900 break;
1901
Shreyas NC6277e832016-08-12 12:29:51 +05301902 case SKL_TKN_U32_PIPE_ID:
1903 ret = skl_tplg_add_pipe(dev,
1904 mconfig, skl, tkn_elem);
1905
1906 if (ret < 0)
1907 return is_pipe_exists;
1908
1909 if (ret == EEXIST)
1910 is_pipe_exists = 1;
1911
1912 break;
1913
1914 case SKL_TKN_U32_PIPE_CONN_TYPE:
1915 case SKL_TKN_U32_PIPE_PRIORITY:
1916 case SKL_TKN_U32_PIPE_MEM_PGS:
Vinod Koul8a0cb232016-11-03 17:07:18 +05301917 case SKL_TKN_U32_PMODE:
Shreyas NC6277e832016-08-12 12:29:51 +05301918 if (is_pipe_exists) {
1919 ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
1920 tkn_elem->token, tkn_elem->value);
1921 if (ret < 0)
1922 return ret;
1923 }
1924
1925 break;
1926
1927 /*
1928 * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
1929 * direction and the pin count. The first four bits represent
1930 * direction and next four the pin count.
1931 */
1932 case SKL_TKN_U32_DIR_PIN_COUNT:
1933 dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
1934 pin_index = (tkn_elem->value &
1935 SKL_PIN_COUNT_MASK) >> 4;
1936
1937 break;
1938
1939 case SKL_TKN_U32_FMT_CH:
1940 case SKL_TKN_U32_FMT_FREQ:
1941 case SKL_TKN_U32_FMT_BIT_DEPTH:
1942 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1943 case SKL_TKN_U32_FMT_CH_CONFIG:
1944 case SKL_TKN_U32_FMT_INTERLEAVE:
1945 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1946 case SKL_TKN_U32_FMT_CH_MAP:
1947 ret = skl_tplg_fill_fmt(dev, mconfig, tkn_elem->token,
1948 tkn_elem->value, dir, pin_index);
1949
1950 if (ret < 0)
1951 return ret;
1952
1953 break;
1954
1955 case SKL_TKN_U32_PIN_MOD_ID:
1956 case SKL_TKN_U32_PIN_INST_ID:
1957 ret = skl_tplg_fill_pins_info(dev,
1958 mconfig, tkn_elem, dir,
1959 pin_index);
1960 if (ret < 0)
1961 return ret;
1962
1963 break;
1964
1965 case SKL_TKN_U32_CAPS_SIZE:
1966 mconfig->formats_config.caps_size =
1967 tkn_elem->value;
1968
1969 break;
1970
1971 case SKL_TKN_U32_PROC_DOMAIN:
1972 mconfig->domain =
1973 tkn_elem->value;
1974
1975 break;
1976
1977 case SKL_TKN_U8_IN_PIN_TYPE:
1978 case SKL_TKN_U8_OUT_PIN_TYPE:
1979 case SKL_TKN_U8_CONN_TYPE:
1980 break;
1981
1982 default:
1983 dev_err(dev, "Token %d not handled\n",
1984 tkn_elem->token);
1985 return -EINVAL;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001986 }
Shreyas NC6277e832016-08-12 12:29:51 +05301987
1988 tkn_count++;
1989
1990 return tkn_count;
1991}
1992
1993/*
1994 * Parse the vendor array for specific tokens to construct
1995 * module private data
1996 */
1997static int skl_tplg_get_tokens(struct device *dev,
1998 char *pvt_data, struct skl *skl,
1999 struct skl_module_cfg *mconfig, int block_size)
2000{
2001 struct snd_soc_tplg_vendor_array *array;
2002 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2003 int tkn_count = 0, ret;
2004 int off = 0, tuple_size = 0;
2005
2006 if (block_size <= 0)
2007 return -EINVAL;
2008
2009 while (tuple_size < block_size) {
2010 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2011
2012 off += array->size;
2013
2014 switch (array->type) {
2015 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002016 dev_warn(dev, "no string tokens expected for skl tplg\n");
Shreyas NC6277e832016-08-12 12:29:51 +05302017 continue;
2018
2019 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
2020 ret = skl_tplg_get_uuid(dev, mconfig, array->uuid);
2021 if (ret < 0)
2022 return ret;
2023
2024 tuple_size += sizeof(*array->uuid);
2025
2026 continue;
2027
2028 default:
2029 tkn_elem = array->value;
2030 tkn_count = 0;
2031 break;
2032 }
2033
2034 while (tkn_count <= (array->num_elems - 1)) {
2035 ret = skl_tplg_get_token(dev, tkn_elem,
2036 skl, mconfig);
2037
2038 if (ret < 0)
2039 return ret;
2040
2041 tkn_count = tkn_count + ret;
2042 tkn_elem++;
2043 }
2044
2045 tuple_size += tkn_count * sizeof(*tkn_elem);
2046 }
2047
2048 return 0;
2049}
2050
2051/*
2052 * Every data block is preceded by a descriptor to read the number
2053 * of data blocks, they type of the block and it's size
2054 */
2055static int skl_tplg_get_desc_blocks(struct device *dev,
2056 struct snd_soc_tplg_vendor_array *array)
2057{
2058 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2059
2060 tkn_elem = array->value;
2061
2062 switch (tkn_elem->token) {
2063 case SKL_TKN_U8_NUM_BLOCKS:
2064 case SKL_TKN_U8_BLOCK_TYPE:
2065 case SKL_TKN_U16_BLOCK_SIZE:
2066 return tkn_elem->value;
2067
2068 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002069 dev_err(dev, "Invalid descriptor token %d\n", tkn_elem->token);
Shreyas NC6277e832016-08-12 12:29:51 +05302070 break;
2071 }
2072
2073 return -EINVAL;
2074}
2075
2076/*
2077 * Parse the private data for the token and corresponding value.
2078 * The private data can have multiple data blocks. So, a data block
2079 * is preceded by a descriptor for number of blocks and a descriptor
2080 * for the type and size of the suceeding data block.
2081 */
2082static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
2083 struct skl *skl, struct device *dev,
2084 struct skl_module_cfg *mconfig)
2085{
2086 struct snd_soc_tplg_vendor_array *array;
2087 int num_blocks, block_size = 0, block_type, off = 0;
2088 char *data;
2089 int ret;
2090
2091 /* Read the NUM_DATA_BLOCKS descriptor */
2092 array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
2093 ret = skl_tplg_get_desc_blocks(dev, array);
2094 if (ret < 0)
2095 return ret;
2096 num_blocks = ret;
2097
2098 off += array->size;
2099 array = (struct snd_soc_tplg_vendor_array *)(tplg_w->priv.data + off);
2100
2101 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2102 while (num_blocks > 0) {
2103 ret = skl_tplg_get_desc_blocks(dev, array);
2104
2105 if (ret < 0)
2106 return ret;
2107 block_type = ret;
2108 off += array->size;
2109
2110 array = (struct snd_soc_tplg_vendor_array *)
2111 (tplg_w->priv.data + off);
2112
2113 ret = skl_tplg_get_desc_blocks(dev, array);
2114
2115 if (ret < 0)
2116 return ret;
2117 block_size = ret;
2118 off += array->size;
2119
2120 array = (struct snd_soc_tplg_vendor_array *)
2121 (tplg_w->priv.data + off);
2122
2123 data = (tplg_w->priv.data + off);
2124
2125 if (block_type == SKL_TYPE_TUPLE) {
2126 ret = skl_tplg_get_tokens(dev, data,
2127 skl, mconfig, block_size);
2128
2129 if (ret < 0)
2130 return ret;
2131
2132 --num_blocks;
2133 } else {
2134 if (mconfig->formats_config.caps_size > 0)
2135 memcpy(mconfig->formats_config.caps, data,
2136 mconfig->formats_config.caps_size);
2137 --num_blocks;
2138 }
2139 }
2140
2141 return 0;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002142}
2143
Dharageswari Rfe3f4442016-06-03 18:29:39 +05302144static void skl_clear_pin_config(struct snd_soc_platform *platform,
2145 struct snd_soc_dapm_widget *w)
2146{
2147 int i;
2148 struct skl_module_cfg *mconfig;
2149 struct skl_pipe *pipe;
2150
2151 if (!strncmp(w->dapm->component->name, platform->component.name,
2152 strlen(platform->component.name))) {
2153 mconfig = w->priv;
2154 pipe = mconfig->pipe;
2155 for (i = 0; i < mconfig->max_in_queue; i++) {
2156 mconfig->m_in_pin[i].in_use = false;
2157 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
2158 }
2159 for (i = 0; i < mconfig->max_out_queue; i++) {
2160 mconfig->m_out_pin[i].in_use = false;
2161 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
2162 }
2163 pipe->state = SKL_PIPE_INVALID;
2164 mconfig->m_state = SKL_MODULE_UNINIT;
2165 }
2166}
2167
2168void skl_cleanup_resources(struct skl *skl)
2169{
2170 struct skl_sst *ctx = skl->skl_sst;
2171 struct snd_soc_platform *soc_platform = skl->platform;
2172 struct snd_soc_dapm_widget *w;
2173 struct snd_soc_card *card;
2174
2175 if (soc_platform == NULL)
2176 return;
2177
2178 card = soc_platform->component.card;
2179 if (!card || !card->instantiated)
2180 return;
2181
2182 skl->resource.mem = 0;
2183 skl->resource.mcps = 0;
2184
2185 list_for_each_entry(w, &card->widgets, list) {
2186 if (is_skl_dsp_widget_type(w) && (w->priv != NULL))
2187 skl_clear_pin_config(soc_platform, w);
2188 }
2189
2190 skl_clear_module_cnt(ctx->dsp);
2191}
2192
Vinod Koul3af36702015-10-07 11:31:56 +01002193/*
2194 * Topology core widget load callback
2195 *
2196 * This is used to save the private data for each widget which gives
2197 * information to the driver about module and pipeline parameters which DSP
2198 * FW expects like ids, resource values, formats etc
2199 */
2200static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002201 struct snd_soc_dapm_widget *w,
2202 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01002203{
2204 int ret;
2205 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2206 struct skl *skl = ebus_to_skl(ebus);
2207 struct hdac_bus *bus = ebus_to_hbus(ebus);
2208 struct skl_module_cfg *mconfig;
Vinod Koul3af36702015-10-07 11:31:56 +01002209
2210 if (!tplg_w->priv.size)
2211 goto bind_event;
2212
2213 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
2214
2215 if (!mconfig)
2216 return -ENOMEM;
2217
2218 w->priv = mconfig;
Shreyas NC09305da2016-04-21 11:45:22 +05302219
Vinod Koulb7c50552016-07-26 18:06:40 +05302220 /*
2221 * module binary can be loaded later, so set it to query when
2222 * module is load for a use case
2223 */
2224 mconfig->id.module_id = -1;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002225
Shreyas NC6277e832016-08-12 12:29:51 +05302226 /* Parse private data for tuples */
2227 ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
2228 if (ret < 0)
2229 return ret;
Vinod Koul3af36702015-10-07 11:31:56 +01002230bind_event:
2231 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01002232 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01002233 return 0;
2234 }
2235
2236 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002237 ARRAY_SIZE(skl_tplg_widget_ops),
2238 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01002239
2240 if (ret) {
2241 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
2242 __func__, tplg_w->event_type);
2243 return -EINVAL;
2244 }
2245
2246 return 0;
2247}
2248
Jeeja KP140adfb2015-11-28 15:01:50 +05302249static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
2250 struct snd_soc_tplg_bytes_control *bc)
2251{
2252 struct skl_algo_data *ac;
2253 struct skl_dfw_algo_data *dfw_ac =
2254 (struct skl_dfw_algo_data *)bc->priv.data;
2255
2256 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
2257 if (!ac)
2258 return -ENOMEM;
2259
2260 /* Fill private data */
2261 ac->max = dfw_ac->max;
2262 ac->param_id = dfw_ac->param_id;
2263 ac->set_params = dfw_ac->set_params;
Dharageswari R0d682102016-07-08 18:15:03 +05302264 ac->size = dfw_ac->max;
Jeeja KP140adfb2015-11-28 15:01:50 +05302265
2266 if (ac->max) {
2267 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
2268 if (!ac->params)
2269 return -ENOMEM;
2270
Alan Coxedd7ea22016-02-22 09:37:27 +05302271 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05302272 }
2273
2274 be->dobj.private = ac;
2275 return 0;
2276}
2277
2278static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
2279 struct snd_kcontrol_new *kctl,
2280 struct snd_soc_tplg_ctl_hdr *hdr)
2281{
2282 struct soc_bytes_ext *sb;
2283 struct snd_soc_tplg_bytes_control *tplg_bc;
2284 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2285 struct hdac_bus *bus = ebus_to_hbus(ebus);
2286
2287 switch (hdr->ops.info) {
2288 case SND_SOC_TPLG_CTL_BYTES:
2289 tplg_bc = container_of(hdr,
2290 struct snd_soc_tplg_bytes_control, hdr);
2291 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
2292 sb = (struct soc_bytes_ext *)kctl->private_value;
2293 if (tplg_bc->priv.size)
2294 return skl_init_algo_data(
2295 bus->dev, sb, tplg_bc);
2296 }
2297 break;
2298
2299 default:
2300 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
2301 hdr->ops.get, hdr->ops.put, hdr->ops.info);
2302 break;
2303 }
2304
2305 return 0;
2306}
2307
Shreyas NC541070c2016-08-23 09:31:03 +05302308static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
2309 struct snd_soc_tplg_vendor_string_elem *str_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302310 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302311{
2312 int tkn_count = 0;
2313 static int ref_count;
2314
2315 switch (str_elem->token) {
2316 case SKL_TKN_STR_LIB_NAME:
Jeeja KPeee0e162017-01-02 09:50:04 +05302317 if (ref_count > skl->skl_sst->lib_count - 1) {
Shreyas NC541070c2016-08-23 09:31:03 +05302318 ref_count = 0;
2319 return -EINVAL;
2320 }
2321
Jeeja KPeee0e162017-01-02 09:50:04 +05302322 strncpy(skl->skl_sst->lib_info[ref_count].name,
2323 str_elem->string,
2324 ARRAY_SIZE(skl->skl_sst->lib_info[ref_count].name));
Shreyas NC541070c2016-08-23 09:31:03 +05302325 ref_count++;
2326 tkn_count++;
2327 break;
2328
2329 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002330 dev_err(dev, "Not a string token %d\n", str_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302331 break;
2332 }
2333
2334 return tkn_count;
2335}
2336
2337static int skl_tplg_get_str_tkn(struct device *dev,
2338 struct snd_soc_tplg_vendor_array *array,
Jeeja KPeee0e162017-01-02 09:50:04 +05302339 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302340{
2341 int tkn_count = 0, ret;
2342 struct snd_soc_tplg_vendor_string_elem *str_elem;
2343
2344 str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
2345 while (tkn_count < array->num_elems) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302346 ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302347 str_elem++;
2348
2349 if (ret < 0)
2350 return ret;
2351
2352 tkn_count = tkn_count + ret;
2353 }
2354
2355 return tkn_count;
2356}
2357
2358static int skl_tplg_get_int_tkn(struct device *dev,
2359 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302360 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302361{
2362 int tkn_count = 0;
2363
2364 switch (tkn_elem->token) {
2365 case SKL_TKN_U32_LIB_COUNT:
Jeeja KPeee0e162017-01-02 09:50:04 +05302366 skl->skl_sst->lib_count = tkn_elem->value;
Shreyas NC541070c2016-08-23 09:31:03 +05302367 tkn_count++;
2368 break;
2369
2370 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002371 dev_err(dev, "Not a manifest token %d\n", tkn_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302372 return -EINVAL;
2373 }
2374
2375 return tkn_count;
2376}
2377
2378/*
2379 * Fill the manifest structure by parsing the tokens based on the
2380 * type.
2381 */
2382static int skl_tplg_get_manifest_tkn(struct device *dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302383 char *pvt_data, struct skl *skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302384 int block_size)
2385{
2386 int tkn_count = 0, ret;
2387 int off = 0, tuple_size = 0;
2388 struct snd_soc_tplg_vendor_array *array;
2389 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2390
2391 if (block_size <= 0)
2392 return -EINVAL;
2393
2394 while (tuple_size < block_size) {
2395 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2396 off += array->size;
2397 switch (array->type) {
2398 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Jeeja KPeee0e162017-01-02 09:50:04 +05302399 ret = skl_tplg_get_str_tkn(dev, array, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302400
2401 if (ret < 0)
2402 return ret;
2403 tkn_count += ret;
2404
2405 tuple_size += tkn_count *
2406 sizeof(struct snd_soc_tplg_vendor_string_elem);
2407 continue;
2408
2409 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002410 dev_warn(dev, "no uuid tokens for skl tplf manifest\n");
Shreyas NC541070c2016-08-23 09:31:03 +05302411 continue;
2412
2413 default:
2414 tkn_elem = array->value;
2415 tkn_count = 0;
2416 break;
2417 }
2418
2419 while (tkn_count <= array->num_elems - 1) {
2420 ret = skl_tplg_get_int_tkn(dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302421 tkn_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302422 if (ret < 0)
2423 return ret;
2424
2425 tkn_count = tkn_count + ret;
2426 tkn_elem++;
2427 tuple_size += tkn_count *
2428 sizeof(struct snd_soc_tplg_vendor_value_elem);
2429 break;
2430 }
2431 tkn_count = 0;
2432 }
2433
2434 return 0;
2435}
2436
2437/*
2438 * Parse manifest private data for tokens. The private data block is
2439 * preceded by descriptors for type and size of data block.
2440 */
2441static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
Jeeja KPeee0e162017-01-02 09:50:04 +05302442 struct device *dev, struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302443{
2444 struct snd_soc_tplg_vendor_array *array;
2445 int num_blocks, block_size = 0, block_type, off = 0;
2446 char *data;
2447 int ret;
2448
2449 /* Read the NUM_DATA_BLOCKS descriptor */
2450 array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
2451 ret = skl_tplg_get_desc_blocks(dev, array);
2452 if (ret < 0)
2453 return ret;
2454 num_blocks = ret;
2455
2456 off += array->size;
2457 array = (struct snd_soc_tplg_vendor_array *)
2458 (manifest->priv.data + off);
2459
2460 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2461 while (num_blocks > 0) {
2462 ret = skl_tplg_get_desc_blocks(dev, array);
2463
2464 if (ret < 0)
2465 return ret;
2466 block_type = ret;
2467 off += array->size;
2468
2469 array = (struct snd_soc_tplg_vendor_array *)
2470 (manifest->priv.data + off);
2471
2472 ret = skl_tplg_get_desc_blocks(dev, array);
2473
2474 if (ret < 0)
2475 return ret;
2476 block_size = ret;
2477 off += array->size;
2478
2479 array = (struct snd_soc_tplg_vendor_array *)
2480 (manifest->priv.data + off);
2481
2482 data = (manifest->priv.data + off);
2483
2484 if (block_type == SKL_TYPE_TUPLE) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302485 ret = skl_tplg_get_manifest_tkn(dev, data, skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302486 block_size);
2487
2488 if (ret < 0)
2489 return ret;
2490
2491 --num_blocks;
2492 } else {
2493 return -EINVAL;
2494 }
2495 }
2496
2497 return 0;
2498}
2499
Kranthi G15ecaba92016-07-26 18:06:43 +05302500static int skl_manifest_load(struct snd_soc_component *cmpnt,
2501 struct snd_soc_tplg_manifest *manifest)
2502{
Kranthi G15ecaba92016-07-26 18:06:43 +05302503 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2504 struct hdac_bus *bus = ebus_to_hbus(ebus);
2505 struct skl *skl = ebus_to_skl(ebus);
Kranthi G15ecaba92016-07-26 18:06:43 +05302506
Vinod Koulc15ad602016-08-24 18:03:13 +05302507 /* proceed only if we have private data defined */
2508 if (manifest->priv.size == 0)
2509 return 0;
2510
Jeeja KPeee0e162017-01-02 09:50:04 +05302511 skl_tplg_get_manifest_data(manifest, bus->dev, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302512
Jeeja KPeee0e162017-01-02 09:50:04 +05302513 if (skl->skl_sst->lib_count > SKL_MAX_LIB) {
Kranthi G15ecaba92016-07-26 18:06:43 +05302514 dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
Jeeja KPeee0e162017-01-02 09:50:04 +05302515 skl->skl_sst->lib_count);
2516 return -EINVAL;
Kranthi G15ecaba92016-07-26 18:06:43 +05302517 }
2518
Jeeja KPeee0e162017-01-02 09:50:04 +05302519 return 0;
Kranthi G15ecaba92016-07-26 18:06:43 +05302520}
2521
Vinod Koul3af36702015-10-07 11:31:56 +01002522static struct snd_soc_tplg_ops skl_tplg_ops = {
2523 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05302524 .control_load = skl_tplg_control_load,
2525 .bytes_ext_ops = skl_tlv_ops,
2526 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Kranthi G15ecaba92016-07-26 18:06:43 +05302527 .manifest = skl_manifest_load,
Vinod Koul3af36702015-10-07 11:31:56 +01002528};
2529
Jeeja KP287af4f2016-06-03 18:29:40 +05302530/*
2531 * A pipe can have multiple modules, each of them will be a DAPM widget as
2532 * well. While managing a pipeline we need to get the list of all the
2533 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
2534 * helps to get the SKL type widgets in that pipeline
2535 */
2536static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform)
2537{
2538 struct snd_soc_dapm_widget *w;
2539 struct skl_module_cfg *mcfg = NULL;
2540 struct skl_pipe_module *p_module = NULL;
2541 struct skl_pipe *pipe;
2542
2543 list_for_each_entry(w, &platform->component.card->widgets, list) {
2544 if (is_skl_dsp_widget_type(w) && w->priv != NULL) {
2545 mcfg = w->priv;
2546 pipe = mcfg->pipe;
2547
2548 p_module = devm_kzalloc(platform->dev,
2549 sizeof(*p_module), GFP_KERNEL);
2550 if (!p_module)
2551 return -ENOMEM;
2552
2553 p_module->w = w;
2554 list_add_tail(&p_module->node, &pipe->w_list);
2555 }
2556 }
2557
2558 return 0;
2559}
2560
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302561static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe)
2562{
2563 struct skl_pipe_module *w_module;
2564 struct snd_soc_dapm_widget *w;
2565 struct skl_module_cfg *mconfig;
2566 bool host_found = false, link_found = false;
2567
2568 list_for_each_entry(w_module, &pipe->w_list, node) {
2569 w = w_module->w;
2570 mconfig = w->priv;
2571
2572 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
2573 host_found = true;
2574 else if (mconfig->dev_type != SKL_DEVICE_NONE)
2575 link_found = true;
2576 }
2577
2578 if (host_found && link_found)
2579 pipe->passthru = true;
2580 else
2581 pipe->passthru = false;
2582}
2583
Vinod Koul3af36702015-10-07 11:31:56 +01002584/* This will be read from topology manifest, currently defined here */
2585#define SKL_MAX_MCPS 30000000
2586#define SKL_FW_MAX_MEM 1000000
2587
2588/*
2589 * SKL topology init routine
2590 */
2591int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
2592{
2593 int ret;
2594 const struct firmware *fw;
2595 struct hdac_bus *bus = ebus_to_hbus(ebus);
2596 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302597 struct skl_pipeline *ppl;
Vinod Koul3af36702015-10-07 11:31:56 +01002598
Vinod Koul4b235c42016-02-19 11:42:34 +05302599 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01002600 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01002601 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05302602 skl->tplg_name, ret);
2603 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
2604 if (ret < 0) {
2605 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
2606 "dfw_sst.bin", ret);
2607 return ret;
2608 }
Vinod Koul3af36702015-10-07 11:31:56 +01002609 }
2610
2611 /*
2612 * The complete tplg for SKL is loaded as index 0, we don't use
2613 * any other index
2614 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01002615 ret = snd_soc_tplg_component_load(&platform->component,
2616 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01002617 if (ret < 0) {
2618 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05302619 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01002620 return -EINVAL;
2621 }
2622
2623 skl->resource.max_mcps = SKL_MAX_MCPS;
2624 skl->resource.max_mem = SKL_FW_MAX_MEM;
2625
Vinod Kould8018362016-01-05 17:16:04 +05302626 skl->tplg = fw;
Jeeja KP287af4f2016-06-03 18:29:40 +05302627 ret = skl_tplg_create_pipe_widget_list(platform);
2628 if (ret < 0)
2629 return ret;
Vinod Kould8018362016-01-05 17:16:04 +05302630
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302631 list_for_each_entry(ppl, &skl->ppl_list, node)
2632 skl_tplg_set_pipe_type(skl, ppl->pipe);
Vinod Koul3af36702015-10-07 11:31:56 +01002633
2634 return 0;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01002635}