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Sergei Shtylyov128296f2014-01-03 15:52:22 +03001/* SuperH Ethernet device driver
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002 *
Hisashi Nakamura966d6db2014-11-13 15:54:05 +09003 * Copyright (C) 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsuf0e81fe2012-03-25 18:59:51 +00004 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
Sergei Shtylyovb356e972014-02-18 03:12:43 +03005 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
Ben Dooks702eca02014-03-12 17:47:40 +00007 * Copyright (C) 2014 Codethink Limited
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07008 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070017 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
Yoshihiro Shimoda06540112011-09-29 17:16:57 +000022#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
David S. Miller823dcd22011-08-20 10:39:12 -070025#include <linux/interrupt.h>
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070026#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
Sergei Shtylyovb356e972014-02-18 03:12:43 +030032#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070036#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
Magnus Dammbcd51492009-10-09 00:20:04 +000039#include <linux/pm_runtime.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090040#include <linux/slab.h>
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +000041#include <linux/ethtool.h>
Yoshihiro Shimodafdb37a72012-02-06 23:55:15 +000042#include <linux/if_vlan.h>
Nobuhiro Iwamatsuf0e81fe2012-03-25 18:59:51 +000043#include <linux/clk.h>
Yoshihiro Shimodad4fa0e32011-09-27 21:49:12 +000044#include <linux/sh_eth.h>
Ben Dooks702eca02014-03-12 17:47:40 +000045#include <linux/of_mdio.h>
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070046
47#include "sh_eth.h"
48
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +000049#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
Ben Hutchings33657112015-02-26 20:34:14 +000055#define SH_ETH_OFFSET_DEFAULTS \
56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
57
Sergei Shtylyovc0013f62013-03-28 11:48:26 +000058static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
Ben Hutchings33657112015-02-26 20:34:14 +000059 SH_ETH_OFFSET_DEFAULTS,
60
Sergei Shtylyovc0013f62013-03-28 11:48:26 +000061 [EDSR] = 0x0000,
62 [EDMR] = 0x0400,
63 [EDTRR] = 0x0408,
64 [EDRRR] = 0x0410,
65 [EESR] = 0x0428,
66 [EESIPR] = 0x0430,
67 [TDLAR] = 0x0010,
68 [TDFAR] = 0x0014,
69 [TDFXR] = 0x0018,
70 [TDFFR] = 0x001c,
71 [RDLAR] = 0x0030,
72 [RDFAR] = 0x0034,
73 [RDFXR] = 0x0038,
74 [RDFFR] = 0x003c,
75 [TRSCER] = 0x0438,
76 [RMFCR] = 0x0440,
77 [TFTR] = 0x0448,
78 [FDR] = 0x0450,
79 [RMCR] = 0x0458,
80 [RPADIR] = 0x0460,
81 [FCFTR] = 0x0468,
82 [CSMR] = 0x04E4,
83
84 [ECMR] = 0x0500,
85 [ECSR] = 0x0510,
86 [ECSIPR] = 0x0518,
87 [PIR] = 0x0520,
88 [PSR] = 0x0528,
89 [PIPR] = 0x052c,
90 [RFLR] = 0x0508,
91 [APR] = 0x0554,
92 [MPR] = 0x0558,
93 [PFTCR] = 0x055c,
94 [PFRCR] = 0x0560,
95 [TPAUSER] = 0x0564,
96 [GECMR] = 0x05b0,
97 [BCULR] = 0x05b4,
98 [MAHR] = 0x05c0,
99 [MALR] = 0x05c8,
100 [TROCR] = 0x0700,
101 [CDCR] = 0x0708,
102 [LCCR] = 0x0710,
103 [CEFCR] = 0x0740,
104 [FRECR] = 0x0748,
105 [TSFRCR] = 0x0750,
106 [TLFRCR] = 0x0758,
107 [RFCR] = 0x0760,
108 [CERCR] = 0x0768,
109 [CEECR] = 0x0770,
110 [MAFCR] = 0x0778,
111 [RMII_MII] = 0x0790,
112
113 [ARSTR] = 0x0000,
114 [TSU_CTRST] = 0x0004,
115 [TSU_FWEN0] = 0x0010,
116 [TSU_FWEN1] = 0x0014,
117 [TSU_FCM] = 0x0018,
118 [TSU_BSYSL0] = 0x0020,
119 [TSU_BSYSL1] = 0x0024,
120 [TSU_PRISL0] = 0x0028,
121 [TSU_PRISL1] = 0x002c,
122 [TSU_FWSL0] = 0x0030,
123 [TSU_FWSL1] = 0x0034,
124 [TSU_FWSLC] = 0x0038,
125 [TSU_QTAG0] = 0x0040,
126 [TSU_QTAG1] = 0x0044,
127 [TSU_FWSR] = 0x0050,
128 [TSU_FWINMK] = 0x0054,
129 [TSU_ADQT0] = 0x0048,
130 [TSU_ADQT1] = 0x004c,
131 [TSU_VTAG0] = 0x0058,
132 [TSU_VTAG1] = 0x005c,
133 [TSU_ADSBSY] = 0x0060,
134 [TSU_TEN] = 0x0064,
135 [TSU_POST1] = 0x0070,
136 [TSU_POST2] = 0x0074,
137 [TSU_POST3] = 0x0078,
138 [TSU_POST4] = 0x007c,
139 [TSU_ADRH0] = 0x0100,
Sergei Shtylyovc0013f62013-03-28 11:48:26 +0000140
141 [TXNLCR0] = 0x0080,
142 [TXALCR0] = 0x0084,
143 [RXNLCR0] = 0x0088,
144 [RXALCR0] = 0x008c,
145 [FWNLCR0] = 0x0090,
146 [FWALCR0] = 0x0094,
147 [TXNLCR1] = 0x00a0,
148 [TXALCR1] = 0x00a0,
149 [RXNLCR1] = 0x00a8,
150 [RXALCR1] = 0x00ac,
151 [FWNLCR1] = 0x00b0,
152 [FWALCR1] = 0x00b4,
153};
154
Simon Hormandb893472014-01-17 09:22:28 +0900155static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
Ben Hutchings33657112015-02-26 20:34:14 +0000156 SH_ETH_OFFSET_DEFAULTS,
157
Simon Hormandb893472014-01-17 09:22:28 +0900158 [EDSR] = 0x0000,
159 [EDMR] = 0x0400,
160 [EDTRR] = 0x0408,
161 [EDRRR] = 0x0410,
162 [EESR] = 0x0428,
163 [EESIPR] = 0x0430,
164 [TDLAR] = 0x0010,
165 [TDFAR] = 0x0014,
166 [TDFXR] = 0x0018,
167 [TDFFR] = 0x001c,
168 [RDLAR] = 0x0030,
169 [RDFAR] = 0x0034,
170 [RDFXR] = 0x0038,
171 [RDFFR] = 0x003c,
172 [TRSCER] = 0x0438,
173 [RMFCR] = 0x0440,
174 [TFTR] = 0x0448,
175 [FDR] = 0x0450,
176 [RMCR] = 0x0458,
177 [RPADIR] = 0x0460,
178 [FCFTR] = 0x0468,
179 [CSMR] = 0x04E4,
180
181 [ECMR] = 0x0500,
182 [RFLR] = 0x0508,
183 [ECSR] = 0x0510,
184 [ECSIPR] = 0x0518,
185 [PIR] = 0x0520,
186 [APR] = 0x0554,
187 [MPR] = 0x0558,
188 [PFTCR] = 0x055c,
189 [PFRCR] = 0x0560,
190 [TPAUSER] = 0x0564,
191 [MAHR] = 0x05c0,
192 [MALR] = 0x05c8,
193 [CEFCR] = 0x0740,
194 [FRECR] = 0x0748,
195 [TSFRCR] = 0x0750,
196 [TLFRCR] = 0x0758,
197 [RFCR] = 0x0760,
198 [MAFCR] = 0x0778,
199
200 [ARSTR] = 0x0000,
201 [TSU_CTRST] = 0x0004,
202 [TSU_VTAG0] = 0x0058,
203 [TSU_ADSBSY] = 0x0060,
204 [TSU_TEN] = 0x0064,
205 [TSU_ADRH0] = 0x0100,
Simon Hormandb893472014-01-17 09:22:28 +0900206
207 [TXNLCR0] = 0x0080,
208 [TXALCR0] = 0x0084,
209 [RXNLCR0] = 0x0088,
210 [RXALCR0] = 0x008C,
211};
212
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000213static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
Ben Hutchings33657112015-02-26 20:34:14 +0000214 SH_ETH_OFFSET_DEFAULTS,
215
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000216 [ECMR] = 0x0300,
217 [RFLR] = 0x0308,
218 [ECSR] = 0x0310,
219 [ECSIPR] = 0x0318,
220 [PIR] = 0x0320,
221 [PSR] = 0x0328,
222 [RDMLR] = 0x0340,
223 [IPGR] = 0x0350,
224 [APR] = 0x0354,
225 [MPR] = 0x0358,
226 [RFCF] = 0x0360,
227 [TPAUSER] = 0x0364,
228 [TPAUSECR] = 0x0368,
229 [MAHR] = 0x03c0,
230 [MALR] = 0x03c8,
231 [TROCR] = 0x03d0,
232 [CDCR] = 0x03d4,
233 [LCCR] = 0x03d8,
234 [CNDCR] = 0x03dc,
235 [CEFCR] = 0x03e4,
236 [FRECR] = 0x03e8,
237 [TSFRCR] = 0x03ec,
238 [TLFRCR] = 0x03f0,
239 [RFCR] = 0x03f4,
240 [MAFCR] = 0x03f8,
241
242 [EDMR] = 0x0200,
243 [EDTRR] = 0x0208,
244 [EDRRR] = 0x0210,
245 [TDLAR] = 0x0218,
246 [RDLAR] = 0x0220,
247 [EESR] = 0x0228,
248 [EESIPR] = 0x0230,
249 [TRSCER] = 0x0238,
250 [RMFCR] = 0x0240,
251 [TFTR] = 0x0248,
252 [FDR] = 0x0250,
253 [RMCR] = 0x0258,
254 [TFUCR] = 0x0264,
255 [RFOCR] = 0x0268,
Simon Horman55754f12013-07-23 10:18:04 +0900256 [RMIIMODE] = 0x026c,
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000257 [FCFTR] = 0x0270,
258 [TRIMD] = 0x027c,
259};
260
Sergei Shtylyovc0013f62013-03-28 11:48:26 +0000261static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
Ben Hutchings33657112015-02-26 20:34:14 +0000262 SH_ETH_OFFSET_DEFAULTS,
263
Sergei Shtylyovc0013f62013-03-28 11:48:26 +0000264 [ECMR] = 0x0100,
265 [RFLR] = 0x0108,
266 [ECSR] = 0x0110,
267 [ECSIPR] = 0x0118,
268 [PIR] = 0x0120,
269 [PSR] = 0x0128,
270 [RDMLR] = 0x0140,
271 [IPGR] = 0x0150,
272 [APR] = 0x0154,
273 [MPR] = 0x0158,
274 [TPAUSER] = 0x0164,
275 [RFCF] = 0x0160,
276 [TPAUSECR] = 0x0168,
277 [BCFRR] = 0x016c,
278 [MAHR] = 0x01c0,
279 [MALR] = 0x01c8,
280 [TROCR] = 0x01d0,
281 [CDCR] = 0x01d4,
282 [LCCR] = 0x01d8,
283 [CNDCR] = 0x01dc,
284 [CEFCR] = 0x01e4,
285 [FRECR] = 0x01e8,
286 [TSFRCR] = 0x01ec,
287 [TLFRCR] = 0x01f0,
288 [RFCR] = 0x01f4,
289 [MAFCR] = 0x01f8,
290 [RTRATE] = 0x01fc,
291
292 [EDMR] = 0x0000,
293 [EDTRR] = 0x0008,
294 [EDRRR] = 0x0010,
295 [TDLAR] = 0x0018,
296 [RDLAR] = 0x0020,
297 [EESR] = 0x0028,
298 [EESIPR] = 0x0030,
299 [TRSCER] = 0x0038,
300 [RMFCR] = 0x0040,
301 [TFTR] = 0x0048,
302 [FDR] = 0x0050,
303 [RMCR] = 0x0058,
304 [TFUCR] = 0x0064,
305 [RFOCR] = 0x0068,
306 [FCFTR] = 0x0070,
307 [RPADIR] = 0x0078,
308 [TRIMD] = 0x007c,
309 [RBWAR] = 0x00c8,
310 [RDFAR] = 0x00cc,
311 [TBRAR] = 0x00d4,
312 [TDFAR] = 0x00d8,
313};
314
315static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
Ben Hutchings33657112015-02-26 20:34:14 +0000316 SH_ETH_OFFSET_DEFAULTS,
317
Sergei Shtylyovd8b04262014-06-03 23:42:26 +0400318 [EDMR] = 0x0000,
319 [EDTRR] = 0x0004,
320 [EDRRR] = 0x0008,
321 [TDLAR] = 0x000c,
322 [RDLAR] = 0x0010,
323 [EESR] = 0x0014,
324 [EESIPR] = 0x0018,
325 [TRSCER] = 0x001c,
326 [RMFCR] = 0x0020,
327 [TFTR] = 0x0024,
328 [FDR] = 0x0028,
329 [RMCR] = 0x002c,
330 [EDOCR] = 0x0030,
331 [FCFTR] = 0x0034,
332 [RPADIR] = 0x0038,
333 [TRIMD] = 0x003c,
334 [RBWAR] = 0x0040,
335 [RDFAR] = 0x0044,
336 [TBRAR] = 0x004c,
337 [TDFAR] = 0x0050,
338
Sergei Shtylyovc0013f62013-03-28 11:48:26 +0000339 [ECMR] = 0x0160,
340 [ECSR] = 0x0164,
341 [ECSIPR] = 0x0168,
342 [PIR] = 0x016c,
343 [MAHR] = 0x0170,
344 [MALR] = 0x0174,
345 [RFLR] = 0x0178,
346 [PSR] = 0x017c,
347 [TROCR] = 0x0180,
348 [CDCR] = 0x0184,
349 [LCCR] = 0x0188,
350 [CNDCR] = 0x018c,
351 [CEFCR] = 0x0194,
352 [FRECR] = 0x0198,
353 [TSFRCR] = 0x019c,
354 [TLFRCR] = 0x01a0,
355 [RFCR] = 0x01a4,
356 [MAFCR] = 0x01a8,
357 [IPGR] = 0x01b4,
358 [APR] = 0x01b8,
359 [MPR] = 0x01bc,
360 [TPAUSER] = 0x01c4,
361 [BCFR] = 0x01cc,
362
363 [ARSTR] = 0x0000,
364 [TSU_CTRST] = 0x0004,
365 [TSU_FWEN0] = 0x0010,
366 [TSU_FWEN1] = 0x0014,
367 [TSU_FCM] = 0x0018,
368 [TSU_BSYSL0] = 0x0020,
369 [TSU_BSYSL1] = 0x0024,
370 [TSU_PRISL0] = 0x0028,
371 [TSU_PRISL1] = 0x002c,
372 [TSU_FWSL0] = 0x0030,
373 [TSU_FWSL1] = 0x0034,
374 [TSU_FWSLC] = 0x0038,
375 [TSU_QTAGM0] = 0x0040,
376 [TSU_QTAGM1] = 0x0044,
377 [TSU_ADQT0] = 0x0048,
378 [TSU_ADQT1] = 0x004c,
379 [TSU_FWSR] = 0x0050,
380 [TSU_FWINMK] = 0x0054,
381 [TSU_ADSBSY] = 0x0060,
382 [TSU_TEN] = 0x0064,
383 [TSU_POST1] = 0x0070,
384 [TSU_POST2] = 0x0074,
385 [TSU_POST3] = 0x0078,
386 [TSU_POST4] = 0x007c,
387
388 [TXNLCR0] = 0x0080,
389 [TXALCR0] = 0x0084,
390 [RXNLCR0] = 0x0088,
391 [RXALCR0] = 0x008c,
392 [FWNLCR0] = 0x0090,
393 [FWALCR0] = 0x0094,
394 [TXNLCR1] = 0x00a0,
395 [TXALCR1] = 0x00a0,
396 [RXNLCR1] = 0x00a8,
397 [RXALCR1] = 0x00ac,
398 [FWNLCR1] = 0x00b0,
399 [FWALCR1] = 0x00b4,
400
401 [TSU_ADRH0] = 0x0100,
Sergei Shtylyovc0013f62013-03-28 11:48:26 +0000402};
403
Ben Hutchings740c7f32015-01-27 00:49:32 +0000404static void sh_eth_rcv_snd_disable(struct net_device *ndev);
405static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
406
Simon Horman504c8ca2014-01-17 09:22:27 +0900407static bool sh_eth_is_gether(struct sh_eth_private *mdp)
Nobuhiro Iwamatsudabdde92013-06-06 09:51:39 +0000408{
Simon Horman504c8ca2014-01-17 09:22:27 +0900409 return mdp->reg_offset == sh_eth_offset_gigabit;
Nobuhiro Iwamatsudabdde92013-06-06 09:51:39 +0000410}
411
Simon Hormandb893472014-01-17 09:22:28 +0900412static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
413{
414 return mdp->reg_offset == sh_eth_offset_fast_rz;
415}
416
Sergei Shtylyov8e994402013-06-12 03:07:29 +0400417static void sh_eth_select_mii(struct net_device *ndev)
Nobuhiro Iwamatsu5e7a76b2012-06-25 17:34:14 +0000418{
419 u32 value = 0x0;
420 struct sh_eth_private *mdp = netdev_priv(ndev);
421
422 switch (mdp->phy_interface) {
423 case PHY_INTERFACE_MODE_GMII:
424 value = 0x2;
425 break;
426 case PHY_INTERFACE_MODE_MII:
427 value = 0x1;
428 break;
429 case PHY_INTERFACE_MODE_RMII:
430 value = 0x0;
431 break;
432 default:
Sergei Shtylyovf75f14e2014-03-15 03:27:54 +0300433 netdev_warn(ndev,
434 "PHY interface mode was not setup. Set to MII.\n");
Nobuhiro Iwamatsu5e7a76b2012-06-25 17:34:14 +0000435 value = 0x1;
436 break;
437 }
438
439 sh_eth_write(ndev, value, RMII_MII);
440}
Nobuhiro Iwamatsu5e7a76b2012-06-25 17:34:14 +0000441
Sergei Shtylyov8e994402013-06-12 03:07:29 +0400442static void sh_eth_set_duplex(struct net_device *ndev)
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000443{
444 struct sh_eth_private *mdp = netdev_priv(ndev);
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000445
446 if (mdp->duplex) /* Full */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000448 else /* Half */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000450}
451
Geert Uytterhoeven99f84be2015-11-24 15:40:57 +0100452static void sh_eth_chip_reset(struct net_device *ndev)
453{
454 struct sh_eth_private *mdp = netdev_priv(ndev);
455
456 /* reset device */
457 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
458 mdelay(1);
459}
460
461#ifdef CONFIG_OF
462/* R7S72100 */
463static struct sh_eth_cpu_data r7s72100_data = {
464 .chip_reset = sh_eth_chip_reset,
465 .set_duplex = sh_eth_set_duplex,
466
467 .register_type = SH_ETH_REG_FAST_RZ,
468
469 .ecsr_value = ECSR_ICD,
470 .ecsipr_value = ECSIPR_ICDIP,
471 .eesipr_value = 0xff7f009f,
472
473 .tx_check = EESR_TC1 | EESR_FTC,
474 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
475 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
476 EESR_TDE | EESR_ECI,
477 .fdr_value = 0x0000070f,
478
479 .no_psr = 1,
480 .apr = 1,
481 .mpr = 1,
482 .tpauser = 1,
483 .hw_swap = 1,
484 .rpadir = 1,
485 .rpadir_value = 2 << 16,
486 .no_trimd = 1,
487 .no_ade = 1,
488 .hw_crc = 1,
489 .tsu = 1,
490 .shift_rd0 = 1,
491};
492#endif /* CONFIG_OF */
493
Nobuhiro Iwamatsu04b0ed22013-06-06 09:45:25 +0000494/* There is CPU dependent code */
Sergei Shtylyov589ebde2013-06-07 14:05:59 +0000495static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000496{
497 struct sh_eth_private *mdp = netdev_priv(ndev);
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000498
499 switch (mdp->speed) {
500 case 10: /* 10BASE */
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000501 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000502 break;
503 case 100:/* 100BASE */
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000504 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
505 break;
506 default:
507 break;
508 }
509}
510
Sergei Shtylyov674853b2013-04-27 10:44:24 +0000511/* R8A7778/9 */
Sergei Shtylyov589ebde2013-06-07 14:05:59 +0000512static struct sh_eth_cpu_data r8a777x_data = {
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000513 .set_duplex = sh_eth_set_duplex,
Sergei Shtylyov589ebde2013-06-07 14:05:59 +0000514 .set_rate = sh_eth_set_rate_r8a777x,
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000515
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400516 .register_type = SH_ETH_REG_FAST_RCAR,
517
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000518 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
519 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
520 .eesipr_value = 0x01ff009f,
521
522 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
Sergei Shtylyovca8c3582013-06-21 01:12:21 +0400523 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
524 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
525 EESR_ECI,
Nobuhiro Iwamatsud407bc02015-01-07 14:40:15 +0900526 .fdr_value = 0x00000f0f,
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000527
528 .apr = 1,
529 .mpr = 1,
530 .tpauser = 1,
531 .hw_swap = 1,
532};
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000533
Sergei Shtylyov94a12b12013-12-08 02:59:18 +0300534/* R8A7790/1 */
535static struct sh_eth_cpu_data r8a779x_data = {
Simon Hormane18dbf72013-07-23 10:18:05 +0900536 .set_duplex = sh_eth_set_duplex,
537 .set_rate = sh_eth_set_rate_r8a777x,
538
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400539 .register_type = SH_ETH_REG_FAST_RCAR,
540
Simon Hormane18dbf72013-07-23 10:18:05 +0900541 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
542 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
543 .eesipr_value = 0x01ff009f,
544
545 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
Laurent Pinchartba361cb2013-07-31 16:42:11 +0900546 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
547 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
548 EESR_ECI,
Nobuhiro Iwamatsud407bc02015-01-07 14:40:15 +0900549 .fdr_value = 0x00000f0f,
Simon Hormane18dbf72013-07-23 10:18:05 +0900550
Geert Uytterhoeven01fbd3f2015-01-15 11:52:19 +0100551 .trscer_err_mask = DESC_I_RINT8,
552
Simon Hormane18dbf72013-07-23 10:18:05 +0900553 .apr = 1,
554 .mpr = 1,
555 .tpauser = 1,
556 .hw_swap = 1,
557 .rmiimode = 1,
558};
559
Sergei Shtylyov9c3beaa2013-06-07 14:03:37 +0000560static void sh_eth_set_rate_sh7724(struct net_device *ndev)
Sergei Shtylyova3f109b2013-03-28 11:51:31 +0000561{
562 struct sh_eth_private *mdp = netdev_priv(ndev);
563
564 switch (mdp->speed) {
565 case 10: /* 10BASE */
566 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
567 break;
568 case 100:/* 100BASE */
569 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000570 break;
571 default:
572 break;
573 }
574}
575
576/* SH7724 */
Sergei Shtylyov9c3beaa2013-06-07 14:03:37 +0000577static struct sh_eth_cpu_data sh7724_data = {
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000578 .set_duplex = sh_eth_set_duplex,
Sergei Shtylyov9c3beaa2013-06-07 14:03:37 +0000579 .set_rate = sh_eth_set_rate_sh7724,
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000580
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400581 .register_type = SH_ETH_REG_FAST_SH4,
582
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000583 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
584 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
Sergei Shtylyova80c3de2013-06-20 02:24:54 +0400585 .eesipr_value = 0x01ff009f,
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000586
587 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
Sergei Shtylyovca8c3582013-06-21 01:12:21 +0400588 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
589 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
590 EESR_ECI,
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000591
592 .apr = 1,
593 .mpr = 1,
594 .tpauser = 1,
595 .hw_swap = 1,
Magnus Damm503914c2009-12-15 21:16:55 -0800596 .rpadir = 1,
597 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000598};
Nobuhiro Iwamatsu5cee1d32012-06-25 17:35:12 +0000599
Sergei Shtylyov24549e22013-06-07 13:59:21 +0000600static void sh_eth_set_rate_sh7757(struct net_device *ndev)
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000601{
602 struct sh_eth_private *mdp = netdev_priv(ndev);
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000603
604 switch (mdp->speed) {
605 case 10: /* 10BASE */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000606 sh_eth_write(ndev, 0, RTRATE);
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000607 break;
608 case 100:/* 100BASE */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000609 sh_eth_write(ndev, 1, RTRATE);
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000610 break;
611 default:
612 break;
613 }
614}
615
616/* SH7757 */
Sergei Shtylyov24549e22013-06-07 13:59:21 +0000617static struct sh_eth_cpu_data sh7757_data = {
618 .set_duplex = sh_eth_set_duplex,
619 .set_rate = sh_eth_set_rate_sh7757,
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000620
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400621 .register_type = SH_ETH_REG_FAST_SH4,
622
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000623 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000624
625 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
Sergei Shtylyovca8c3582013-06-21 01:12:21 +0400626 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
627 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
628 EESR_ECI,
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000629
Nobuhiro Iwamatsu5b3dfd12013-06-06 09:49:30 +0000630 .irq_flags = IRQF_SHARED,
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000631 .apr = 1,
632 .mpr = 1,
633 .tpauser = 1,
634 .hw_swap = 1,
635 .no_ade = 1,
Yoshihiro Shimoda2e98e792011-07-05 20:33:57 +0000636 .rpadir = 1,
637 .rpadir_value = 2 << 16,
Ben Hutchings6b4b4fe2015-02-26 20:34:35 +0000638 .rtrate = 1,
Yoshihiro Shimodaf29a3d02010-07-05 18:32:50 +0000639};
Yoshihiro Shimoda65ac8852009-05-24 23:54:30 +0000640
David S. Millere403d292013-06-07 23:40:41 -0700641#define SH_GIGA_ETH_BASE 0xfee00000UL
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000642#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
643#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
644static void sh_eth_chip_reset_giga(struct net_device *ndev)
645{
646 int i;
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +0100647 u32 mahr[2], malr[2];
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000648
649 /* save MAHR and MALR */
650 for (i = 0; i < 2; i++) {
Yoshihiro Shimodaae706442011-09-27 21:48:58 +0000651 malr[i] = ioread32((void *)GIGA_MALR(i));
652 mahr[i] = ioread32((void *)GIGA_MAHR(i));
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000653 }
654
655 /* reset device */
Yoshihiro Shimodaae706442011-09-27 21:48:58 +0000656 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000657 mdelay(1);
658
659 /* restore MAHR and MALR */
660 for (i = 0; i < 2; i++) {
Yoshihiro Shimodaae706442011-09-27 21:48:58 +0000661 iowrite32(malr[i], (void *)GIGA_MALR(i));
662 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000663 }
664}
665
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000666static void sh_eth_set_rate_giga(struct net_device *ndev)
667{
668 struct sh_eth_private *mdp = netdev_priv(ndev);
669
670 switch (mdp->speed) {
671 case 10: /* 10BASE */
672 sh_eth_write(ndev, 0x00000000, GECMR);
673 break;
674 case 100:/* 100BASE */
675 sh_eth_write(ndev, 0x00000010, GECMR);
676 break;
677 case 1000: /* 1000BASE */
678 sh_eth_write(ndev, 0x00000020, GECMR);
679 break;
680 default:
681 break;
682 }
683}
684
685/* SH7757(GETHERC) */
Sergei Shtylyov24549e22013-06-07 13:59:21 +0000686static struct sh_eth_cpu_data sh7757_data_giga = {
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000687 .chip_reset = sh_eth_chip_reset_giga,
Nobuhiro Iwamatsu04b0ed22013-06-06 09:45:25 +0000688 .set_duplex = sh_eth_set_duplex,
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000689 .set_rate = sh_eth_set_rate_giga,
690
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400691 .register_type = SH_ETH_REG_GIGABIT,
692
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000693 .ecsr_value = ECSR_ICD | ECSR_MPD,
694 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
695 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
696
697 .tx_check = EESR_TC1 | EESR_FTC,
Sergei Shtylyovca8c3582013-06-21 01:12:21 +0400698 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
699 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
700 EESR_TDE | EESR_ECI,
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000701 .fdr_value = 0x0000072f,
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000702
Nobuhiro Iwamatsu5b3dfd12013-06-06 09:49:30 +0000703 .irq_flags = IRQF_SHARED,
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000704 .apr = 1,
705 .mpr = 1,
706 .tpauser = 1,
707 .bculr = 1,
708 .hw_swap = 1,
709 .rpadir = 1,
710 .rpadir_value = 2 << 16,
711 .no_trimd = 1,
712 .no_ade = 1,
Yoshihiro Shimoda3acbc972012-02-15 17:54:51 +0000713 .tsu = 1,
Yoshihiro Shimoda8fcd4962011-03-07 21:59:49 +0000714};
715
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000716static void sh_eth_set_rate_gether(struct net_device *ndev)
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000717{
718 struct sh_eth_private *mdp = netdev_priv(ndev);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000719
720 switch (mdp->speed) {
721 case 10: /* 10BASE */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000722 sh_eth_write(ndev, GECMR_10, GECMR);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000723 break;
724 case 100:/* 100BASE */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000725 sh_eth_write(ndev, GECMR_100, GECMR);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000726 break;
727 case 1000: /* 1000BASE */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000728 sh_eth_write(ndev, GECMR_1000, GECMR);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000729 break;
730 default:
731 break;
732 }
733}
734
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000735/* SH7734 */
736static struct sh_eth_cpu_data sh7734_data = {
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000737 .chip_reset = sh_eth_chip_reset,
738 .set_duplex = sh_eth_set_duplex,
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000739 .set_rate = sh_eth_set_rate_gether,
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000740
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400741 .register_type = SH_ETH_REG_GIGABIT,
742
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000743 .ecsr_value = ECSR_ICD | ECSR_MPD,
744 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
745 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
746
747 .tx_check = EESR_TC1 | EESR_FTC,
Sergei Shtylyovca8c3582013-06-21 01:12:21 +0400748 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
749 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
750 EESR_TDE | EESR_ECI,
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000751
752 .apr = 1,
753 .mpr = 1,
754 .tpauser = 1,
755 .bculr = 1,
756 .hw_swap = 1,
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000757 .no_trimd = 1,
758 .no_ade = 1,
Yoshihiro Shimoda4986b992011-03-07 21:59:34 +0000759 .tsu = 1,
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000760 .hw_crc = 1,
761 .select_mii = 1,
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000762};
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000763
764/* SH7763 */
765static struct sh_eth_cpu_data sh7763_data = {
766 .chip_reset = sh_eth_chip_reset,
767 .set_duplex = sh_eth_set_duplex,
768 .set_rate = sh_eth_set_rate_gether,
769
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400770 .register_type = SH_ETH_REG_GIGABIT,
771
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
Sergei Shtylyov128296f2014-01-03 15:52:22 +0300777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000779 EESR_ECI,
Sergei Shtylyovf5d12762013-06-07 13:58:18 +0000780
781 .apr = 1,
782 .mpr = 1,
783 .tpauser = 1,
784 .bculr = 1,
785 .hw_swap = 1,
786 .no_trimd = 1,
787 .no_ade = 1,
788 .tsu = 1,
789 .irq_flags = IRQF_SHARED,
790};
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000791
Sergei Shtylyove5c9b4c2013-06-07 13:57:12 +0000792static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000793{
794 struct sh_eth_private *mdp = netdev_priv(ndev);
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000795
796 /* reset device */
797 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
798 mdelay(1);
799
Nobuhiro Iwamatsu5e7a76b2012-06-25 17:34:14 +0000800 sh_eth_select_mii(ndev);
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000801}
802
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000803/* R8A7740 */
Sergei Shtylyove5c9b4c2013-06-07 13:57:12 +0000804static struct sh_eth_cpu_data r8a7740_data = {
805 .chip_reset = sh_eth_chip_reset_r8a7740,
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000806 .set_duplex = sh_eth_set_duplex,
Sergei Shtylyove5c9b4c2013-06-07 13:57:12 +0000807 .set_rate = sh_eth_set_rate_gether,
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000808
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400809 .register_type = SH_ETH_REG_GIGABIT,
810
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000811 .ecsr_value = ECSR_ICD | ECSR_MPD,
812 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
813 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
814
815 .tx_check = EESR_TC1 | EESR_FTC,
Sergei Shtylyovca8c3582013-06-21 01:12:21 +0400816 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
817 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
818 EESR_TDE | EESR_ECI,
Simon Hormancc235282013-10-10 14:51:16 +0900819 .fdr_value = 0x0000070f,
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000820
821 .apr = 1,
822 .mpr = 1,
823 .tpauser = 1,
824 .bculr = 1,
825 .hw_swap = 1,
Simon Hormancc235282013-10-10 14:51:16 +0900826 .rpadir = 1,
827 .rpadir_value = 2 << 16,
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000828 .no_trimd = 1,
829 .no_ade = 1,
830 .tsu = 1,
Nobuhiro Iwamatsu5e7a76b2012-06-25 17:34:14 +0000831 .select_mii = 1,
Sergei Shtylyovac8025a2013-06-13 22:12:45 +0400832 .shift_rd0 = 1,
Yoshihiro Shimoda73a0d902012-04-04 18:37:10 +0000833};
834
Sergei Shtylyovc18a79a2013-06-07 13:56:05 +0000835static struct sh_eth_cpu_data sh7619_data = {
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400836 .register_type = SH_ETH_REG_FAST_SH3_SH2,
837
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000838 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
839
840 .apr = 1,
841 .mpr = 1,
842 .tpauser = 1,
843 .hw_swap = 1,
844};
Sergei Shtylyov7bbe1502013-06-07 13:55:08 +0000845
846static struct sh_eth_cpu_data sh771x_data = {
Sergei Shtylyova3153d82013-08-18 03:11:28 +0400847 .register_type = SH_ETH_REG_FAST_SH3_SH2,
848
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000849 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
Yoshihiro Shimoda4986b992011-03-07 21:59:34 +0000850 .tsu = 1,
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000851};
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000852
853static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
854{
855 if (!cd->ecsr_value)
856 cd->ecsr_value = DEFAULT_ECSR_INIT;
857
858 if (!cd->ecsipr_value)
859 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
860
861 if (!cd->fcftr_value)
Sergei Shtylyov128296f2014-01-03 15:52:22 +0300862 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000863 DEFAULT_FIFO_F_D_RFD;
864
865 if (!cd->fdr_value)
866 cd->fdr_value = DEFAULT_FDR_INIT;
867
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000868 if (!cd->tx_check)
869 cd->tx_check = DEFAULT_TX_CHECK;
870
871 if (!cd->eesr_err_check)
872 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
Nobuhiro Iwamatsub284fbe2015-01-08 15:25:07 +0900873
874 if (!cd->trscer_err_mask)
875 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000876}
877
Nobuhiro Iwamatsu5cee1d32012-06-25 17:35:12 +0000878static int sh_eth_check_reset(struct net_device *ndev)
879{
880 int ret = 0;
881 int cnt = 100;
882
883 while (cnt > 0) {
884 if (!(sh_eth_read(ndev, EDMR) & 0x3))
885 break;
886 mdelay(1);
887 cnt--;
888 }
Sergei Shtylyov9f8c4262013-06-05 23:54:01 +0400889 if (cnt <= 0) {
Sergei Shtylyovf75f14e2014-03-15 03:27:54 +0300890 netdev_err(ndev, "Device reset failed\n");
Nobuhiro Iwamatsu5cee1d32012-06-25 17:35:12 +0000891 ret = -ETIMEDOUT;
892 }
893 return ret;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000894}
Nobuhiro Iwamatsudabdde92013-06-06 09:51:39 +0000895
896static int sh_eth_reset(struct net_device *ndev)
897{
898 struct sh_eth_private *mdp = netdev_priv(ndev);
899 int ret = 0;
900
Simon Hormandb893472014-01-17 09:22:28 +0900901 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
Nobuhiro Iwamatsudabdde92013-06-06 09:51:39 +0000902 sh_eth_write(ndev, EDSR_ENALL, EDSR);
903 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
904 EDMR);
905
906 ret = sh_eth_check_reset(ndev);
907 if (ret)
Laurent Pinchartf738a132014-03-20 15:00:35 +0100908 return ret;
Nobuhiro Iwamatsudabdde92013-06-06 09:51:39 +0000909
910 /* Table Init */
911 sh_eth_write(ndev, 0x0, TDLAR);
912 sh_eth_write(ndev, 0x0, TDFAR);
913 sh_eth_write(ndev, 0x0, TDFXR);
914 sh_eth_write(ndev, 0x0, TDFFR);
915 sh_eth_write(ndev, 0x0, RDLAR);
916 sh_eth_write(ndev, 0x0, RDFAR);
917 sh_eth_write(ndev, 0x0, RDFXR);
918 sh_eth_write(ndev, 0x0, RDFFR);
919
920 /* Reset HW CRC register */
921 if (mdp->cd->hw_crc)
922 sh_eth_write(ndev, 0x0, CSMR);
923
924 /* Select MII mode */
925 if (mdp->cd->select_mii)
926 sh_eth_select_mii(ndev);
927 } else {
928 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
929 EDMR);
930 mdelay(3);
931 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
932 EDMR);
933 }
934
Nobuhiro Iwamatsudabdde92013-06-06 09:51:39 +0000935 return ret;
936}
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000937
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000938static void sh_eth_set_receive_align(struct sk_buff *skb)
939{
Mitsuhiro Kimura4d6a9492014-11-27 20:34:00 +0900940 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000941
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000942 if (reserve)
Mitsuhiro Kimura4d6a9492014-11-27 20:34:00 +0900943 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000944}
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +0000945
946
Yoshinori Sato71557a32008-08-06 19:49:00 -0400947/* CPU <-> EDMAC endian convert */
948static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
949{
950 switch (mdp->edmac_endian) {
951 case EDMAC_LITTLE_ENDIAN:
952 return cpu_to_le32(x);
953 case EDMAC_BIG_ENDIAN:
954 return cpu_to_be32(x);
955 }
956 return x;
957}
958
959static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
960{
961 switch (mdp->edmac_endian) {
962 case EDMAC_LITTLE_ENDIAN:
963 return le32_to_cpu(x);
964 case EDMAC_BIG_ENDIAN:
965 return be32_to_cpu(x);
966 }
967 return x;
968}
969
Sergei Shtylyov128296f2014-01-03 15:52:22 +0300970/* Program the hardware MAC address from dev->dev_addr. */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700971static void update_mac_address(struct net_device *ndev)
972{
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000973 sh_eth_write(ndev,
Sergei Shtylyov128296f2014-01-03 15:52:22 +0300974 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
975 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000976 sh_eth_write(ndev,
Sergei Shtylyov128296f2014-01-03 15:52:22 +0300977 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700978}
979
Sergei Shtylyov128296f2014-01-03 15:52:22 +0300980/* Get MAC address from SuperH MAC address register
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700981 *
982 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
983 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
984 * When you want use this device, you must set MAC address in bootloader.
985 *
986 */
Magnus Damm748031f2009-10-09 00:17:14 +0000987static void read_mac_address(struct net_device *ndev, unsigned char *mac)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700988{
Magnus Damm748031f2009-10-09 00:17:14 +0000989 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
Joe Perchesd458cdf2013-10-01 19:04:40 -0700990 memcpy(ndev->dev_addr, mac, ETH_ALEN);
Magnus Damm748031f2009-10-09 00:17:14 +0000991 } else {
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +0000992 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
993 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
994 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
995 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
996 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
997 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
Magnus Damm748031f2009-10-09 00:17:14 +0000998 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700999}
1000
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +01001001static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00001002{
Simon Hormandb893472014-01-17 09:22:28 +09001003 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00001004 return EDTRR_TRNS_GETHER;
1005 else
1006 return EDTRR_TRNS_ETHER;
1007}
1008
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001009struct bb_info {
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001010 void (*set_gate)(void *addr);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001011 struct mdiobb_ctrl ctrl;
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001012 void *addr;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001013 u32 mmd_msk;/* MMD */
1014 u32 mdo_msk;
1015 u32 mdi_msk;
1016 u32 mdc_msk;
1017};
1018
1019/* PHY bit set */
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001020static void bb_set(void *addr, u32 msk)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001021{
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001022 iowrite32(ioread32(addr) | msk, addr);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001023}
1024
1025/* PHY bit clear */
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001026static void bb_clr(void *addr, u32 msk)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001027{
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001028 iowrite32((ioread32(addr) & ~msk), addr);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001029}
1030
1031/* PHY bit read */
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001032static int bb_read(void *addr, u32 msk)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001033{
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00001034 return (ioread32(addr) & msk) != 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001035}
1036
1037/* Data I/O pin control */
1038static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1039{
1040 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
Yoshihiro Shimodab3017e62011-03-07 21:59:55 +00001041
1042 if (bitbang->set_gate)
1043 bitbang->set_gate(bitbang->addr);
1044
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001045 if (bit)
1046 bb_set(bitbang->addr, bitbang->mmd_msk);
1047 else
1048 bb_clr(bitbang->addr, bitbang->mmd_msk);
1049}
1050
1051/* Set bit data*/
1052static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1053{
1054 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1055
Yoshihiro Shimodab3017e62011-03-07 21:59:55 +00001056 if (bitbang->set_gate)
1057 bitbang->set_gate(bitbang->addr);
1058
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001059 if (bit)
1060 bb_set(bitbang->addr, bitbang->mdo_msk);
1061 else
1062 bb_clr(bitbang->addr, bitbang->mdo_msk);
1063}
1064
1065/* Get bit data*/
1066static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1067{
1068 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
Yoshihiro Shimodab3017e62011-03-07 21:59:55 +00001069
1070 if (bitbang->set_gate)
1071 bitbang->set_gate(bitbang->addr);
1072
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001073 return bb_read(bitbang->addr, bitbang->mdi_msk);
1074}
1075
1076/* MDC pin control */
1077static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1078{
1079 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1080
Yoshihiro Shimodab3017e62011-03-07 21:59:55 +00001081 if (bitbang->set_gate)
1082 bitbang->set_gate(bitbang->addr);
1083
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001084 if (bit)
1085 bb_set(bitbang->addr, bitbang->mdc_msk);
1086 else
1087 bb_clr(bitbang->addr, bitbang->mdc_msk);
1088}
1089
1090/* mdio bus control struct */
1091static struct mdiobb_ops bb_ops = {
1092 .owner = THIS_MODULE,
1093 .set_mdc = sh_mdc_ctrl,
1094 .set_mdio_dir = sh_mmd_ctrl,
1095 .set_mdio_data = sh_set_mdio,
1096 .get_mdio_data = sh_get_mdio,
1097};
1098
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001099/* free skb and descriptor buffer */
1100static void sh_eth_ring_free(struct net_device *ndev)
1101{
1102 struct sh_eth_private *mdp = netdev_priv(ndev);
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03001103 int ringsize, i;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001104
1105 /* Free Rx skb ringbuffer */
1106 if (mdp->rx_skbuff) {
Sergei Shtylyov179d80a2014-06-28 04:10:00 +04001107 for (i = 0; i < mdp->num_rx_ring; i++)
1108 dev_kfree_skb(mdp->rx_skbuff[i]);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001109 }
1110 kfree(mdp->rx_skbuff);
Yoshihiro Shimoda91c77552012-06-26 20:00:01 +00001111 mdp->rx_skbuff = NULL;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001112
1113 /* Free Tx skb ringbuffer */
1114 if (mdp->tx_skbuff) {
Sergei Shtylyov179d80a2014-06-28 04:10:00 +04001115 for (i = 0; i < mdp->num_tx_ring; i++)
1116 dev_kfree_skb(mdp->tx_skbuff[i]);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001117 }
1118 kfree(mdp->tx_skbuff);
Yoshihiro Shimoda91c77552012-06-26 20:00:01 +00001119 mdp->tx_skbuff = NULL;
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03001120
1121 if (mdp->rx_ring) {
1122 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1123 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1124 mdp->rx_desc_dma);
1125 mdp->rx_ring = NULL;
1126 }
1127
1128 if (mdp->tx_ring) {
1129 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1130 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1131 mdp->tx_desc_dma);
1132 mdp->tx_ring = NULL;
1133 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001134}
1135
1136/* format skb and descriptor buffer */
1137static void sh_eth_ring_format(struct net_device *ndev)
1138{
1139 struct sh_eth_private *mdp = netdev_priv(ndev);
1140 int i;
1141 struct sk_buff *skb;
1142 struct sh_eth_rxdesc *rxdesc = NULL;
1143 struct sh_eth_txdesc *txdesc = NULL;
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001144 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1145 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
Sergei Shtylyovcb368592015-10-24 00:46:40 +03001146 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001147 dma_addr_t dma_addr;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001148
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001149 mdp->cur_rx = 0;
1150 mdp->cur_tx = 0;
1151 mdp->dirty_rx = 0;
1152 mdp->dirty_tx = 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001153
1154 memset(mdp->rx_ring, 0, rx_ringsize);
1155
1156 /* build Rx ring buffer */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001157 for (i = 0; i < mdp->num_rx_ring; i++) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001158 /* skb */
1159 mdp->rx_skbuff[i] = NULL;
Mitsuhiro Kimura4d6a9492014-11-27 20:34:00 +09001160 skb = netdev_alloc_skb(ndev, skbuff_size);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001161 if (skb == NULL)
1162 break;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001163 sh_eth_set_receive_align(skb);
1164
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001165 /* RX descriptor */
1166 rxdesc = &mdp->rx_ring[i];
Sergei Shtylyovab857912015-10-24 00:46:03 +03001167 /* The size of the buffer is a multiple of 32 bytes. */
1168 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001169 dma_addr = dma_map_single(&ndev->dev, skb->data,
1170 rxdesc->buffer_length,
1171 DMA_FROM_DEVICE);
1172 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1173 kfree_skb(skb);
1174 break;
1175 }
1176 mdp->rx_skbuff[i] = skb;
1177 rxdesc->addr = dma_addr;
Yoshinori Sato71557a32008-08-06 19:49:00 -04001178 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001179
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001180 /* Rx descriptor address set */
1181 if (i == 0) {
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001182 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
Simon Hormandb893472014-01-17 09:22:28 +09001183 if (sh_eth_is_gether(mdp) ||
1184 sh_eth_is_rz_fast_ether(mdp))
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00001185 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001186 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001187 }
1188
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001189 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001190
1191 /* Mark the last entry as wrapping the ring. */
Sergei Shtylyovc2380412015-11-03 01:28:07 +03001192 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001193
1194 memset(mdp->tx_ring, 0, tx_ringsize);
1195
1196 /* build Tx ring buffer */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001197 for (i = 0; i < mdp->num_tx_ring; i++) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001198 mdp->tx_skbuff[i] = NULL;
1199 txdesc = &mdp->tx_ring[i];
Yoshinori Sato71557a32008-08-06 19:49:00 -04001200 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001201 txdesc->buffer_length = 0;
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001202 if (i == 0) {
Yoshinori Sato71557a32008-08-06 19:49:00 -04001203 /* Tx descriptor address set */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001204 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
Simon Hormandb893472014-01-17 09:22:28 +09001205 if (sh_eth_is_gether(mdp) ||
1206 sh_eth_is_rz_fast_ether(mdp))
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00001207 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001208 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001209 }
1210
Yoshinori Sato71557a32008-08-06 19:49:00 -04001211 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001212}
1213
1214/* Get skb and descriptor buffer */
1215static int sh_eth_ring_init(struct net_device *ndev)
1216{
1217 struct sh_eth_private *mdp = netdev_priv(ndev);
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001218 int rx_ringsize, tx_ringsize;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001219
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001220 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001221 * card needs room to do 8 byte alignment, +2 so we can reserve
1222 * the first 2 bytes, and +16 gets room for the status word from the
1223 * card.
1224 */
1225 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1226 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
Magnus Damm503914c2009-12-15 21:16:55 -08001227 if (mdp->cd->rpadir)
1228 mdp->rx_buf_sz += NET_IP_ALIGN;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001229
1230 /* Allocate RX and TX skb rings */
Sergei Shtylyov2c94e852015-10-31 02:05:56 +03001231 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1232 GFP_KERNEL);
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001233 if (!mdp->rx_skbuff)
1234 return -ENOMEM;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001235
Sergei Shtylyov2c94e852015-10-31 02:05:56 +03001236 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1237 GFP_KERNEL);
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001238 if (!mdp->tx_skbuff)
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03001239 goto ring_free;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001240
1241 /* Allocate all Rx descriptors. */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001242 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001243 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
Joe Perchesd0320f72013-03-14 13:07:21 +00001244 GFP_KERNEL);
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001245 if (!mdp->rx_ring)
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03001246 goto ring_free;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001247
1248 mdp->dirty_rx = 0;
1249
1250 /* Allocate all Tx descriptors. */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001251 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001252 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
Joe Perchesd0320f72013-03-14 13:07:21 +00001253 GFP_KERNEL);
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001254 if (!mdp->tx_ring)
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03001255 goto ring_free;
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001256 return 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001257
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03001258ring_free:
1259 /* Free Rx and Tx skb ring buffer and DMA buffer */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001260 sh_eth_ring_free(ndev);
1261
Sergei Shtylyov91d80682015-11-04 00:17:08 +03001262 return -ENOMEM;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001263}
1264
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001265static int sh_eth_dev_init(struct net_device *ndev, bool start)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001266{
1267 int ret = 0;
1268 struct sh_eth_private *mdp = netdev_priv(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001269 u32 val;
1270
1271 /* Soft Reset */
Nobuhiro Iwamatsu5cee1d32012-06-25 17:35:12 +00001272 ret = sh_eth_reset(ndev);
1273 if (ret)
Laurent Pinchartf738a132014-03-20 15:00:35 +01001274 return ret;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001275
Simon Horman55754f12013-07-23 10:18:04 +09001276 if (mdp->cd->rmiimode)
1277 sh_eth_write(ndev, 0x1, RMIIMODE);
1278
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001279 /* Descriptor format */
1280 sh_eth_ring_format(ndev);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001281 if (mdp->cd->rpadir)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001282 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001283
1284 /* all sh_eth int mask */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001285 sh_eth_write(ndev, 0, EESIPR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001286
Yoshihiro Shimoda10b91942012-03-29 19:32:08 +00001287#if defined(__LITTLE_ENDIAN)
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001288 if (mdp->cd->hw_swap)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001289 sh_eth_write(ndev, EDMR_EL, EDMR);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001290 else
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001291#endif
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001292 sh_eth_write(ndev, 0, EDMR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001293
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001294 /* FIFO size set */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001295 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1296 sh_eth_write(ndev, 0, TFTR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001297
Ben Dooks530aa2d2014-06-03 12:21:13 +01001298 /* Frame recv control (enable multiple-packets per rx irq) */
1299 sh_eth_write(ndev, RMCR_RNC, RMCR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001300
Nobuhiro Iwamatsub284fbe2015-01-08 15:25:07 +09001301 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001302
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001303 if (mdp->cd->bculr)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001304 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001305
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001306 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001307
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001308 if (!mdp->cd->no_trimd)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001309 sh_eth_write(ndev, 0, TRIMD);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001310
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001311 /* Recv frame limit set register */
Yoshihiro Shimodafdb37a72012-02-06 23:55:15 +00001312 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1313 RFLR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001314
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001315 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
Ben Hutchings283e38d2015-01-22 12:44:08 +00001316 if (start) {
1317 mdp->irq_enabled = true;
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001318 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
Ben Hutchings283e38d2015-01-22 12:44:08 +00001319 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001320
1321 /* PAUSE Prohibition */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001322 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001323 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1324
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001325 sh_eth_write(ndev, val, ECMR);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001326
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001327 if (mdp->cd->set_rate)
1328 mdp->cd->set_rate(ndev);
1329
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001330 /* E-MAC Status Register clear */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001331 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001332
1333 /* E-MAC Interrupt Enable register */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001334 if (start)
1335 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001336
1337 /* Set MAC address */
1338 update_mac_address(ndev);
1339
1340 /* mask reset */
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001341 if (mdp->cd->apr)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001342 sh_eth_write(ndev, APR_AP, APR);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001343 if (mdp->cd->mpr)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001344 sh_eth_write(ndev, MPR_MP, MPR);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001345 if (mdp->cd->tpauser)
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001346 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001347
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001348 if (start) {
1349 /* Setting the Rx mode will start the Rx process. */
1350 sh_eth_write(ndev, EDRRR_R, EDRRR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001351
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001352 netif_start_queue(ndev);
1353 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001354
1355 return ret;
1356}
1357
Ben Hutchings740c7f32015-01-27 00:49:32 +00001358static void sh_eth_dev_exit(struct net_device *ndev)
1359{
1360 struct sh_eth_private *mdp = netdev_priv(ndev);
1361 int i;
1362
1363 /* Deactivate all TX descriptors, so DMA should stop at next
1364 * packet boundary if it's currently running
1365 */
1366 for (i = 0; i < mdp->num_tx_ring; i++)
1367 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1368
1369 /* Disable TX FIFO egress to MAC */
1370 sh_eth_rcv_snd_disable(ndev);
1371
1372 /* Stop RX DMA at next packet boundary */
1373 sh_eth_write(ndev, 0, EDRRR);
1374
1375 /* Aside from TX DMA, we can't tell when the hardware is
1376 * really stopped, so we need to reset to make sure.
1377 * Before doing that, wait for long enough to *probably*
1378 * finish transmitting the last packet and poll stats.
1379 */
1380 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1381 sh_eth_get_stats(ndev);
1382 sh_eth_reset(ndev);
Geert Uytterhoevena14c7d12015-02-27 17:16:26 +01001383
1384 /* Set MAC address again */
1385 update_mac_address(ndev);
Ben Hutchings740c7f32015-01-27 00:49:32 +00001386}
1387
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001388/* free Tx skb function */
1389static int sh_eth_txfree(struct net_device *ndev)
1390{
1391 struct sh_eth_private *mdp = netdev_priv(ndev);
1392 struct sh_eth_txdesc *txdesc;
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001393 int free_num = 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001394 int entry = 0;
1395
1396 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001397 entry = mdp->dirty_tx % mdp->num_tx_ring;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001398 txdesc = &mdp->tx_ring[entry];
Yoshinori Sato71557a32008-08-06 19:49:00 -04001399 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001400 break;
Ben Hutchings7d7355f2015-03-03 00:52:00 +00001401 /* TACT bit must be checked before all the following reads */
Sergei Shtylyovf32bfb92015-11-03 22:36:04 +03001402 dma_rmb();
Ben Hutchingse5fd13f2015-02-26 20:34:46 +00001403 netif_info(mdp, tx_done, ndev,
1404 "tx entry %d status 0x%08x\n",
1405 entry, edmac_to_cpu(mdp, txdesc->status));
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001406 /* Free the original skb. */
1407 if (mdp->tx_skbuff[entry]) {
Yoshihiro Shimoda31fcb992011-06-30 22:52:13 +00001408 dma_unmap_single(&ndev->dev, txdesc->addr,
1409 txdesc->buffer_length, DMA_TO_DEVICE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001410 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1411 mdp->tx_skbuff[entry] = NULL;
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001412 free_num++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001413 }
Yoshinori Sato71557a32008-08-06 19:49:00 -04001414 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001415 if (entry >= mdp->num_tx_ring - 1)
Yoshinori Sato71557a32008-08-06 19:49:00 -04001416 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001417
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001418 ndev->stats.tx_packets++;
1419 ndev->stats.tx_bytes += txdesc->buffer_length;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001420 }
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001421 return free_num;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001422}
1423
1424/* Packet receive function */
Sergei Shtylyov37191092013-06-19 23:30:23 +04001425static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001426{
1427 struct sh_eth_private *mdp = netdev_priv(ndev);
1428 struct sh_eth_rxdesc *rxdesc;
1429
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001430 int entry = mdp->cur_rx % mdp->num_rx_ring;
1431 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
Mitsuhiro Kimura319cd522014-12-09 21:23:42 +09001432 int limit;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001433 struct sk_buff *skb;
1434 u16 pkt_len = 0;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001435 u32 desc_status;
Sergei Shtylyovcb368592015-10-24 00:46:40 +03001436 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001437 dma_addr_t dma_addr;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001438
Mitsuhiro Kimura319cd522014-12-09 21:23:42 +09001439 boguscnt = min(boguscnt, *quota);
1440 limit = boguscnt;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001441 rxdesc = &mdp->rx_ring[entry];
Yoshinori Sato71557a32008-08-06 19:49:00 -04001442 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
Ben Hutchings7d7355f2015-03-03 00:52:00 +00001443 /* RACT bit must be checked before all the following reads */
Sergei Shtylyovf32bfb92015-11-03 22:36:04 +03001444 dma_rmb();
Yoshinori Sato71557a32008-08-06 19:49:00 -04001445 desc_status = edmac_to_cpu(mdp, rxdesc->status);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001446 pkt_len = rxdesc->frame_length;
1447
1448 if (--boguscnt < 0)
1449 break;
1450
Ben Hutchingse5fd13f2015-02-26 20:34:46 +00001451 netif_info(mdp, rx_status, ndev,
1452 "rx entry %d status 0x%08x len %d\n",
1453 entry, desc_status, pkt_len);
1454
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001455 if (!(desc_status & RDFEND))
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001456 ndev->stats.rx_length_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001457
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001458 /* In case of almost all GETHER/ETHERs, the Receive Frame State
Yoshihiro Shimodadd019892013-06-13 10:15:45 +09001459 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
Ben Hutchings9b4a6362015-03-03 00:52:39 +00001460 * bit 0. However, in case of the R8A7740 and R7S72100
1461 * the RFS bits are from bit 25 to bit 16. So, the
Simon Hormandb893472014-01-17 09:22:28 +09001462 * driver needs right shifting by 16.
Yoshihiro Shimodadd019892013-06-13 10:15:45 +09001463 */
Sergei Shtylyovac8025a2013-06-13 22:12:45 +04001464 if (mdp->cd->shift_rd0)
1465 desc_status >>= 16;
Yoshihiro Shimodadd019892013-06-13 10:15:45 +09001466
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001467 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1468 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001469 ndev->stats.rx_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001470 if (desc_status & RD_RFS1)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001471 ndev->stats.rx_crc_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001472 if (desc_status & RD_RFS2)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001473 ndev->stats.rx_frame_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001474 if (desc_status & RD_RFS3)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001475 ndev->stats.rx_length_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001476 if (desc_status & RD_RFS4)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001477 ndev->stats.rx_length_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001478 if (desc_status & RD_RFS6)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001479 ndev->stats.rx_missed_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001480 if (desc_status & RD_RFS10)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001481 ndev->stats.rx_over_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001482 } else {
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001483 if (!mdp->cd->hw_swap)
1484 sh_eth_soft_swap(
1485 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1486 pkt_len + 2);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001487 skb = mdp->rx_skbuff[entry];
1488 mdp->rx_skbuff[entry] = NULL;
Magnus Damm503914c2009-12-15 21:16:55 -08001489 if (mdp->cd->rpadir)
1490 skb_reserve(skb, NET_IP_ALIGN);
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001491 dma_unmap_single(&ndev->dev, rxdesc->addr,
Sergei Shtylyovab857912015-10-24 00:46:03 +03001492 ALIGN(mdp->rx_buf_sz, 32),
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001493 DMA_FROM_DEVICE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001494 skb_put(skb, pkt_len);
1495 skb->protocol = eth_type_trans(skb, ndev);
Sergei Shtylyova8e9fd02013-09-03 03:03:10 +04001496 netif_receive_skb(skb);
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001497 ndev->stats.rx_packets++;
1498 ndev->stats.rx_bytes += pkt_len;
Ben Hutchings25b77ad2015-02-26 20:33:30 +00001499 if (desc_status & RD_RFS8)
1500 ndev->stats.multicast++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001501 }
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001502 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
Yoshihiro Shimoda862df492009-05-24 23:53:40 +00001503 rxdesc = &mdp->rx_ring[entry];
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001504 }
1505
1506 /* Refill the Rx ring buffers. */
1507 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001508 entry = mdp->dirty_rx % mdp->num_rx_ring;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001509 rxdesc = &mdp->rx_ring[entry];
Sergei Shtylyovab857912015-10-24 00:46:03 +03001510 /* The size of the buffer is 32 byte boundary. */
1511 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001512
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001513 if (mdp->rx_skbuff[entry] == NULL) {
Mitsuhiro Kimura4d6a9492014-11-27 20:34:00 +09001514 skb = netdev_alloc_skb(ndev, skbuff_size);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001515 if (skb == NULL)
1516 break; /* Better luck next round. */
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001517 sh_eth_set_receive_align(skb);
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001518 dma_addr = dma_map_single(&ndev->dev, skb->data,
1519 rxdesc->buffer_length,
1520 DMA_FROM_DEVICE);
1521 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1522 kfree_skb(skb);
1523 break;
1524 }
1525 mdp->rx_skbuff[entry] = skb;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001526
Eric Dumazetbc8acf22010-09-02 13:07:41 -07001527 skb_checksum_none_assert(skb);
Ben Hutchings52b9fa32015-01-27 00:50:24 +00001528 rxdesc->addr = dma_addr;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001529 }
Sergei Shtylyovf32bfb92015-11-03 22:36:04 +03001530 dma_wmb(); /* RACT bit must be set after all the above writes */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00001531 if (entry >= mdp->num_rx_ring - 1)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001532 rxdesc->status |=
Sergei Shtylyovc2380412015-11-03 01:28:07 +03001533 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001534 else
1535 rxdesc->status |=
Yoshinori Sato71557a32008-08-06 19:49:00 -04001536 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001537 }
1538
1539 /* Restart Rx engine if stopped. */
1540 /* If we don't need to check status, don't. -KDU */
Yoshihiro Shimoda79fba9f2012-05-28 23:07:55 +00001541 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
Yoshihiro Shimodaa18e08b2012-06-20 15:26:34 +00001542 /* fix the values for the next receiving if RDE is set */
Ben Hutchings33657112015-02-26 20:34:14 +00001543 if (intr_status & EESR_RDE &&
1544 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001545 u32 count = (sh_eth_read(ndev, RDFAR) -
1546 sh_eth_read(ndev, RDLAR)) >> 4;
1547
1548 mdp->cur_rx = count;
1549 mdp->dirty_rx = count;
1550 }
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001551 sh_eth_write(ndev, EDRRR_R, EDRRR);
Yoshihiro Shimoda79fba9f2012-05-28 23:07:55 +00001552 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001553
Mitsuhiro Kimura319cd522014-12-09 21:23:42 +09001554 *quota -= limit - boguscnt - 1;
1555
Yoshihiro Shimoda4f809ce2014-06-10 09:40:14 +09001556 return *quota <= 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001557}
1558
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001559static void sh_eth_rcv_snd_disable(struct net_device *ndev)
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001560{
1561 /* disable tx and rx */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001562 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1563 ~(ECMR_RE | ECMR_TE), ECMR);
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001564}
1565
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001566static void sh_eth_rcv_snd_enable(struct net_device *ndev)
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001567{
1568 /* enable tx and rx */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001569 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1570 (ECMR_RE | ECMR_TE), ECMR);
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001571}
1572
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001573/* error control function */
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +01001574static void sh_eth_error(struct net_device *ndev, u32 intr_status)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001575{
1576 struct sh_eth_private *mdp = netdev_priv(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001577 u32 felic_stat;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001578 u32 link_stat;
1579 u32 mask;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001580
1581 if (intr_status & EESR_ECI) {
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001582 felic_stat = sh_eth_read(ndev, ECSR);
1583 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001584 if (felic_stat & ECSR_ICD)
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001585 ndev->stats.tx_carrier_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001586 if (felic_stat & ECSR_LCHNG) {
1587 /* Link Changed */
Yoshihiro Shimoda49235762009-08-27 23:25:03 +00001588 if (mdp->cd->no_psr || mdp->no_ether_link) {
Sergei Shtylyov1e1b8122013-03-31 09:50:07 +00001589 goto ignore_link;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001590 } else {
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001591 link_stat = (sh_eth_read(ndev, PSR));
Yoshihiro Shimoda49235762009-08-27 23:25:03 +00001592 if (mdp->ether_link_active_low)
1593 link_stat = ~link_stat;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001594 }
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001595 if (!(link_stat & PHY_ST_LINK)) {
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001596 sh_eth_rcv_snd_disable(ndev);
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001597 } else {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001598 /* Link Up */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001599 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001600 ~DMAC_M_ECI, EESIPR);
1601 /* clear int */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001602 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001603 ECSR);
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001604 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001605 DMAC_M_ECI, EESIPR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001606 /* enable tx and rx */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001607 sh_eth_rcv_snd_enable(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001608 }
1609 }
1610 }
1611
Sergei Shtylyov1e1b8122013-03-31 09:50:07 +00001612ignore_link:
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001613 if (intr_status & EESR_TWB) {
Sergei Shtylyov4eb313a2013-06-21 01:13:42 +04001614 /* Unused write back interrupt */
1615 if (intr_status & EESR_TABT) { /* Transmit Abort int */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001616 ndev->stats.tx_aborted_errors++;
Sergei Shtylyov8d5009f2014-03-15 03:30:59 +03001617 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
Sergei Shtylyov4eb313a2013-06-21 01:13:42 +04001618 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001619 }
1620
1621 if (intr_status & EESR_RABT) {
1622 /* Receive Abort int */
1623 if (intr_status & EESR_RFRMER) {
1624 /* Receive Frame Overflow int */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001625 ndev->stats.rx_frame_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001626 }
1627 }
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001628
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001629 if (intr_status & EESR_TDE) {
1630 /* Transmit Descriptor Empty int */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001631 ndev->stats.tx_fifo_errors++;
Sergei Shtylyov8d5009f2014-03-15 03:30:59 +03001632 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001633 }
1634
1635 if (intr_status & EESR_TFE) {
1636 /* FIFO under flow */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001637 ndev->stats.tx_fifo_errors++;
Sergei Shtylyov8d5009f2014-03-15 03:30:59 +03001638 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001639 }
1640
1641 if (intr_status & EESR_RDE) {
1642 /* Receive Descriptor Empty int */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001643 ndev->stats.rx_over_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001644 }
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001645
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001646 if (intr_status & EESR_RFE) {
1647 /* Receive FIFO Overflow int */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001648 ndev->stats.rx_fifo_errors++;
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001649 }
1650
1651 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1652 /* Address Error */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00001653 ndev->stats.tx_fifo_errors++;
Sergei Shtylyov8d5009f2014-03-15 03:30:59 +03001654 netif_err(mdp, tx_err, ndev, "Address Error\n");
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001655 }
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001656
1657 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1658 if (mdp->cd->no_ade)
1659 mask &= ~EESR_ADE;
1660 if (intr_status & mask) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001661 /* Tx error */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001662 u32 edtrr = sh_eth_read(ndev, EDTRR);
Sergei Shtylyov090d5602014-01-11 02:41:49 +03001663
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001664 /* dmesg */
Sergei Shtylyovda246852014-03-15 03:29:14 +03001665 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1666 intr_status, mdp->cur_tx, mdp->dirty_tx,
1667 (u32)ndev->state, edtrr);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001668 /* dirty buffer free */
1669 sh_eth_txfree(ndev);
1670
1671 /* SH7712 BUG */
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00001672 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001673 /* tx dma start */
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00001674 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001675 }
1676 /* wakeup */
1677 netif_wake_queue(ndev);
1678 }
1679}
1680
1681static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1682{
1683 struct net_device *ndev = netdev;
1684 struct sh_eth_private *mdp = netdev_priv(ndev);
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001685 struct sh_eth_cpu_data *cd = mdp->cd;
Nobuhiro Iwamatsu0e0fde32009-03-16 19:50:57 +00001686 irqreturn_t ret = IRQ_NONE;
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +01001687 u32 intr_status, intr_enable;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001688
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001689 spin_lock(&mdp->lock);
1690
Sergei Shtylyov3893b273452013-03-31 09:54:20 +00001691 /* Get interrupt status */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001692 intr_status = sh_eth_read(ndev, EESR);
Sergei Shtylyov3893b273452013-03-31 09:54:20 +00001693 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1694 * enabled since it's the one that comes thru regardless of the mask,
1695 * and we need to fully handle it in sh_eth_error() in order to quench
1696 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1697 */
Sergei Shtylyov37191092013-06-19 23:30:23 +04001698 intr_enable = sh_eth_read(ndev, EESIPR);
1699 intr_status &= intr_enable | DMAC_M_ECI;
1700 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
Nobuhiro Iwamatsu0e0fde32009-03-16 19:50:57 +00001701 ret = IRQ_HANDLED;
Sergei Shtylyov37191092013-06-19 23:30:23 +04001702 else
Ben Hutchings283e38d2015-01-22 12:44:08 +00001703 goto out;
1704
1705 if (!likely(mdp->irq_enabled)) {
1706 sh_eth_write(ndev, 0, EESIPR);
1707 goto out;
1708 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001709
Sergei Shtylyov37191092013-06-19 23:30:23 +04001710 if (intr_status & EESR_RX_CHECK) {
1711 if (napi_schedule_prep(&mdp->napi)) {
1712 /* Mask Rx interrupts */
1713 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1714 EESIPR);
1715 __napi_schedule(&mdp->napi);
1716 } else {
Sergei Shtylyovda246852014-03-15 03:29:14 +03001717 netdev_warn(ndev,
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +01001718 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
Sergei Shtylyovda246852014-03-15 03:29:14 +03001719 intr_status, intr_enable);
Sergei Shtylyov37191092013-06-19 23:30:23 +04001720 }
1721 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001722
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09001723 /* Tx Check */
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001724 if (intr_status & cd->tx_check) {
Sergei Shtylyov37191092013-06-19 23:30:23 +04001725 /* Clear Tx interrupts */
1726 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1727
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001728 sh_eth_txfree(ndev);
1729 netif_wake_queue(ndev);
1730 }
1731
Sergei Shtylyov37191092013-06-19 23:30:23 +04001732 if (intr_status & cd->eesr_err_check) {
1733 /* Clear error interrupts */
1734 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1735
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001736 sh_eth_error(ndev, intr_status);
Sergei Shtylyov37191092013-06-19 23:30:23 +04001737 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001738
Ben Hutchings283e38d2015-01-22 12:44:08 +00001739out:
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001740 spin_unlock(&mdp->lock);
1741
Nobuhiro Iwamatsu0e0fde32009-03-16 19:50:57 +00001742 return ret;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001743}
1744
Sergei Shtylyov37191092013-06-19 23:30:23 +04001745static int sh_eth_poll(struct napi_struct *napi, int budget)
1746{
1747 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1748 napi);
1749 struct net_device *ndev = napi->dev;
1750 int quota = budget;
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +01001751 u32 intr_status;
Sergei Shtylyov37191092013-06-19 23:30:23 +04001752
1753 for (;;) {
1754 intr_status = sh_eth_read(ndev, EESR);
1755 if (!(intr_status & EESR_RX_CHECK))
1756 break;
1757 /* Clear Rx interrupts */
1758 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1759
1760 if (sh_eth_rx(ndev, intr_status, &quota))
1761 goto out;
1762 }
1763
1764 napi_complete(napi);
1765
1766 /* Reenable Rx interrupts */
Ben Hutchings283e38d2015-01-22 12:44:08 +00001767 if (mdp->irq_enabled)
1768 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
Sergei Shtylyov37191092013-06-19 23:30:23 +04001769out:
1770 return budget - quota;
1771}
1772
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001773/* PHY state control function */
1774static void sh_eth_adjust_link(struct net_device *ndev)
1775{
1776 struct sh_eth_private *mdp = netdev_priv(ndev);
1777 struct phy_device *phydev = mdp->phydev;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001778 int new_state = 0;
1779
Sergei Shtylyov3340d2a2013-03-31 10:11:04 +00001780 if (phydev->link) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001781 if (phydev->duplex != mdp->duplex) {
1782 new_state = 1;
1783 mdp->duplex = phydev->duplex;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001784 if (mdp->cd->set_duplex)
1785 mdp->cd->set_duplex(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001786 }
1787
1788 if (phydev->speed != mdp->speed) {
1789 new_state = 1;
1790 mdp->speed = phydev->speed;
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001791 if (mdp->cd->set_rate)
1792 mdp->cd->set_rate(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001793 }
Sergei Shtylyov3340d2a2013-03-31 10:11:04 +00001794 if (!mdp->link) {
Yoshihiro Shimoda91a56152011-07-05 20:33:51 +00001795 sh_eth_write(ndev,
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001796 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1797 ECMR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001798 new_state = 1;
1799 mdp->link = phydev->link;
Sergei Shtylyov1e1b8122013-03-31 09:50:07 +00001800 if (mdp->cd->no_psr || mdp->no_ether_link)
1801 sh_eth_rcv_snd_enable(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001802 }
1803 } else if (mdp->link) {
1804 new_state = 1;
Sergei Shtylyov3340d2a2013-03-31 10:11:04 +00001805 mdp->link = 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001806 mdp->speed = 0;
1807 mdp->duplex = -1;
Sergei Shtylyov1e1b8122013-03-31 09:50:07 +00001808 if (mdp->cd->no_psr || mdp->no_ether_link)
1809 sh_eth_rcv_snd_disable(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001810 }
1811
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001812 if (new_state && netif_msg_link(mdp))
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001813 phy_print_status(phydev);
1814}
1815
1816/* PHY init function */
1817static int sh_eth_phy_init(struct net_device *ndev)
1818{
Ben Dooks702eca02014-03-12 17:47:40 +00001819 struct device_node *np = ndev->dev.parent->of_node;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001820 struct sh_eth_private *mdp = netdev_priv(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001821 struct phy_device *phydev = NULL;
1822
Sergei Shtylyov3340d2a2013-03-31 10:11:04 +00001823 mdp->link = 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001824 mdp->speed = 0;
1825 mdp->duplex = -1;
1826
1827 /* Try connect to PHY */
Ben Dooks702eca02014-03-12 17:47:40 +00001828 if (np) {
1829 struct device_node *pn;
1830
1831 pn = of_parse_phandle(np, "phy-handle", 0);
1832 phydev = of_phy_connect(ndev, pn,
1833 sh_eth_adjust_link, 0,
1834 mdp->phy_interface);
1835
1836 if (!phydev)
1837 phydev = ERR_PTR(-ENOENT);
1838 } else {
1839 char phy_id[MII_BUS_ID_SIZE + 3];
1840
1841 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1842 mdp->mii_bus->id, mdp->phy_id);
1843
1844 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1845 mdp->phy_interface);
1846 }
1847
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001848 if (IS_ERR(phydev)) {
Sergei Shtylyovda246852014-03-15 03:29:14 +03001849 netdev_err(ndev, "failed to connect PHY\n");
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001850 return PTR_ERR(phydev);
1851 }
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00001852
Sergei Shtylyovda246852014-03-15 03:29:14 +03001853 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1854 phydev->addr, phydev->irq, phydev->drv->name);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001855
1856 mdp->phydev = phydev;
1857
1858 return 0;
1859}
1860
1861/* PHY control start function */
1862static int sh_eth_phy_start(struct net_device *ndev)
1863{
1864 struct sh_eth_private *mdp = netdev_priv(ndev);
1865 int ret;
1866
1867 ret = sh_eth_phy_init(ndev);
1868 if (ret)
1869 return ret;
1870
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001871 phy_start(mdp->phydev);
1872
1873 return 0;
1874}
1875
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001876static int sh_eth_get_settings(struct net_device *ndev,
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001877 struct ethtool_cmd *ecmd)
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001878{
1879 struct sh_eth_private *mdp = netdev_priv(ndev);
1880 unsigned long flags;
1881 int ret;
1882
Ben Hutchings4f9dce232015-01-16 17:51:25 +00001883 if (!mdp->phydev)
1884 return -ENODEV;
1885
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001886 spin_lock_irqsave(&mdp->lock, flags);
1887 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1888 spin_unlock_irqrestore(&mdp->lock, flags);
1889
1890 return ret;
1891}
1892
1893static int sh_eth_set_settings(struct net_device *ndev,
Sergei Shtylyov128296f2014-01-03 15:52:22 +03001894 struct ethtool_cmd *ecmd)
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001895{
1896 struct sh_eth_private *mdp = netdev_priv(ndev);
1897 unsigned long flags;
1898 int ret;
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001899
Ben Hutchings4f9dce232015-01-16 17:51:25 +00001900 if (!mdp->phydev)
1901 return -ENODEV;
1902
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001903 spin_lock_irqsave(&mdp->lock, flags);
1904
1905 /* disable tx and rx */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001906 sh_eth_rcv_snd_disable(ndev);
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001907
1908 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1909 if (ret)
1910 goto error_exit;
1911
1912 if (ecmd->duplex == DUPLEX_FULL)
1913 mdp->duplex = 1;
1914 else
1915 mdp->duplex = 0;
1916
1917 if (mdp->cd->set_duplex)
1918 mdp->cd->set_duplex(ndev);
1919
1920error_exit:
1921 mdelay(1);
1922
1923 /* enable tx and rx */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00001924 sh_eth_rcv_snd_enable(ndev);
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00001925
1926 spin_unlock_irqrestore(&mdp->lock, flags);
1927
1928 return ret;
1929}
1930
Ben Hutchings6b4b4fe2015-02-26 20:34:35 +00001931/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1932 * version must be bumped as well. Just adding registers up to that
1933 * limit is fine, as long as the existing register indices don't
1934 * change.
1935 */
1936#define SH_ETH_REG_DUMP_VERSION 1
1937#define SH_ETH_REG_DUMP_MAX_REGS 256
1938
1939static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1940{
1941 struct sh_eth_private *mdp = netdev_priv(ndev);
1942 struct sh_eth_cpu_data *cd = mdp->cd;
1943 u32 *valid_map;
1944 size_t len;
1945
1946 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1947
1948 /* Dump starts with a bitmap that tells ethtool which
1949 * registers are defined for this chip.
1950 */
1951 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1952 if (buf) {
1953 valid_map = buf;
1954 buf += len;
1955 } else {
1956 valid_map = NULL;
1957 }
1958
1959 /* Add a register to the dump, if it has a defined offset.
1960 * This automatically skips most undefined registers, but for
1961 * some it is also necessary to check a capability flag in
1962 * struct sh_eth_cpu_data.
1963 */
1964#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1965#define add_reg_from(reg, read_expr) do { \
1966 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1967 if (buf) { \
1968 mark_reg_valid(reg); \
1969 *buf++ = read_expr; \
1970 } \
1971 ++len; \
1972 } \
1973 } while (0)
1974#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1975#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1976
1977 add_reg(EDSR);
1978 add_reg(EDMR);
1979 add_reg(EDTRR);
1980 add_reg(EDRRR);
1981 add_reg(EESR);
1982 add_reg(EESIPR);
1983 add_reg(TDLAR);
1984 add_reg(TDFAR);
1985 add_reg(TDFXR);
1986 add_reg(TDFFR);
1987 add_reg(RDLAR);
1988 add_reg(RDFAR);
1989 add_reg(RDFXR);
1990 add_reg(RDFFR);
1991 add_reg(TRSCER);
1992 add_reg(RMFCR);
1993 add_reg(TFTR);
1994 add_reg(FDR);
1995 add_reg(RMCR);
1996 add_reg(TFUCR);
1997 add_reg(RFOCR);
1998 if (cd->rmiimode)
1999 add_reg(RMIIMODE);
2000 add_reg(FCFTR);
2001 if (cd->rpadir)
2002 add_reg(RPADIR);
2003 if (!cd->no_trimd)
2004 add_reg(TRIMD);
2005 add_reg(ECMR);
2006 add_reg(ECSR);
2007 add_reg(ECSIPR);
2008 add_reg(PIR);
2009 if (!cd->no_psr)
2010 add_reg(PSR);
2011 add_reg(RDMLR);
2012 add_reg(RFLR);
2013 add_reg(IPGR);
2014 if (cd->apr)
2015 add_reg(APR);
2016 if (cd->mpr)
2017 add_reg(MPR);
2018 add_reg(RFCR);
2019 add_reg(RFCF);
2020 if (cd->tpauser)
2021 add_reg(TPAUSER);
2022 add_reg(TPAUSECR);
2023 add_reg(GECMR);
2024 if (cd->bculr)
2025 add_reg(BCULR);
2026 add_reg(MAHR);
2027 add_reg(MALR);
2028 add_reg(TROCR);
2029 add_reg(CDCR);
2030 add_reg(LCCR);
2031 add_reg(CNDCR);
2032 add_reg(CEFCR);
2033 add_reg(FRECR);
2034 add_reg(TSFRCR);
2035 add_reg(TLFRCR);
2036 add_reg(CERCR);
2037 add_reg(CEECR);
2038 add_reg(MAFCR);
2039 if (cd->rtrate)
2040 add_reg(RTRATE);
2041 if (cd->hw_crc)
2042 add_reg(CSMR);
2043 if (cd->select_mii)
2044 add_reg(RMII_MII);
2045 add_reg(ARSTR);
2046 if (cd->tsu) {
2047 add_tsu_reg(TSU_CTRST);
2048 add_tsu_reg(TSU_FWEN0);
2049 add_tsu_reg(TSU_FWEN1);
2050 add_tsu_reg(TSU_FCM);
2051 add_tsu_reg(TSU_BSYSL0);
2052 add_tsu_reg(TSU_BSYSL1);
2053 add_tsu_reg(TSU_PRISL0);
2054 add_tsu_reg(TSU_PRISL1);
2055 add_tsu_reg(TSU_FWSL0);
2056 add_tsu_reg(TSU_FWSL1);
2057 add_tsu_reg(TSU_FWSLC);
2058 add_tsu_reg(TSU_QTAG0);
2059 add_tsu_reg(TSU_QTAG1);
2060 add_tsu_reg(TSU_QTAGM0);
2061 add_tsu_reg(TSU_QTAGM1);
2062 add_tsu_reg(TSU_FWSR);
2063 add_tsu_reg(TSU_FWINMK);
2064 add_tsu_reg(TSU_ADQT0);
2065 add_tsu_reg(TSU_ADQT1);
2066 add_tsu_reg(TSU_VTAG0);
2067 add_tsu_reg(TSU_VTAG1);
2068 add_tsu_reg(TSU_ADSBSY);
2069 add_tsu_reg(TSU_TEN);
2070 add_tsu_reg(TSU_POST1);
2071 add_tsu_reg(TSU_POST2);
2072 add_tsu_reg(TSU_POST3);
2073 add_tsu_reg(TSU_POST4);
2074 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2075 /* This is the start of a table, not just a single
2076 * register.
2077 */
2078 if (buf) {
2079 unsigned int i;
2080
2081 mark_reg_valid(TSU_ADRH0);
2082 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2083 *buf++ = ioread32(
2084 mdp->tsu_addr +
2085 mdp->reg_offset[TSU_ADRH0] +
2086 i * 4);
2087 }
2088 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2089 }
2090 }
2091
2092#undef mark_reg_valid
2093#undef add_reg_from
2094#undef add_reg
2095#undef add_tsu_reg
2096
2097 return len * 4;
2098}
2099
2100static int sh_eth_get_regs_len(struct net_device *ndev)
2101{
2102 return __sh_eth_get_regs(ndev, NULL);
2103}
2104
2105static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2106 void *buf)
2107{
2108 struct sh_eth_private *mdp = netdev_priv(ndev);
2109
2110 regs->version = SH_ETH_REG_DUMP_VERSION;
2111
2112 pm_runtime_get_sync(&mdp->pdev->dev);
2113 __sh_eth_get_regs(ndev, buf);
2114 pm_runtime_put_sync(&mdp->pdev->dev);
2115}
2116
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002117static int sh_eth_nway_reset(struct net_device *ndev)
2118{
2119 struct sh_eth_private *mdp = netdev_priv(ndev);
2120 unsigned long flags;
2121 int ret;
2122
Ben Hutchings4f9dce232015-01-16 17:51:25 +00002123 if (!mdp->phydev)
2124 return -ENODEV;
2125
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002126 spin_lock_irqsave(&mdp->lock, flags);
2127 ret = phy_start_aneg(mdp->phydev);
2128 spin_unlock_irqrestore(&mdp->lock, flags);
2129
2130 return ret;
2131}
2132
2133static u32 sh_eth_get_msglevel(struct net_device *ndev)
2134{
2135 struct sh_eth_private *mdp = netdev_priv(ndev);
2136 return mdp->msg_enable;
2137}
2138
2139static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2140{
2141 struct sh_eth_private *mdp = netdev_priv(ndev);
2142 mdp->msg_enable = value;
2143}
2144
2145static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2146 "rx_current", "tx_current",
2147 "rx_dirty", "tx_dirty",
2148};
2149#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2150
2151static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2152{
2153 switch (sset) {
2154 case ETH_SS_STATS:
2155 return SH_ETH_STATS_LEN;
2156 default:
2157 return -EOPNOTSUPP;
2158 }
2159}
2160
2161static void sh_eth_get_ethtool_stats(struct net_device *ndev,
Sergei Shtylyov128296f2014-01-03 15:52:22 +03002162 struct ethtool_stats *stats, u64 *data)
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002163{
2164 struct sh_eth_private *mdp = netdev_priv(ndev);
2165 int i = 0;
2166
2167 /* device-specific stats */
2168 data[i++] = mdp->cur_rx;
2169 data[i++] = mdp->cur_tx;
2170 data[i++] = mdp->dirty_rx;
2171 data[i++] = mdp->dirty_tx;
2172}
2173
2174static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2175{
2176 switch (stringset) {
2177 case ETH_SS_STATS:
2178 memcpy(data, *sh_eth_gstrings_stats,
Sergei Shtylyov128296f2014-01-03 15:52:22 +03002179 sizeof(sh_eth_gstrings_stats));
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002180 break;
2181 }
2182}
2183
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002184static void sh_eth_get_ringparam(struct net_device *ndev,
2185 struct ethtool_ringparam *ring)
2186{
2187 struct sh_eth_private *mdp = netdev_priv(ndev);
2188
2189 ring->rx_max_pending = RX_RING_MAX;
2190 ring->tx_max_pending = TX_RING_MAX;
2191 ring->rx_pending = mdp->num_rx_ring;
2192 ring->tx_pending = mdp->num_tx_ring;
2193}
2194
2195static int sh_eth_set_ringparam(struct net_device *ndev,
2196 struct ethtool_ringparam *ring)
2197{
2198 struct sh_eth_private *mdp = netdev_priv(ndev);
2199 int ret;
2200
2201 if (ring->tx_pending > TX_RING_MAX ||
2202 ring->rx_pending > RX_RING_MAX ||
2203 ring->tx_pending < TX_RING_MIN ||
2204 ring->rx_pending < RX_RING_MIN)
2205 return -EINVAL;
2206 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2207 return -EINVAL;
2208
2209 if (netif_running(ndev)) {
Ben Hutchingsbd888912015-01-22 12:40:25 +00002210 netif_device_detach(ndev);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002211 netif_tx_disable(ndev);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002212
Ben Hutchings283e38d2015-01-22 12:44:08 +00002213 /* Serialise with the interrupt handler and NAPI, then
2214 * disable interrupts. We have to clear the
2215 * irq_enabled flag first to ensure that interrupts
2216 * won't be re-enabled.
2217 */
2218 mdp->irq_enabled = false;
2219 synchronize_irq(ndev->irq);
2220 napi_synchronize(&mdp->napi);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002221 sh_eth_write(ndev, 0x0000, EESIPR);
Ben Hutchings283e38d2015-01-22 12:44:08 +00002222
Ben Hutchings740c7f32015-01-27 00:49:32 +00002223 sh_eth_dev_exit(ndev);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002224
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03002225 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
Ben Hutchings084236d2015-01-22 12:41:34 +00002226 sh_eth_ring_free(ndev);
Ben Hutchings084236d2015-01-22 12:41:34 +00002227 }
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002228
2229 /* Set new parameters */
2230 mdp->num_rx_ring = ring->rx_pending;
2231 mdp->num_tx_ring = ring->tx_pending;
2232
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002233 if (netif_running(ndev)) {
Ben Hutchings084236d2015-01-22 12:41:34 +00002234 ret = sh_eth_ring_init(ndev);
2235 if (ret < 0) {
2236 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2237 __func__);
2238 return ret;
2239 }
2240 ret = sh_eth_dev_init(ndev, false);
2241 if (ret < 0) {
2242 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2243 __func__);
2244 return ret;
2245 }
2246
Ben Hutchings283e38d2015-01-22 12:44:08 +00002247 mdp->irq_enabled = true;
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002248 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2249 /* Setting the Rx mode will start the Rx process. */
2250 sh_eth_write(ndev, EDRRR_R, EDRRR);
Ben Hutchingsbd888912015-01-22 12:40:25 +00002251 netif_device_attach(ndev);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002252 }
2253
2254 return 0;
2255}
2256
stephen hemminger9b07be42012-01-04 12:59:49 +00002257static const struct ethtool_ops sh_eth_ethtool_ops = {
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002258 .get_settings = sh_eth_get_settings,
2259 .set_settings = sh_eth_set_settings,
Ben Hutchings6b4b4fe2015-02-26 20:34:35 +00002260 .get_regs_len = sh_eth_get_regs_len,
2261 .get_regs = sh_eth_get_regs,
stephen hemminger9b07be42012-01-04 12:59:49 +00002262 .nway_reset = sh_eth_nway_reset,
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002263 .get_msglevel = sh_eth_get_msglevel,
2264 .set_msglevel = sh_eth_set_msglevel,
stephen hemminger9b07be42012-01-04 12:59:49 +00002265 .get_link = ethtool_op_get_link,
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002266 .get_strings = sh_eth_get_strings,
2267 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2268 .get_sset_count = sh_eth_get_sset_count,
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002269 .get_ringparam = sh_eth_get_ringparam,
2270 .set_ringparam = sh_eth_set_ringparam,
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00002271};
2272
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002273/* network device open function */
2274static int sh_eth_open(struct net_device *ndev)
2275{
2276 int ret = 0;
2277 struct sh_eth_private *mdp = netdev_priv(ndev);
2278
Magnus Dammbcd51492009-10-09 00:20:04 +00002279 pm_runtime_get_sync(&mdp->pdev->dev);
2280
Sergei Shtylyovd2779e92013-09-04 02:41:27 +04002281 napi_enable(&mdp->napi);
2282
Joe Perchesa0607fd2009-11-18 23:29:17 -08002283 ret = request_irq(ndev->irq, sh_eth_interrupt,
Nobuhiro Iwamatsu5b3dfd12013-06-06 09:49:30 +00002284 mdp->cd->irq_flags, ndev->name, ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002285 if (ret) {
Sergei Shtylyovda246852014-03-15 03:29:14 +03002286 netdev_err(ndev, "Can not assign IRQ number\n");
Sergei Shtylyovd2779e92013-09-04 02:41:27 +04002287 goto out_napi_off;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002288 }
2289
2290 /* Descriptor set */
2291 ret = sh_eth_ring_init(ndev);
2292 if (ret)
2293 goto out_free_irq;
2294
2295 /* device init */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002296 ret = sh_eth_dev_init(ndev, true);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002297 if (ret)
2298 goto out_free_irq;
2299
2300 /* PHY control start*/
2301 ret = sh_eth_phy_start(ndev);
2302 if (ret)
2303 goto out_free_irq;
2304
Mitsuhiro Kimura7fa29552014-11-28 10:04:15 +09002305 mdp->is_opened = 1;
2306
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002307 return ret;
2308
2309out_free_irq:
2310 free_irq(ndev->irq, ndev);
Sergei Shtylyovd2779e92013-09-04 02:41:27 +04002311out_napi_off:
2312 napi_disable(&mdp->napi);
Magnus Dammbcd51492009-10-09 00:20:04 +00002313 pm_runtime_put_sync(&mdp->pdev->dev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002314 return ret;
2315}
2316
2317/* Timeout function */
2318static void sh_eth_tx_timeout(struct net_device *ndev)
2319{
2320 struct sh_eth_private *mdp = netdev_priv(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002321 struct sh_eth_rxdesc *rxdesc;
2322 int i;
2323
2324 netif_stop_queue(ndev);
2325
Sergei Shtylyov8d5009f2014-03-15 03:30:59 +03002326 netif_err(mdp, timer, ndev,
2327 "transmit timed out, status %8.8x, resetting...\n",
Geert Uytterhoeven0799c2d2015-01-15 11:54:28 +01002328 sh_eth_read(ndev, EESR));
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002329
2330 /* tx_errors count up */
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00002331 ndev->stats.tx_errors++;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002332
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002333 /* Free all the skbuffs in the Rx queue. */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002334 for (i = 0; i < mdp->num_rx_ring; i++) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002335 rxdesc = &mdp->rx_ring[i];
2336 rxdesc->status = 0;
2337 rxdesc->addr = 0xBADF00D0;
Sergei Shtylyov179d80a2014-06-28 04:10:00 +04002338 dev_kfree_skb(mdp->rx_skbuff[i]);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002339 mdp->rx_skbuff[i] = NULL;
2340 }
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002341 for (i = 0; i < mdp->num_tx_ring; i++) {
Sergei Shtylyov179d80a2014-06-28 04:10:00 +04002342 dev_kfree_skb(mdp->tx_skbuff[i]);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002343 mdp->tx_skbuff[i] = NULL;
2344 }
2345
2346 /* device init */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002347 sh_eth_dev_init(ndev, true);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002348}
2349
2350/* Packet transmit function */
2351static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2352{
2353 struct sh_eth_private *mdp = netdev_priv(ndev);
2354 struct sh_eth_txdesc *txdesc;
2355 u32 entry;
Nobuhiro Iwamatsufb5e2f92008-11-17 20:29:58 +00002356 unsigned long flags;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002357
2358 spin_lock_irqsave(&mdp->lock, flags);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002359 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002360 if (!sh_eth_txfree(ndev)) {
Sergei Shtylyov8d5009f2014-03-15 03:30:59 +03002361 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002362 netif_stop_queue(ndev);
2363 spin_unlock_irqrestore(&mdp->lock, flags);
Patrick McHardy5b548142009-06-12 06:22:29 +00002364 return NETDEV_TX_BUSY;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002365 }
2366 }
2367 spin_unlock_irqrestore(&mdp->lock, flags);
2368
Ben Hutchingsdacc73e2015-03-03 00:53:08 +00002369 if (skb_put_padto(skb, ETH_ZLEN))
Ben Hutchingseebfb642015-01-22 12:40:13 +00002370 return NETDEV_TX_OK;
2371
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002372 entry = mdp->cur_tx % mdp->num_tx_ring;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002373 mdp->tx_skbuff[entry] = skb;
2374 txdesc = &mdp->tx_ring[entry];
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002375 /* soft swap. */
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00002376 if (!mdp->cd->hw_swap)
2377 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2378 skb->len + 2);
Yoshihiro Shimoda31fcb992011-06-30 22:52:13 +00002379 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2380 DMA_TO_DEVICE);
Ben Hutchingsaa3933b2015-01-27 00:49:47 +00002381 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2382 kfree_skb(skb);
2383 return NETDEV_TX_OK;
2384 }
Ben Hutchingseebfb642015-01-22 12:40:13 +00002385 txdesc->buffer_length = skb->len;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002386
Sergei Shtylyovf32bfb92015-11-03 22:36:04 +03002387 dma_wmb(); /* TACT bit must be set after all the above writes */
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00002388 if (entry >= mdp->num_tx_ring - 1)
Yoshinori Sato71557a32008-08-06 19:49:00 -04002389 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002390 else
Yoshinori Sato71557a32008-08-06 19:49:00 -04002391 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002392
2393 mdp->cur_tx++;
2394
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00002395 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2396 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +09002397
Patrick McHardy6ed10652009-06-23 06:03:08 +00002398 return NETDEV_TX_OK;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002399}
2400
Ben Hutchings4398f9c2015-02-26 20:35:05 +00002401/* The statistics registers have write-clear behaviour, which means we
2402 * will lose any increment between the read and write. We mitigate
2403 * this by only clearing when we read a non-zero value, so we will
2404 * never falsely report a total of zero.
2405 */
2406static void
2407sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2408{
2409 u32 delta = sh_eth_read(ndev, reg);
2410
2411 if (delta) {
2412 *stat += delta;
2413 sh_eth_write(ndev, 0, reg);
2414 }
2415}
2416
Mitsuhiro Kimura7fa29552014-11-28 10:04:15 +09002417static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2418{
2419 struct sh_eth_private *mdp = netdev_priv(ndev);
2420
2421 if (sh_eth_is_rz_fast_ether(mdp))
2422 return &ndev->stats;
2423
2424 if (!mdp->is_opened)
2425 return &ndev->stats;
2426
Ben Hutchings4398f9c2015-02-26 20:35:05 +00002427 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2428 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2429 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
Mitsuhiro Kimura7fa29552014-11-28 10:04:15 +09002430
2431 if (sh_eth_is_gether(mdp)) {
Ben Hutchings4398f9c2015-02-26 20:35:05 +00002432 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2433 CERCR);
2434 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2435 CEECR);
Mitsuhiro Kimura7fa29552014-11-28 10:04:15 +09002436 } else {
Ben Hutchings4398f9c2015-02-26 20:35:05 +00002437 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2438 CNDCR);
Mitsuhiro Kimura7fa29552014-11-28 10:04:15 +09002439 }
2440
2441 return &ndev->stats;
2442}
2443
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002444/* device close function */
2445static int sh_eth_close(struct net_device *ndev)
2446{
2447 struct sh_eth_private *mdp = netdev_priv(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002448
2449 netif_stop_queue(ndev);
2450
Ben Hutchings283e38d2015-01-22 12:44:08 +00002451 /* Serialise with the interrupt handler and NAPI, then disable
2452 * interrupts. We have to clear the irq_enabled flag first to
2453 * ensure that interrupts won't be re-enabled.
2454 */
2455 mdp->irq_enabled = false;
2456 synchronize_irq(ndev->irq);
2457 napi_disable(&mdp->napi);
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002458 sh_eth_write(ndev, 0x0000, EESIPR);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002459
Ben Hutchings740c7f32015-01-27 00:49:32 +00002460 sh_eth_dev_exit(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002461
2462 /* PHY Disconnect */
2463 if (mdp->phydev) {
2464 phy_stop(mdp->phydev);
2465 phy_disconnect(mdp->phydev);
Ben Hutchings4f9dce232015-01-16 17:51:25 +00002466 mdp->phydev = NULL;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002467 }
2468
2469 free_irq(ndev->irq, ndev);
2470
Sergei Shtylyov8e03a5e2015-11-04 00:55:13 +03002471 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002472 sh_eth_ring_free(ndev);
2473
Magnus Dammbcd51492009-10-09 00:20:04 +00002474 pm_runtime_put_sync(&mdp->pdev->dev);
2475
Mitsuhiro Kimura7fa29552014-11-28 10:04:15 +09002476 mdp->is_opened = 0;
2477
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002478 return 0;
2479}
2480
Eric Dumazetbb7d92e2012-02-06 22:17:21 +00002481/* ioctl to device function */
Sergei Shtylyov128296f2014-01-03 15:52:22 +03002482static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002483{
2484 struct sh_eth_private *mdp = netdev_priv(ndev);
2485 struct phy_device *phydev = mdp->phydev;
2486
2487 if (!netif_running(ndev))
2488 return -EINVAL;
2489
2490 if (!phydev)
2491 return -ENODEV;
2492
Richard Cochran28b04112010-07-17 08:48:55 +00002493 return phy_mii_ioctl(phydev, rq, cmd);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002494}
2495
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002496/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2497static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2498 int entry)
2499{
2500 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2501}
2502
2503static u32 sh_eth_tsu_get_post_mask(int entry)
2504{
2505 return 0x0f << (28 - ((entry % 8) * 4));
2506}
2507
2508static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2509{
2510 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2511}
2512
2513static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2514 int entry)
2515{
2516 struct sh_eth_private *mdp = netdev_priv(ndev);
2517 u32 tmp;
2518 void *reg_offset;
2519
2520 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2521 tmp = ioread32(reg_offset);
2522 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2523}
2524
2525static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2526 int entry)
2527{
2528 struct sh_eth_private *mdp = netdev_priv(ndev);
2529 u32 post_mask, ref_mask, tmp;
2530 void *reg_offset;
2531
2532 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2533 post_mask = sh_eth_tsu_get_post_mask(entry);
2534 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2535
2536 tmp = ioread32(reg_offset);
2537 iowrite32(tmp & ~post_mask, reg_offset);
2538
2539 /* If other port enables, the function returns "true" */
2540 return tmp & ref_mask;
2541}
2542
2543static int sh_eth_tsu_busy(struct net_device *ndev)
2544{
2545 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2546 struct sh_eth_private *mdp = netdev_priv(ndev);
2547
2548 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2549 udelay(10);
2550 timeout--;
2551 if (timeout <= 0) {
Sergei Shtylyovda246852014-03-15 03:29:14 +03002552 netdev_err(ndev, "%s: timeout\n", __func__);
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002553 return -ETIMEDOUT;
2554 }
2555 }
2556
2557 return 0;
2558}
2559
2560static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2561 const u8 *addr)
2562{
2563 u32 val;
2564
2565 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2566 iowrite32(val, reg);
2567 if (sh_eth_tsu_busy(ndev) < 0)
2568 return -EBUSY;
2569
2570 val = addr[4] << 8 | addr[5];
2571 iowrite32(val, reg + 4);
2572 if (sh_eth_tsu_busy(ndev) < 0)
2573 return -EBUSY;
2574
2575 return 0;
2576}
2577
2578static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2579{
2580 u32 val;
2581
2582 val = ioread32(reg);
2583 addr[0] = (val >> 24) & 0xff;
2584 addr[1] = (val >> 16) & 0xff;
2585 addr[2] = (val >> 8) & 0xff;
2586 addr[3] = val & 0xff;
2587 val = ioread32(reg + 4);
2588 addr[4] = (val >> 8) & 0xff;
2589 addr[5] = val & 0xff;
2590}
2591
2592
2593static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2594{
2595 struct sh_eth_private *mdp = netdev_priv(ndev);
2596 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2597 int i;
2598 u8 c_addr[ETH_ALEN];
2599
2600 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2601 sh_eth_tsu_read_entry(reg_offset, c_addr);
dingtianhongc4bde292013-12-30 15:41:17 +08002602 if (ether_addr_equal(addr, c_addr))
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002603 return i;
2604 }
2605
2606 return -ENOENT;
2607}
2608
2609static int sh_eth_tsu_find_empty(struct net_device *ndev)
2610{
2611 u8 blank[ETH_ALEN];
2612 int entry;
2613
2614 memset(blank, 0, sizeof(blank));
2615 entry = sh_eth_tsu_find_entry(ndev, blank);
2616 return (entry < 0) ? -ENOMEM : entry;
2617}
2618
2619static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2620 int entry)
2621{
2622 struct sh_eth_private *mdp = netdev_priv(ndev);
2623 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2624 int ret;
2625 u8 blank[ETH_ALEN];
2626
2627 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2628 ~(1 << (31 - entry)), TSU_TEN);
2629
2630 memset(blank, 0, sizeof(blank));
2631 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2632 if (ret < 0)
2633 return ret;
2634 return 0;
2635}
2636
2637static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2638{
2639 struct sh_eth_private *mdp = netdev_priv(ndev);
2640 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2641 int i, ret;
2642
2643 if (!mdp->cd->tsu)
2644 return 0;
2645
2646 i = sh_eth_tsu_find_entry(ndev, addr);
2647 if (i < 0) {
2648 /* No entry found, create one */
2649 i = sh_eth_tsu_find_empty(ndev);
2650 if (i < 0)
2651 return -ENOMEM;
2652 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2653 if (ret < 0)
2654 return ret;
2655
2656 /* Enable the entry */
2657 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2658 (1 << (31 - i)), TSU_TEN);
2659 }
2660
2661 /* Entry found or created, enable POST */
2662 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2663
2664 return 0;
2665}
2666
2667static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2668{
2669 struct sh_eth_private *mdp = netdev_priv(ndev);
2670 int i, ret;
2671
2672 if (!mdp->cd->tsu)
2673 return 0;
2674
2675 i = sh_eth_tsu_find_entry(ndev, addr);
2676 if (i) {
2677 /* Entry found */
2678 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2679 goto done;
2680
2681 /* Disable the entry if both ports was disabled */
2682 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2683 if (ret < 0)
2684 return ret;
2685 }
2686done:
2687 return 0;
2688}
2689
2690static int sh_eth_tsu_purge_all(struct net_device *ndev)
2691{
2692 struct sh_eth_private *mdp = netdev_priv(ndev);
2693 int i, ret;
2694
Ben Hutchingsb37feed2015-01-16 17:51:12 +00002695 if (!mdp->cd->tsu)
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002696 return 0;
2697
2698 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2699 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2700 continue;
2701
2702 /* Disable the entry if both ports was disabled */
2703 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2704 if (ret < 0)
2705 return ret;
2706 }
2707
2708 return 0;
2709}
2710
2711static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2712{
2713 struct sh_eth_private *mdp = netdev_priv(ndev);
2714 u8 addr[ETH_ALEN];
2715 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2716 int i;
2717
Ben Hutchingsb37feed2015-01-16 17:51:12 +00002718 if (!mdp->cd->tsu)
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002719 return;
2720
2721 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2722 sh_eth_tsu_read_entry(reg_offset, addr);
2723 if (is_multicast_ether_addr(addr))
2724 sh_eth_tsu_del_entry(ndev, addr);
2725 }
2726}
2727
Ben Hutchingsb37feed2015-01-16 17:51:12 +00002728/* Update promiscuous flag and multicast filter */
2729static void sh_eth_set_rx_mode(struct net_device *ndev)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002730{
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002731 struct sh_eth_private *mdp = netdev_priv(ndev);
2732 u32 ecmr_bits;
2733 int mcast_all = 0;
2734 unsigned long flags;
2735
2736 spin_lock_irqsave(&mdp->lock, flags);
Sergei Shtylyov128296f2014-01-03 15:52:22 +03002737 /* Initial condition is MCT = 1, PRM = 0.
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002738 * Depending on ndev->flags, set PRM or clear MCT
2739 */
Ben Hutchingsb37feed2015-01-16 17:51:12 +00002740 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2741 if (mdp->cd->tsu)
2742 ecmr_bits |= ECMR_MCT;
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002743
2744 if (!(ndev->flags & IFF_MULTICAST)) {
2745 sh_eth_tsu_purge_mcast(ndev);
2746 mcast_all = 1;
2747 }
2748 if (ndev->flags & IFF_ALLMULTI) {
2749 sh_eth_tsu_purge_mcast(ndev);
2750 ecmr_bits &= ~ECMR_MCT;
2751 mcast_all = 1;
2752 }
2753
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002754 if (ndev->flags & IFF_PROMISC) {
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002755 sh_eth_tsu_purge_all(ndev);
2756 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2757 } else if (mdp->cd->tsu) {
2758 struct netdev_hw_addr *ha;
2759 netdev_for_each_mc_addr(ha, ndev) {
2760 if (mcast_all && is_multicast_ether_addr(ha->addr))
2761 continue;
2762
2763 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2764 if (!mcast_all) {
2765 sh_eth_tsu_purge_mcast(ndev);
2766 ecmr_bits &= ~ECMR_MCT;
2767 mcast_all = 1;
2768 }
2769 }
2770 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002771 }
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00002772
2773 /* update the ethernet mode */
2774 sh_eth_write(ndev, ecmr_bits, ECMR);
2775
2776 spin_unlock_irqrestore(&mdp->lock, flags);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002777}
Yoshihiro Shimoda71cc7c32012-02-15 17:55:06 +00002778
2779static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2780{
2781 if (!mdp->port)
2782 return TSU_VTAG0;
2783 else
2784 return TSU_VTAG1;
2785}
2786
Patrick McHardy80d5c362013-04-19 02:04:28 +00002787static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2788 __be16 proto, u16 vid)
Yoshihiro Shimoda71cc7c32012-02-15 17:55:06 +00002789{
2790 struct sh_eth_private *mdp = netdev_priv(ndev);
2791 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2792
2793 if (unlikely(!mdp->cd->tsu))
2794 return -EPERM;
2795
2796 /* No filtering if vid = 0 */
2797 if (!vid)
2798 return 0;
2799
2800 mdp->vlan_num_ids++;
2801
Sergei Shtylyov128296f2014-01-03 15:52:22 +03002802 /* The controller has one VLAN tag HW filter. So, if the filter is
Yoshihiro Shimoda71cc7c32012-02-15 17:55:06 +00002803 * already enabled, the driver disables it and the filte
2804 */
2805 if (mdp->vlan_num_ids > 1) {
2806 /* disable VLAN filter */
2807 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2808 return 0;
2809 }
2810
2811 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2812 vtag_reg_index);
2813
2814 return 0;
2815}
2816
Patrick McHardy80d5c362013-04-19 02:04:28 +00002817static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2818 __be16 proto, u16 vid)
Yoshihiro Shimoda71cc7c32012-02-15 17:55:06 +00002819{
2820 struct sh_eth_private *mdp = netdev_priv(ndev);
2821 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2822
2823 if (unlikely(!mdp->cd->tsu))
2824 return -EPERM;
2825
2826 /* No filtering if vid = 0 */
2827 if (!vid)
2828 return 0;
2829
2830 mdp->vlan_num_ids--;
2831 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2832
2833 return 0;
2834}
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002835
2836/* SuperH's TSU register init function */
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002837static void sh_eth_tsu_init(struct sh_eth_private *mdp)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002838{
Simon Hormandb893472014-01-17 09:22:28 +09002839 if (sh_eth_is_rz_fast_ether(mdp)) {
2840 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2841 return;
2842 }
2843
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002844 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2845 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2846 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2847 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2848 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2849 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2850 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2851 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2852 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2853 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
Yoshihiro Shimodac5ed5362011-03-07 21:59:38 +00002854 if (sh_eth_is_gether(mdp)) {
2855 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2856 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2857 } else {
2858 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2859 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2860 }
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002861 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2862 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2863 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2864 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2865 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2866 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2867 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002868}
2869
2870/* MDIO bus release function */
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002871static int sh_mdio_release(struct sh_eth_private *mdp)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002872{
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002873 /* unregister mdio bus */
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002874 mdiobus_unregister(mdp->mii_bus);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002875
2876 /* free bitbang info */
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002877 free_mdio_bitbang(mdp->mii_bus);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002878
2879 return 0;
2880}
2881
2882/* MDIO bus init function */
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002883static int sh_mdio_init(struct sh_eth_private *mdp,
Yoshihiro Shimodab3017e62011-03-07 21:59:55 +00002884 struct sh_eth_plat_data *pd)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002885{
2886 int ret, i;
2887 struct bb_info *bitbang;
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002888 struct platform_device *pdev = mdp->pdev;
Laurent Pinchartaa8d4222014-03-20 15:00:31 +01002889 struct device *dev = &mdp->pdev->dev;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002890
2891 /* create bit control struct for PHY */
Laurent Pinchartaa8d4222014-03-20 15:00:31 +01002892 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
Laurent Pinchartf738a132014-03-20 15:00:35 +01002893 if (!bitbang)
2894 return -ENOMEM;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002895
2896 /* bitbang init */
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00002897 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
Yoshihiro Shimodab3017e62011-03-07 21:59:55 +00002898 bitbang->set_gate = pd->set_mdio_gate;
Sergei Shtylyovdfed5e72013-03-21 10:37:54 +00002899 bitbang->mdi_msk = PIR_MDI;
2900 bitbang->mdo_msk = PIR_MDO;
2901 bitbang->mmd_msk = PIR_MMD;
2902 bitbang->mdc_msk = PIR_MDC;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002903 bitbang->ctrl.ops = &bb_ops;
2904
Stefan Weilc2e07b32010-08-03 19:44:52 +02002905 /* MII controller setting */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002906 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
Laurent Pinchartf738a132014-03-20 15:00:35 +01002907 if (!mdp->mii_bus)
2908 return -ENOMEM;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002909
2910 /* Hook up MII support for ethtool */
2911 mdp->mii_bus->name = "sh_mii";
Laurent Pincharta5bd60602014-03-20 15:00:32 +01002912 mdp->mii_bus->parent = dev;
Florian Fainelli5278fb52012-01-09 23:59:17 +00002913 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002914 pdev->name, pdev->id);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002915
2916 /* PHY IRQ */
Sergei Shtylyov86b5d252014-05-13 02:30:14 +04002917 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2918 GFP_KERNEL);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002919 if (!mdp->mii_bus->irq) {
2920 ret = -ENOMEM;
2921 goto out_free_bus;
2922 }
2923
Laurent Pinchartbd920ff2014-03-20 15:00:33 +01002924 /* register MDIO bus */
2925 if (dev->of_node) {
2926 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
Ben Dooks702eca02014-03-12 17:47:40 +00002927 } else {
2928 for (i = 0; i < PHY_MAX_ADDR; i++)
2929 mdp->mii_bus->irq[i] = PHY_POLL;
2930 if (pd->phy_irq > 0)
2931 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2932
2933 ret = mdiobus_register(mdp->mii_bus);
2934 }
2935
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002936 if (ret)
Sergei Shtylyovd5e07e62013-03-21 10:41:11 +00002937 goto out_free_bus;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002938
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002939 return 0;
2940
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002941out_free_bus:
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07002942 free_mdio_bitbang(mdp->mii_bus);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07002943 return ret;
2944}
2945
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002946static const u16 *sh_eth_get_register_offset(int register_type)
2947{
2948 const u16 *reg_offset = NULL;
2949
2950 switch (register_type) {
2951 case SH_ETH_REG_GIGABIT:
2952 reg_offset = sh_eth_offset_gigabit;
2953 break;
Simon Hormandb893472014-01-17 09:22:28 +09002954 case SH_ETH_REG_FAST_RZ:
2955 reg_offset = sh_eth_offset_fast_rz;
2956 break;
Sergei Shtylyova3f109b2013-03-28 11:51:31 +00002957 case SH_ETH_REG_FAST_RCAR:
2958 reg_offset = sh_eth_offset_fast_rcar;
2959 break;
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002960 case SH_ETH_REG_FAST_SH4:
2961 reg_offset = sh_eth_offset_fast_sh4;
2962 break;
2963 case SH_ETH_REG_FAST_SH3_SH2:
2964 reg_offset = sh_eth_offset_fast_sh3_sh2;
2965 break;
2966 default:
Yoshihiro Shimoda4a555302011-03-07 21:59:26 +00002967 break;
2968 }
2969
2970 return reg_offset;
2971}
2972
Sergei Shtylyov8f728d72013-06-13 00:55:34 +04002973static const struct net_device_ops sh_eth_netdev_ops = {
Alexander Beregalovebf84ea2009-04-11 07:40:49 +00002974 .ndo_open = sh_eth_open,
2975 .ndo_stop = sh_eth_close,
2976 .ndo_start_xmit = sh_eth_start_xmit,
2977 .ndo_get_stats = sh_eth_get_stats,
Ben Hutchingsb37feed2015-01-16 17:51:12 +00002978 .ndo_set_rx_mode = sh_eth_set_rx_mode,
Alexander Beregalovebf84ea2009-04-11 07:40:49 +00002979 .ndo_tx_timeout = sh_eth_tx_timeout,
2980 .ndo_do_ioctl = sh_eth_do_ioctl,
2981 .ndo_validate_addr = eth_validate_addr,
2982 .ndo_set_mac_address = eth_mac_addr,
2983 .ndo_change_mtu = eth_change_mtu,
2984};
2985
Sergei Shtylyov8f728d72013-06-13 00:55:34 +04002986static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2987 .ndo_open = sh_eth_open,
2988 .ndo_stop = sh_eth_close,
2989 .ndo_start_xmit = sh_eth_start_xmit,
2990 .ndo_get_stats = sh_eth_get_stats,
Ben Hutchingsb37feed2015-01-16 17:51:12 +00002991 .ndo_set_rx_mode = sh_eth_set_rx_mode,
Sergei Shtylyov8f728d72013-06-13 00:55:34 +04002992 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2993 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2994 .ndo_tx_timeout = sh_eth_tx_timeout,
2995 .ndo_do_ioctl = sh_eth_do_ioctl,
2996 .ndo_validate_addr = eth_validate_addr,
2997 .ndo_set_mac_address = eth_mac_addr,
2998 .ndo_change_mtu = eth_change_mtu,
2999};
3000
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003001#ifdef CONFIG_OF
3002static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3003{
3004 struct device_node *np = dev->of_node;
3005 struct sh_eth_plat_data *pdata;
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003006 const char *mac_addr;
3007
3008 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3009 if (!pdata)
3010 return NULL;
3011
3012 pdata->phy_interface = of_get_phy_mode(np);
3013
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003014 mac_addr = of_get_mac_address(np);
3015 if (mac_addr)
3016 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3017
3018 pdata->no_ether_link =
3019 of_property_read_bool(np, "renesas,no-ether-link");
3020 pdata->ether_link_active_low =
3021 of_property_read_bool(np, "renesas,ether-link-active-low");
3022
3023 return pdata;
3024}
3025
3026static const struct of_device_id sh_eth_match_table[] = {
3027 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3028 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3029 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3030 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3031 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
Hisashi Nakamura9488e1e2014-11-13 15:59:07 +09003032 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
Hisashi Nakamura0f76b9d2014-08-01 17:03:00 +02003033 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003034 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3035 { }
3036};
3037MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3038#else
3039static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3040{
3041 return NULL;
3042}
3043#endif
3044
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003045static int sh_eth_drv_probe(struct platform_device *pdev)
3046{
Kuninori Morimoto9c386572010-08-19 00:39:45 -07003047 int ret, devno = 0;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003048 struct resource *res;
3049 struct net_device *ndev = NULL;
Kuninori Morimotoec0d7552011-06-23 16:02:38 +00003050 struct sh_eth_private *mdp = NULL;
Jingoo Han0b76b862013-08-30 14:00:11 +09003051 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
Sergei Shtylyovafe391a2013-06-07 13:54:02 +00003052 const struct platform_device_id *id = platform_get_device_id(pdev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003053
3054 /* get base addr */
3055 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003056
3057 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
Laurent Pinchartf738a132014-03-20 15:00:35 +01003058 if (!ndev)
3059 return -ENOMEM;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003060
Ben Dooksb5893a02014-03-21 12:09:14 +01003061 pm_runtime_enable(&pdev->dev);
3062 pm_runtime_get_sync(&pdev->dev);
3063
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003064 devno = pdev->id;
3065 if (devno < 0)
3066 devno = 0;
3067
3068 ndev->dma = -1;
roel kluincc3c0802008-09-10 19:22:44 +02003069 ret = platform_get_irq(pdev, 0);
Sergei Shtylyov7a468ac2015-08-28 16:56:01 +03003070 if (ret < 0)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003071 goto out_release;
roel kluincc3c0802008-09-10 19:22:44 +02003072 ndev->irq = ret;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003073
3074 SET_NETDEV_DEV(ndev, &pdev->dev);
3075
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003076 mdp = netdev_priv(ndev);
Yoshihiro Shimoda525b8072012-06-26 20:00:03 +00003077 mdp->num_tx_ring = TX_RING_SIZE;
3078 mdp->num_rx_ring = RX_RING_SIZE;
Sergei Shtylyovd5e07e62013-03-21 10:41:11 +00003079 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3080 if (IS_ERR(mdp->addr)) {
3081 ret = PTR_ERR(mdp->addr);
Yoshihiro Shimodaae706442011-09-27 21:48:58 +00003082 goto out_release;
3083 }
3084
Varka Bhadramc9608042014-10-24 07:42:09 +05303085 ndev->base_addr = res->start;
3086
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003087 spin_lock_init(&mdp->lock);
Magnus Dammbcd51492009-10-09 00:20:04 +00003088 mdp->pdev = pdev;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003089
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003090 if (pdev->dev.of_node)
3091 pd = sh_eth_parse_dt(&pdev->dev);
Sergei Shtylyov3b4c5cb2013-10-30 23:30:19 +03003092 if (!pd) {
3093 dev_err(&pdev->dev, "no platform data\n");
3094 ret = -EINVAL;
3095 goto out_release;
3096 }
3097
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003098 /* get PHY ID */
Yoshinori Sato71557a32008-08-06 19:49:00 -04003099 mdp->phy_id = pd->phy;
Yoshihiro Shimodae47c9052011-03-07 21:59:45 +00003100 mdp->phy_interface = pd->phy_interface;
Yoshinori Sato71557a32008-08-06 19:49:00 -04003101 /* EDMAC endian */
3102 mdp->edmac_endian = pd->edmac_endian;
Yoshihiro Shimoda49235762009-08-27 23:25:03 +00003103 mdp->no_ether_link = pd->no_ether_link;
3104 mdp->ether_link_active_low = pd->ether_link_active_low;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003105
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00003106 /* set cpu data */
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003107 if (id) {
3108 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3109 } else {
3110 const struct of_device_id *match;
3111
3112 match = of_match_device(of_match_ptr(sh_eth_match_table),
3113 &pdev->dev);
3114 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3115 }
Sergei Shtylyova3153d82013-08-18 03:11:28 +04003116 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
Sergei Shtylyov264be2f2014-03-15 03:11:24 +03003117 if (!mdp->reg_offset) {
3118 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3119 mdp->cd->register_type);
3120 ret = -EINVAL;
3121 goto out_release;
3122 }
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00003123 sh_eth_set_default_cpu_data(mdp->cd);
3124
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003125 /* set function */
Sergei Shtylyov8f728d72013-06-13 00:55:34 +04003126 if (mdp->cd->tsu)
3127 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3128 else
3129 ndev->netdev_ops = &sh_eth_netdev_ops;
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00003130 ndev->ethtool_ops = &sh_eth_ethtool_ops;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003131 ndev->watchdog_timeo = TX_TIMEOUT;
3132
Nobuhiro Iwamatsudc19e4e2011-02-15 21:17:32 +00003133 /* debug message level */
3134 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003135
3136 /* read and set MAC address */
Magnus Damm748031f2009-10-09 00:17:14 +00003137 read_mac_address(ndev, pd->mac_addr);
Sergei Shtylyovff6e7222013-04-29 09:49:42 +00003138 if (!is_valid_ether_addr(ndev->dev_addr)) {
3139 dev_warn(&pdev->dev,
3140 "no valid MAC address supplied, using a random one.\n");
3141 eth_hw_addr_random(ndev);
3142 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003143
Yoshihiro Shimoda6ba88022012-02-15 17:55:01 +00003144 /* ioremap the TSU registers */
3145 if (mdp->cd->tsu) {
3146 struct resource *rtsu;
3147 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Sergei Shtylyovd5e07e62013-03-21 10:41:11 +00003148 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3149 if (IS_ERR(mdp->tsu_addr)) {
3150 ret = PTR_ERR(mdp->tsu_addr);
Sergei Shtylyovfc0c0902013-03-19 13:41:32 +00003151 goto out_release;
3152 }
Yoshihiro Shimoda6743fe62012-02-15 17:55:03 +00003153 mdp->port = devno % 2;
Patrick McHardyf6469682013-04-19 02:04:27 +00003154 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
Yoshihiro Shimoda6ba88022012-02-15 17:55:01 +00003155 }
3156
Yoshihiro Shimoda150647f2012-02-15 17:54:56 +00003157 /* initialize first or needed device */
3158 if (!devno || pd->needs_init) {
Yoshihiro Shimoda380af9e2009-05-24 23:54:21 +00003159 if (mdp->cd->chip_reset)
3160 mdp->cd->chip_reset(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003161
Yoshihiro Shimoda4986b992011-03-07 21:59:34 +00003162 if (mdp->cd->tsu) {
3163 /* TSU init (Init only)*/
3164 sh_eth_tsu_init(mdp);
3165 }
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003166 }
3167
Hisashi Nakamura966d6db2014-11-13 15:54:05 +09003168 if (mdp->cd->rmiimode)
3169 sh_eth_write(ndev, 0x1, RMIIMODE);
3170
Laurent Pinchartdaacf032014-03-20 15:00:34 +01003171 /* MDIO bus init */
3172 ret = sh_mdio_init(mdp, pd);
3173 if (ret) {
3174 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3175 goto out_release;
3176 }
3177
Sergei Shtylyov37191092013-06-19 23:30:23 +04003178 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3179
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003180 /* network device register */
3181 ret = register_netdev(ndev);
3182 if (ret)
Sergei Shtylyov37191092013-06-19 23:30:23 +04003183 goto out_napi_del;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003184
Lucas De Marchi25985ed2011-03-30 22:57:33 -03003185 /* print device information */
Sergei Shtylyovf75f14e2014-03-15 03:27:54 +03003186 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3187 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003188
Ben Dooksb5893a02014-03-21 12:09:14 +01003189 pm_runtime_put(&pdev->dev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003190 platform_set_drvdata(pdev, ndev);
3191
3192 return ret;
3193
Sergei Shtylyov37191092013-06-19 23:30:23 +04003194out_napi_del:
3195 netif_napi_del(&mdp->napi);
Laurent Pinchartdaacf032014-03-20 15:00:34 +01003196 sh_mdio_release(mdp);
Sergei Shtylyov37191092013-06-19 23:30:23 +04003197
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003198out_release:
3199 /* net_dev free */
3200 if (ndev)
3201 free_netdev(ndev);
3202
Ben Dooksb5893a02014-03-21 12:09:14 +01003203 pm_runtime_put(&pdev->dev);
3204 pm_runtime_disable(&pdev->dev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003205 return ret;
3206}
3207
3208static int sh_eth_drv_remove(struct platform_device *pdev)
3209{
3210 struct net_device *ndev = platform_get_drvdata(pdev);
Sergei Shtylyov37191092013-06-19 23:30:23 +04003211 struct sh_eth_private *mdp = netdev_priv(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003212
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003213 unregister_netdev(ndev);
Sergei Shtylyov37191092013-06-19 23:30:23 +04003214 netif_napi_del(&mdp->napi);
Laurent Pinchartdaacf032014-03-20 15:00:34 +01003215 sh_mdio_release(mdp);
Magnus Dammbcd51492009-10-09 00:20:04 +00003216 pm_runtime_disable(&pdev->dev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003217 free_netdev(ndev);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003218
3219 return 0;
3220}
3221
Nobuhiro Iwamatsu540ad1b2013-06-06 09:52:37 +00003222#ifdef CONFIG_PM
Mikhail Ulyanovb71af042015-01-22 01:19:48 +03003223#ifdef CONFIG_PM_SLEEP
3224static int sh_eth_suspend(struct device *dev)
3225{
3226 struct net_device *ndev = dev_get_drvdata(dev);
3227 int ret = 0;
3228
3229 if (netif_running(ndev)) {
3230 netif_device_detach(ndev);
3231 ret = sh_eth_close(ndev);
3232 }
3233
3234 return ret;
3235}
3236
3237static int sh_eth_resume(struct device *dev)
3238{
3239 struct net_device *ndev = dev_get_drvdata(dev);
3240 int ret = 0;
3241
3242 if (netif_running(ndev)) {
3243 ret = sh_eth_open(ndev);
3244 if (ret < 0)
3245 return ret;
3246 netif_device_attach(ndev);
3247 }
3248
3249 return ret;
3250}
3251#endif
3252
Magnus Dammbcd51492009-10-09 00:20:04 +00003253static int sh_eth_runtime_nop(struct device *dev)
3254{
Sergei Shtylyov128296f2014-01-03 15:52:22 +03003255 /* Runtime PM callback shared between ->runtime_suspend()
Magnus Dammbcd51492009-10-09 00:20:04 +00003256 * and ->runtime_resume(). Simply returns success.
3257 *
3258 * This driver re-initializes all registers after
3259 * pm_runtime_get_sync() anyway so there is no need
3260 * to save and restore registers here.
3261 */
3262 return 0;
3263}
3264
Nobuhiro Iwamatsu540ad1b2013-06-06 09:52:37 +00003265static const struct dev_pm_ops sh_eth_dev_pm_ops = {
Mikhail Ulyanovb71af042015-01-22 01:19:48 +03003266 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
Mikhail Ulyanove7d7e892015-01-22 01:18:44 +03003267 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
Magnus Dammbcd51492009-10-09 00:20:04 +00003268};
Nobuhiro Iwamatsu540ad1b2013-06-06 09:52:37 +00003269#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3270#else
3271#define SH_ETH_PM_OPS NULL
3272#endif
Magnus Dammbcd51492009-10-09 00:20:04 +00003273
Sergei Shtylyovafe391a2013-06-07 13:54:02 +00003274static struct platform_device_id sh_eth_id_table[] = {
Sergei Shtylyovc18a79a2013-06-07 13:56:05 +00003275 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
Sergei Shtylyov7bbe1502013-06-07 13:55:08 +00003276 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
Sergei Shtylyov9c3beaa2013-06-07 14:03:37 +00003277 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
Sergei Shtylyovf5d12762013-06-07 13:58:18 +00003278 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
Sergei Shtylyov24549e22013-06-07 13:59:21 +00003279 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3280 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
Sergei Shtylyovf5d12762013-06-07 13:58:18 +00003281 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
Sergei Shtylyove5c9b4c2013-06-07 13:57:12 +00003282 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
Sergei Shtylyov589ebde2013-06-07 14:05:59 +00003283 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
Sergei Shtylyov94a12b12013-12-08 02:59:18 +03003284 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3285 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
Hisashi Nakamura9488e1e2014-11-13 15:59:07 +09003286 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
Hisashi Nakamura0f76b9d2014-08-01 17:03:00 +02003287 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
Sergei Shtylyovafe391a2013-06-07 13:54:02 +00003288 { }
3289};
3290MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3291
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003292static struct platform_driver sh_eth_driver = {
3293 .probe = sh_eth_drv_probe,
3294 .remove = sh_eth_drv_remove,
Sergei Shtylyovafe391a2013-06-07 13:54:02 +00003295 .id_table = sh_eth_id_table,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003296 .driver = {
3297 .name = CARDNAME,
Nobuhiro Iwamatsu540ad1b2013-06-06 09:52:37 +00003298 .pm = SH_ETH_PM_OPS,
Sergei Shtylyovb356e972014-02-18 03:12:43 +03003299 .of_match_table = of_match_ptr(sh_eth_match_table),
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003300 },
3301};
3302
Axel Lindb62f682011-11-27 16:44:17 +00003303module_platform_driver(sh_eth_driver);
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07003304
3305MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3306MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3307MODULE_LICENSE("GPL v2");