Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC |
| 3 | * applies to AT91SAM9G45, AT91SAM9M10, |
| 4 | * AT91SAM9G46, AT91SAM9M11 SoC |
| 5 | * |
| 6 | * Copyright (C) 2011 Atmel, |
| 7 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> |
| 8 | * |
| 9 | * Licensed under GPLv2 or later. |
| 10 | */ |
| 11 | |
| 12 | /include/ "skeleton.dtsi" |
| 13 | |
| 14 | / { |
| 15 | model = "Atmel AT91SAM9G45 family SoC"; |
| 16 | compatible = "atmel,at91sam9g45"; |
| 17 | interrupt-parent = <&aic>; |
| 18 | |
| 19 | aliases { |
| 20 | serial0 = &dbgu; |
| 21 | serial1 = &usart0; |
| 22 | serial2 = &usart1; |
| 23 | serial3 = &usart2; |
| 24 | serial4 = &usart3; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 25 | gpio0 = &pioA; |
| 26 | gpio1 = &pioB; |
| 27 | gpio2 = &pioC; |
| 28 | gpio3 = &pioD; |
| 29 | gpio4 = &pioE; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 30 | tcb0 = &tcb0; |
| 31 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 32 | i2c0 = &i2c0; |
| 33 | i2c1 = &i2c1; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 34 | }; |
| 35 | cpus { |
| 36 | cpu@0 { |
| 37 | compatible = "arm,arm926ejs"; |
| 38 | }; |
| 39 | }; |
| 40 | |
Ludovic Desroches | dcce6ce | 2012-04-02 20:44:20 +0200 | [diff] [blame] | 41 | memory { |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 42 | reg = <0x70000000 0x10000000>; |
| 43 | }; |
| 44 | |
| 45 | ahb { |
| 46 | compatible = "simple-bus"; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <1>; |
| 49 | ranges; |
| 50 | |
| 51 | apb { |
| 52 | compatible = "simple-bus"; |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <1>; |
| 55 | ranges; |
| 56 | |
| 57 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 58 | #interrupt-cells = <3>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 59 | compatible = "atmel,at91rm9200-aic"; |
| 60 | interrupt-controller; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 61 | reg = <0xfffff000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | c657394 | 2012-04-09 19:36:36 +0800 | [diff] [blame] | 62 | atmel,external-irqs = <31>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 63 | }; |
| 64 | |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 65 | ramc0: ramc@ffffe400 { |
| 66 | compatible = "atmel,at91sam9g45-ddramc"; |
| 67 | reg = <0xffffe400 0x200 |
| 68 | 0xffffe600 0x200>; |
| 69 | }; |
| 70 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 71 | pmc: pmc@fffffc00 { |
| 72 | compatible = "atmel,at91rm9200-pmc"; |
| 73 | reg = <0xfffffc00 0x100>; |
| 74 | }; |
| 75 | |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 76 | rstc@fffffd00 { |
| 77 | compatible = "atmel,at91sam9g45-rstc"; |
| 78 | reg = <0xfffffd00 0x10>; |
| 79 | }; |
| 80 | |
Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 81 | pit: timer@fffffd30 { |
| 82 | compatible = "atmel,at91sam9260-pit"; |
| 83 | reg = <0xfffffd30 0xf>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 84 | interrupts = <1 4 7>; |
Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 85 | }; |
| 86 | |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 88 | shdwc@fffffd10 { |
| 89 | compatible = "atmel,at91sam9rl-shdwc"; |
| 90 | reg = <0xfffffd10 0x10>; |
| 91 | }; |
| 92 | |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 93 | tcb0: timer@fff7c000 { |
| 94 | compatible = "atmel,at91rm9200-tcb"; |
| 95 | reg = <0xfff7c000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 96 | interrupts = <18 4 0>; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | tcb1: timer@fffd4000 { |
| 100 | compatible = "atmel,at91rm9200-tcb"; |
| 101 | reg = <0xfffd4000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 102 | interrupts = <18 4 0>; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 103 | }; |
| 104 | |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 105 | dma: dma-controller@ffffec00 { |
| 106 | compatible = "atmel,at91sam9g45-dma"; |
| 107 | reg = <0xffffec00 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 108 | interrupts = <21 4 0>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 109 | }; |
| 110 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 111 | pinctrl@fffff200 { |
| 112 | #address-cells = <1>; |
| 113 | #size-cells = <1>; |
| 114 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; |
| 115 | ranges = <0xfffff200 0xfffff200 0xa00>; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 117 | atmel,mux-mask = < |
| 118 | /* A B */ |
| 119 | 0xffffffff 0xffc003ff /* pioA */ |
| 120 | 0xffffffff 0x800f8f00 /* pioB */ |
| 121 | 0xffffffff 0x00000e00 /* pioC */ |
| 122 | 0xffffffff 0xff0c1381 /* pioD */ |
| 123 | 0xffffffff 0x81ffff81 /* pioE */ |
| 124 | >; |
| 125 | |
| 126 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 127 | dbgu { |
| 128 | pinctrl_dbgu: dbgu-0 { |
| 129 | atmel,pins = |
| 130 | <1 12 0x1 0x0 /* PB12 periph A */ |
| 131 | 1 13 0x1 0x0>; /* PB13 periph A */ |
| 132 | }; |
| 133 | }; |
| 134 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 135 | usart0 { |
| 136 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 137 | atmel,pins = |
| 138 | <1 19 0x1 0x1 /* PB19 periph A with pullup */ |
| 139 | 1 18 0x1 0x0>; /* PB18 periph A */ |
| 140 | }; |
| 141 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 142 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 143 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 144 | <1 17 0x2 0x0>; /* PB17 periph B */ |
| 145 | }; |
| 146 | |
| 147 | pinctrl_usart0_cts: usart0_cts-0 { |
| 148 | atmel,pins = |
| 149 | <1 15 0x2 0x0>; /* PB15 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 150 | }; |
| 151 | }; |
| 152 | |
| 153 | uart1 { |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 154 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 155 | atmel,pins = |
| 156 | <1 4 0x1 0x1 /* PB4 periph A with pullup */ |
| 157 | 1 5 0x1 0x0>; /* PB5 periph A */ |
| 158 | }; |
| 159 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 160 | pinctrl_usart1_rts: usart1_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 161 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 162 | <3 16 0x1 0x0>; /* PD16 periph A */ |
| 163 | }; |
| 164 | |
| 165 | pinctrl_usart1_cts: usart1_cts-0 { |
| 166 | atmel,pins = |
| 167 | <3 17 0x1 0x0>; /* PD17 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 168 | }; |
| 169 | }; |
| 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 171 | usart2 { |
| 172 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 173 | atmel,pins = |
| 174 | <1 6 0x1 0x1 /* PB6 periph A with pullup */ |
| 175 | 1 7 0x1 0x0>; /* PB7 periph A */ |
| 176 | }; |
| 177 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 178 | pinctrl_usart2_rts: usart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 179 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 180 | <2 9 0x2 0x0>; /* PC9 periph B */ |
| 181 | }; |
| 182 | |
| 183 | pinctrl_usart2_cts: usart2_cts-0 { |
| 184 | atmel,pins = |
| 185 | <2 11 0x2 0x0>; /* PC11 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 186 | }; |
| 187 | }; |
| 188 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 189 | usart3 { |
| 190 | pinctrl_usart3: usart3-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 191 | atmel,pins = |
| 192 | <1 8 0x1 0x1 /* PB9 periph A with pullup */ |
| 193 | 1 9 0x1 0x0>; /* PB8 periph A */ |
| 194 | }; |
| 195 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 196 | pinctrl_usart3_rts: usart3_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 197 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 198 | <0 23 0x2 0x0>; /* PA23 periph B */ |
| 199 | }; |
| 200 | |
| 201 | pinctrl_usart3_cts: usart3_cts-0 { |
| 202 | atmel,pins = |
| 203 | <0 24 0x2 0x0>; /* PA24 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 204 | }; |
| 205 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 206 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 207 | nand { |
| 208 | pinctrl_nand: nand-0 { |
| 209 | atmel,pins = |
| 210 | <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/ |
| 211 | 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ |
| 212 | }; |
| 213 | }; |
| 214 | |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 215 | macb { |
| 216 | pinctrl_macb_rmii: macb_rmii-0 { |
| 217 | atmel,pins = |
| 218 | <0 10 0x1 0x0 /* PA10 periph A */ |
| 219 | 0 11 0x1 0x0 /* PA11 periph A */ |
| 220 | 0 12 0x1 0x0 /* PA12 periph A */ |
| 221 | 0 13 0x1 0x0 /* PA13 periph A */ |
| 222 | 0 14 0x1 0x0 /* PA14 periph A */ |
| 223 | 0 15 0x1 0x0 /* PA15 periph A */ |
| 224 | 0 16 0x1 0x0 /* PA16 periph A */ |
| 225 | 0 17 0x1 0x0 /* PA17 periph A */ |
| 226 | 0 18 0x1 0x0 /* PA18 periph A */ |
| 227 | 0 19 0x1 0x0>; /* PA19 periph A */ |
| 228 | }; |
| 229 | |
| 230 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 231 | atmel,pins = |
| 232 | <0 6 0x2 0x0 /* PA6 periph B */ |
| 233 | 0 7 0x2 0x0 /* PA7 periph B */ |
| 234 | 0 8 0x2 0x0 /* PA8 periph B */ |
| 235 | 0 9 0x2 0x0 /* PA9 periph B */ |
| 236 | 0 27 0x2 0x0 /* PA27 periph B */ |
| 237 | 0 28 0x2 0x0 /* PA28 periph B */ |
| 238 | 0 29 0x2 0x0 /* PA29 periph B */ |
| 239 | 0 30 0x2 0x0>; /* PA30 periph B */ |
| 240 | }; |
| 241 | }; |
| 242 | |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame^] | 243 | mmc0 { |
| 244 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 245 | atmel,pins = |
| 246 | <0 0 0x1 0x0 /* PA0 periph A */ |
| 247 | 0 1 0x1 0x1 /* PA1 periph A with pullup */ |
| 248 | 0 2 0x1 0x1>; /* PA2 periph A with pullup */ |
| 249 | }; |
| 250 | |
| 251 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 252 | atmel,pins = |
| 253 | <0 3 0x1 0x1 /* PA3 periph A with pullup */ |
| 254 | 0 4 0x1 0x1 /* PA4 periph A with pullup */ |
| 255 | 0 5 0x1 0x1>; /* PA5 periph A with pullup */ |
| 256 | }; |
| 257 | |
| 258 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 259 | atmel,pins = |
| 260 | <0 6 0x1 0x1 /* PA6 periph A with pullup */ |
| 261 | 0 7 0x1 0x1 /* PA7 periph A with pullup */ |
| 262 | 0 8 0x1 0x1 /* PA8 periph A with pullup */ |
| 263 | 0 9 0x1 0x1>; /* PA9 periph A with pullup */ |
| 264 | }; |
| 265 | }; |
| 266 | |
| 267 | mmc1 { |
| 268 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 269 | atmel,pins = |
| 270 | <0 31 0x1 0x0 /* PA31 periph A */ |
| 271 | 0 22 0x1 0x1 /* PA22 periph A with pullup */ |
| 272 | 0 23 0x1 0x1>; /* PA23 periph A with pullup */ |
| 273 | }; |
| 274 | |
| 275 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 276 | atmel,pins = |
| 277 | <0 24 0x1 0x1 /* PA24 periph A with pullup */ |
| 278 | 0 25 0x1 0x1 /* PA25 periph A with pullup */ |
| 279 | 0 26 0x1 0x1>; /* PA26 periph A with pullup */ |
| 280 | }; |
| 281 | |
| 282 | pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { |
| 283 | atmel,pins = |
| 284 | <0 27 0x1 0x1 /* PA27 periph A with pullup */ |
| 285 | 0 28 0x1 0x1 /* PA28 periph A with pullup */ |
| 286 | 0 29 0x1 0x1 /* PA29 periph A with pullup */ |
| 287 | 0 20 0x1 0x1>; /* PA30 periph A with pullup */ |
| 288 | }; |
| 289 | }; |
| 290 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 291 | pioA: gpio@fffff200 { |
| 292 | compatible = "atmel,at91rm9200-gpio"; |
| 293 | reg = <0xfffff200 0x200>; |
| 294 | interrupts = <2 4 1>; |
| 295 | #gpio-cells = <2>; |
| 296 | gpio-controller; |
| 297 | interrupt-controller; |
| 298 | #interrupt-cells = <2>; |
| 299 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 300 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 301 | pioB: gpio@fffff400 { |
| 302 | compatible = "atmel,at91rm9200-gpio"; |
| 303 | reg = <0xfffff400 0x200>; |
| 304 | interrupts = <3 4 1>; |
| 305 | #gpio-cells = <2>; |
| 306 | gpio-controller; |
| 307 | interrupt-controller; |
| 308 | #interrupt-cells = <2>; |
| 309 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 310 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 311 | pioC: gpio@fffff600 { |
| 312 | compatible = "atmel,at91rm9200-gpio"; |
| 313 | reg = <0xfffff600 0x200>; |
| 314 | interrupts = <4 4 1>; |
| 315 | #gpio-cells = <2>; |
| 316 | gpio-controller; |
| 317 | interrupt-controller; |
| 318 | #interrupt-cells = <2>; |
| 319 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 320 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 321 | pioD: gpio@fffff800 { |
| 322 | compatible = "atmel,at91rm9200-gpio"; |
| 323 | reg = <0xfffff800 0x200>; |
| 324 | interrupts = <5 4 1>; |
| 325 | #gpio-cells = <2>; |
| 326 | gpio-controller; |
| 327 | interrupt-controller; |
| 328 | #interrupt-cells = <2>; |
| 329 | }; |
| 330 | |
| 331 | pioE: gpio@fffffa00 { |
| 332 | compatible = "atmel,at91rm9200-gpio"; |
| 333 | reg = <0xfffffa00 0x200>; |
| 334 | interrupts = <5 4 1>; |
| 335 | #gpio-cells = <2>; |
| 336 | gpio-controller; |
| 337 | interrupt-controller; |
| 338 | #interrupt-cells = <2>; |
| 339 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 340 | }; |
| 341 | |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 342 | dbgu: serial@ffffee00 { |
| 343 | compatible = "atmel,at91sam9260-usart"; |
| 344 | reg = <0xffffee00 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 345 | interrupts = <1 4 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 346 | pinctrl-names = "default"; |
| 347 | pinctrl-0 = <&pinctrl_dbgu>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 348 | status = "disabled"; |
| 349 | }; |
| 350 | |
| 351 | usart0: serial@fff8c000 { |
| 352 | compatible = "atmel,at91sam9260-usart"; |
| 353 | reg = <0xfff8c000 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 354 | interrupts = <7 4 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 355 | atmel,use-dma-rx; |
| 356 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 357 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 358 | pinctrl-0 = <&pinctrl_usart0>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 359 | status = "disabled"; |
| 360 | }; |
| 361 | |
| 362 | usart1: serial@fff90000 { |
| 363 | compatible = "atmel,at91sam9260-usart"; |
| 364 | reg = <0xfff90000 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 365 | interrupts = <8 4 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 366 | atmel,use-dma-rx; |
| 367 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 368 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 369 | pinctrl-0 = <&pinctrl_usart1>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 370 | status = "disabled"; |
| 371 | }; |
| 372 | |
| 373 | usart2: serial@fff94000 { |
| 374 | compatible = "atmel,at91sam9260-usart"; |
| 375 | reg = <0xfff94000 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 376 | interrupts = <9 4 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 377 | atmel,use-dma-rx; |
| 378 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 379 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 380 | pinctrl-0 = <&pinctrl_usart2>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 381 | status = "disabled"; |
| 382 | }; |
| 383 | |
| 384 | usart3: serial@fff98000 { |
| 385 | compatible = "atmel,at91sam9260-usart"; |
| 386 | reg = <0xfff98000 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 387 | interrupts = <10 4 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 388 | atmel,use-dma-rx; |
| 389 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 390 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 391 | pinctrl-0 = <&pinctrl_usart3>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 392 | status = "disabled"; |
| 393 | }; |
Nicolas Ferre | 0d4f99d | 2011-12-05 18:03:05 +0100 | [diff] [blame] | 394 | |
| 395 | macb0: ethernet@fffbc000 { |
| 396 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 397 | reg = <0xfffbc000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 398 | interrupts = <25 4 3>; |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 399 | pinctrl-names = "default"; |
| 400 | pinctrl-0 = <&pinctrl_macb_rmii>; |
Nicolas Ferre | 0d4f99d | 2011-12-05 18:03:05 +0100 | [diff] [blame] | 401 | status = "disabled"; |
| 402 | }; |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 403 | |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 404 | i2c0: i2c@fff84000 { |
| 405 | compatible = "atmel,at91sam9g10-i2c"; |
| 406 | reg = <0xfff84000 0x100>; |
| 407 | interrupts = <12 4 6>; |
| 408 | #address-cells = <1>; |
| 409 | #size-cells = <0>; |
| 410 | status = "disabled"; |
| 411 | }; |
| 412 | |
| 413 | i2c1: i2c@fff88000 { |
| 414 | compatible = "atmel,at91sam9g10-i2c"; |
| 415 | reg = <0xfff88000 0x100>; |
| 416 | interrupts = <13 4 6>; |
| 417 | #address-cells = <1>; |
| 418 | #size-cells = <0>; |
| 419 | status = "disabled"; |
| 420 | }; |
| 421 | |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 422 | adc0: adc@fffb0000 { |
| 423 | compatible = "atmel,at91sam9260-adc"; |
| 424 | reg = <0xfffb0000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 425 | interrupts = <20 4 0>; |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 426 | atmel,adc-use-external-triggers; |
| 427 | atmel,adc-channels-used = <0xff>; |
| 428 | atmel,adc-vref = <3300>; |
| 429 | atmel,adc-num-channels = <8>; |
| 430 | atmel,adc-startup-time = <40>; |
| 431 | atmel,adc-channel-base = <0x30>; |
| 432 | atmel,adc-drdy-mask = <0x10000>; |
| 433 | atmel,adc-status-register = <0x1c>; |
| 434 | atmel,adc-trigger-register = <0x08>; |
| 435 | |
| 436 | trigger@0 { |
| 437 | trigger-name = "external-rising"; |
| 438 | trigger-value = <0x1>; |
| 439 | trigger-external; |
| 440 | }; |
| 441 | trigger@1 { |
| 442 | trigger-name = "external-falling"; |
| 443 | trigger-value = <0x2>; |
| 444 | trigger-external; |
| 445 | }; |
| 446 | |
| 447 | trigger@2 { |
| 448 | trigger-name = "external-any"; |
| 449 | trigger-value = <0x3>; |
| 450 | trigger-external; |
| 451 | }; |
| 452 | |
| 453 | trigger@3 { |
| 454 | trigger-name = "continuous"; |
| 455 | trigger-value = <0x6>; |
| 456 | }; |
| 457 | }; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 458 | |
| 459 | mmc0: mmc@fff80000 { |
| 460 | compatible = "atmel,hsmci"; |
| 461 | reg = <0xfff80000 0x600>; |
| 462 | interrupts = <11 4 0>; |
| 463 | #address-cells = <1>; |
| 464 | #size-cells = <0>; |
| 465 | status = "disabled"; |
| 466 | }; |
| 467 | |
| 468 | mmc1: mmc@fffd0000 { |
| 469 | compatible = "atmel,hsmci"; |
| 470 | reg = <0xfffd0000 0x600>; |
| 471 | interrupts = <29 4 0>; |
| 472 | #address-cells = <1>; |
| 473 | #size-cells = <0>; |
| 474 | status = "disabled"; |
| 475 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 476 | }; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 477 | |
| 478 | nand0: nand@40000000 { |
| 479 | compatible = "atmel,at91rm9200-nand"; |
| 480 | #address-cells = <1>; |
| 481 | #size-cells = <1>; |
| 482 | reg = <0x40000000 0x10000000 |
| 483 | 0xffffe200 0x200 |
| 484 | >; |
| 485 | atmel,nand-addr-offset = <21>; |
| 486 | atmel,nand-cmd-offset = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 487 | pinctrl-names = "default"; |
| 488 | pinctrl-0 = <&pinctrl_nand>; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 489 | gpios = <&pioC 8 0 |
| 490 | &pioC 14 0 |
| 491 | 0 |
| 492 | >; |
| 493 | status = "disabled"; |
| 494 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 495 | |
| 496 | usb0: ohci@00700000 { |
| 497 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 498 | reg = <0x00700000 0x100000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 499 | interrupts = <22 4 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 500 | status = "disabled"; |
| 501 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 502 | |
| 503 | usb1: ehci@00800000 { |
| 504 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 505 | reg = <0x00800000 0x100000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 506 | interrupts = <22 4 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 507 | status = "disabled"; |
| 508 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 509 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 8f24bda | 2012-02-05 18:32:37 +0800 | [diff] [blame] | 510 | |
| 511 | i2c@0 { |
| 512 | compatible = "i2c-gpio"; |
| 513 | gpios = <&pioA 20 0 /* sda */ |
| 514 | &pioA 21 0 /* scl */ |
| 515 | >; |
| 516 | i2c-gpio,sda-open-drain; |
| 517 | i2c-gpio,scl-open-drain; |
| 518 | i2c-gpio,delay-us = <5>; /* ~100 kHz */ |
| 519 | #address-cells = <1>; |
| 520 | #size-cells = <0>; |
| 521 | status = "disabled"; |
| 522 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 523 | }; |