Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / e011c6ce2b4fc7c577ade41485d74431a4e6ea1a / . / drivers / gpu / drm / i915 / gvt / handlers.c
blob: acc1cf4fa6f53360efe85d15c8d104aff3bf8277 [file] [log] [blame]
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +0800[diff] [blame]40#include "gvt.h"
41#include "i915_pvinfo.h"
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]42
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]50unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51{
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
Xu Hane3476c02017-03-29 10:13:59 +0800[diff] [blame]56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]58
59 return 0;
60}
61
62bool intel_gvt_match_device(struct intel_gvt *gvt,
63 unsigned long device)
64{
65 return intel_gvt_get_device_type(gvt) & device;
66}
67
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]68static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
69 void *p_data, unsigned int bytes)
70{
71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
72}
73
74static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76{
77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
78}
79
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]80static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
81 unsigned int offset)
82{
83 struct intel_gvt_mmio_info *e;
84
85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
86 if (e->offset == offset)
87 return e;
88 }
89 return NULL;
90}
91
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]92static int new_mmio_info(struct intel_gvt *gvt,
Changbin Du56a78de2017-06-06 15:56:11 +0800[diff] [blame]93 u32 offset, u8 flags, u32 size,
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]94 u32 addr_mask, u32 ro_mask, u32 device,
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]95 gvt_mmio_func read, gvt_mmio_func write)
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]96{
97 struct intel_gvt_mmio_info *info, *p;
98 u32 start, end, i;
99
100 if (!intel_gvt_match_device(gvt, device))
101 return 0;
102
103 if (WARN_ON(!IS_ALIGNED(offset, 4)))
104 return -EINVAL;
105
106 start = offset;
107 end = offset + size;
108
109 for (i = start; i < end; i += 4) {
110 info = kzalloc(sizeof(*info), GFP_KERNEL);
111 if (!info)
112 return -ENOMEM;
113
114 info->offset = i;
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]115 p = find_mmio_info(gvt, info->offset);
Jian Jun Chen36ed7e92017-07-19 12:18:39 +0800[diff] [blame]116 if (p) {
117 WARN(1, "dup mmio definition offset %x\n",
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]118 info->offset);
Jian Jun Chen36ed7e92017-07-19 12:18:39 +0800[diff] [blame]119 kfree(info);
120
121 /* We return -EEXIST here to make GVT-g load fail.
122 * So duplicated MMIO can be found as soon as
123 * possible.
124 */
125 return -EEXIST;
126 }
Changbin Dud8d94ba2017-06-06 15:56:10 +0800[diff] [blame]127
Zhao Yan4ec3dd82017-03-02 15:12:47 +0800[diff] [blame]128 info->ro_mask = ro_mask;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]129 info->device = device;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]130 info->read = read ? read : intel_vgpu_default_mmio_read;
131 info->write = write ? write : intel_vgpu_default_mmio_write;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]132 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
133 INIT_HLIST_NODE(&info->node);
134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
Changbin Dufbfd76c2017-06-06 15:56:13 +0800[diff] [blame]135 gvt->mmio.num_tracked_mmio++;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]136 }
137 return 0;
138}
139
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]140static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
141{
Zhenyu Wang0fac21e2016-10-20 13:30:33 +0800[diff] [blame]142 enum intel_engine_id id;
143 struct intel_engine_cs *engine;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]144
145 reg &= ~GENMASK(11, 0);
Zhenyu Wang0fac21e2016-10-20 13:30:33 +0800[diff] [blame]146 for_each_engine(engine, gvt->dev_priv, id) {
147 if (engine->mmio_base == reg)
148 return id;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]149 }
150 return -1;
151}
152
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]153#define offset_to_fence_num(offset) \
154 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
155
156#define fence_num_to_offset(num) \
157 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
158
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]159
fred gaoe011c6c2017-09-19 15:11:28 +0800[diff] [blame^]160void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]161{
162 switch (reason) {
163 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
164 pr_err("Detected your guest driver doesn't support GVT-g.\n");
165 break;
Min Hea33fc7a2017-02-17 16:42:38 +0800[diff] [blame]166 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
167 pr_err("Graphics resource is not enough for the guest\n");
fred gaoe011c6c2017-09-19 15:11:28 +0800[diff] [blame^]168 case GVT_FAILSAFE_GUEST_ERR:
169 pr_err("GVT Internal error for the guest\n");
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]170 default:
171 break;
172 }
173 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
174 vgpu->failsafe = true;
175}
176
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]177static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
178 unsigned int fence_num, void *p_data, unsigned int bytes)
179{
180 if (fence_num >= vgpu_fence_sz(vgpu)) {
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]181
182 /* When guest access oob fence regs without access
183 * pv_info first, we treat guest not supporting GVT,
184 * and we will let vgpu enter failsafe mode.
185 */
Zhao, Xindad1be3712017-02-17 14:38:33 +0800[diff] [blame]186 if (!vgpu->pv_notified)
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]187 enter_failsafe_mode(vgpu,
188 GVT_FAILSAFE_UNSUPPORTED_GUEST);
Zhao, Xindad1be3712017-02-17 14:38:33 +0800[diff] [blame]189
190 if (!vgpu->mmio.disable_warn_untrack) {
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]191 gvt_vgpu_err("found oob fence register access\n");
192 gvt_vgpu_err("total fence %d, access fence %d\n",
193 vgpu_fence_sz(vgpu), fence_num);
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]194 }
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]195 memset(p_data, 0, bytes);
Zhao, Xindad1be3712017-02-17 14:38:33 +0800[diff] [blame]196 return -EINVAL;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]197 }
198 return 0;
199}
200
201static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
202 void *p_data, unsigned int bytes)
203{
204 int ret;
205
206 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
207 p_data, bytes);
208 if (ret)
209 return ret;
210 read_vreg(vgpu, off, p_data, bytes);
211 return 0;
212}
213
214static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
215 void *p_data, unsigned int bytes)
216{
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]217 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]218 unsigned int fence_num = offset_to_fence_num(off);
219 int ret;
220
221 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
222 if (ret)
223 return ret;
224 write_vreg(vgpu, off, p_data, bytes);
225
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]226 mmio_hw_access_pre(dev_priv);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]227 intel_vgpu_write_fence(vgpu, fence_num,
228 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]229 mmio_hw_access_post(dev_priv);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]230 return 0;
231}
232
233#define CALC_MODE_MASK_REG(old, new) \
234 (((new) & GENMASK(31, 16)) \
235 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
236 | ((new) & ((new) >> 16))))
237
238static int mul_force_wake_write(struct intel_vgpu *vgpu,
239 unsigned int offset, void *p_data, unsigned int bytes)
240{
241 u32 old, new;
242 uint32_t ack_reg_offset;
243
244 old = vgpu_vreg(vgpu, offset);
245 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
246
Xu Hane3476c02017-03-29 10:13:59 +0800[diff] [blame]247 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
248 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]249 switch (offset) {
250 case FORCEWAKE_RENDER_GEN9_REG:
251 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
252 break;
253 case FORCEWAKE_BLITTER_GEN9_REG:
254 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
255 break;
256 case FORCEWAKE_MEDIA_GEN9_REG:
257 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
258 break;
259 default:
260 /*should not hit here*/
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]261 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
Changbin Du39762ad2016-12-27 13:25:06 +0800[diff] [blame]262 return -EINVAL;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]263 }
264 } else {
265 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
266 }
267
268 vgpu_vreg(vgpu, offset) = new;
269 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
270 return 0;
271}
272
273static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]274 void *p_data, unsigned int bytes)
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]275{
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]276 unsigned int engine_mask = 0;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]277 u32 data;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]278
Ping Gao40d24282016-10-26 09:38:50 +0800[diff] [blame]279 write_vreg(vgpu, offset, p_data, bytes);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]280 data = vgpu_vreg(vgpu, offset);
281
282 if (data & GEN6_GRDOM_FULL) {
283 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]284 engine_mask = ALL_ENGINES;
285 } else {
286 if (data & GEN6_GRDOM_RENDER) {
287 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
288 engine_mask |= (1 << RCS);
289 }
290 if (data & GEN6_GRDOM_MEDIA) {
291 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
292 engine_mask |= (1 << VCS);
293 }
294 if (data & GEN6_GRDOM_BLT) {
295 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
296 engine_mask |= (1 << BCS);
297 }
298 if (data & GEN6_GRDOM_VECS) {
299 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
300 engine_mask |= (1 << VECS);
301 }
302 if (data & GEN8_GRDOM_MEDIA2) {
303 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
304 if (HAS_BSD2(vgpu->gvt->dev_priv))
305 engine_mask |= (1 << VCS2);
306 }
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]307 }
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]308
309 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
310
fred gao0811fa62017-05-24 12:02:24 +0800[diff] [blame]311 /* sw will wait for the device to ack the reset request */
312 vgpu_vreg(vgpu, offset) = 0;
313
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]314 return 0;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]315}
316
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]317static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
318 void *p_data, unsigned int bytes)
319{
320 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
321}
322
323static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
324 void *p_data, unsigned int bytes)
325{
326 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
327}
328
329static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
330 unsigned int offset, void *p_data, unsigned int bytes)
331{
332 write_vreg(vgpu, offset, p_data, bytes);
333
334 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
335 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
336 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
337 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
338 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
339
340 } else
341 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
342 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
343 | PP_CYCLE_DELAY_ACTIVE);
344 return 0;
345}
346
347static int transconf_mmio_write(struct intel_vgpu *vgpu,
348 unsigned int offset, void *p_data, unsigned int bytes)
349{
350 write_vreg(vgpu, offset, p_data, bytes);
351
352 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
353 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
354 else
355 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
356 return 0;
357}
358
359static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
360 void *p_data, unsigned int bytes)
361{
362 write_vreg(vgpu, offset, p_data, bytes);
363
364 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
365 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
366 else
367 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
368
369 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
370 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
371 else
372 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
373
374 return 0;
375}
376
377static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
378 void *p_data, unsigned int bytes)
379{
Changbin Du5cd82b72017-06-13 10:15:26 +0800[diff] [blame]380 switch (offset) {
381 case 0xe651c:
382 case 0xe661c:
383 case 0xe671c:
384 case 0xe681c:
385 vgpu_vreg(vgpu, offset) = 1 << 17;
386 break;
387 case 0xe6c04:
388 vgpu_vreg(vgpu, offset) = 0x3;
389 break;
390 case 0xe6e1c:
391 vgpu_vreg(vgpu, offset) = 0x2f << 16;
392 break;
393 default:
394 return -EINVAL;
395 }
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]396
Changbin Du5cd82b72017-06-13 10:15:26 +0800[diff] [blame]397 read_vreg(vgpu, offset, p_data, bytes);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]398 return 0;
399}
400
401static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
402 void *p_data, unsigned int bytes)
403{
404 u32 data;
405
406 write_vreg(vgpu, offset, p_data, bytes);
407 data = vgpu_vreg(vgpu, offset);
408
409 if (data & PIPECONF_ENABLE)
410 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
411 else
412 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
413 intel_gvt_check_vblank_emulation(vgpu->gvt);
414 return 0;
415}
416
Zhao Yane6cedfe2017-02-21 10:38:53 +0800[diff] [blame]417/* ascendingly sorted */
418static i915_reg_t force_nonpriv_white_list[] = {
419 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
420 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
421 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
422 _MMIO(0x2690),
423 _MMIO(0x2694),
424 _MMIO(0x2698),
425 _MMIO(0x4de0),
426 _MMIO(0x4de4),
427 _MMIO(0x4dfc),
428 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
429 _MMIO(0x7014),
430 HDC_CHICKEN0,//_MMIO(0x7300)
431 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
432 _MMIO(0x7700),
433 _MMIO(0x7704),
434 _MMIO(0x7708),
435 _MMIO(0x770c),
436 _MMIO(0xb110),
437 GEN8_L3SQCREG4,//_MMIO(0xb118)
438 _MMIO(0xe100),
439 _MMIO(0xe18c),
440 _MMIO(0xe48c),
441 _MMIO(0xe5f4),
442};
443
444/* a simple bsearch */
445static inline bool in_whitelist(unsigned int reg)
446{
447 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
448 i915_reg_t *array = force_nonpriv_white_list;
449
450 while (left < right) {
451 int mid = (left + right)/2;
452
453 if (reg > array[mid].reg)
454 left = mid + 1;
455 else if (reg < array[mid].reg)
456 right = mid;
457 else
458 return true;
459 }
460 return false;
461}
462
463static int force_nonpriv_write(struct intel_vgpu *vgpu,
464 unsigned int offset, void *p_data, unsigned int bytes)
465{
466 u32 reg_nonpriv = *(u32 *)p_data;
467 int ret = -EINVAL;
468
469 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
470 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
471 vgpu->id, offset, bytes);
472 return ret;
473 }
474
475 if (in_whitelist(reg_nonpriv)) {
476 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
477 bytes);
478 } else {
479 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
480 vgpu->id, reg_nonpriv);
481 }
482 return ret;
483}
484
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]485static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
486 void *p_data, unsigned int bytes)
487{
488 write_vreg(vgpu, offset, p_data, bytes);
489
490 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
491 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
492 } else {
493 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
494 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
495 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
496 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
497 }
498 return 0;
499}
500
501static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
502 unsigned int offset, void *p_data, unsigned int bytes)
503{
504 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
505 return 0;
506}
507
508#define FDI_LINK_TRAIN_PATTERN1 0
509#define FDI_LINK_TRAIN_PATTERN2 1
510
511static int fdi_auto_training_started(struct intel_vgpu *vgpu)
512{
513 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
514 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
515 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
516
517 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
518 (rx_ctl & FDI_RX_ENABLE) &&
519 (rx_ctl & FDI_AUTO_TRAINING) &&
520 (tx_ctl & DP_TP_CTL_ENABLE) &&
521 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
522 return 1;
523 else
524 return 0;
525}
526
527static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
528 enum pipe pipe, unsigned int train_pattern)
529{
530 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
531 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
532 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
533 unsigned int fdi_iir_check_bits;
534
535 fdi_rx_imr = FDI_RX_IMR(pipe);
536 fdi_tx_ctl = FDI_TX_CTL(pipe);
537 fdi_rx_ctl = FDI_RX_CTL(pipe);
538
539 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
540 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
541 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
542 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
543 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
544 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
545 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
546 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
547 } else {
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]548 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]549 return -EINVAL;
550 }
551
552 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
553 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
554
555 /* If imr bit has been masked */
556 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
557 return 0;
558
559 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
560 == fdi_tx_check_bits)
561 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
562 == fdi_rx_check_bits))
563 return 1;
564 else
565 return 0;
566}
567
568#define INVALID_INDEX (~0U)
569
570static unsigned int calc_index(unsigned int offset, unsigned int start,
571 unsigned int next, unsigned int end, i915_reg_t i915_end)
572{
573 unsigned int range = next - start;
574
575 if (!end)
576 end = i915_mmio_reg_offset(i915_end);
577 if (offset < start || offset > end)
578 return INVALID_INDEX;
579 offset -= start;
580 return offset / range;
581}
582
583#define FDI_RX_CTL_TO_PIPE(offset) \
584 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
585
586#define FDI_TX_CTL_TO_PIPE(offset) \
587 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
588
589#define FDI_RX_IMR_TO_PIPE(offset) \
590 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
591
592static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
593 unsigned int offset, void *p_data, unsigned int bytes)
594{
595 i915_reg_t fdi_rx_iir;
596 unsigned int index;
597 int ret;
598
599 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
600 index = FDI_RX_CTL_TO_PIPE(offset);
601 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
602 index = FDI_TX_CTL_TO_PIPE(offset);
603 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
604 index = FDI_RX_IMR_TO_PIPE(offset);
605 else {
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]606 gvt_vgpu_err("Unsupport registers %x\n", offset);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]607 return -EINVAL;
608 }
609
610 write_vreg(vgpu, offset, p_data, bytes);
611
612 fdi_rx_iir = FDI_RX_IIR(index);
613
614 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
615 if (ret < 0)
616 return ret;
617 if (ret)
618 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
619
620 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
621 if (ret < 0)
622 return ret;
623 if (ret)
624 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
625
626 if (offset == _FDI_RXA_CTL)
627 if (fdi_auto_training_started(vgpu))
628 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
629 DP_TP_STATUS_AUTOTRAIN_DONE;
630 return 0;
631}
632
633#define DP_TP_CTL_TO_PORT(offset) \
634 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
635
636static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
637 void *p_data, unsigned int bytes)
638{
639 i915_reg_t status_reg;
640 unsigned int index;
641 u32 data;
642
643 write_vreg(vgpu, offset, p_data, bytes);
644
645 index = DP_TP_CTL_TO_PORT(offset);
646 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
647 if (data == 0x2) {
648 status_reg = DP_TP_STATUS(index);
649 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
650 }
651 return 0;
652}
653
654static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
655 unsigned int offset, void *p_data, unsigned int bytes)
656{
657 u32 reg_val;
658 u32 sticky_mask;
659
660 reg_val = *((u32 *)p_data);
661 sticky_mask = GENMASK(27, 26) | (1 << 24);
662
663 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
664 (vgpu_vreg(vgpu, offset) & sticky_mask);
665 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
666 return 0;
667}
668
669static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
670 unsigned int offset, void *p_data, unsigned int bytes)
671{
672 u32 data;
673
674 write_vreg(vgpu, offset, p_data, bytes);
675 data = vgpu_vreg(vgpu, offset);
676
677 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
678 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
679 return 0;
680}
681
682static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
683 unsigned int offset, void *p_data, unsigned int bytes)
684{
685 u32 data;
686
687 write_vreg(vgpu, offset, p_data, bytes);
688 data = vgpu_vreg(vgpu, offset);
689
690 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
691 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
692 else
693 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
694 return 0;
695}
696
697#define DSPSURF_TO_PIPE(offset) \
698 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
699
700static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
701 void *p_data, unsigned int bytes)
702{
703 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
704 unsigned int index = DSPSURF_TO_PIPE(offset);
705 i915_reg_t surflive_reg = DSPSURFLIVE(index);
706 int flip_event[] = {
707 [PIPE_A] = PRIMARY_A_FLIP_DONE,
708 [PIPE_B] = PRIMARY_B_FLIP_DONE,
709 [PIPE_C] = PRIMARY_C_FLIP_DONE,
710 };
711
712 write_vreg(vgpu, offset, p_data, bytes);
713 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
714
715 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
716 return 0;
717}
718
719#define SPRSURF_TO_PIPE(offset) \
720 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
721
722static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
723 void *p_data, unsigned int bytes)
724{
725 unsigned int index = SPRSURF_TO_PIPE(offset);
726 i915_reg_t surflive_reg = SPRSURFLIVE(index);
727 int flip_event[] = {
728 [PIPE_A] = SPRITE_A_FLIP_DONE,
729 [PIPE_B] = SPRITE_B_FLIP_DONE,
730 [PIPE_C] = SPRITE_C_FLIP_DONE,
731 };
732
733 write_vreg(vgpu, offset, p_data, bytes);
734 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
735
736 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
737 return 0;
738}
739
740static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
741 unsigned int reg)
742{
743 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
744 enum intel_gvt_event_type event;
745
746 if (reg == _DPA_AUX_CH_CTL)
747 event = AUX_CHANNEL_A;
748 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
749 event = AUX_CHANNEL_B;
750 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
751 event = AUX_CHANNEL_C;
752 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
753 event = AUX_CHANNEL_D;
754 else {
755 WARN_ON(true);
756 return -EINVAL;
757 }
758
759 intel_vgpu_trigger_virtual_event(vgpu, event);
760 return 0;
761}
762
763static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
764 unsigned int reg, int len, bool data_valid)
765{
766 /* mark transaction done */
767 value |= DP_AUX_CH_CTL_DONE;
768 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
769 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
770
771 if (data_valid)
772 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
773 else
774 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
775
776 /* message size */
777 value &= ~(0xf << 20);
778 value |= (len << 20);
779 vgpu_vreg(vgpu, reg) = value;
780
781 if (value & DP_AUX_CH_CTL_INTERRUPT)
782 return trigger_aux_channel_interrupt(vgpu, reg);
783 return 0;
784}
785
786static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
787 uint8_t t)
788{
789 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
790 /* training pattern 1 for CR */
791 /* set LANE0_CR_DONE, LANE1_CR_DONE */
792 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
793 /* set LANE2_CR_DONE, LANE3_CR_DONE */
794 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
795 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
796 DPCD_TRAINING_PATTERN_2) {
797 /* training pattern 2 for EQ */
798 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
799 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
800 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
801 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
802 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
803 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
804 /* set INTERLANE_ALIGN_DONE */
805 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
806 DPCD_INTERLANE_ALIGN_DONE;
807 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
808 DPCD_LINK_TRAINING_DISABLED) {
809 /* finish link training */
810 /* set sink status as synchronized */
811 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
812 }
813}
814
815#define _REG_HSW_DP_AUX_CH_CTL(dp) \
816 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
817
818#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
819
820#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
821
822#define dpy_is_valid_port(port) \
823 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
824
825static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
826 unsigned int offset, void *p_data, unsigned int bytes)
827{
828 struct intel_vgpu_display *display = &vgpu->display;
829 int msg, addr, ctrl, op, len;
830 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
831 struct intel_vgpu_dpcd_data *dpcd = NULL;
832 struct intel_vgpu_port *port = NULL;
833 u32 data;
834
835 if (!dpy_is_valid_port(port_index)) {
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]836 gvt_vgpu_err("Unsupported DP port access!\n");
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]837 return 0;
838 }
839
840 write_vreg(vgpu, offset, p_data, bytes);
841 data = vgpu_vreg(vgpu, offset);
842
Xu Hane3476c02017-03-29 10:13:59 +0800[diff] [blame]843 if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
844 || IS_KABYLAKE(vgpu->gvt->dev_priv))
845 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]846 /* SKL DPB/C/D aux ctl register changed */
847 return 0;
848 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
849 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
850 /* write to the data registers */
851 return 0;
852 }
853
854 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
855 /* just want to clear the sticky bits */
856 vgpu_vreg(vgpu, offset) = 0;
857 return 0;
858 }
859
860 port = &display->ports[port_index];
861 dpcd = port->dpcd;
862
863 /* read out message from DATA1 register */
864 msg = vgpu_vreg(vgpu, offset + 4);
865 addr = (msg >> 8) & 0xffff;
866 ctrl = (msg >> 24) & 0xff;
867 len = msg & 0xff;
868 op = ctrl >> 4;
869
870 if (op == GVT_AUX_NATIVE_WRITE) {
871 int t;
872 uint8_t buf[16];
873
874 if ((addr + len + 1) >= DPCD_SIZE) {
875 /*
876 * Write request exceeds what we supported,
877 * DCPD spec: When a Source Device is writing a DPCD
878 * address not supported by the Sink Device, the Sink
879 * Device shall reply with AUX NACK and “M” equal to
880 * zero.
881 */
882
883 /* NAK the write */
884 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
885 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
886 return 0;
887 }
888
889 /*
890 * Write request format: (command + address) occupies
891 * 3 bytes, followed by (len + 1) bytes of data.
892 */
893 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
894 return -EINVAL;
895
896 /* unpack data from vreg to buf */
897 for (t = 0; t < 4; t++) {
898 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
899
900 buf[t * 4] = (r >> 24) & 0xff;
901 buf[t * 4 + 1] = (r >> 16) & 0xff;
902 buf[t * 4 + 2] = (r >> 8) & 0xff;
903 buf[t * 4 + 3] = r & 0xff;
904 }
905
906 /* write to virtual DPCD */
907 if (dpcd && dpcd->data_valid) {
908 for (t = 0; t <= len; t++) {
909 int p = addr + t;
910
911 dpcd->data[p] = buf[t];
912 /* check for link training */
913 if (p == DPCD_TRAINING_PATTERN_SET)
914 dp_aux_ch_ctl_link_training(dpcd,
915 buf[t]);
916 }
917 }
918
919 /* ACK the write */
920 vgpu_vreg(vgpu, offset + 4) = 0;
921 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
922 dpcd && dpcd->data_valid);
923 return 0;
924 }
925
926 if (op == GVT_AUX_NATIVE_READ) {
927 int idx, i, ret = 0;
928
929 if ((addr + len + 1) >= DPCD_SIZE) {
930 /*
931 * read request exceeds what we supported
932 * DPCD spec: A Sink Device receiving a Native AUX CH
933 * read request for an unsupported DPCD address must
934 * reply with an AUX ACK and read data set equal to
935 * zero instead of replying with AUX NACK.
936 */
937
938 /* ACK the READ*/
939 vgpu_vreg(vgpu, offset + 4) = 0;
940 vgpu_vreg(vgpu, offset + 8) = 0;
941 vgpu_vreg(vgpu, offset + 12) = 0;
942 vgpu_vreg(vgpu, offset + 16) = 0;
943 vgpu_vreg(vgpu, offset + 20) = 0;
944
945 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
946 true);
947 return 0;
948 }
949
950 for (idx = 1; idx <= 5; idx++) {
951 /* clear the data registers */
952 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
953 }
954
955 /*
956 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
957 */
958 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
959 return -EINVAL;
960
961 /* read from virtual DPCD to vreg */
962 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
963 if (dpcd && dpcd->data_valid) {
964 for (i = 1; i <= (len + 1); i++) {
965 int t;
966
967 t = dpcd->data[addr + i - 1];
968 t <<= (24 - 8 * (i % 4));
969 ret |= t;
970
971 if ((i % 4 == 3) || (i == (len + 1))) {
972 vgpu_vreg(vgpu, offset +
973 (i / 4 + 1) * 4) = ret;
974 ret = 0;
975 }
976 }
977 }
978 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
979 dpcd && dpcd->data_valid);
980 return 0;
981 }
982
983 /* i2c transaction starts */
984 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
985
986 if (data & DP_AUX_CH_CTL_INTERRUPT)
987 trigger_aux_channel_interrupt(vgpu, offset);
988 return 0;
989}
990
Pei Zhang975629c2017-03-20 23:49:19 +0800[diff] [blame]991static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
992 void *p_data, unsigned int bytes)
993{
994 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
995 write_vreg(vgpu, offset, p_data, bytes);
996 return 0;
997}
998
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]999static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1000 void *p_data, unsigned int bytes)
1001{
1002 bool vga_disable;
1003
1004 write_vreg(vgpu, offset, p_data, bytes);
1005 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1006
1007 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1008 vga_disable ? "Disable" : "Enable");
1009 return 0;
1010}
1011
1012static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1013 unsigned int sbi_offset)
1014{
1015 struct intel_vgpu_display *display = &vgpu->display;
1016 int num = display->sbi.number;
1017 int i;
1018
1019 for (i = 0; i < num; ++i)
1020 if (display->sbi.registers[i].offset == sbi_offset)
1021 break;
1022
1023 if (i == num)
1024 return 0;
1025
1026 return display->sbi.registers[i].value;
1027}
1028
1029static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1030 unsigned int offset, u32 value)
1031{
1032 struct intel_vgpu_display *display = &vgpu->display;
1033 int num = display->sbi.number;
1034 int i;
1035
1036 for (i = 0; i < num; ++i) {
1037 if (display->sbi.registers[i].offset == offset)
1038 break;
1039 }
1040
1041 if (i == num) {
1042 if (num == SBI_REG_MAX) {
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]1043 gvt_vgpu_err("SBI caching meets maximum limits\n");
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1044 return;
1045 }
1046 display->sbi.number++;
1047 }
1048
1049 display->sbi.registers[i].offset = offset;
1050 display->sbi.registers[i].value = value;
1051}
1052
1053static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1054 void *p_data, unsigned int bytes)
1055{
1056 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1057 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1058 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1059 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1060 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1061 sbi_offset);
1062 }
1063 read_vreg(vgpu, offset, p_data, bytes);
1064 return 0;
1065}
1066
Nicolas Iooss3e70c5d2016-12-26 14:52:23 +0100[diff] [blame]1067static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1068 void *p_data, unsigned int bytes)
1069{
1070 u32 data;
1071
1072 write_vreg(vgpu, offset, p_data, bytes);
1073 data = vgpu_vreg(vgpu, offset);
1074
1075 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1076 data |= SBI_READY;
1077
1078 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1079 data |= SBI_RESPONSE_SUCCESS;
1080
1081 vgpu_vreg(vgpu, offset) = data;
1082
1083 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1084 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1085 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1086 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1087
1088 write_virtual_sbi_register(vgpu, sbi_offset,
1089 vgpu_vreg(vgpu, SBI_DATA));
1090 }
1091 return 0;
1092}
1093
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1094#define _vgtif_reg(x) \
1095 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1096
1097static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1098 void *p_data, unsigned int bytes)
1099{
1100 bool invalid_read = false;
1101
1102 read_vreg(vgpu, offset, p_data, bytes);
1103
1104 switch (offset) {
1105 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1106 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1107 invalid_read = true;
1108 break;
1109 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1110 _vgtif_reg(avail_rs.fence_num):
1111 if (offset + bytes >
1112 _vgtif_reg(avail_rs.fence_num) + 4)
1113 invalid_read = true;
1114 break;
1115 case 0x78010: /* vgt_caps */
1116 case 0x7881c:
1117 break;
1118 default:
1119 invalid_read = true;
1120 break;
1121 }
1122 if (invalid_read)
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]1123 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1124 offset, bytes, *(u32 *)p_data);
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]1125 vgpu->pv_notified = true;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1126 return 0;
1127}
1128
1129static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1130{
1131 int ret = 0;
1132
1133 switch (notification) {
1134 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1135 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1136 break;
1137 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1138 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1139 break;
1140 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1141 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1142 break;
1143 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1144 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1145 break;
1146 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1147 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1148 case 1: /* Remove this in guest driver. */
1149 break;
1150 default:
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]1151 gvt_vgpu_err("Invalid PV notification %d\n", notification);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1152 }
1153 return ret;
1154}
1155
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1156static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1157{
1158 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1159 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1160 char *env[3] = {NULL, NULL, NULL};
1161 char vmid_str[20];
1162 char display_ready_str[20];
1163
Takashi Iwaid8e9b2b2017-02-20 14:58:25 +0100[diff] [blame]1164 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1165 env[0] = display_ready_str;
1166
1167 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1168 env[1] = vmid_str;
1169
1170 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1171}
1172
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1173static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1174 void *p_data, unsigned int bytes)
1175{
1176 u32 data;
1177 int ret;
1178
1179 write_vreg(vgpu, offset, p_data, bytes);
1180 data = vgpu_vreg(vgpu, offset);
1181
1182 switch (offset) {
1183 case _vgtif_reg(display_ready):
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1184 send_display_ready_uevent(vgpu, data ? 1 : 0);
1185 break;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1186 case _vgtif_reg(g2v_notify):
1187 ret = handle_g2v_notification(vgpu, data);
1188 break;
1189 /* add xhot and yhot to handled list to avoid error log */
1190 case 0x78830:
1191 case 0x78834:
1192 case _vgtif_reg(pdp[0].lo):
1193 case _vgtif_reg(pdp[0].hi):
1194 case _vgtif_reg(pdp[1].lo):
1195 case _vgtif_reg(pdp[1].hi):
1196 case _vgtif_reg(pdp[2].lo):
1197 case _vgtif_reg(pdp[2].hi):
1198 case _vgtif_reg(pdp[3].lo):
1199 case _vgtif_reg(pdp[3].hi):
1200 case _vgtif_reg(execlist_context_descriptor_lo):
1201 case _vgtif_reg(execlist_context_descriptor_hi):
1202 break;
Min Hea33fc7a2017-02-17 16:42:38 +0800[diff] [blame]1203 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1204 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1205 break;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1206 default:
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]1207 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1208 offset, bytes, data);
1209 break;
1210 }
1211 return 0;
1212}
1213
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1214static int pf_write(struct intel_vgpu *vgpu,
1215 unsigned int offset, void *p_data, unsigned int bytes)
1216{
1217 u32 val = *(u32 *)p_data;
1218
1219 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1220 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1221 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1222 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1223 vgpu->id);
1224 return 0;
1225 }
1226
1227 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1228}
1229
1230static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1231 unsigned int offset, void *p_data, unsigned int bytes)
1232{
1233 write_vreg(vgpu, offset, p_data, bytes);
1234
Imre Deak1af474f2017-07-06 17:40:34 +0300[diff] [blame]1235 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
1236 vgpu_vreg(vgpu, offset) |=
1237 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1238 else
Imre Deak1af474f2017-07-06 17:40:34 +0300[diff] [blame]1239 vgpu_vreg(vgpu, offset) &=
1240 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1241 return 0;
1242}
1243
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1244static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1245 unsigned int offset, void *p_data, unsigned int bytes)
1246{
1247 write_vreg(vgpu, offset, p_data, bytes);
1248
1249 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1250 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1251 return 0;
1252}
1253
1254static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1255 void *p_data, unsigned int bytes)
1256{
Ping Gao5f399f12016-10-27 14:46:40 +0800[diff] [blame]1257 u32 mode;
1258
1259 write_vreg(vgpu, offset, p_data, bytes);
1260 mode = vgpu_vreg(vgpu, offset);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1261
1262 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
Colin Ian King7f48d0b2017-04-25 10:05:12 +0100[diff] [blame]1263 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1264 vgpu->id);
1265 return 0;
1266 }
1267
1268 return 0;
1269}
1270
1271static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1272 void *p_data, unsigned int bytes)
1273{
1274 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1275 u32 trtte = *(u32 *)p_data;
1276
1277 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1278 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1279 vgpu->id);
1280 return -EINVAL;
1281 }
1282 write_vreg(vgpu, offset, p_data, bytes);
1283 /* TRTTE is not per-context */
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]1284
1285 mmio_hw_access_pre(dev_priv);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1286 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]1287 mmio_hw_access_post(dev_priv);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1288
1289 return 0;
1290}
1291
1292static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1293 void *p_data, unsigned int bytes)
1294{
1295 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1296 u32 val = *(u32 *)p_data;
1297
1298 if (val & 1) {
1299 /* unblock hw logic */
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]1300 mmio_hw_access_pre(dev_priv);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1301 I915_WRITE(_MMIO(offset), val);
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]1302 mmio_hw_access_post(dev_priv);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1303 }
1304 write_vreg(vgpu, offset, p_data, bytes);
1305 return 0;
1306}
1307
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1308static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1309 void *p_data, unsigned int bytes)
1310{
1311 u32 v = 0;
1312
1313 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1314 v |= (1 << 0);
1315
1316 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1317 v |= (1 << 8);
1318
1319 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1320 v |= (1 << 16);
1321
1322 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1323 v |= (1 << 24);
1324
1325 vgpu_vreg(vgpu, offset) = v;
1326
1327 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1328}
1329
1330static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1331 void *p_data, unsigned int bytes)
1332{
1333 u32 value = *(u32 *)p_data;
1334 u32 cmd = value & 0xff;
1335 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1336
1337 switch (cmd) {
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1338 case GEN9_PCODE_READ_MEM_LATENCY:
Xu Hane3476c02017-03-29 10:13:59 +0800[diff] [blame]1339 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1340 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1341 /**
1342 * "Read memory latency" command on gen9.
1343 * Below memory latency values are read
1344 * from skylake platform.
1345 */
1346 if (!*data0)
1347 *data0 = 0x1e1a1100;
1348 else
1349 *data0 = 0x61514b3d;
1350 }
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1351 break;
Weinan Lid8a355b2017-02-22 11:03:24 +0800[diff] [blame]1352 case SKL_PCODE_CDCLK_CONTROL:
Xu Hane3476c02017-03-29 10:13:59 +0800[diff] [blame]1353 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1354 || IS_KABYLAKE(vgpu->gvt->dev_priv))
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1355 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
Weinan Lid8a355b2017-02-22 11:03:24 +0800[diff] [blame]1356 break;
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1357 case GEN6_PCODE_READ_RC6VIDS:
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1358 *data0 |= 0x1;
1359 break;
1360 }
1361
1362 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1363 vgpu->id, value, *data0);
Weinan Lid8a355b2017-02-22 11:03:24 +0800[diff] [blame]1364 /**
1365 * PCODE_READY clear means ready for pcode read/write,
1366 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1367 * always emulate as pcode read/write success and ready for access
1368 * anytime, since we don't touch real physical registers here.
1369 */
1370 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1371 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1372}
1373
1374static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1375 unsigned int offset, void *p_data, unsigned int bytes)
1376{
1377 u32 v = *(u32 *)p_data;
1378
1379 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1380 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1381 v |= (v >> 1);
1382
1383 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1384}
1385
1386static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1387 void *p_data, unsigned int bytes)
1388{
1389 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
Chuanxiao Dong1999f102017-05-17 15:49:01 +0800[diff] [blame]1390 u32 v = *(u32 *)p_data;
1391
1392 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
1393 return intel_vgpu_default_mmio_write(vgpu,
1394 offset, p_data, bytes);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1395
1396 switch (offset) {
1397 case 0x4ddc:
Chuanxiao Dong1999f102017-05-17 15:49:01 +0800[diff] [blame]1398 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1399 vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1400 break;
1401 case 0x42080:
Chuanxiao Dong1999f102017-05-17 15:49:01 +0800[diff] [blame]1402 /* bypass WaCompressedResourceDisplayNewHashMode */
1403 vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
1404 break;
1405 case 0xe194:
1406 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1407 vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
1408 break;
1409 case 0x7014:
1410 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1411 vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1412 break;
1413 default:
1414 return -EINVAL;
1415 }
1416
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1417 return 0;
1418}
1419
1420static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1421 void *p_data, unsigned int bytes)
1422{
1423 u32 v = *(u32 *)p_data;
1424
1425 /* other bits are MBZ. */
1426 v &= (1 << 31) | (1 << 30);
1427 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1428
1429 vgpu_vreg(vgpu, offset) = v;
1430
1431 return 0;
1432}
1433
Xiong Zhang20a2bcd2017-10-14 06:34:46 +0800[diff] [blame]1434static int mmio_read_from_hw(struct intel_vgpu *vgpu,
Weinan Li23ce0592017-05-19 23:48:34 +0800[diff] [blame]1435 unsigned int offset, void *p_data, unsigned int bytes)
1436{
1437 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1438
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]1439 mmio_hw_access_pre(dev_priv);
Weinan Li23ce0592017-05-19 23:48:34 +0800[diff] [blame]1440 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
Chuanxiao Dong9b7bd652017-06-02 15:34:23 +0800[diff] [blame]1441 mmio_hw_access_post(dev_priv);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1442 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1443}
1444
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1445static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1446 void *p_data, unsigned int bytes)
1447{
1448 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1449 struct intel_vgpu_execlist *execlist;
1450 u32 data = *(u32 *)p_data;
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1451 int ret = 0;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1452
Zhenyu Wang0fac21e2016-10-20 13:30:33 +0800[diff] [blame]1453 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1454 return -EINVAL;
1455
Zhi Wang1406a142017-09-10 21:15:18 +0800[diff] [blame]1456 execlist = &vgpu->submission.execlist[ring_id];
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1457
Zhi Wang54cff642017-09-10 16:40:04 +0800[diff] [blame]1458 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1459 if (execlist->elsp_dwords.index == 3) {
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1460 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1461 if(ret)
Tina Zhang695fbc02017-03-10 04:26:53 -0500[diff] [blame]1462 gvt_vgpu_err("fail submit workload on ring %d\n",
1463 ring_id);
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1464 }
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1465
1466 ++execlist->elsp_dwords.index;
1467 execlist->elsp_dwords.index &= 0x3;
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1468 return ret;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1469}
1470
Zhi Wang4b639602016-05-01 17:09:58 -0400[diff] [blame]1471static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1472 void *p_data, unsigned int bytes)
1473{
1474 u32 data = *(u32 *)p_data;
1475 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1476 bool enable_execlist;
1477
1478 write_vreg(vgpu, offset, p_data, bytes);
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]1479
1480 /* when PPGTT mode enabled, we will check if guest has called
1481 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1482 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1483 */
1484 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1485 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1486 && !vgpu->pv_notified) {
1487 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1488 return 0;
1489 }
Zhi Wang4b639602016-05-01 17:09:58 -0400[diff] [blame]1490 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1491 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1492 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1493
1494 gvt_dbg_core("EXECLIST %s on ring %d\n",
1495 (enable_execlist ? "enabling" : "disabling"),
1496 ring_id);
1497
1498 if (enable_execlist)
1499 intel_vgpu_start_schedule(vgpu);
1500 }
1501 return 0;
1502}
1503
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1504static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1505 unsigned int offset, void *p_data, unsigned int bytes)
1506{
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1507 unsigned int id = 0;
1508
Ping Gaof24940e2016-10-27 14:37:41 +0800[diff] [blame]1509 write_vreg(vgpu, offset, p_data, bytes);
Ping Gao4f3f1ae2016-11-10 15:27:20 +0800[diff] [blame]1510 vgpu_vreg(vgpu, offset) = 0;
Ping Gaof24940e2016-10-27 14:37:41 +0800[diff] [blame]1511
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1512 switch (offset) {
1513 case 0x4260:
1514 id = RCS;
1515 break;
1516 case 0x4264:
1517 id = VCS;
1518 break;
1519 case 0x4268:
1520 id = VCS2;
1521 break;
1522 case 0x426c:
1523 id = BCS;
1524 break;
1525 case 0x4270:
1526 id = VECS;
1527 break;
1528 default:
Changbin Dua1201052016-12-27 13:24:52 +0800[diff] [blame]1529 return -EINVAL;
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1530 }
Zhi Wang91d5d852017-09-10 21:33:20 +0800[diff] [blame]1531 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1532
Changbin Dua1201052016-12-27 13:24:52 +0800[diff] [blame]1533 return 0;
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1534}
1535
Du, Changbin2fb39fa2016-11-04 12:21:37 +0800[diff] [blame]1536static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1537 unsigned int offset, void *p_data, unsigned int bytes)
1538{
1539 u32 data;
1540
1541 write_vreg(vgpu, offset, p_data, bytes);
1542 data = vgpu_vreg(vgpu, offset);
1543
1544 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1545 data |= RESET_CTL_READY_TO_RESET;
1546 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1547 data &= ~RESET_CTL_READY_TO_RESET;
1548
1549 vgpu_vreg(vgpu, offset) = data;
1550 return 0;
1551}
1552
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1553#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1554 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1555 f, s, am, rm, d, r, w); \
1556 if (ret) \
1557 return ret; \
1558} while (0)
1559
1560#define MMIO_D(reg, d) \
1561 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1562
1563#define MMIO_DH(reg, d, r, w) \
1564 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1565
1566#define MMIO_DFH(reg, d, f, r, w) \
1567 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1568
1569#define MMIO_GM(reg, d, r, w) \
1570 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1571
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1572#define MMIO_GM_RDR(reg, d, r, w) \
1573 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1574
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1575#define MMIO_RO(reg, d, f, rm, r, w) \
1576 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1577
1578#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1579 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1580 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1581 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1582 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
Zhi Wangedee7ec2017-09-30 17:32:16 +0800[diff] [blame]1583 if (HAS_BSD2(dev_priv)) \
1584 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1585} while (0)
1586
1587#define MMIO_RING_D(prefix, d) \
1588 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1589
1590#define MMIO_RING_DFH(prefix, d, f, r, w) \
1591 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1592
1593#define MMIO_RING_GM(prefix, d, r, w) \
1594 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1595
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1596#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1597 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1598
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1599#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1600 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1601
1602static int init_generic_mmio_info(struct intel_gvt *gvt)
1603{
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1604 struct drm_i915_private *dev_priv = gvt->dev_priv;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1605 int ret;
1606
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1607 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1608 intel_vgpu_reg_imr_handler);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1609
1610 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1611 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1612 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1613 MMIO_D(SDEISR, D_ALL);
1614
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1615 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1616
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1617 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1618 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1619 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1620 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1621
1622#define RING_REG(base) (base + 0x28)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1623 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1624#undef RING_REG
1625
1626#define RING_REG(base) (base + 0x134)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1627 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1628#undef RING_REG
1629
Weinan Li23ce0592017-05-19 23:48:34 +0800[diff] [blame]1630#define RING_REG(base) (base + 0x6c)
Xiong Zhang20a2bcd2017-10-14 06:34:46 +0800[diff] [blame]1631 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
Weinan Li23ce0592017-05-19 23:48:34 +0800[diff] [blame]1632#undef RING_REG
Xiong Zhang20a2bcd2017-10-14 06:34:46 +0800[diff] [blame]1633 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
Weinan Li23ce0592017-05-19 23:48:34 +0800[diff] [blame]1634
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1635 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1636 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1637 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1638 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1639
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1640 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1641 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1642 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
Xiong Zhang894e2872017-10-14 06:34:47 +0800[diff] [blame]1643 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1644 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1645
1646 /* RING MODE */
1647#define RING_REG(base) (base + 0x29c)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1648 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1649 ring_mode_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1650#undef RING_REG
1651
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1652 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1653 NULL, NULL);
Pei Zhang41bfab32017-02-24 16:03:28 +0800[diff] [blame]1654 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1655 NULL, NULL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1656 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
Xiong Zhang20a2bcd2017-10-14 06:34:46 +0800[diff] [blame]1657 mmio_read_from_hw, NULL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1658 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
Xiong Zhang20a2bcd2017-10-14 06:34:46 +0800[diff] [blame]1659 mmio_read_from_hw, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1660
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1661 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1662 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1663 NULL, NULL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]1664 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1665 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1666 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1667
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1668 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1669 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1670 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1671 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1672 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1673 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1674 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1675 NULL, NULL);
Chuanxiao Dong1999f102017-05-17 15:49:01 +0800[diff] [blame]1676 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1677 skl_misc_ctl_write);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1678 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1679 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1680 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1681 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1682 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1683 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1684 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1685 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]1686 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Pei Zhang187447a2017-02-21 21:58:14 +0800[diff] [blame]1687 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1688
1689 /* display */
1690 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1691 MMIO_D(0x602a0, D_ALL);
1692
1693 MMIO_D(0x65050, D_ALL);
1694 MMIO_D(0x650b4, D_ALL);
1695
1696 MMIO_D(0xc4040, D_ALL);
1697 MMIO_D(DERRMR, D_ALL);
1698
1699 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1700 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1701 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1702 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1703
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1704 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1705 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1706 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1707 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1708
1709 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1710 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1711 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1712 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1713
1714 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1715 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1716 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1717 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1718
1719 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1720 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1721 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1722 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1723
1724 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1725 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1726 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1727
1728 MMIO_D(CURPOS(PIPE_A), D_ALL);
1729 MMIO_D(CURPOS(PIPE_B), D_ALL);
1730 MMIO_D(CURPOS(PIPE_C), D_ALL);
1731
1732 MMIO_D(CURBASE(PIPE_A), D_ALL);
1733 MMIO_D(CURBASE(PIPE_B), D_ALL);
1734 MMIO_D(CURBASE(PIPE_C), D_ALL);
1735
1736 MMIO_D(0x700ac, D_ALL);
1737 MMIO_D(0x710ac, D_ALL);
1738 MMIO_D(0x720ac, D_ALL);
1739
1740 MMIO_D(0x70090, D_ALL);
1741 MMIO_D(0x70094, D_ALL);
1742 MMIO_D(0x70098, D_ALL);
1743 MMIO_D(0x7009c, D_ALL);
1744
1745 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1746 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1747 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1748 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1749 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1750 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1751 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1752 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1753
1754 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1755 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1756 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1757 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1758 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1759 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1760 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1761 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1762
1763 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1764 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1765 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1766 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1767 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1768 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1769 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1770 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1771
1772 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1773 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1774 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1775 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1776 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1777 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1778 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1779 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1780 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1781 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1782 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1783 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1784
1785 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1786 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1787 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1788 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1789 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1790 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1791 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1792 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1793 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1794 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1795 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1796 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1797
1798 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1799 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1800 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1801 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1802 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1803 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1804 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1805 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1806 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1807 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1808 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1809 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1810
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1811 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1812 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1813 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1814 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1815 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1816 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1817 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1818 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1819 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1820
1821 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1822 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1823 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1824 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1825 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1826 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1827 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1828 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1829 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1830
1831 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1832 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1833 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1834 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1835 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1836 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1837 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1838 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1839 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1840
1841 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1842 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1843 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1844 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1845 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1846 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1847 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1848 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1849
1850 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1851 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1852 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1853 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1854 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1855 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1856 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1857 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1858
1859 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1860 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1861 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1862 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1863 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1864 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1865 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1866 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1867
1868 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1869 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1870 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1871 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1872 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1873 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1874 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1875 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1876
1877 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1878 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1879 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1880 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1881 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1882 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1883 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1884 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1885
1886 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1887 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1888 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1889 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1890 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1891
1892 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1893 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1894 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1895 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1896 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1897
1898 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1899 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1900 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1901 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1902 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1903
1904 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1905 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1906 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1907 MMIO_D(WM1_LP_ILK, D_ALL);
1908 MMIO_D(WM2_LP_ILK, D_ALL);
1909 MMIO_D(WM3_LP_ILK, D_ALL);
1910 MMIO_D(WM1S_LP_ILK, D_ALL);
1911 MMIO_D(WM2S_LP_IVB, D_ALL);
1912 MMIO_D(WM3S_LP_IVB, D_ALL);
1913
1914 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1915 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1916 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1917 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1918
1919 MMIO_D(0x48268, D_ALL);
1920
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1921 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1922 gmbus_mmio_write);
1923 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1924 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1925
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1926 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1927 dp_aux_ch_ctl_mmio_write);
1928 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1929 dp_aux_ch_ctl_mmio_write);
1930 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1931 dp_aux_ch_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1932
Xiong Zhang75e64ff2017-06-28 02:03:16 +0800[diff] [blame]1933 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1934
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1935 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1936 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1937
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1938 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1939 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1940 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1941 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1942 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1943 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1944 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1945 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1946 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1947
1948 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1949 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1950 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1951 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1952 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1953 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1954 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
1955
1956 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
1957 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
1958 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
1959 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
1960 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
1961 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
1962 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
1963
1964 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
1965 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
1966 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
1967 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
1968 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
1969 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
1970 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
1971 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
1972
1973 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
1974 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
1975 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
1976
1977 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
1978 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
1979 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
1980
1981 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
1982 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
1983 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
1984
1985 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
1986 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
1987 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
1988
1989 MMIO_D(_FDI_RXA_MISC, D_ALL);
1990 MMIO_D(_FDI_RXB_MISC, D_ALL);
1991 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1992 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1993 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1994 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1995
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1996 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1997 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1998 MMIO_D(PCH_PP_STATUS, D_ALL);
1999 MMIO_D(PCH_LVDS, D_ALL);
2000 MMIO_D(_PCH_DPLL_A, D_ALL);
2001 MMIO_D(_PCH_DPLL_B, D_ALL);
2002 MMIO_D(_PCH_FPA0, D_ALL);
2003 MMIO_D(_PCH_FPA1, D_ALL);
2004 MMIO_D(_PCH_FPB0, D_ALL);
2005 MMIO_D(_PCH_FPB1, D_ALL);
2006 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2007 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2008 MMIO_D(PCH_DPLL_SEL, D_ALL);
2009
2010 MMIO_D(0x61208, D_ALL);
2011 MMIO_D(0x6120c, D_ALL);
2012 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2013 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2014
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2015 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
2016 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
2017 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
2018 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
Changbin Du5cd82b72017-06-13 10:15:26 +0800[diff] [blame]2019 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL);
2020 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2021
2022 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2023 PORTA_HOTPLUG_STATUS_MASK
2024 | PORTB_HOTPLUG_STATUS_MASK
2025 | PORTC_HOTPLUG_STATUS_MASK
2026 | PORTD_HOTPLUG_STATUS_MASK,
2027 NULL, NULL);
2028
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2029 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2030 MMIO_D(FUSE_STRAP, D_ALL);
2031 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2032
2033 MMIO_D(DISP_ARB_CTL, D_ALL);
2034 MMIO_D(DISP_ARB_CTL2, D_ALL);
2035
2036 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2037 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2038 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2039
2040 MMIO_D(SOUTH_CHICKEN1, D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2041 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2042 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
2043 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
2044 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2045 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
2046 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
2047
2048 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2049 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2050 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2051 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2052 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2053 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2054 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2055
2056 MMIO_D(IPS_CTL, D_ALL);
2057
2058 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2059 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2060 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2061 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2062 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2063 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2064 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2065 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2066 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2067 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2068 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2069 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2070 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2071
2072 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2073 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2074 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2075 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2076 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2077 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2078 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2079 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2080 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2081 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2082 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2083 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2084 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2085
2086 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2087 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2088 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2089 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2090 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2091 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2092 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2093 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2094 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2095 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2096 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2097 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2098 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2099
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2100 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2101 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2102 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2103
2104 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2105 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2106 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2107
2108 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2109 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2110 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2111
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2112 MMIO_D(0x60110, D_ALL);
2113 MMIO_D(0x61110, D_ALL);
2114 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2115 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2116 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2117 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2118 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2119 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2120 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2121 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2122 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2123
2124 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2125 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2126 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2127 MMIO_D(SPLL_CTL, D_ALL);
2128 MMIO_D(_WRPLL_CTL1, D_ALL);
2129 MMIO_D(_WRPLL_CTL2, D_ALL);
2130 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2131 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2132 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2133 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2134 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2135 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2136 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2137 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2138
2139 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2140 MMIO_D(0x46508, D_ALL);
2141
2142 MMIO_D(0x49080, D_ALL);
2143 MMIO_D(0x49180, D_ALL);
2144 MMIO_D(0x49280, D_ALL);
2145
2146 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2147 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2148 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2149
2150 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2151 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2152 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2153
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2154 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2155 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2156 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2157
2158 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2159 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2160 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2161
2162 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2163 MMIO_D(SBI_ADDR, D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2164 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2165 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2166 MMIO_D(PIXCLK_GATE, D_ALL);
2167
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2168 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
2169 dp_aux_ch_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2170
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2171 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2172 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2173 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2174 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2175 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2176
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2177 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2178 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2179 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2180 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2181 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2182
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2183 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2184 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2185 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2186 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2187 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2188
2189 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2190 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2191 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2192 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2193 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2194
2195 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2196 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2197
2198 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2199 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2200 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2201 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2202
2203 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2204 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2205 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2206 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2207
2208 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2209 MMIO_D(FORCEWAKE_ACK, D_ALL);
2210 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2211 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2212 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2213 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2214 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
fred gaoa1dcba92017-05-25 15:32:27 +0800[diff] [blame]2215 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2216 MMIO_D(ECOBUS, D_ALL);
2217 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2218 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2219 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2220 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2221 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2222 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2223 MMIO_D(GEN6_RPSTAT1, D_ALL);
2224 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2225 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2226 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2227 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2228 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2229 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2230 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2231 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2232 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2233 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2234 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2235 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2236 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2237 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2238 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2239 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2240 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2241 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2242 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2243 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2244 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2245 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2246 MMIO_D(GEN6_PMINTRMSK, D_ALL);
Imre Deak9c3a16c2017-08-14 18:15:30 +0300[diff] [blame]2247 /*
2248 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2249 * register.
2250 */
2251 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2252 power_well_ctl_mmio_write);
2253 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2254 power_well_ctl_mmio_write);
2255 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2256 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2257 power_well_ctl_mmio_write);
fred gaoa1dcba92017-05-25 15:32:27 +0800[diff] [blame]2258 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2259 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2260
2261 MMIO_D(RSTDBYCTL, D_ALL);
2262
2263 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2264 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2265 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2266
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2267 MMIO_D(TILECTL, D_ALL);
2268
2269 MMIO_D(GEN6_UCGCTL1, D_ALL);
2270 MMIO_D(GEN6_UCGCTL2, D_ALL);
2271
2272 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2273
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2274 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2275 MMIO_D(0x13812c, D_ALL);
2276 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2277 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2278 MMIO_D(HSW_IDICR, D_ALL);
2279 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2280
2281 MMIO_D(0x3c, D_ALL);
2282 MMIO_D(0x860, D_ALL);
2283 MMIO_D(ECOSKPD, D_ALL);
2284 MMIO_D(0x121d0, D_ALL);
2285 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2286 MMIO_D(0x41d0, D_ALL);
2287 MMIO_D(GAC_ECO_BITS, D_ALL);
2288 MMIO_D(0x6200, D_ALL);
2289 MMIO_D(0x6204, D_ALL);
2290 MMIO_D(0x6208, D_ALL);
2291 MMIO_D(0x7118, D_ALL);
2292 MMIO_D(0x7180, D_ALL);
2293 MMIO_D(0x7408, D_ALL);
2294 MMIO_D(0x7c00, D_ALL);
Pei Zhang975629c2017-03-20 23:49:19 +0800[diff] [blame]2295 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2296 MMIO_D(0x911c, D_ALL);
2297 MMIO_D(0x9120, D_ALL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2298 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2299
2300 MMIO_D(GAB_CTL, D_ALL);
2301 MMIO_D(0x48800, D_ALL);
2302 MMIO_D(0xce044, D_ALL);
2303 MMIO_D(0xe6500, D_ALL);
2304 MMIO_D(0xe6504, D_ALL);
2305 MMIO_D(0xe6600, D_ALL);
2306 MMIO_D(0xe6604, D_ALL);
2307 MMIO_D(0xe6700, D_ALL);
2308 MMIO_D(0xe6704, D_ALL);
2309 MMIO_D(0xe6800, D_ALL);
2310 MMIO_D(0xe6804, D_ALL);
2311 MMIO_D(PCH_GMBUS4, D_ALL);
2312 MMIO_D(PCH_GMBUS5, D_ALL);
2313
2314 MMIO_D(0x902c, D_ALL);
2315 MMIO_D(0xec008, D_ALL);
2316 MMIO_D(0xec00c, D_ALL);
2317 MMIO_D(0xec008 + 0x18, D_ALL);
2318 MMIO_D(0xec00c + 0x18, D_ALL);
2319 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2320 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2321 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2322 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2323 MMIO_D(0xec408, D_ALL);
2324 MMIO_D(0xec40c, D_ALL);
2325 MMIO_D(0xec408 + 0x18, D_ALL);
2326 MMIO_D(0xec40c + 0x18, D_ALL);
2327 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2328 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2329 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2330 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2331 MMIO_D(0xfc810, D_ALL);
2332 MMIO_D(0xfc81c, D_ALL);
2333 MMIO_D(0xfc828, D_ALL);
2334 MMIO_D(0xfc834, D_ALL);
2335 MMIO_D(0xfcc00, D_ALL);
2336 MMIO_D(0xfcc0c, D_ALL);
2337 MMIO_D(0xfcc18, D_ALL);
2338 MMIO_D(0xfcc24, D_ALL);
2339 MMIO_D(0xfd000, D_ALL);
2340 MMIO_D(0xfd00c, D_ALL);
2341 MMIO_D(0xfd018, D_ALL);
2342 MMIO_D(0xfd024, D_ALL);
2343 MMIO_D(0xfd034, D_ALL);
2344
2345 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2346 MMIO_D(0x2054, D_ALL);
2347 MMIO_D(0x12054, D_ALL);
2348 MMIO_D(0x22054, D_ALL);
2349 MMIO_D(0x1a054, D_ALL);
2350
2351 MMIO_D(0x44070, D_ALL);
fred gaoa1dcba92017-05-25 15:32:27 +0800[diff] [blame]2352 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2353 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2354 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2355 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2356 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2357
fred gaoa1dcba92017-05-25 15:32:27 +0800[diff] [blame]2358 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2359 MMIO_D(0x2b00, D_BDW_PLUS);
2360 MMIO_D(0x2360, D_BDW_PLUS);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2361 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2362 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2363 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2364
2365 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2366 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2367 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2368
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2369 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2370 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2371 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2372 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2373 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2374 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2375 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2376 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2377 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2378 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2379 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]2380 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2381 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2382 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2383 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2384 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2385 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2386
Zhao Yan9112caa2017-02-28 15:40:10 +0800[diff] [blame]2387 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2388 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2389 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2390 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2391 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2392 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2393 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2394 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2395 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2396 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2397 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2398 return 0;
2399}
2400
2401static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2402{
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2403 struct drm_i915_private *dev_priv = gvt->dev_priv;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2404 int ret;
2405
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2406 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2407 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2408 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2409 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2410
2411 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2412 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2413 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2414 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2415
2416 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2417 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2418 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2419 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2420
2421 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2422 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2423 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2424 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2425
2426 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2427 intel_vgpu_reg_imr_handler);
2428 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2429 intel_vgpu_reg_ier_handler);
2430 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2431 intel_vgpu_reg_iir_handler);
2432 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2433
2434 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2435 intel_vgpu_reg_imr_handler);
2436 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2437 intel_vgpu_reg_ier_handler);
2438 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2439 intel_vgpu_reg_iir_handler);
2440 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2441
2442 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2443 intel_vgpu_reg_imr_handler);
2444 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2445 intel_vgpu_reg_ier_handler);
2446 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2447 intel_vgpu_reg_iir_handler);
2448 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2449
2450 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2451 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2452 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2453 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2454
2455 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2456 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2457 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2458 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2459
2460 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2461 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2462 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2463 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2464
2465 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2466 intel_vgpu_reg_master_irq_handler);
2467
Xiong Zhang894e2872017-10-14 06:34:47 +0800[diff] [blame]2468 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2469 mmio_read_from_hw, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2470
Du, Changbin2fb39fa2016-11-04 12:21:37 +0800[diff] [blame]2471#define RING_REG(base) (base + 0xd0)
2472 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2473 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2474 ring_reset_ctl_write);
Du, Changbin2fb39fa2016-11-04 12:21:37 +0800[diff] [blame]2475#undef RING_REG
2476
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2477#define RING_REG(base) (base + 0x230)
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]2478 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2479#undef RING_REG
2480
2481#define RING_REG(base) (base + 0x234)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2482 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2483 NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2484#undef RING_REG
2485
2486#define RING_REG(base) (base + 0x244)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2487 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2488#undef RING_REG
2489
2490#define RING_REG(base) (base + 0x370)
2491 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2492#undef RING_REG
2493
2494#define RING_REG(base) (base + 0x3a0)
2495 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2496#undef RING_REG
2497
2498 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2499 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2500 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2501 MMIO_D(0x1c1d0, D_BDW_PLUS);
2502 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2503 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2504 MMIO_D(0x1c054, D_BDW_PLUS);
2505
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]2506 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2507
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2508 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2509 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2510
2511 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2512
2513#define RING_REG(base) (base + 0x270)
2514 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2515#undef RING_REG
2516
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2517 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2518
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2519 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2520
Zhao Yan593e59b2017-02-20 15:51:13 +0800[diff] [blame]2521 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2522 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2523 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2524
2525 MMIO_D(WM_MISC, D_BDW);
2526 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2527
2528 MMIO_D(0x66c00, D_BDW_PLUS);
2529 MMIO_D(0x66c04, D_BDW_PLUS);
2530
2531 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2532
2533 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2534 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2535 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2536
Zhao Yan593e59b2017-02-20 15:51:13 +0800[diff] [blame]2537 MMIO_D(0xfdc, D_BDW_PLUS);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2538 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2539 NULL, NULL);
2540 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2541 NULL, NULL);
2542 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2543
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2544 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2545 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2546 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2547 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL);
2548 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2549 MMIO_D(0xb110, D_BDW);
2550
Zhao Yane6cedfe2017-02-21 10:38:53 +0800[diff] [blame]2551 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2552 NULL, force_nonpriv_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2553
Zhao Yan593e59b2017-02-20 15:51:13 +0800[diff] [blame]2554 MMIO_D(0x44484, D_BDW_PLUS);
2555 MMIO_D(0x4448c, D_BDW_PLUS);
2556
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2557 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2558 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2559
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2560 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2561
2562 MMIO_D(0x110000, D_BDW_PLUS);
2563
2564 MMIO_D(0x48400, D_BDW_PLUS);
2565
2566 MMIO_D(0x6e570, D_BDW_PLUS);
2567 MMIO_D(0x65f10, D_BDW_PLUS);
2568
Chuanxiao Dong1999f102017-05-17 15:49:01 +0800[diff] [blame]2569 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2570 skl_misc_ctl_write);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2571 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2572 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2573 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2574
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2575 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2576
Zhao Yan9112caa2017-02-28 15:40:10 +0800[diff] [blame]2577 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2578 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2579 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2580 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2581 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2582 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2583 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2584 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2585 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2586 return 0;
2587}
2588
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2589static int init_skl_mmio_info(struct intel_gvt *gvt)
2590{
2591 struct drm_i915_private *dev_priv = gvt->dev_priv;
2592 int ret;
2593
2594 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2595 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2596 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2597 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2598 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2599 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2600
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2601 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2602 dp_aux_ch_ctl_mmio_write);
2603 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2604 dp_aux_ch_ctl_mmio_write);
2605 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2606 dp_aux_ch_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2607
Imre Deak9c3a16c2017-08-14 18:15:30 +0300[diff] [blame]2608 /*
2609 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2610 * register.
2611 */
2612 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2613 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2614 skl_power_well_ctl_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2615
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2616 MMIO_D(0xa210, D_SKL_PLUS);
2617 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2618 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2619 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2620 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
2621 MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
2622 MMIO_D(0x45504, D_SKL_PLUS);
2623 MMIO_D(0x45520, D_SKL_PLUS);
2624 MMIO_D(0x46000, D_SKL_PLUS);
2625 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write);
2626 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write);
2627 MMIO_D(0x6C040, D_SKL | D_KBL);
2628 MMIO_D(0x6C048, D_SKL | D_KBL);
2629 MMIO_D(0x6C050, D_SKL | D_KBL);
2630 MMIO_D(0x6C044, D_SKL | D_KBL);
2631 MMIO_D(0x6C04C, D_SKL | D_KBL);
2632 MMIO_D(0x6C054, D_SKL | D_KBL);
2633 MMIO_D(0x6c058, D_SKL | D_KBL);
2634 MMIO_D(0x6c05c, D_SKL | D_KBL);
2635 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2636
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2637 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2638 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2639 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2640 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2641 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2642 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2643
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2644 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2645 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2646 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2647 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2648 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2649 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2650
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2651 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2652 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2653 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2654 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2655 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2656 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2657
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2658 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2659 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2660 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2661 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2662
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2663 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2664 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2665 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2666 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2667
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2668 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2669 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2670 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2671 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2672
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2673 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2674 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2675 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2676
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2677 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2678 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2679 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2680
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2681 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2682 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2683 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2684
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2685 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2686 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2687 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2688
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2689 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2690 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2691 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2692
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2693 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2694 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2695 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2696
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2697 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2698 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2699 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2700
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2701 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2703 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2704
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2705 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2706 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2707 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2708
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2709 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2710 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2711 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2712 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2713
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2714 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2715 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2716 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2717 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2718
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2719 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2720 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2721 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2722 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2723
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2724 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2725 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2726 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2727 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2728
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2729 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2730 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2731 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2732 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2733
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2734 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2735 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2736 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2737 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2738
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2739 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2740 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2741 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2742 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2743
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2744 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2745 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2746 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2747 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2748
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2749 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2750 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2751 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2752 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2753
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2754 MMIO_D(0x70380, D_SKL_PLUS);
2755 MMIO_D(0x71380, D_SKL_PLUS);
2756 MMIO_D(0x72380, D_SKL_PLUS);
2757 MMIO_D(0x7039c, D_SKL_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2758
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2759 MMIO_D(0x8f074, D_SKL | D_KBL);
2760 MMIO_D(0x8f004, D_SKL | D_KBL);
2761 MMIO_D(0x8f034, D_SKL | D_KBL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2762
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2763 MMIO_D(0xb11c, D_SKL | D_KBL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2764
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2765 MMIO_D(0x51000, D_SKL | D_KBL);
2766 MMIO_D(0x6c00c, D_SKL_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2767
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2768 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2769 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2770
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2771 MMIO_D(0xd08, D_SKL_PLUS);
2772 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2773 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2774
2775 /* TRTT */
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2776 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2777 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2778 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2779 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2780 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2781 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
2782 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2783
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2784 MMIO_D(0x45008, D_SKL | D_KBL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2785
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2786 MMIO_D(0x46430, D_SKL | D_KBL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2787
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2788 MMIO_D(0x46520, D_SKL | D_KBL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2789
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2790 MMIO_D(0xc403c, D_SKL | D_KBL);
2791 MMIO_D(0xb004, D_SKL_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2792 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2793
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2794 MMIO_D(0x65900, D_SKL_PLUS);
2795 MMIO_D(0x1082c0, D_SKL | D_KBL);
2796 MMIO_D(0x4068, D_SKL | D_KBL);
2797 MMIO_D(0x67054, D_SKL | D_KBL);
2798 MMIO_D(0x6e560, D_SKL | D_KBL);
2799 MMIO_D(0x6e554, D_SKL | D_KBL);
2800 MMIO_D(0x2b20, D_SKL | D_KBL);
2801 MMIO_D(0x65f00, D_SKL | D_KBL);
2802 MMIO_D(0x65f08, D_SKL | D_KBL);
2803 MMIO_D(0x320f0, D_SKL | D_KBL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2804
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2805 MMIO_D(0x70034, D_SKL_PLUS);
2806 MMIO_D(0x71034, D_SKL_PLUS);
2807 MMIO_D(0x72034, D_SKL_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2808
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2809 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS);
2810 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS);
2811 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS);
2812 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS);
2813 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS);
2814 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2815
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2816 MMIO_D(0x44500, D_SKL_PLUS);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2817 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2818 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
Zhao Yan9112caa2017-02-28 15:40:10 +0800[diff] [blame]2819 NULL, NULL);
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2820
2821 MMIO_D(0x4ab8, D_KBL);
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2822 MMIO_D(0x2248, D_SKL_PLUS | D_KBL);
Xu Han5cf5fe82017-03-29 10:13:57 +0800[diff] [blame]2823
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2824 return 0;
2825}
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2826
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]2827static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2828 unsigned int offset)
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2829{
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]2830 unsigned long device = intel_gvt_get_device_type(gvt);
Tina Zhang02b6ed42017-08-04 17:39:41 +0800[diff] [blame]2831 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2832 int num = gvt->mmio.num_mmio_block;
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]2833 int i;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2834
Tina Zhang02b6ed42017-08-04 17:39:41 +0800[diff] [blame]2835 for (i = 0; i < num; i++, block++) {
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]2836 if (!(device & block->device))
2837 continue;
2838 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) &&
2839 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size)
2840 return block;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2841 }
2842 return NULL;
2843}
2844
2845/**
2846 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2847 * @gvt: GVT device
2848 *
2849 * This function is called at the driver unloading stage, to clean up the MMIO
2850 * information table of GVT device
2851 *
2852 */
2853void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2854{
2855 struct hlist_node *tmp;
2856 struct intel_gvt_mmio_info *e;
2857 int i;
2858
2859 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2860 kfree(e);
2861
2862 vfree(gvt->mmio.mmio_attribute);
2863 gvt->mmio.mmio_attribute = NULL;
2864}
2865
Tina Zhang02b6ed42017-08-04 17:39:41 +0800[diff] [blame]2866/* Special MMIO blocks. */
2867static struct gvt_mmio_block mmio_blocks[] = {
2868 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
2869 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
2870 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
2871 pvinfo_mmio_read, pvinfo_mmio_write},
2872 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
2873 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
2874 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
2875};
2876
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2877/**
2878 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2879 * @gvt: GVT device
2880 *
2881 * This function is called at the initialization stage, to setup the MMIO
2882 * information table for GVT device
2883 *
2884 * Returns:
2885 * zero on success, negative if failed.
2886 */
2887int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2888{
2889 struct intel_gvt_device_info *info = &gvt->device_info;
2890 struct drm_i915_private *dev_priv = gvt->dev_priv;
Changbin Du56a78de2017-06-06 15:56:11 +0800[diff] [blame]2891 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2892 int ret;
2893
Changbin Du56a78de2017-06-06 15:56:11 +0800[diff] [blame]2894 gvt->mmio.mmio_attribute = vzalloc(size);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2895 if (!gvt->mmio.mmio_attribute)
2896 return -ENOMEM;
2897
2898 ret = init_generic_mmio_info(gvt);
2899 if (ret)
2900 goto err;
2901
2902 if (IS_BROADWELL(dev_priv)) {
2903 ret = init_broadwell_mmio_info(gvt);
2904 if (ret)
2905 goto err;
Xu Hane3476c02017-03-29 10:13:59 +0800[diff] [blame]2906 } else if (IS_SKYLAKE(dev_priv)
2907 || IS_KABYLAKE(dev_priv)) {
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2908 ret = init_broadwell_mmio_info(gvt);
2909 if (ret)
2910 goto err;
2911 ret = init_skl_mmio_info(gvt);
2912 if (ret)
2913 goto err;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2914 }
Changbin Dufbfd76c2017-06-06 15:56:13 +0800[diff] [blame]2915
Tina Zhang02b6ed42017-08-04 17:39:41 +0800[diff] [blame]2916 gvt->mmio.mmio_block = mmio_blocks;
2917 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
2918
Changbin Dufbfd76c2017-06-06 15:56:13 +0800[diff] [blame]2919 gvt_dbg_mmio("traced %u virtual mmio registers\n",
2920 gvt->mmio.num_tracked_mmio);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2921 return 0;
2922err:
2923 intel_gvt_clean_mmio_info(gvt);
2924 return ret;
2925}
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2926
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2927
2928/**
2929 * intel_vgpu_default_mmio_read - default MMIO read handler
2930 * @vgpu: a vGPU
2931 * @offset: access offset
2932 * @p_data: data return buffer
2933 * @bytes: access data length
2934 *
2935 * Returns:
2936 * Zero on success, negative error code if failed.
2937 */
2938int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
2939 void *p_data, unsigned int bytes)
2940{
2941 read_vreg(vgpu, offset, p_data, bytes);
2942 return 0;
2943}
2944
2945/**
2946 * intel_t_default_mmio_write - default MMIO write handler
2947 * @vgpu: a vGPU
2948 * @offset: access offset
2949 * @p_data: write data buffer
2950 * @bytes: access data length
2951 *
2952 * Returns:
2953 * Zero on success, negative error code if failed.
2954 */
2955int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2956 void *p_data, unsigned int bytes)
2957{
2958 write_vreg(vgpu, offset, p_data, bytes);
2959 return 0;
2960}
Zhao Yan4938ca92017-03-09 10:09:44 +0800[diff] [blame]2961
2962/**
2963 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
2964 * force-nopriv register
2965 *
2966 * @gvt: a GVT device
2967 * @offset: register offset
2968 *
2969 * Returns:
2970 * True if the register is in force-nonpriv whitelist;
2971 * False if outside;
2972 */
2973bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
2974 unsigned int offset)
2975{
2976 return in_whitelist(offset);
2977}
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]2978
2979/**
2980 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
2981 * @vgpu: a vGPU
2982 * @offset: register offset
2983 * @pdata: data buffer
2984 * @bytes: data length
2985 *
2986 * Returns:
2987 * Zero on success, negative error code if failed.
2988 */
2989int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
2990 void *pdata, unsigned int bytes, bool is_read)
2991{
2992 struct intel_gvt *gvt = vgpu->gvt;
2993 struct intel_gvt_mmio_info *mmio_info;
2994 struct gvt_mmio_block *mmio_block;
2995 gvt_mmio_func func;
2996 int ret;
2997
Xiong Zhangd6086592017-08-02 10:31:01 +0800[diff] [blame]2998 if (WARN_ON(bytes > 8))
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]2999 return -EINVAL;
3000
3001 /*
3002 * Handle special MMIO blocks.
3003 */
3004 mmio_block = find_mmio_block(gvt, offset);
3005 if (mmio_block) {
3006 func = is_read ? mmio_block->read : mmio_block->write;
3007 if (func)
3008 return func(vgpu, offset, pdata, bytes);
3009 goto default_rw;
3010 }
3011
3012 /*
3013 * Normal tracked MMIOs.
3014 */
3015 mmio_info = find_mmio_info(gvt, offset);
3016 if (!mmio_info) {
3017 if (!vgpu->mmio.disable_warn_untrack)
3018 gvt_vgpu_err("untracked MMIO %08x len %d\n",
3019 offset, bytes);
3020 goto default_rw;
3021 }
3022
Changbin Du65f9f6f2017-06-06 15:56:09 +0800[diff] [blame]3023 if (is_read)
3024 return mmio_info->read(vgpu, offset, pdata, bytes);
3025 else {
3026 u64 ro_mask = mmio_info->ro_mask;
3027 u32 old_vreg = 0, old_sreg = 0;
3028 u64 data = 0;
3029
3030 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3031 old_vreg = vgpu_vreg(vgpu, offset);
3032 old_sreg = vgpu_sreg(vgpu, offset);
3033 }
3034
3035 if (likely(!ro_mask))
3036 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3037 else if (!~ro_mask) {
3038 gvt_vgpu_err("try to write RO reg %x\n", offset);
3039 return 0;
3040 } else {
3041 /* keep the RO bits in the virtual register */
3042 memcpy(&data, pdata, bytes);
3043 data &= ~ro_mask;
3044 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3045 ret = mmio_info->write(vgpu, offset, &data, bytes);
3046 }
3047
3048 /* higher 16bits of mode ctl regs are mask bits for change */
3049 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3050 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3051
3052 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3053 | (vgpu_vreg(vgpu, offset) & mask);
3054 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
3055 | (vgpu_sreg(vgpu, offset) & mask);
3056 }
3057 }
3058
3059 return ret;
3060
3061default_rw:
3062 return is_read ?
3063 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3064 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3065}