blob: 8255bd93ead2aff621cd74b05da2f1e965675e46 [file] [log] [blame]
Kalle Valo5e3dd152013-06-12 20:52:10 +03001/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
Michal Kazioredb82362013-07-05 16:15:14 +030018#include "core.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030019#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
Kalle Valoa9bf0502013-09-03 11:43:55 +030023#include "trace.h"
Michal Kazioraa5b4fb2014-07-23 12:20:33 +020024#include "mac.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030025
26#include <linux/log2.h>
27
28/* slightly larger than one large A-MPDU */
29#define HTT_RX_RING_SIZE_MIN 128
30
31/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
32#define HTT_RX_RING_SIZE_MAX 2048
33
34#define HTT_RX_AVG_FRM_BYTES 1000
35
36/* ms, very conservative */
37#define HTT_RX_HOST_LATENCY_MAX_MS 20
38
39/* ms, conservative */
40#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
41
42/* when under memory pressure rx ring refill may fail and needs a retry */
43#define HTT_RX_RING_REFILL_RETRY_MS 50
44
Michal Kaziorf6dc2092013-09-26 10:12:22 +030045static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
Michal Kazior6c5151a2014-02-27 18:50:04 +020046static void ath10k_htt_txrx_compl_task(unsigned long ptr);
Michal Kaziorf6dc2092013-09-26 10:12:22 +030047
Kalle Valo5e3dd152013-06-12 20:52:10 +030048static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
Kalle Valo8cc7f262014-09-14 12:50:39 +0300135 idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
Kalle Valo8cc7f262014-09-14 12:50:39 +0300173 *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
Michal Kazior6e712d42013-09-24 10:18:36 +0200185 int ret, num_deficit, num_to_fill;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300186
Michal Kazior6e712d42013-09-24 10:18:36 +0200187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300202 spin_lock_bh(&htt->rx_ring.lock);
Michal Kazior6e712d42013-09-24 10:18:36 +0200203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
Michal Kazior6e712d42013-09-24 10:18:36 +0200216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
Kalle Valoaf762c02014-09-14 12:50:17 +0300225
Kalle Valo5e3dd152013-06-12 20:52:10 +0300226 ath10k_htt_rx_msdu_buff_replenish(htt);
227}
228
Michal Kazior3e841fd2014-05-14 16:23:31 +0300229static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt)
230{
231 struct sk_buff *skb;
232 int i;
233
234 for (i = 0; i < htt->rx_ring.size; i++) {
235 skb = htt->rx_ring.netbufs_ring[i];
236 if (!skb)
237 continue;
238
239 dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr,
240 skb->len + skb_tailroom(skb),
241 DMA_FROM_DEVICE);
242 dev_kfree_skb_any(skb);
243 htt->rx_ring.netbufs_ring[i] = NULL;
244 }
245}
246
Michal Kazior95bf21f2014-05-16 17:15:39 +0300247void ath10k_htt_rx_free(struct ath10k_htt *htt)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300248{
Kalle Valo5e3dd152013-06-12 20:52:10 +0300249 del_timer_sync(&htt->rx_ring.refill_retry_timer);
Michal Kazior6e712d42013-09-24 10:18:36 +0200250 tasklet_kill(&htt->rx_replenish_task);
Michal Kazior6c5151a2014-02-27 18:50:04 +0200251 tasklet_kill(&htt->txrx_compl_task);
252
253 skb_queue_purge(&htt->tx_compl_q);
254 skb_queue_purge(&htt->rx_compl_q);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300255
Michal Kazior3e841fd2014-05-14 16:23:31 +0300256 ath10k_htt_rx_ring_clean_up(htt);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300257
258 dma_free_coherent(htt->ar->dev,
259 (htt->rx_ring.size *
260 sizeof(htt->rx_ring.paddrs_ring)),
261 htt->rx_ring.paddrs_ring,
262 htt->rx_ring.base_paddr);
263
264 dma_free_coherent(htt->ar->dev,
265 sizeof(*htt->rx_ring.alloc_idx.vaddr),
266 htt->rx_ring.alloc_idx.vaddr,
267 htt->rx_ring.alloc_idx.paddr);
268
269 kfree(htt->rx_ring.netbufs_ring);
270}
271
272static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
273{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200274 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300275 int idx;
276 struct sk_buff *msdu;
277
Michal Kazior45967082014-02-27 18:50:05 +0200278 lockdep_assert_held(&htt->rx_ring.lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300279
Michal Kazior8d60ee82014-02-27 18:50:05 +0200280 if (htt->rx_ring.fill_cnt == 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200281 ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n");
Michal Kazior8d60ee82014-02-27 18:50:05 +0200282 return NULL;
283 }
Kalle Valo5e3dd152013-06-12 20:52:10 +0300284
285 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
286 msdu = htt->rx_ring.netbufs_ring[idx];
Michal Kazior3e841fd2014-05-14 16:23:31 +0300287 htt->rx_ring.netbufs_ring[idx] = NULL;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300288
289 idx++;
290 idx &= htt->rx_ring.size_mask;
291 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
292 htt->rx_ring.fill_cnt--;
293
Michal Kazior4de02802014-10-23 17:04:23 +0300294 dma_unmap_single(htt->ar->dev,
295 ATH10K_SKB_CB(msdu)->paddr,
296 msdu->len + skb_tailroom(msdu),
297 DMA_FROM_DEVICE);
298 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx netbuf pop: ",
299 msdu->data, msdu->len + skb_tailroom(msdu));
Michal Kazior4de02802014-10-23 17:04:23 +0300300
Kalle Valo5e3dd152013-06-12 20:52:10 +0300301 return msdu;
302}
303
Janusz Dziedzicd84dd602014-03-24 21:23:20 +0100304/* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300305static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
306 u8 **fw_desc, int *fw_desc_len,
Michal Kazior9aa505d2014-11-18 09:24:47 +0200307 struct sk_buff_head *amsdu,
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +0300308 u32 *attention)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300309{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200310 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300311 int msdu_len, msdu_chaining = 0;
Michal Kazior9aa505d2014-11-18 09:24:47 +0200312 struct sk_buff *msdu;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300313 struct htt_rx_desc *rx_desc;
314
Michal Kazior45967082014-02-27 18:50:05 +0200315 lockdep_assert_held(&htt->rx_ring.lock);
316
Michal Kazior9aa505d2014-11-18 09:24:47 +0200317 for (;;) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300318 int last_msdu, msdu_len_invalid, msdu_chained;
319
Michal Kazior9aa505d2014-11-18 09:24:47 +0200320 msdu = ath10k_htt_rx_netbuf_pop(htt);
321 if (!msdu) {
Michal Kazior9aa505d2014-11-18 09:24:47 +0200322 __skb_queue_purge(amsdu);
Michal Kaziore0bd7512014-11-18 09:24:48 +0200323 return -ENOENT;
Michal Kazior9aa505d2014-11-18 09:24:47 +0200324 }
325
326 __skb_queue_tail(amsdu, msdu);
327
Kalle Valo5e3dd152013-06-12 20:52:10 +0300328 rx_desc = (struct htt_rx_desc *)msdu->data;
329
330 /* FIXME: we must report msdu payload since this is what caller
331 * expects now */
332 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
333 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
334
335 /*
336 * Sanity check - confirm the HW is finished filling in the
337 * rx data.
338 * If the HW and SW are working correctly, then it's guaranteed
339 * that the HW's MAC DMA is done before this point in the SW.
340 * To prevent the case that we handle a stale Rx descriptor,
341 * just assert for now until we have a way to recover.
342 */
343 if (!(__le32_to_cpu(rx_desc->attention.flags)
344 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
Michal Kazior9aa505d2014-11-18 09:24:47 +0200345 __skb_queue_purge(amsdu);
Michal Kaziore0bd7512014-11-18 09:24:48 +0200346 return -EIO;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300347 }
348
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +0300349 *attention |= __le32_to_cpu(rx_desc->attention.flags) &
350 (RX_ATTENTION_FLAGS_TKIP_MIC_ERR |
351 RX_ATTENTION_FLAGS_DECRYPT_ERR |
352 RX_ATTENTION_FLAGS_FCS_ERR |
353 RX_ATTENTION_FLAGS_MGMT_TYPE);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300354 /*
355 * Copy the FW rx descriptor for this MSDU from the rx
356 * indication message into the MSDU's netbuf. HL uses the
357 * same rx indication message definition as LL, and simply
358 * appends new info (fields from the HW rx desc, and the
359 * MSDU payload itself). So, the offset into the rx
360 * indication message only has to account for the standard
361 * offset of the per-MSDU FW rx desc info within the
362 * message, and how many bytes of the per-MSDU FW rx desc
363 * info have already been consumed. (And the endianness of
364 * the host, since for a big-endian host, the rx ind
365 * message contents, including the per-MSDU rx desc bytes,
366 * were byteswapped during upload.)
367 */
368 if (*fw_desc_len > 0) {
369 rx_desc->fw_desc.info0 = **fw_desc;
370 /*
371 * The target is expected to only provide the basic
372 * per-MSDU rx descriptors. Just to be sure, verify
373 * that the target has not attached extension data
374 * (e.g. LRO flow ID).
375 */
376
377 /* or more, if there's extension data */
378 (*fw_desc)++;
379 (*fw_desc_len)--;
380 } else {
381 /*
382 * When an oversized AMSDU happened, FW will lost
383 * some of MSDU status - in this case, the FW
384 * descriptors provided will be less than the
385 * actual MSDUs inside this MPDU. Mark the FW
386 * descriptors so that it will still deliver to
387 * upper stack, if no CRC error for this MPDU.
388 *
389 * FIX THIS - the FW descriptors are actually for
390 * MSDUs in the end of this A-MSDU instead of the
391 * beginning.
392 */
393 rx_desc->fw_desc.info0 = 0;
394 }
395
396 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
397 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
398 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
399 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
400 RX_MSDU_START_INFO0_MSDU_LENGTH);
401 msdu_chained = rx_desc->frag_info.ring2_more_count;
402
403 if (msdu_len_invalid)
404 msdu_len = 0;
405
406 skb_trim(msdu, 0);
407 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
408 msdu_len -= msdu->len;
409
Michal Kazior9aa505d2014-11-18 09:24:47 +0200410 /* Note: Chained buffers do not contain rx descriptor */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300411 while (msdu_chained--) {
Michal Kazior9aa505d2014-11-18 09:24:47 +0200412 msdu = ath10k_htt_rx_netbuf_pop(htt);
413 if (!msdu) {
Michal Kazior9aa505d2014-11-18 09:24:47 +0200414 __skb_queue_purge(amsdu);
Michal Kaziore0bd7512014-11-18 09:24:48 +0200415 return -ENOENT;
Michal Kaziorb30595a2014-10-23 17:04:24 +0300416 }
417
Michal Kazior9aa505d2014-11-18 09:24:47 +0200418 __skb_queue_tail(amsdu, msdu);
419 skb_trim(msdu, 0);
420 skb_put(msdu, min(msdu_len, HTT_RX_BUF_SIZE));
421 msdu_len -= msdu->len;
Michal Kaziorede9c8e2014-05-14 16:23:31 +0300422 msdu_chaining = 1;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300423 }
424
Kalle Valo5e3dd152013-06-12 20:52:10 +0300425 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
426 RX_MSDU_END_INFO0_LAST_MSDU;
427
Michal Kaziorb04e2042014-10-23 17:04:27 +0300428 trace_ath10k_htt_rx_desc(ar, &rx_desc->attention,
Rajkumar Manoharana0883cf2014-10-03 08:02:47 +0300429 sizeof(*rx_desc) - sizeof(u32));
Michal Kazior9aa505d2014-11-18 09:24:47 +0200430
431 if (last_msdu)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300432 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300433 }
Kalle Valo5e3dd152013-06-12 20:52:10 +0300434
Michal Kazior9aa505d2014-11-18 09:24:47 +0200435 if (skb_queue_empty(amsdu))
Janusz Dziedzicd84dd602014-03-24 21:23:20 +0100436 msdu_chaining = -1;
437
Kalle Valo5e3dd152013-06-12 20:52:10 +0300438 /*
439 * Don't refill the ring yet.
440 *
441 * First, the elements popped here are still in use - it is not
442 * safe to overwrite them until the matching call to
443 * mpdu_desc_list_next. Second, for efficiency it is preferable to
444 * refill the rx ring with 1 PPDU's worth of rx buffers (something
445 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
446 * (something like 3 buffers). Consequently, we'll rely on the txrx
447 * SW to tell us when it is done pulling all the PPDU's rx buffers
448 * out of the rx ring, and then refill it just once.
449 */
450
451 return msdu_chaining;
452}
453
Michal Kazior6e712d42013-09-24 10:18:36 +0200454static void ath10k_htt_rx_replenish_task(unsigned long ptr)
455{
456 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
Kalle Valoaf762c02014-09-14 12:50:17 +0300457
Michal Kazior6e712d42013-09-24 10:18:36 +0200458 ath10k_htt_rx_msdu_buff_replenish(htt);
459}
460
Michal Kazior95bf21f2014-05-16 17:15:39 +0300461int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300462{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200463 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300464 dma_addr_t paddr;
465 void *vaddr;
Kalle Valobd8bdbb2014-09-14 12:50:00 +0300466 size_t size;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300467 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
468
Michal Kazior51fc7d72014-10-23 17:04:24 +0300469 htt->rx_confused = false;
470
Kalle Valo5e3dd152013-06-12 20:52:10 +0300471 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
472 if (!is_power_of_2(htt->rx_ring.size)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200473 ath10k_warn(ar, "htt rx ring size is not power of 2\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +0300474 return -EINVAL;
475 }
476
477 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
478
479 /*
480 * Set the initial value for the level to which the rx ring
481 * should be filled, based on the max throughput and the
482 * worst likely latency for the host to fill the rx ring
483 * with new buffers. In theory, this fill level can be
484 * dynamically adjusted from the initial value set here, to
485 * reflect the actual host latency rather than a
486 * conservative assumption about the host latency.
487 */
488 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
489
490 htt->rx_ring.netbufs_ring =
Michal Kazior3e841fd2014-05-14 16:23:31 +0300491 kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
Kalle Valo5e3dd152013-06-12 20:52:10 +0300492 GFP_KERNEL);
493 if (!htt->rx_ring.netbufs_ring)
494 goto err_netbuf;
495
Kalle Valobd8bdbb2014-09-14 12:50:00 +0300496 size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring);
497
498 vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300499 if (!vaddr)
500 goto err_dma_ring;
501
502 htt->rx_ring.paddrs_ring = vaddr;
503 htt->rx_ring.base_paddr = paddr;
504
505 vaddr = dma_alloc_coherent(htt->ar->dev,
506 sizeof(*htt->rx_ring.alloc_idx.vaddr),
507 &paddr, GFP_DMA);
508 if (!vaddr)
509 goto err_dma_idx;
510
511 htt->rx_ring.alloc_idx.vaddr = vaddr;
512 htt->rx_ring.alloc_idx.paddr = paddr;
513 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
514 *htt->rx_ring.alloc_idx.vaddr = 0;
515
516 /* Initialize the Rx refill retry timer */
517 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
518
519 spin_lock_init(&htt->rx_ring.lock);
520
521 htt->rx_ring.fill_cnt = 0;
522 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
523 goto err_fill_ring;
524
Michal Kazior6e712d42013-09-24 10:18:36 +0200525 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
526 (unsigned long)htt);
527
Michal Kazior6c5151a2014-02-27 18:50:04 +0200528 skb_queue_head_init(&htt->tx_compl_q);
529 skb_queue_head_init(&htt->rx_compl_q);
530
531 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
532 (unsigned long)htt);
533
Michal Kazior7aa7a722014-08-25 12:09:38 +0200534 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +0300535 htt->rx_ring.size, htt->rx_ring.fill_level);
536 return 0;
537
538err_fill_ring:
539 ath10k_htt_rx_ring_free(htt);
540 dma_free_coherent(htt->ar->dev,
541 sizeof(*htt->rx_ring.alloc_idx.vaddr),
542 htt->rx_ring.alloc_idx.vaddr,
543 htt->rx_ring.alloc_idx.paddr);
544err_dma_idx:
545 dma_free_coherent(htt->ar->dev,
546 (htt->rx_ring.size *
547 sizeof(htt->rx_ring.paddrs_ring)),
548 htt->rx_ring.paddrs_ring,
549 htt->rx_ring.base_paddr);
550err_dma_ring:
551 kfree(htt->rx_ring.netbufs_ring);
552err_netbuf:
553 return -ENOMEM;
554}
555
Michal Kazior7aa7a722014-08-25 12:09:38 +0200556static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar,
557 enum htt_rx_mpdu_encrypt_type type)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300558{
559 switch (type) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300560 case HTT_RX_MPDU_ENCRYPT_NONE:
561 return 0;
Michal Kazior890d3b22014-10-23 17:04:22 +0300562 case HTT_RX_MPDU_ENCRYPT_WEP40:
563 case HTT_RX_MPDU_ENCRYPT_WEP104:
564 return IEEE80211_WEP_IV_LEN;
565 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
566 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
567 return IEEE80211_TKIP_IV_LEN;
568 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
569 return IEEE80211_CCMP_HDR_LEN;
570 case HTT_RX_MPDU_ENCRYPT_WEP128:
571 case HTT_RX_MPDU_ENCRYPT_WAPI:
572 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300573 }
574
Michal Kazior890d3b22014-10-23 17:04:22 +0300575 ath10k_warn(ar, "unsupported encryption type %d\n", type);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300576 return 0;
577}
578
Michal Kazior890d3b22014-10-23 17:04:22 +0300579#define MICHAEL_MIC_LEN 8
580
Michal Kazior7aa7a722014-08-25 12:09:38 +0200581static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar,
582 enum htt_rx_mpdu_encrypt_type type)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300583{
584 switch (type) {
585 case HTT_RX_MPDU_ENCRYPT_NONE:
Michal Kazior890d3b22014-10-23 17:04:22 +0300586 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300587 case HTT_RX_MPDU_ENCRYPT_WEP40:
588 case HTT_RX_MPDU_ENCRYPT_WEP104:
Michal Kazior890d3b22014-10-23 17:04:22 +0300589 return IEEE80211_WEP_ICV_LEN;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300590 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
591 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
Michal Kazior890d3b22014-10-23 17:04:22 +0300592 return IEEE80211_TKIP_ICV_LEN;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300593 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
Michal Kazior890d3b22014-10-23 17:04:22 +0300594 return IEEE80211_CCMP_MIC_LEN;
595 case HTT_RX_MPDU_ENCRYPT_WEP128:
596 case HTT_RX_MPDU_ENCRYPT_WAPI:
597 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300598 }
599
Michal Kazior890d3b22014-10-23 17:04:22 +0300600 ath10k_warn(ar, "unsupported encryption type %d\n", type);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300601 return 0;
602}
603
604/* Applies for first msdu in chain, before altering it. */
605static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
606{
607 struct htt_rx_desc *rxd;
608 enum rx_msdu_decap_format fmt;
609
610 rxd = (void *)skb->data - sizeof(*rxd);
611 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Kalle Valo5b07e072014-09-14 12:50:06 +0300612 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300613
614 if (fmt == RX_MSDU_DECAP_RAW)
615 return (void *)skb->data;
Kalle Valod8bb26b2014-09-14 12:50:33 +0300616
617 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300618}
619
620/* This function only applies for first msdu in an msdu chain */
621static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
622{
Kalle Valoaf762c02014-09-14 12:50:17 +0300623 u8 *qc;
624
Kalle Valo5e3dd152013-06-12 20:52:10 +0300625 if (ieee80211_is_data_qos(hdr->frame_control)) {
Kalle Valoaf762c02014-09-14 12:50:17 +0300626 qc = ieee80211_get_qos_ctl(hdr);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300627 if (qc[0] & 0x80)
628 return true;
629 }
630 return false;
631}
632
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300633struct rfc1042_hdr {
634 u8 llc_dsap;
635 u8 llc_ssap;
636 u8 llc_ctrl;
637 u8 snap_oui[3];
638 __be16 snap_type;
639} __packed;
640
641struct amsdu_subframe_hdr {
642 u8 dst[ETH_ALEN];
643 u8 src[ETH_ALEN];
644 __be16 len;
645} __packed;
646
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100647static const u8 rx_legacy_rate_idx[] = {
648 3, /* 0x00 - 11Mbps */
649 2, /* 0x01 - 5.5Mbps */
650 1, /* 0x02 - 2Mbps */
651 0, /* 0x03 - 1Mbps */
652 3, /* 0x04 - 11Mbps */
653 2, /* 0x05 - 5.5Mbps */
654 1, /* 0x06 - 2Mbps */
655 0, /* 0x07 - 1Mbps */
656 10, /* 0x08 - 48Mbps */
657 8, /* 0x09 - 24Mbps */
658 6, /* 0x0A - 12Mbps */
659 4, /* 0x0B - 6Mbps */
660 11, /* 0x0C - 54Mbps */
661 9, /* 0x0D - 36Mbps */
662 7, /* 0x0E - 18Mbps */
663 5, /* 0x0F - 9Mbps */
664};
665
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100666static void ath10k_htt_rx_h_rates(struct ath10k *ar,
Janusz Dziedziccfadd9b2014-03-24 21:23:16 +0100667 enum ieee80211_band band,
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100668 u8 info0, u32 info1, u32 info2,
Janusz Dziedziccfadd9b2014-03-24 21:23:16 +0100669 struct ieee80211_rx_status *status)
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100670{
671 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100672 u8 preamble = 0;
673
674 /* Check if valid fields */
675 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
676 return;
677
678 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
679
680 switch (preamble) {
681 case HTT_RX_LEGACY:
682 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
683 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
684 rate_idx = 0;
685
686 if (rate < 0x08 || rate > 0x0F)
687 break;
688
689 switch (band) {
690 case IEEE80211_BAND_2GHZ:
691 if (cck)
692 rate &= ~BIT(3);
693 rate_idx = rx_legacy_rate_idx[rate];
694 break;
695 case IEEE80211_BAND_5GHZ:
696 rate_idx = rx_legacy_rate_idx[rate];
697 /* We are using same rate table registering
698 HW - ath10k_rates[]. In case of 5GHz skip
699 CCK rates, so -4 here */
700 rate_idx -= 4;
701 break;
702 default:
703 break;
704 }
705
706 status->rate_idx = rate_idx;
707 break;
708 case HTT_RX_HT:
709 case HTT_RX_HT_WITH_TXBF:
710 /* HT-SIG - Table 20-11 in info1 and info2 */
711 mcs = info1 & 0x1F;
712 nss = mcs >> 3;
713 bw = (info1 >> 7) & 1;
714 sgi = (info2 >> 7) & 1;
715
716 status->rate_idx = mcs;
717 status->flag |= RX_FLAG_HT;
718 if (sgi)
719 status->flag |= RX_FLAG_SHORT_GI;
720 if (bw)
721 status->flag |= RX_FLAG_40MHZ;
722 break;
723 case HTT_RX_VHT:
724 case HTT_RX_VHT_WITH_TXBF:
725 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
726 TODO check this */
727 mcs = (info2 >> 4) & 0x0F;
728 nss = ((info1 >> 10) & 0x07) + 1;
729 bw = info1 & 3;
730 sgi = info2 & 1;
731
732 status->rate_idx = mcs;
733 status->vht_nss = nss;
734
735 if (sgi)
736 status->flag |= RX_FLAG_SHORT_GI;
737
738 switch (bw) {
739 /* 20MHZ */
740 case 0:
741 break;
742 /* 40MHZ */
743 case 1:
744 status->flag |= RX_FLAG_40MHZ;
745 break;
746 /* 80MHZ */
747 case 2:
748 status->vht_flag |= RX_VHT_FLAG_80MHZ;
749 }
750
751 status->flag |= RX_FLAG_VHT;
752 break;
753 default:
754 break;
755 }
756}
757
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100758static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100759 struct ieee80211_rx_status *rx_status,
760 struct sk_buff *skb,
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300761 enum htt_rx_mpdu_encrypt_type enctype,
762 enum rx_msdu_decap_format fmt,
763 bool dot11frag)
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100764{
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100765 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100766
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300767 rx_status->flag &= ~(RX_FLAG_DECRYPTED |
768 RX_FLAG_IV_STRIPPED |
769 RX_FLAG_MMIC_STRIPPED);
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100770
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300771 if (enctype == HTT_RX_MPDU_ENCRYPT_NONE)
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100772 return;
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300773
774 /*
775 * There's no explicit rx descriptor flag to indicate whether a given
776 * frame has been decrypted or not. We're forced to use the decap
777 * format as an implicit indication. However fragmentation rx is always
778 * raw and it probably never reports undecrypted raws.
779 *
780 * This makes sure sniffed frames are reported as-is without stripping
781 * the protected flag.
782 */
783 if (fmt == RX_MSDU_DECAP_RAW && !dot11frag)
784 return;
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100785
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100786 rx_status->flag |= RX_FLAG_DECRYPTED |
787 RX_FLAG_IV_STRIPPED |
788 RX_FLAG_MMIC_STRIPPED;
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100789 hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
790 ~IEEE80211_FCTL_PROTECTED);
791}
792
Janusz Dziedzic36653f02014-03-24 21:23:18 +0100793static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
794 struct ieee80211_rx_status *status)
795{
796 struct ieee80211_channel *ch;
797
798 spin_lock_bh(&ar->data_lock);
799 ch = ar->scan_channel;
800 if (!ch)
801 ch = ar->rx_channel;
802 spin_unlock_bh(&ar->data_lock);
803
804 if (!ch)
805 return false;
806
807 status->band = ch->band;
808 status->freq = ch->center_freq;
809
810 return true;
811}
812
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300813static const char * const tid_to_ac[] = {
814 "BE",
815 "BK",
816 "BK",
817 "BE",
818 "VI",
819 "VI",
820 "VO",
821 "VO",
822};
823
824static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size)
825{
826 u8 *qc;
827 int tid;
828
829 if (!ieee80211_is_data_qos(hdr->frame_control))
830 return "";
831
832 qc = ieee80211_get_qos_ctl(hdr);
833 tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
834 if (tid < 8)
835 snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]);
836 else
837 snprintf(out, size, "tid %d", tid);
838
839 return out;
840}
841
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100842static void ath10k_process_rx(struct ath10k *ar,
843 struct ieee80211_rx_status *rx_status,
844 struct sk_buff *skb)
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100845{
846 struct ieee80211_rx_status *status;
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300847 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
848 char tid[32];
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100849
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100850 status = IEEE80211_SKB_RXCB(skb);
851 *status = *rx_status;
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100852
Michal Kazior7aa7a722014-08-25 12:09:38 +0200853 ath10k_dbg(ar, ATH10K_DBG_DATA,
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300854 "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100855 skb,
856 skb->len,
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300857 ieee80211_get_SA(hdr),
858 ath10k_get_tid(hdr, tid, sizeof(tid)),
859 is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
860 "mcast" : "ucast",
861 (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100862 status->flag == 0 ? "legacy" : "",
863 status->flag & RX_FLAG_HT ? "ht" : "",
864 status->flag & RX_FLAG_VHT ? "vht" : "",
865 status->flag & RX_FLAG_40MHZ ? "40" : "",
866 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
867 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
868 status->rate_idx,
869 status->vht_nss,
870 status->freq,
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100871 status->band, status->flag,
Janusz Dziedzic78433f92014-03-24 21:23:21 +0100872 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300873 !!(status->flag & RX_FLAG_MMIC_ERROR),
874 !!(status->flag & RX_FLAG_AMSDU_MORE));
Michal Kazior7aa7a722014-08-25 12:09:38 +0200875 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100876 skb->data, skb->len);
Rajkumar Manoharan5ce8e7f2014-11-05 19:14:31 +0530877 trace_ath10k_rx_hdr(ar, skb->data, skb->len);
878 trace_ath10k_rx_payload(ar, skb->data, skb->len);
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100879
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100880 ieee80211_rx(ar->hw, skb);
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100881}
882
Michal Kaziord960c362014-02-25 09:29:57 +0200883static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
884{
885 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
886 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
887}
888
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300889static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100890 struct ieee80211_rx_status *rx_status,
Michal Kazior9aa505d2014-11-18 09:24:47 +0200891 struct sk_buff_head *amsdu)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300892{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200893 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300894 struct htt_rx_desc *rxd;
Michal Kazior9aa505d2014-11-18 09:24:47 +0200895 struct sk_buff *skb;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300896 struct sk_buff *first;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300897 enum rx_msdu_decap_format fmt;
898 enum htt_rx_mpdu_encrypt_type enctype;
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300899 struct ieee80211_hdr *hdr;
Michal Kazior72bdeb82014-07-28 23:59:42 +0300900 u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300901 unsigned int hdr_len;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300902
Michal Kazior9aa505d2014-11-18 09:24:47 +0200903 first = skb_peek(amsdu);
904
905 rxd = (void *)first->data - sizeof(*rxd);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300906 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
Kalle Valo5b07e072014-09-14 12:50:06 +0300907 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300908
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300909 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
910 hdr_len = ieee80211_hdrlen(hdr->frame_control);
911 memcpy(hdr_buf, hdr, hdr_len);
912 hdr = (struct ieee80211_hdr *)hdr_buf;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300913
Michal Kazior9aa505d2014-11-18 09:24:47 +0200914 while ((skb = __skb_dequeue(amsdu))) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300915 void *decap_hdr;
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300916 int len;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300917
918 rxd = (void *)skb->data - sizeof(*rxd);
919 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300920 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300921 decap_hdr = (void *)rxd->rx_hdr_status;
922
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300923 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
924
925 /* First frame in an A-MSDU chain has more decapped data. */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300926 if (skb == first) {
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300927 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
Michal Kazior7aa7a722014-08-25 12:09:38 +0200928 len += round_up(ath10k_htt_rx_crypto_param_len(ar,
929 enctype), 4);
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300930 decap_hdr += len;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300931 }
932
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300933 switch (fmt) {
934 case RX_MSDU_DECAP_RAW:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +0300935 /* remove trailing FCS */
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300936 skb_trim(skb, skb->len - FCS_LEN);
937 break;
938 case RX_MSDU_DECAP_NATIVE_WIFI:
Michal Kazior72bdeb82014-07-28 23:59:42 +0300939 /* pull decapped header and copy SA & DA */
Michal Kazior784f69d2013-09-26 10:12:23 +0300940 hdr = (struct ieee80211_hdr *)skb->data;
Michal Kaziord960c362014-02-25 09:29:57 +0200941 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
Kalle Valob25f32c2014-09-14 12:50:49 +0300942 ether_addr_copy(da, ieee80211_get_DA(hdr));
943 ether_addr_copy(sa, ieee80211_get_SA(hdr));
Michal Kazior784f69d2013-09-26 10:12:23 +0300944 skb_pull(skb, hdr_len);
945
946 /* push original 802.11 header */
947 hdr = (struct ieee80211_hdr *)hdr_buf;
948 hdr_len = ieee80211_hdrlen(hdr->frame_control);
949 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
950
951 /* original A-MSDU header has the bit set but we're
952 * not including A-MSDU subframe header */
953 hdr = (struct ieee80211_hdr *)skb->data;
954 qos = ieee80211_get_qos_ctl(hdr);
955 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
956
Michal Kazior72bdeb82014-07-28 23:59:42 +0300957 /* original 802.11 header has a different DA and in
958 * case of 4addr it may also have different SA
959 */
Kalle Valob25f32c2014-09-14 12:50:49 +0300960 ether_addr_copy(ieee80211_get_DA(hdr), da);
961 ether_addr_copy(ieee80211_get_SA(hdr), sa);
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300962 break;
963 case RX_MSDU_DECAP_ETHERNET2_DIX:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +0300964 /* strip ethernet header and insert decapped 802.11
965 * header, amsdu subframe header and rfc1042 header */
966
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300967 len = 0;
968 len += sizeof(struct rfc1042_hdr);
969 len += sizeof(struct amsdu_subframe_hdr);
Michal Kaziordfa95b52013-08-13 07:59:37 +0200970
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300971 skb_pull(skb, sizeof(struct ethhdr));
972 memcpy(skb_push(skb, len), decap_hdr, len);
973 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
974 break;
975 case RX_MSDU_DECAP_8023_SNAP_LLC:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +0300976 /* insert decapped 802.11 header making a singly
977 * A-MSDU */
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300978 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
979 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300980 }
981
Michal Kazior9aa505d2014-11-18 09:24:47 +0200982 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt,
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300983 false);
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300984
Michal Kazior9aa505d2014-11-18 09:24:47 +0200985 if (skb_queue_empty(amsdu))
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100986 rx_status->flag &= ~RX_FLAG_AMSDU_MORE;
Michal Kazior9aa505d2014-11-18 09:24:47 +0200987 else
988 rx_status->flag |= RX_FLAG_AMSDU_MORE;
Kalle Valo652de352013-11-13 15:23:30 +0200989
Michal Kazior9aa505d2014-11-18 09:24:47 +0200990 ath10k_process_rx(htt->ar, rx_status, skb);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300991 }
992
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300993 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
994 * monitor interface active for sniffing purposes. */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300995}
996
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100997static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
998 struct ieee80211_rx_status *rx_status,
999 struct sk_buff *skb)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001000{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001001 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001002 struct htt_rx_desc *rxd;
1003 struct ieee80211_hdr *hdr;
1004 enum rx_msdu_decap_format fmt;
1005 enum htt_rx_mpdu_encrypt_type enctype;
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001006 int hdr_len;
1007 void *rfc1042;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001008
Kalle Valo5e3dd152013-06-12 20:52:10 +03001009 rxd = (void *)skb->data - sizeof(*rxd);
1010 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Kalle Valo5b07e072014-09-14 12:50:06 +03001011 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001012 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
Kalle Valo5b07e072014-09-14 12:50:06 +03001013 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001014 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1015 hdr_len = ieee80211_hdrlen(hdr->frame_control);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001016
Michal Kaziorf6dc2092013-09-26 10:12:22 +03001017 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
1018
Kalle Valo5e3dd152013-06-12 20:52:10 +03001019 switch (fmt) {
1020 case RX_MSDU_DECAP_RAW:
1021 /* remove trailing FCS */
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001022 skb_trim(skb, skb->len - FCS_LEN);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001023 break;
1024 case RX_MSDU_DECAP_NATIVE_WIFI:
Michal Kazior784f69d2013-09-26 10:12:23 +03001025 /* Pull decapped header */
1026 hdr = (struct ieee80211_hdr *)skb->data;
Michal Kaziord960c362014-02-25 09:29:57 +02001027 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
Michal Kazior784f69d2013-09-26 10:12:23 +03001028 skb_pull(skb, hdr_len);
1029
1030 /* Push original header */
1031 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1032 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1033 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001034 break;
1035 case RX_MSDU_DECAP_ETHERNET2_DIX:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001036 /* strip ethernet header and insert decapped 802.11 header and
1037 * rfc1042 header */
1038
1039 rfc1042 = hdr;
1040 rfc1042 += roundup(hdr_len, 4);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001041 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar,
1042 enctype), 4);
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001043
1044 skb_pull(skb, sizeof(struct ethhdr));
1045 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
1046 rfc1042, sizeof(struct rfc1042_hdr));
1047 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001048 break;
1049 case RX_MSDU_DECAP_8023_SNAP_LLC:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001050 /* remove A-MSDU subframe header and insert
1051 * decapped 802.11 header. rfc1042 header is already there */
1052
1053 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
1054 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001055 break;
1056 }
1057
Michal Kaziorc071dcb2014-05-23 11:33:18 +03001058 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false);
Michal Kaziorf6dc2092013-09-26 10:12:22 +03001059
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001060 ath10k_process_rx(htt->ar, rx_status, skb);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001061}
1062
Michal Kazior605f81a2013-07-31 10:47:56 +02001063static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1064{
1065 struct htt_rx_desc *rxd;
1066 u32 flags, info;
1067 bool is_ip4, is_ip6;
1068 bool is_tcp, is_udp;
1069 bool ip_csum_ok, tcpudp_csum_ok;
1070
1071 rxd = (void *)skb->data - sizeof(*rxd);
1072 flags = __le32_to_cpu(rxd->attention.flags);
1073 info = __le32_to_cpu(rxd->msdu_start.info1);
1074
1075 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1076 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1077 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1078 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1079 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1080 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1081
1082 if (!is_ip4 && !is_ip6)
1083 return CHECKSUM_NONE;
1084 if (!is_tcp && !is_udp)
1085 return CHECKSUM_NONE;
1086 if (!ip_csum_ok)
1087 return CHECKSUM_NONE;
1088 if (!tcpudp_csum_ok)
1089 return CHECKSUM_NONE;
1090
1091 return CHECKSUM_UNNECESSARY;
1092}
1093
Michal Kazior9aa505d2014-11-18 09:24:47 +02001094static int ath10k_unchain_msdu(struct sk_buff_head *amsdu)
Ben Greearbfa35362014-03-03 14:07:09 -08001095{
Michal Kazior9aa505d2014-11-18 09:24:47 +02001096 struct sk_buff *skb, *first;
Ben Greearbfa35362014-03-03 14:07:09 -08001097 int space;
1098 int total_len = 0;
1099
1100 /* TODO: Might could optimize this by using
1101 * skb_try_coalesce or similar method to
1102 * decrease copying, or maybe get mac80211 to
1103 * provide a way to just receive a list of
1104 * skb?
1105 */
1106
Michal Kazior9aa505d2014-11-18 09:24:47 +02001107 first = __skb_dequeue(amsdu);
Ben Greearbfa35362014-03-03 14:07:09 -08001108
1109 /* Allocate total length all at once. */
Michal Kazior9aa505d2014-11-18 09:24:47 +02001110 skb_queue_walk(amsdu, skb)
1111 total_len += skb->len;
Ben Greearbfa35362014-03-03 14:07:09 -08001112
Michal Kazior9aa505d2014-11-18 09:24:47 +02001113 space = total_len - skb_tailroom(first);
Ben Greearbfa35362014-03-03 14:07:09 -08001114 if ((space > 0) &&
Michal Kazior9aa505d2014-11-18 09:24:47 +02001115 (pskb_expand_head(first, 0, space, GFP_ATOMIC) < 0)) {
Ben Greearbfa35362014-03-03 14:07:09 -08001116 /* TODO: bump some rx-oom error stat */
1117 /* put it back together so we can free the
1118 * whole list at once.
1119 */
Michal Kazior9aa505d2014-11-18 09:24:47 +02001120 __skb_queue_head(amsdu, first);
Ben Greearbfa35362014-03-03 14:07:09 -08001121 return -1;
1122 }
1123
1124 /* Walk list again, copying contents into
1125 * msdu_head
1126 */
Michal Kazior9aa505d2014-11-18 09:24:47 +02001127 while ((skb = __skb_dequeue(amsdu))) {
1128 skb_copy_from_linear_data(skb, skb_put(first, skb->len),
1129 skb->len);
1130 dev_kfree_skb_any(skb);
Ben Greearbfa35362014-03-03 14:07:09 -08001131 }
1132
Michal Kazior9aa505d2014-11-18 09:24:47 +02001133 __skb_queue_head(amsdu, first);
Ben Greearbfa35362014-03-03 14:07:09 -08001134 return 0;
1135}
1136
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001137static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1138 struct sk_buff *head,
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001139 bool channel_set,
1140 u32 attention)
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001141{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001142 struct ath10k *ar = htt->ar;
1143
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001144 if (head->len == 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001145 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001146 "htt rx dropping due to zero-len\n");
1147 return false;
1148 }
1149
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001150 if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001151 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001152 "htt rx dropping due to decrypt-err\n");
1153 return false;
1154 }
1155
Janusz Dziedzic36653f02014-03-24 21:23:18 +01001156 if (!channel_set) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001157 ath10k_warn(ar, "no channel configured; ignoring frame!\n");
Janusz Dziedzic36653f02014-03-24 21:23:18 +01001158 return false;
1159 }
1160
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001161 /* Skip mgmt frames while we handle this in WMI */
Michal Kaziorf6b946e2014-10-23 17:04:22 +03001162 if (attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001163 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001164 return false;
1165 }
1166
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001167 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001168 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001169 "htt rx CAC running\n");
1170 return false;
1171 }
1172
1173 return true;
1174}
1175
Kalle Valo5e3dd152013-06-12 20:52:10 +03001176static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1177 struct htt_rx_indication *rx)
1178{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001179 struct ath10k *ar = htt->ar;
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001180 struct ieee80211_rx_status *rx_status = &htt->rx_status;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001181 struct htt_rx_indication_mpdu_range *mpdu_ranges;
Michal Kazior9aa505d2014-11-18 09:24:47 +02001182 struct sk_buff_head amsdu;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001183 struct ieee80211_hdr *hdr;
1184 int num_mpdu_ranges;
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001185 u32 attention;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001186 int fw_desc_len;
1187 u8 *fw_desc;
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001188 bool channel_set;
Michal Kaziord5406902014-11-18 09:24:47 +02001189 int i, ret, mpdu_count = 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001190
Michal Kazior45967082014-02-27 18:50:05 +02001191 lockdep_assert_held(&htt->rx_ring.lock);
1192
Michal Kaziore0bd7512014-11-18 09:24:48 +02001193 if (htt->rx_confused)
1194 return;
1195
Kalle Valo5e3dd152013-06-12 20:52:10 +03001196 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1197 fw_desc = (u8 *)&rx->fw_desc;
1198
1199 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1200 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1201 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1202
Janusz Dziedzice8dc1a92014-03-19 07:09:41 +01001203 /* Fill this once, while this is per-ppdu */
Janusz Dziedzic22891882014-03-24 21:24:58 +01001204 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) {
1205 memset(rx_status, 0, sizeof(*rx_status));
1206 rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR +
1207 rx->ppdu.combined_rssi;
1208 }
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001209
1210 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
1211 /* TSF available only in 32-bit */
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001212 rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
1213 rx_status->flag |= RX_FLAG_MACTIME_END;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001214 }
Janusz Dziedzice8dc1a92014-03-19 07:09:41 +01001215
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001216 channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status);
Janusz Dziedzic36653f02014-03-24 21:23:18 +01001217
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001218 if (channel_set) {
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001219 ath10k_htt_rx_h_rates(htt->ar, rx_status->band,
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001220 rx->ppdu.info0,
1221 __le32_to_cpu(rx->ppdu.info1),
1222 __le32_to_cpu(rx->ppdu.info2),
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001223 rx_status);
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001224 }
Janusz Dziedzice8dc1a92014-03-19 07:09:41 +01001225
Michal Kazior7aa7a722014-08-25 12:09:38 +02001226 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001227 rx, sizeof(*rx) +
1228 (sizeof(struct htt_rx_indication_mpdu_range) *
1229 num_mpdu_ranges));
1230
Michal Kaziord5406902014-11-18 09:24:47 +02001231 for (i = 0; i < num_mpdu_ranges; i++)
1232 mpdu_count += mpdu_ranges[i].mpdu_count;
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001233
Michal Kaziord5406902014-11-18 09:24:47 +02001234 while (mpdu_count--) {
1235 attention = 0;
1236 __skb_queue_head_init(&amsdu);
1237 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc,
1238 &fw_desc_len, &amsdu,
1239 &attention);
1240 if (ret < 0) {
Michal Kaziore0bd7512014-11-18 09:24:48 +02001241 ath10k_warn(ar, "rx ring became corrupted: %d\n", ret);
Michal Kaziord5406902014-11-18 09:24:47 +02001242 __skb_queue_purge(&amsdu);
Michal Kaziore0bd7512014-11-18 09:24:48 +02001243 /* FIXME: It's probably a good idea to reboot the
1244 * device instead of leaving it inoperable.
1245 */
1246 htt->rx_confused = true;
1247 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001248 }
Michal Kaziord5406902014-11-18 09:24:47 +02001249
1250 if (!ath10k_htt_rx_amsdu_allowed(htt, skb_peek(&amsdu),
1251 channel_set, attention)) {
1252 __skb_queue_purge(&amsdu);
1253 continue;
1254 }
1255
1256 if (ret > 0 && ath10k_unchain_msdu(&amsdu) < 0) {
1257 __skb_queue_purge(&amsdu);
1258 continue;
1259 }
1260
1261 if (attention & RX_ATTENTION_FLAGS_FCS_ERR)
1262 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
1263 else
1264 rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC;
1265
1266 if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
1267 rx_status->flag |= RX_FLAG_MMIC_ERROR;
1268 else
1269 rx_status->flag &= ~RX_FLAG_MMIC_ERROR;
1270
1271 hdr = ath10k_htt_rx_skb_get_hdr(skb_peek(&amsdu));
1272
1273 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
1274 ath10k_htt_rx_amsdu(htt, rx_status, &amsdu);
1275 else
1276 ath10k_htt_rx_msdu(htt, rx_status,
1277 __skb_dequeue(&amsdu));
Kalle Valo5e3dd152013-06-12 20:52:10 +03001278 }
1279
Michal Kazior6e712d42013-09-24 10:18:36 +02001280 tasklet_schedule(&htt->rx_replenish_task);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001281}
1282
1283static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
Kalle Valo5b07e072014-09-14 12:50:06 +03001284 struct htt_rx_fragment_indication *frag)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001285{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001286 struct ath10k *ar = htt->ar;
Michal Kazior9aa505d2014-11-18 09:24:47 +02001287 struct sk_buff *msdu;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001288 enum htt_rx_mpdu_encrypt_type enctype;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001289 struct htt_rx_desc *rxd;
1290 enum rx_msdu_decap_format fmt;
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001291 struct ieee80211_rx_status *rx_status = &htt->rx_status;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001292 struct ieee80211_hdr *hdr;
Michal Kazior9aa505d2014-11-18 09:24:47 +02001293 struct sk_buff_head amsdu;
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001294 int ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001295 bool tkip_mic_err;
1296 bool decrypt_err;
1297 u8 *fw_desc;
1298 int fw_desc_len, hdrlen, paramlen;
1299 int trim;
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001300 u32 attention = 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001301
1302 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1303 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1304
Michal Kazior9aa505d2014-11-18 09:24:47 +02001305 __skb_queue_head_init(&amsdu);
Michal Kazior45967082014-02-27 18:50:05 +02001306
1307 spin_lock_bh(&htt->rx_ring.lock);
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001308 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
Michal Kazior9aa505d2014-11-18 09:24:47 +02001309 &amsdu, &attention);
Michal Kazior45967082014-02-27 18:50:05 +02001310 spin_unlock_bh(&htt->rx_ring.lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001311
Michal Kazior686687c2014-10-23 17:04:24 +03001312 tasklet_schedule(&htt->rx_replenish_task);
1313
Michal Kazior7aa7a722014-08-25 12:09:38 +02001314 ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001315
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001316 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001317 ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n",
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001318 ret);
Michal Kazior9aa505d2014-11-18 09:24:47 +02001319 __skb_queue_purge(&amsdu);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001320 return;
1321 }
1322
Michal Kazior9aa505d2014-11-18 09:24:47 +02001323 if (skb_queue_len(&amsdu) != 1) {
1324 ath10k_warn(ar, "failed to pop frag amsdu: too many msdus\n");
1325 __skb_queue_purge(&amsdu);
1326 return;
1327 }
1328
1329 msdu = __skb_dequeue(&amsdu);
1330
Kalle Valo5e3dd152013-06-12 20:52:10 +03001331 /* FIXME: implement signal strength */
Ben Greear4b81d172014-05-26 12:46:04 +03001332 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001333
Michal Kazior9aa505d2014-11-18 09:24:47 +02001334 hdr = (struct ieee80211_hdr *)msdu->data;
1335 rxd = (void *)msdu->data - sizeof(*rxd);
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001336 tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1337 decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001338 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Kalle Valo5b07e072014-09-14 12:50:06 +03001339 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001340
1341 if (fmt != RX_MSDU_DECAP_RAW) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001342 ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n");
Michal Kazior9aa505d2014-11-18 09:24:47 +02001343 dev_kfree_skb_any(msdu);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001344 goto end;
1345 }
1346
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001347 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1348 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
Michal Kazior9aa505d2014-11-18 09:24:47 +02001349 ath10k_htt_rx_h_protected(htt, rx_status, msdu, enctype, fmt,
Michal Kaziorc071dcb2014-05-23 11:33:18 +03001350 true);
Michal Kazior9aa505d2014-11-18 09:24:47 +02001351 msdu->ip_summed = ath10k_htt_rx_get_csum_state(msdu);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001352
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001353 if (tkip_mic_err)
Michal Kazior7aa7a722014-08-25 12:09:38 +02001354 ath10k_warn(ar, "tkip mic error\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001355
1356 if (decrypt_err) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001357 ath10k_warn(ar, "decryption err in fragmented rx\n");
Michal Kazior9aa505d2014-11-18 09:24:47 +02001358 dev_kfree_skb_any(msdu);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001359 goto end;
1360 }
1361
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001362 if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
Kalle Valo5e3dd152013-06-12 20:52:10 +03001363 hdrlen = ieee80211_hdrlen(hdr->frame_control);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001364 paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001365
1366 /* It is more efficient to move the header than the payload */
Michal Kazior9aa505d2014-11-18 09:24:47 +02001367 memmove((void *)msdu->data + paramlen,
1368 (void *)msdu->data,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001369 hdrlen);
Michal Kazior9aa505d2014-11-18 09:24:47 +02001370 skb_pull(msdu, paramlen);
1371 hdr = (struct ieee80211_hdr *)msdu->data;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001372 }
1373
1374 /* remove trailing FCS */
1375 trim = 4;
1376
1377 /* remove crypto trailer */
Michal Kazior7aa7a722014-08-25 12:09:38 +02001378 trim += ath10k_htt_rx_crypto_tail_len(ar, enctype);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001379
1380 /* last fragment of TKIP frags has MIC */
1381 if (!ieee80211_has_morefrags(hdr->frame_control) &&
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001382 enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
Michal Kazior890d3b22014-10-23 17:04:22 +03001383 trim += MICHAEL_MIC_LEN;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001384
Michal Kazior9aa505d2014-11-18 09:24:47 +02001385 if (trim > msdu->len) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001386 ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n");
Michal Kazior9aa505d2014-11-18 09:24:47 +02001387 dev_kfree_skb_any(msdu);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001388 goto end;
1389 }
1390
Michal Kazior9aa505d2014-11-18 09:24:47 +02001391 skb_trim(msdu, msdu->len - trim);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001392
Michal Kazior7aa7a722014-08-25 12:09:38 +02001393 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
Michal Kazior9aa505d2014-11-18 09:24:47 +02001394 msdu->data, msdu->len);
1395 ath10k_process_rx(htt->ar, rx_status, msdu);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001396
1397end:
1398 if (fw_desc_len > 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001399 ath10k_dbg(ar, ATH10K_DBG_HTT,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001400 "expecting more fragmented rx in one indication %d\n",
1401 fw_desc_len);
1402 }
1403}
1404
Michal Kazior6c5151a2014-02-27 18:50:04 +02001405static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1406 struct sk_buff *skb)
1407{
1408 struct ath10k_htt *htt = &ar->htt;
1409 struct htt_resp *resp = (struct htt_resp *)skb->data;
1410 struct htt_tx_done tx_done = {};
1411 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1412 __le16 msdu_id;
1413 int i;
1414
Michal Kazior45967082014-02-27 18:50:05 +02001415 lockdep_assert_held(&htt->tx_lock);
1416
Michal Kazior6c5151a2014-02-27 18:50:04 +02001417 switch (status) {
1418 case HTT_DATA_TX_STATUS_NO_ACK:
1419 tx_done.no_ack = true;
1420 break;
1421 case HTT_DATA_TX_STATUS_OK:
1422 break;
1423 case HTT_DATA_TX_STATUS_DISCARD:
1424 case HTT_DATA_TX_STATUS_POSTPONE:
1425 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1426 tx_done.discard = true;
1427 break;
1428 default:
Michal Kazior7aa7a722014-08-25 12:09:38 +02001429 ath10k_warn(ar, "unhandled tx completion status %d\n", status);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001430 tx_done.discard = true;
1431 break;
1432 }
1433
Michal Kazior7aa7a722014-08-25 12:09:38 +02001434 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
Michal Kazior6c5151a2014-02-27 18:50:04 +02001435 resp->data_tx_completion.num_msdus);
1436
1437 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1438 msdu_id = resp->data_tx_completion.msdus[i];
1439 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1440 ath10k_txrx_tx_unref(htt, &tx_done);
1441 }
1442}
1443
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001444static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
1445{
1446 struct htt_rx_addba *ev = &resp->rx_addba;
1447 struct ath10k_peer *peer;
1448 struct ath10k_vif *arvif;
1449 u16 info0, tid, peer_id;
1450
1451 info0 = __le16_to_cpu(ev->info0);
1452 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1453 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1454
Michal Kazior7aa7a722014-08-25 12:09:38 +02001455 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001456 "htt rx addba tid %hu peer_id %hu size %hhu\n",
1457 tid, peer_id, ev->window_size);
1458
1459 spin_lock_bh(&ar->data_lock);
1460 peer = ath10k_peer_find_by_id(ar, peer_id);
1461 if (!peer) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001462 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001463 peer_id);
1464 spin_unlock_bh(&ar->data_lock);
1465 return;
1466 }
1467
1468 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1469 if (!arvif) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001470 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001471 peer->vdev_id);
1472 spin_unlock_bh(&ar->data_lock);
1473 return;
1474 }
1475
Michal Kazior7aa7a722014-08-25 12:09:38 +02001476 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001477 "htt rx start rx ba session sta %pM tid %hu size %hhu\n",
1478 peer->addr, tid, ev->window_size);
1479
1480 ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1481 spin_unlock_bh(&ar->data_lock);
1482}
1483
1484static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
1485{
1486 struct htt_rx_delba *ev = &resp->rx_delba;
1487 struct ath10k_peer *peer;
1488 struct ath10k_vif *arvif;
1489 u16 info0, tid, peer_id;
1490
1491 info0 = __le16_to_cpu(ev->info0);
1492 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1493 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1494
Michal Kazior7aa7a722014-08-25 12:09:38 +02001495 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001496 "htt rx delba tid %hu peer_id %hu\n",
1497 tid, peer_id);
1498
1499 spin_lock_bh(&ar->data_lock);
1500 peer = ath10k_peer_find_by_id(ar, peer_id);
1501 if (!peer) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001502 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001503 peer_id);
1504 spin_unlock_bh(&ar->data_lock);
1505 return;
1506 }
1507
1508 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1509 if (!arvif) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001510 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001511 peer->vdev_id);
1512 spin_unlock_bh(&ar->data_lock);
1513 return;
1514 }
1515
Michal Kazior7aa7a722014-08-25 12:09:38 +02001516 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001517 "htt rx stop rx ba session sta %pM tid %hu\n",
1518 peer->addr, tid);
1519
1520 ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1521 spin_unlock_bh(&ar->data_lock);
1522}
1523
Kalle Valo5e3dd152013-06-12 20:52:10 +03001524void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1525{
Michal Kazioredb82362013-07-05 16:15:14 +03001526 struct ath10k_htt *htt = &ar->htt;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001527 struct htt_resp *resp = (struct htt_resp *)skb->data;
1528
1529 /* confirm alignment */
1530 if (!IS_ALIGNED((unsigned long)skb->data, 4))
Michal Kazior7aa7a722014-08-25 12:09:38 +02001531 ath10k_warn(ar, "unaligned htt message, expect trouble\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001532
Michal Kazior7aa7a722014-08-25 12:09:38 +02001533 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001534 resp->hdr.msg_type);
1535 switch (resp->hdr.msg_type) {
1536 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1537 htt->target_version_major = resp->ver_resp.major;
1538 htt->target_version_minor = resp->ver_resp.minor;
1539 complete(&htt->target_version_received);
1540 break;
1541 }
Michal Kazior6c5151a2014-02-27 18:50:04 +02001542 case HTT_T2H_MSG_TYPE_RX_IND:
Michal Kazior45967082014-02-27 18:50:05 +02001543 spin_lock_bh(&htt->rx_ring.lock);
1544 __skb_queue_tail(&htt->rx_compl_q, skb);
1545 spin_unlock_bh(&htt->rx_ring.lock);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001546 tasklet_schedule(&htt->txrx_compl_task);
1547 return;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001548 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1549 struct htt_peer_map_event ev = {
1550 .vdev_id = resp->peer_map.vdev_id,
1551 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1552 };
1553 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1554 ath10k_peer_map_event(htt, &ev);
1555 break;
1556 }
1557 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1558 struct htt_peer_unmap_event ev = {
1559 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1560 };
1561 ath10k_peer_unmap_event(htt, &ev);
1562 break;
1563 }
1564 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1565 struct htt_tx_done tx_done = {};
1566 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1567
1568 tx_done.msdu_id =
1569 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1570
1571 switch (status) {
1572 case HTT_MGMT_TX_STATUS_OK:
1573 break;
1574 case HTT_MGMT_TX_STATUS_RETRY:
1575 tx_done.no_ack = true;
1576 break;
1577 case HTT_MGMT_TX_STATUS_DROP:
1578 tx_done.discard = true;
1579 break;
1580 }
1581
Michal Kazior6c5151a2014-02-27 18:50:04 +02001582 spin_lock_bh(&htt->tx_lock);
Michal Kazior0a89f8a2013-09-18 14:43:20 +02001583 ath10k_txrx_tx_unref(htt, &tx_done);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001584 spin_unlock_bh(&htt->tx_lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001585 break;
1586 }
Michal Kazior6c5151a2014-02-27 18:50:04 +02001587 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1588 spin_lock_bh(&htt->tx_lock);
1589 __skb_queue_tail(&htt->tx_compl_q, skb);
1590 spin_unlock_bh(&htt->tx_lock);
1591 tasklet_schedule(&htt->txrx_compl_task);
1592 return;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001593 case HTT_T2H_MSG_TYPE_SEC_IND: {
1594 struct ath10k *ar = htt->ar;
1595 struct htt_security_indication *ev = &resp->security_indication;
1596
Michal Kazior7aa7a722014-08-25 12:09:38 +02001597 ath10k_dbg(ar, ATH10K_DBG_HTT,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001598 "sec ind peer_id %d unicast %d type %d\n",
1599 __le16_to_cpu(ev->peer_id),
1600 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1601 MS(ev->flags, HTT_SECURITY_TYPE));
1602 complete(&ar->install_key_done);
1603 break;
1604 }
1605 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001606 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001607 skb->data, skb->len);
1608 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1609 break;
1610 }
1611 case HTT_T2H_MSG_TYPE_TEST:
1612 /* FIX THIS */
1613 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001614 case HTT_T2H_MSG_TYPE_STATS_CONF:
Michal Kaziord35a6c12014-09-02 11:00:21 +03001615 trace_ath10k_htt_stats(ar, skb->data, skb->len);
Kalle Valoa9bf0502013-09-03 11:43:55 +03001616 break;
1617 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
Michal Kazior708b9bd2014-07-21 20:52:59 +03001618 /* Firmware can return tx frames if it's unable to fully
1619 * process them and suspects host may be able to fix it. ath10k
1620 * sends all tx frames as already inspected so this shouldn't
1621 * happen unless fw has a bug.
1622 */
Michal Kazior7aa7a722014-08-25 12:09:38 +02001623 ath10k_warn(ar, "received an unexpected htt tx inspect event\n");
Michal Kazior708b9bd2014-07-21 20:52:59 +03001624 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001625 case HTT_T2H_MSG_TYPE_RX_ADDBA:
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001626 ath10k_htt_rx_addba(ar, resp);
1627 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001628 case HTT_T2H_MSG_TYPE_RX_DELBA:
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001629 ath10k_htt_rx_delba(ar, resp);
1630 break;
Rajkumar Manoharanbfdd7932014-10-03 08:02:40 +03001631 case HTT_T2H_MSG_TYPE_PKTLOG: {
1632 struct ath10k_pktlog_hdr *hdr =
1633 (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload;
1634
1635 trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload,
1636 sizeof(*hdr) +
1637 __le16_to_cpu(hdr->size));
1638 break;
1639 }
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001640 case HTT_T2H_MSG_TYPE_RX_FLUSH: {
1641 /* Ignore this event because mac80211 takes care of Rx
1642 * aggregation reordering.
1643 */
1644 break;
1645 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03001646 default:
Michal Kazior2358a542014-10-02 13:32:55 +02001647 ath10k_warn(ar, "htt event (%d) not handled\n",
1648 resp->hdr.msg_type);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001649 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001650 skb->data, skb->len);
1651 break;
1652 };
1653
1654 /* Free the indication buffer */
1655 dev_kfree_skb_any(skb);
1656}
Michal Kazior6c5151a2014-02-27 18:50:04 +02001657
1658static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1659{
1660 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1661 struct htt_resp *resp;
1662 struct sk_buff *skb;
1663
Michal Kazior45967082014-02-27 18:50:05 +02001664 spin_lock_bh(&htt->tx_lock);
1665 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
Michal Kazior6c5151a2014-02-27 18:50:04 +02001666 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1667 dev_kfree_skb_any(skb);
1668 }
Michal Kazior45967082014-02-27 18:50:05 +02001669 spin_unlock_bh(&htt->tx_lock);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001670
Michal Kazior45967082014-02-27 18:50:05 +02001671 spin_lock_bh(&htt->rx_ring.lock);
1672 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
Michal Kazior6c5151a2014-02-27 18:50:04 +02001673 resp = (struct htt_resp *)skb->data;
1674 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1675 dev_kfree_skb_any(skb);
1676 }
Michal Kazior45967082014-02-27 18:50:05 +02001677 spin_unlock_bh(&htt->rx_ring.lock);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001678}