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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Jesse Barnes585fb112008-07-29 11:54:06 -070033#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_bios.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070035#include <linux/io-mapping.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070044#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
Jesse Barnes317c35d2008-08-25 15:11:06 -070046enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
Keith Packard52440212008-11-18 09:30:25 -080051#define I915_NUM_PIPE 2
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* Interface history:
54 *
55 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110056 * 1.2: Add Power Management
57 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110058 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100059 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100060 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 */
63#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100064#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#define DRIVER_PATCHLEVEL 0
66
Eric Anholt673a3942008-07-30 12:06:12 -070067#define WATCH_COHERENCY 0
68#define WATCH_BUF 0
69#define WATCH_EXEC 0
70#define WATCH_LRU 0
71#define WATCH_RELOC 0
72#define WATCH_INACTIVE 0
73#define WATCH_PWRITE 0
74
Dave Airlie71acb5e2008-12-30 20:31:46 +100075#define I915_GEM_PHYS_CURSOR_0 1
76#define I915_GEM_PHYS_CURSOR_1 2
77#define I915_GEM_PHYS_OVERLAY_REGS 3
78#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
79
80struct drm_i915_gem_phys_object {
81 int id;
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
85};
86
Linus Torvalds1da177e2005-04-16 15:20:36 -070087typedef struct _drm_i915_ring_buffer {
88 int tail_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 unsigned long Size;
90 u8 *virtual_start;
91 int head;
92 int tail;
93 int space;
94 drm_local_map_t map;
Eric Anholt673a3942008-07-30 12:06:12 -070095 struct drm_gem_object *ring_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096} drm_i915_ring_buffer_t;
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104};
105
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100111struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 int enabled;
117};
118
Dave Airlie7c1c2872008-11-28 14:22:24 +1000119struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
122};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800123#define I915_FENCE_REG_NONE -1
124
125struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
127};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129typedef struct drm_i915_private {
Eric Anholt673a3942008-07-30 12:06:12 -0700130 struct drm_device *dev;
131
Dave Airlieac5c4e72008-12-19 15:38:34 +1000132 int has_gem;
133
Eric Anholt3043c602008-10-02 12:24:47 -0700134 void __iomem *regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 drm_i915_ring_buffer_t ring;
137
Dave Airlie9c8da5e2005-07-10 15:38:56 +1000138 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 dma_addr_t dma_status_page;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700141 uint32_t counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000142 unsigned int status_gfx_addr;
143 drm_local_map_t hws_map;
Eric Anholt673a3942008-07-30 12:06:12 -0700144 struct drm_gem_object *hws_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000146 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 int back_offset;
148 int front_offset;
149 int current_page;
150 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151
152 wait_queue_head_t irq_queue;
153 atomic_t irq_received;
Eric Anholted4cb412008-07-29 12:10:39 -0700154 /** Protects user_irq_refcount and irq_mask_reg */
155 spinlock_t user_irq_lock;
156 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
157 int user_irq_refcount;
158 /** Cached value of IMR to avoid reads in updating the bitfield */
159 u32 irq_mask_reg;
Keith Packard7c463582008-11-04 02:03:27 -0800160 u32 pipestat[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162 int tex_lru_log_granularity;
163 int allow_batchbuffer;
164 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100165 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000166 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000167
Jesse Barnes79e53942008-11-07 14:24:08 -0800168 bool cursor_needs_physical;
169
170 struct drm_mm vram;
171
172 int irq_enabled;
173
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100174 struct intel_opregion opregion;
175
Jesse Barnes79e53942008-11-07 14:24:08 -0800176 /* LVDS info */
177 int backlight_duty_cycle; /* restore backlight to this value */
178 bool panel_wants_dither;
179 struct drm_display_mode *panel_fixed_mode;
180 struct drm_display_mode *vbt_mode; /* if any */
181
182 /* Feature bits from the VBIOS */
Hannes Eder95281e32008-12-18 15:09:00 +0100183 unsigned int int_tv_support:1;
184 unsigned int lvds_dither:1;
185 unsigned int lvds_vbt:1;
186 unsigned int int_crt_support:1;
Jesse Barnes79e53942008-11-07 14:24:08 -0800187
Jesse Barnesde151cf2008-11-12 10:03:55 -0800188 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
189 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
190 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
191
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000192 /* Register state */
193 u8 saveLBB;
194 u32 saveDSPACNTR;
195 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000196 u32 saveDSPARB;
Keith Packard881ee982008-11-02 23:08:44 -0800197 u32 saveRENDERSTANDBY;
Peng Li461cba22008-11-18 12:39:02 +0800198 u32 saveHWS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000199 u32 savePIPEACONF;
200 u32 savePIPEBCONF;
201 u32 savePIPEASRC;
202 u32 savePIPEBSRC;
203 u32 saveFPA0;
204 u32 saveFPA1;
205 u32 saveDPLL_A;
206 u32 saveDPLL_A_MD;
207 u32 saveHTOTAL_A;
208 u32 saveHBLANK_A;
209 u32 saveHSYNC_A;
210 u32 saveVTOTAL_A;
211 u32 saveVBLANK_A;
212 u32 saveVSYNC_A;
213 u32 saveBCLRPAT_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000214 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000215 u32 saveDSPASTRIDE;
216 u32 saveDSPASIZE;
217 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700218 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000219 u32 saveDSPASURF;
220 u32 saveDSPATILEOFF;
221 u32 savePFIT_PGM_RATIOS;
222 u32 saveBLC_PWM_CTL;
223 u32 saveBLC_PWM_CTL2;
224 u32 saveFPB0;
225 u32 saveFPB1;
226 u32 saveDPLL_B;
227 u32 saveDPLL_B_MD;
228 u32 saveHTOTAL_B;
229 u32 saveHBLANK_B;
230 u32 saveHSYNC_B;
231 u32 saveVTOTAL_B;
232 u32 saveVBLANK_B;
233 u32 saveVSYNC_B;
234 u32 saveBCLRPAT_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000235 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000236 u32 saveDSPBSTRIDE;
237 u32 saveDSPBSIZE;
238 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700239 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000240 u32 saveDSPBSURF;
241 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700242 u32 saveVGA0;
243 u32 saveVGA1;
244 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000245 u32 saveVGACNTRL;
246 u32 saveADPA;
247 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700248 u32 savePP_ON_DELAYS;
249 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000250 u32 saveDVOA;
251 u32 saveDVOB;
252 u32 saveDVOC;
253 u32 savePP_ON;
254 u32 savePP_OFF;
255 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700256 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000257 u32 savePFIT_CONTROL;
258 u32 save_palette_a[256];
259 u32 save_palette_b[256];
260 u32 saveFBC_CFB_BASE;
261 u32 saveFBC_LL_BASE;
262 u32 saveFBC_CONTROL;
263 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000264 u32 saveIER;
265 u32 saveIIR;
266 u32 saveIMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800267 u32 saveCACHE_MODE_0;
Keith Packarde948e992008-05-07 12:27:53 +1000268 u32 saveD_STATE;
Jesse Barnes585fb112008-07-29 11:54:06 -0700269 u32 saveCG_2D_DIS;
Keith Packard1f84e552008-02-16 19:19:29 -0800270 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000271 u32 saveSWF0[16];
272 u32 saveSWF1[16];
273 u32 saveSWF2[3];
274 u8 saveMSR;
275 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800276 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000277 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000278 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000279 u8 saveDACMASK;
280 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
Jesse Barnesa59e1222008-05-07 12:25:46 +1000281 u8 saveCR[37];
Eric Anholt673a3942008-07-30 12:06:12 -0700282
283 struct {
284 struct drm_mm gtt_space;
285
Keith Packard0839ccb2008-10-30 19:38:48 -0700286 struct io_mapping *gtt_mapping;
Eric Anholtab657db12009-01-23 12:57:47 -0800287 int gtt_mtrr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700288
Eric Anholt673a3942008-07-30 12:06:12 -0700289 /**
290 * List of objects currently involved in rendering from the
291 * ringbuffer.
292 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800293 * Includes buffers having the contents of their GPU caches
294 * flushed, not necessarily primitives. last_rendering_seqno
295 * represents when the rendering involved will be completed.
296 *
Eric Anholt673a3942008-07-30 12:06:12 -0700297 * A reference is held on the buffer while on this list.
298 */
299 struct list_head active_list;
300
301 /**
302 * List of objects which are not in the ringbuffer but which
303 * still have a write_domain which needs to be flushed before
304 * unbinding.
305 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800306 * last_rendering_seqno is 0 while an object is in this list.
307 *
Eric Anholt673a3942008-07-30 12:06:12 -0700308 * A reference is held on the buffer while on this list.
309 */
310 struct list_head flushing_list;
311
312 /**
313 * LRU list of objects which are not in the ringbuffer and
314 * are ready to unbind, but are still in the GTT.
315 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800316 * last_rendering_seqno is 0 while an object is in this list.
317 *
Eric Anholt673a3942008-07-30 12:06:12 -0700318 * A reference is not held on the buffer while on this list,
319 * as merely being GTT-bound shouldn't prevent its being
320 * freed, and we'll pull it off the list in the free path.
321 */
322 struct list_head inactive_list;
323
324 /**
325 * List of breadcrumbs associated with GPU requests currently
326 * outstanding.
327 */
328 struct list_head request_list;
329
330 /**
331 * We leave the user IRQ off as much as possible,
332 * but this means that requests will finish and never
333 * be retired once the system goes idle. Set a timer to
334 * fire periodically while the ring is running. When it
335 * fires, go retire requests.
336 */
337 struct delayed_work retire_work;
338
339 uint32_t next_gem_seqno;
340
341 /**
342 * Waiting sequence number, if any
343 */
344 uint32_t waiting_gem_seqno;
345
346 /**
347 * Last seq seen at irq time
348 */
349 uint32_t irq_gem_seqno;
350
351 /**
352 * Flag if the X Server, and thus DRM, is not currently in
353 * control of the device.
354 *
355 * This is set between LeaveVT and EnterVT. It needs to be
356 * replaced with a semaphore. It also needs to be
357 * transitioned away from for kernel modesetting.
358 */
359 int suspended;
360
361 /**
362 * Flag if the hardware appears to be wedged.
363 *
364 * This is set when attempts to idle the device timeout.
365 * It prevents command submission from occuring and makes
366 * every pending request fail
367 */
368 int wedged;
369
370 /** Bit 6 swizzling required for X tiling */
371 uint32_t bit_6_swizzle_x;
372 /** Bit 6 swizzling required for Y tiling */
373 uint32_t bit_6_swizzle_y;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000374
375 /* storage for physical objects */
376 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
Eric Anholt673a3942008-07-30 12:06:12 -0700377 } mm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378} drm_i915_private_t;
379
Eric Anholt673a3942008-07-30 12:06:12 -0700380/** driver private structure attached to each drm_gem_object */
381struct drm_i915_gem_object {
382 struct drm_gem_object *obj;
383
384 /** Current space allocated to this object in the GTT, if any. */
385 struct drm_mm_node *gtt_space;
386
387 /** This object's place on the active/flushing/inactive lists */
388 struct list_head list;
389
390 /**
391 * This is set if the object is on the active or flushing lists
392 * (has pending rendering), and is not set if it's on inactive (ready
393 * to be unbound).
394 */
395 int active;
396
397 /**
398 * This is set if the object has been written to since last bound
399 * to the GTT
400 */
401 int dirty;
402
403 /** AGP memory structure for our GTT binding. */
404 DRM_AGP_MEM *agp_mem;
405
406 struct page **page_list;
407
408 /**
409 * Current offset of the object in GTT space.
410 *
411 * This is the same as gtt_space->start
412 */
413 uint32_t gtt_offset;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800414 /**
415 * Required alignment for the object
416 */
417 uint32_t gtt_alignment;
418 /**
419 * Fake offset for use by mmap(2)
420 */
421 uint64_t mmap_offset;
422
423 /**
424 * Fence register bits (if any) for this object. Will be set
425 * as needed when mapped into the GTT.
426 * Protected by dev->struct_mutex.
427 */
428 int fence_reg;
Eric Anholt673a3942008-07-30 12:06:12 -0700429
430 /** Boolean whether this object has a valid gtt offset. */
431 int gtt_bound;
432
433 /** How many users have pinned this object in GTT space */
434 int pin_count;
435
436 /** Breadcrumb of last rendering to the buffer. */
437 uint32_t last_rendering_seqno;
438
439 /** Current tiling mode for the object. */
440 uint32_t tiling_mode;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800441 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -0700442
Keith Packardba1eb1d2008-10-14 19:55:10 -0700443 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
444 uint32_t agp_type;
445
Eric Anholt673a3942008-07-30 12:06:12 -0700446 /**
Eric Anholte47c68e2008-11-14 13:35:19 -0800447 * If present, while GEM_DOMAIN_CPU is in the read domain this array
448 * flags which individual pages are valid.
Eric Anholt673a3942008-07-30 12:06:12 -0700449 */
450 uint8_t *page_cpu_valid;
Jesse Barnes79e53942008-11-07 14:24:08 -0800451
452 /** User space pin count and filp owning the pin */
453 uint32_t user_pin_count;
454 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000455
456 /** for phy allocated objects */
457 struct drm_i915_gem_phys_object *phys_obj;
Eric Anholt673a3942008-07-30 12:06:12 -0700458};
459
460/**
461 * Request queue structure.
462 *
463 * The request queue allows us to note sequence numbers that have been emitted
464 * and may be associated with active buffers to be retired.
465 *
466 * By keeping this list, we can avoid having to do questionable
467 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
468 * an emission time with seqnos for tracking how far ahead of the GPU we are.
469 */
470struct drm_i915_gem_request {
471 /** GEM sequence number associated with this request. */
472 uint32_t seqno;
473
474 /** Time at which this request was emitted, in jiffies. */
475 unsigned long emitted_jiffies;
476
Eric Anholt673a3942008-07-30 12:06:12 -0700477 struct list_head list;
478};
479
480struct drm_i915_file_private {
481 struct {
482 uint32_t last_gem_seqno;
483 uint32_t last_gem_throttle_seqno;
484 } mm;
485};
486
Jesse Barnes79e53942008-11-07 14:24:08 -0800487enum intel_chip_family {
488 CHIP_I8XX = 0x01,
489 CHIP_I9XX = 0x02,
490 CHIP_I915 = 0x04,
491 CHIP_I965 = 0x08,
492};
493
Eric Anholtc153f452007-09-03 12:06:45 +1000494extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000495extern int i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -0800496extern unsigned int i915_fbpercrtc;
Dave Airlieb3a83632005-09-30 18:37:36 +1000497
Dave Airlie7c1c2872008-11-28 14:22:24 +1000498extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
499extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
500
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000502extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100503extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000504extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -0700505extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000506extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000507extern void i915_driver_preclose(struct drm_device *dev,
508 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700509extern void i915_driver_postclose(struct drm_device *dev,
510 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000511extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100512extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
513 unsigned long arg);
Eric Anholt673a3942008-07-30 12:06:12 -0700514extern int i915_emit_box(struct drm_device *dev,
515 struct drm_clip_rect __user *boxes,
516 int i, int DR1, int DR4);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000517
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518/* i915_irq.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000519extern int i915_irq_emit(struct drm_device *dev, void *data,
520 struct drm_file *file_priv);
521extern int i915_irq_wait(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700523void i915_user_irq_get(struct drm_device *dev);
524void i915_user_irq_put(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800525extern void i915_enable_interrupt (struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526
527extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000528extern void i915_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700529extern int i915_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000530extern void i915_driver_irq_uninstall(struct drm_device * dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000531extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
532 struct drm_file *file_priv);
533extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
534 struct drm_file *file_priv);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700535extern int i915_enable_vblank(struct drm_device *dev, int crtc);
536extern void i915_disable_vblank(struct drm_device *dev, int crtc);
537extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
Eric Anholtc153f452007-09-03 12:06:45 +1000538extern int i915_vblank_swap(struct drm_device *dev, void *data,
539 struct drm_file *file_priv);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100540extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541
Keith Packard7c463582008-11-04 02:03:27 -0800542void
543i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
544
545void
546i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
547
548
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549/* i915_mem.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000550extern int i915_mem_alloc(struct drm_device *dev, void *data,
551 struct drm_file *file_priv);
552extern int i915_mem_free(struct drm_device *dev, void *data,
553 struct drm_file *file_priv);
554extern int i915_mem_init_heap(struct drm_device *dev, void *data,
555 struct drm_file *file_priv);
556extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
557 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000559extern void i915_mem_release(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000560 struct drm_file *file_priv, struct mem_block *heap);
Eric Anholt673a3942008-07-30 12:06:12 -0700561/* i915_gem.c */
562int i915_gem_init_ioctl(struct drm_device *dev, void *data,
563 struct drm_file *file_priv);
564int i915_gem_create_ioctl(struct drm_device *dev, void *data,
565 struct drm_file *file_priv);
566int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
567 struct drm_file *file_priv);
568int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
569 struct drm_file *file_priv);
570int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
571 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800572int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
573 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700574int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
575 struct drm_file *file_priv);
576int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv);
578int i915_gem_execbuffer(struct drm_device *dev, void *data,
579 struct drm_file *file_priv);
580int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
581 struct drm_file *file_priv);
582int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
583 struct drm_file *file_priv);
584int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
585 struct drm_file *file_priv);
586int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
587 struct drm_file *file_priv);
588int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
589 struct drm_file *file_priv);
590int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
591 struct drm_file *file_priv);
592int i915_gem_set_tiling(struct drm_device *dev, void *data,
593 struct drm_file *file_priv);
594int i915_gem_get_tiling(struct drm_device *dev, void *data,
595 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -0700596int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
597 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700598void i915_gem_load(struct drm_device *dev);
599int i915_gem_proc_init(struct drm_minor *minor);
600void i915_gem_proc_cleanup(struct drm_minor *minor);
601int i915_gem_init_object(struct drm_gem_object *obj);
602void i915_gem_free_object(struct drm_gem_object *obj);
603int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
604void i915_gem_object_unpin(struct drm_gem_object *obj);
Jesse Barnes0f973f22009-01-26 17:10:45 -0800605int i915_gem_object_unbind(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700606void i915_gem_lastclose(struct drm_device *dev);
607uint32_t i915_get_gem_seqno(struct drm_device *dev);
608void i915_gem_retire_requests(struct drm_device *dev);
609void i915_gem_retire_work_handler(struct work_struct *work);
610void i915_gem_clflush_object(struct drm_gem_object *obj);
Jesse Barnes79e53942008-11-07 14:24:08 -0800611int i915_gem_object_set_domain(struct drm_gem_object *obj,
612 uint32_t read_domains,
613 uint32_t write_domain);
614int i915_gem_init_ringbuffer(struct drm_device *dev);
615void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
616int i915_gem_do_init(struct drm_device *dev, unsigned long start,
617 unsigned long end);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800618int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Jesse Barnes79e53942008-11-07 14:24:08 -0800619int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
620 int write);
Dave Airlie71acb5e2008-12-30 20:31:46 +1000621int i915_gem_attach_phys_object(struct drm_device *dev,
622 struct drm_gem_object *obj, int id);
623void i915_gem_detach_phys_object(struct drm_device *dev,
624 struct drm_gem_object *obj);
625void i915_gem_free_all_phys_object(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -0700626
627/* i915_gem_tiling.c */
628void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
629
630/* i915_gem_debug.c */
631void i915_gem_dump_object(struct drm_gem_object *obj, int len,
632 const char *where, uint32_t mark);
633#if WATCH_INACTIVE
634void i915_verify_inactive(struct drm_device *dev, char *file, int line);
635#else
636#define i915_verify_inactive(dev, file, line)
637#endif
638void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
639void i915_gem_dump_object(struct drm_gem_object *obj, int len,
640 const char *where, uint32_t mark);
641void i915_dump_lru(struct drm_device *dev, const char *where);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642
Jesse Barnes317c35d2008-08-25 15:11:06 -0700643/* i915_suspend.c */
644extern int i915_save_state(struct drm_device *dev);
645extern int i915_restore_state(struct drm_device *dev);
646
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700647/* i915_suspend.c */
648extern int i915_save_state(struct drm_device *dev);
649extern int i915_restore_state(struct drm_device *dev);
650
Len Brown65e082c2008-10-24 17:18:10 -0400651#ifdef CONFIG_ACPI
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100652/* i915_opregion.c */
653extern int intel_opregion_init(struct drm_device *dev);
654extern void intel_opregion_free(struct drm_device *dev);
655extern void opregion_asle_intr(struct drm_device *dev);
656extern void opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -0400657#else
658static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
659static inline void intel_opregion_free(struct drm_device *dev) { return; }
660static inline void opregion_asle_intr(struct drm_device *dev) { return; }
661static inline void opregion_enable_asle(struct drm_device *dev) { return; }
662#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100663
Jesse Barnes79e53942008-11-07 14:24:08 -0800664/* modesetting */
665extern void intel_modeset_init(struct drm_device *dev);
666extern void intel_modeset_cleanup(struct drm_device *dev);
667
Eric Anholt546b0972008-09-01 16:45:29 -0700668/**
669 * Lock test for when it's just for synchronization of ring access.
670 *
671 * In that case, we don't need to do it when GEM is initialized as nobody else
672 * has access to the ring.
673 */
674#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
675 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
676 LOCK_TEST_WITH_RETURN(dev, file_priv); \
677} while (0)
678
Eric Anholt3043c602008-10-02 12:24:47 -0700679#define I915_READ(reg) readl(dev_priv->regs + (reg))
680#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
681#define I915_READ16(reg) readw(dev_priv->regs + (reg))
682#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
683#define I915_READ8(reg) readb(dev_priv->regs + (reg))
684#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
Jesse Barnesde151cf2008-11-12 10:03:55 -0800685#ifdef writeq
686#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
687#else
688#define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
689 writel(upper_32_bits(val), dev_priv->regs + \
690 (reg) + 4))
691#endif
Eric Anholt7d573822009-01-02 13:33:00 -0800692#define POSTING_READ(reg) (void)I915_READ(reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693
694#define I915_VERBOSE 0
695
696#define RING_LOCALS unsigned int outring, ringmask, outcount; \
697 volatile char *virt;
698
699#define BEGIN_LP_RING(n) do { \
700 if (I915_VERBOSE) \
Márton Németh3e684ea2008-01-24 15:58:57 +1000701 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
702 if (dev_priv->ring.space < (n)*4) \
Harvey Harrisonbf9d8922008-04-30 00:55:10 -0700703 i915_wait_ring(dev, (n)*4, __func__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 outcount = 0; \
705 outring = dev_priv->ring.tail; \
706 ringmask = dev_priv->ring.tail_mask; \
707 virt = dev_priv->ring.virtual_start; \
708} while (0)
709
710#define OUT_RING(n) do { \
711 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000712 *(volatile unsigned int *)(virt + outring) = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 outcount++; \
714 outring += 4; \
715 outring &= ringmask; \
716} while (0)
717
718#define ADVANCE_LP_RING() do { \
719 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
720 dev_priv->ring.tail = outring; \
721 dev_priv->ring.space -= outcount * 4; \
Jesse Barnes585fb112008-07-29 11:54:06 -0700722 I915_WRITE(PRB0_TAIL, outring); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723} while(0)
724
Jesse Barnes585fb112008-07-29 11:54:06 -0700725/**
726 * Reads a dword out of the status page, which is written to from the command
727 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
728 * MI_STORE_DATA_IMM.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000729 *
Jesse Barnes585fb112008-07-29 11:54:06 -0700730 * The following dwords have a reserved meaning:
Keith Packard0cdad7e2008-10-14 17:19:38 -0700731 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
732 * 0x04: ring 0 head pointer
733 * 0x05: ring 1 head pointer (915-class)
734 * 0x06: ring 2 head pointer (915-class)
735 * 0x10-0x1b: Context status DWords (GM45)
736 * 0x1f: Last written status offset. (GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -0700737 *
Keith Packard0cdad7e2008-10-14 17:19:38 -0700738 * The area from dword 0x20 to 0x3ff is available for driver usage.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000739 */
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000740#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
Keith Packard0baf8232008-11-08 11:44:14 +1000741#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
Keith Packard0cdad7e2008-10-14 17:19:38 -0700742#define I915_GEM_HWS_INDEX 0x20
Keith Packard0baf8232008-11-08 11:44:14 +1000743#define I915_BREADCRUMB_INDEX 0x21
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000744
Jesse Barnes585fb112008-07-29 11:54:06 -0700745extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000746
747#define IS_I830(dev) ((dev)->pci_device == 0x3577)
748#define IS_845G(dev) ((dev)->pci_device == 0x2562)
749#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
750#define IS_I855(dev) ((dev)->pci_device == 0x3582)
751#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
752
Carlos Martín4d1f7882008-01-23 16:41:17 +1000753#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000754#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
755#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
Jesse Barnes3bf48462008-04-06 11:55:04 -0700756#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
757 (dev)->pci_device == 0x27AE)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000758#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
759 (dev)->pci_device == 0x2982 || \
760 (dev)->pci_device == 0x2992 || \
761 (dev)->pci_device == 0x29A2 || \
762 (dev)->pci_device == 0x2A02 || \
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000763 (dev)->pci_device == 0x2A12 || \
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000764 (dev)->pci_device == 0x2A42 || \
765 (dev)->pci_device == 0x2E02 || \
766 (dev)->pci_device == 0x2E12 || \
767 (dev)->pci_device == 0x2E22)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000768
769#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
770
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700771#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000772
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000773#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
774 (dev)->pci_device == 0x2E12 || \
Eric Anholt60fd99e2008-12-03 22:50:02 -0800775 (dev)->pci_device == 0x2E22 || \
776 IS_GM45(dev))
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000777
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000778#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
779 (dev)->pci_device == 0x29B2 || \
780 (dev)->pci_device == 0x29D2)
781
782#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
783 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
784
785#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700786 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000787
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700788#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
Jesse Barnes0f973f22009-01-26 17:10:45 -0800789/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
790 * rows, which changed the alignment requirements and fence programming.
791 */
792#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
793 IS_I915GM(dev)))
Eric Anholt7d573822009-01-02 13:33:00 -0800794#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
Zhenyu Wangb39d50e2008-02-19 20:59:09 +1000795
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000796#define PRIMARY_RINGBUFFER_SIZE (128*1024)
Dave Airlie0d6aa602006-01-02 20:14:23 +1100797
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798#endif