blob: e1c7937e4ae091d0ee1f8379c29a0a41fd398f70 [file] [log] [blame]
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafad3935822012-10-09 11:23:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Olav Haugan54166782013-01-28 16:59:51 -080014/include/ "msm-iommu-v0.dtsi"
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -080015/include/ "msm8610-ion.dtsi"
Lokesh Batra8d55eec2013-02-26 11:31:21 -080016/include/ "msm8610-gpu.dtsi"
Matt Wagantall1bf56932012-11-29 15:03:29 -080017/include/ "msm-gdsc.dtsi"
Aparna Dasd16555b2013-03-06 15:46:38 -080018/include/ "msm8610-coresight.dtsi"
Praveen Chidambarama1f98282012-11-29 09:56:57 -070019/include/ "msm8610-pm.dtsi"
Jeff Hugo53dcf0f2013-03-20 12:37:50 -060020/include/ "msm8610-smp2p.dtsi"
Gagan Macbced3872013-02-04 19:18:04 -070021/include/ "msm8610-bus.dtsi"
Syed Rameez Mustafad3935822012-10-09 11:23:20 -070022
23/ {
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -080024 model = "Qualcomm MSM 8610";
25 compatible = "qcom,msm8610";
Syed Rameez Mustafad3935822012-10-09 11:23:20 -070026 interrupt-parent = <&intc>;
27
28 intc: interrupt-controller@f9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
31 #interrupt-cells = <3>;
32 reg = <0xf9000000 0x1000>,
33 <0xf9002000 0x1000>;
34 };
35
36 msmgpio: gpio@fd510000 {
37 compatible = "qcom,msm-gpio";
38 interrupt-controller;
39 #interrupt-cells = <2>;
40 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -080041 gpio-controller;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -070042 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -080043 ngpio = <102>;
Rohit Vaswanid2001522012-12-05 19:23:44 -080044 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -080045 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -070046 };
47
Laura Abbott429e82b2013-03-25 13:03:06 -070048 memory {
49
50 qsecom_mem: qsecom_region {
51 linux,contiguous-region;
52 reg = <0 0x100000>;
53 label = "qsecom_mem";
54 };
55
56 };
57
Gilad Avidovf58f1832013-01-09 17:31:28 -070058 aliases {
59 spi0 = &spi_0;
Venkat Gopalakrishnana6ce5f22013-04-04 14:24:57 -070060 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
61 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
Gilad Avidovf58f1832013-01-09 17:31:28 -070062 };
63
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -070064 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -080065 compatible = "arm,armv7-timer";
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -070066 interrupts = <1 2 0 1 3 0>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -070067 clock-frequency = <19200000>;
68 };
69
Stephen Boyda61ac642013-04-10 14:20:27 -070070 timer@f9020000 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74 compatible = "arm,armv7-timer-mem";
75 reg = <0xf9020000 0x1000>;
76 clock-frequency = <19200000>;
77
78 frame@f9021000 {
79 frame-number = <0>;
80 interrupts = <0 8 0x4>,
81 <0 7 0x4>;
82 reg = <0xf9021000 0x1000>,
83 <0xf9022000 0x1000>;
84 };
85
86 frame@f9023000 {
87 frame-number = <1>;
88 interrupts = <0 9 0x4>;
89 reg = <0xf9023000 0x1000>;
90 status = "disabled";
91 };
92
93 frame@f9024000 {
94 frame-number = <2>;
95 interrupts = <0 10 0x4>;
96 reg = <0xf9024000 0x1000>;
97 status = "disabled";
98 };
99
100 frame@f9025000 {
101 frame-number = <3>;
102 interrupts = <0 11 0x4>;
103 reg = <0xf9025000 0x1000>;
104 status = "disabled";
105 };
106
107 frame@f9026000 {
108 frame-number = <4>;
109 interrupts = <0 12 0x4>;
110 reg = <0xf9026000 0x1000>;
111 status = "disabled";
112 };
113
114 frame@f9027000 {
115 frame-number = <5>;
116 interrupts = <0 13 0x4>;
117 reg = <0xf9027000 0x1000>;
118 status = "disabled";
119 };
120
121 frame@f9028000 {
122 frame-number = <6>;
123 interrupts = <0 14 0x4>;
124 reg = <0xf9028000 0x1000>;
125 status = "disabled";
126 };
127 };
128
Arun Menon2a7e3772013-01-17 12:06:59 -0800129 qcom,msm-adsp-loader {
130 compatible = "qcom,adsp-loader";
131 qcom,adsp-state = <0>;
132 };
133
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -0800134 qcom,msm-imem@fe805000 {
135 compatible = "qcom,msm-imem";
136 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
137 };
138
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700139 serial@f991f000 {
140 compatible = "qcom,msm-lsuart-v14";
141 reg = <0xf991f000 0x1000>;
142 interrupts = <0 109 0>;
143 status = "disabled";
144 };
Mayank Rana55db0cb2012-10-15 16:50:06 +0530145
Hanumant Singh6b346712013-04-09 16:26:09 -0700146 serial@f991e000 {
147 compatible = "qcom,msm-lsuart-v14";
148 reg = <0xf991e000 0x1000>;
149 interrupts = <0 108 0>;
150 status = "disabled";
151 };
152
Arun Menon8e25dd42013-01-11 14:11:54 -0800153 qcom,vidc@fdc00000 {
154 compatible = "qcom,msm-vidc";
Sachin Shah4e1c8fe2013-03-20 15:10:05 -0700155 qcom,vidc-ns-map = <0x40000000 0x40000000>;
156 qcom,iommu-groups = <&q6_domain_ns>;
157 qcom,iommu-group-buffer-types = <0xfff>;
158 qcom,buffer-type-tz-usage-map = <0x1 0x1>,
159 <0x1fe 0x2>;
160 qcom,hfi = "q6";
Deva Ramasubramanian74b1dda2013-03-27 13:16:17 -0700161 qcom,max-hw-load = <97200>; /* FWVGA @ 30 * 2 */
Arun Menon8e25dd42013-01-11 14:11:54 -0800162 };
163
Vamsi Krishna872fbbc2013-04-09 18:04:52 -0700164 qcom,usbbam@f9a44000 {
165 compatible = "qcom,usb-bam-msm";
166 reg = <0xf9a44000 0x11000>;
167 reg-names = "hsusb";
168 interrupts = <0 135 0>;
169 interrupt-names = "hsusb";
170 qcom,usb-bam-num-pipes = <16>;
171 qcom,usb-bam-fifo-baseaddr = <0xfe803000>;
172 qcom,ignore-core-reset-ack;
173 qcom,disable-clk-gating;
174
175 qcom,pipe0 {
176 label = "hsusb-qdss-in-0";
177 qcom,usb-bam-mem-type = <3>;
178 qcom,bam-type = <1>;
179 qcom,dir = <1>;
180 qcom,pipe-num = <0>;
181 qcom,peer-bam = <1>;
182 qcom,src-bam-physical-address = <0xfc37c000>;
183 qcom,src-bam-pipe-index = <0>;
184 qcom,dst-bam-physical-address = <0xf9a44000>;
185 qcom,dst-bam-pipe-index = <2>;
186 qcom,data-fifo-offset = <0x0>;
187 qcom,data-fifo-size = <0x600>;
188 qcom,descriptor-fifo-offset = <0x600>;
189 qcom,descriptor-fifo-size = <0x200>;
190 };
191 };
192
Mayank Rana55db0cb2012-10-15 16:50:06 +0530193 usb@f9a55000 {
194 compatible = "qcom,hsusb-otg";
195 reg = <0xf9a55000 0x400>;
Mayank Rana33d26662013-01-17 10:22:25 +0530196 interrupts = <0 134 0>, <0 140 0>;
197 interrupt-names = "core_irq", "async_irq";
Mayank Rana76c6ce22012-11-07 17:07:58 +0530198 HSUSB_VDDCX-supply = <&pm8110_s1>;
199 HSUSB_1p8-supply = <&pm8110_l10>;
200 HSUSB_3p3-supply = <&pm8110_l20>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530201
202 qcom,hsusb-otg-phy-type = <2>;
203 qcom,hsusb-otg-mode = <1>;
Mayank Rana29bb9f22013-04-04 18:25:12 +0530204 qcom,hsusb-otg-otg-control = <2>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530205 qcom,hsusb-otg-disable-reset;
Mayank Ranaa5491122013-04-04 18:32:25 +0530206 qcom,dp-manual-pullup;
Mayank Ranaf9295802013-04-04 18:36:44 +0530207
208 qcom,msm-bus,name = "usb2";
209 qcom,msm-bus,num-cases = <2>;
210 qcom,msm-bus,active-only = <0>;
211 qcom,msm-bus,num-paths = <1>;
212 qcom,msm-bus,vectors-KBps =
213 <87 512 0 0>,
214 <87 512 60000 960000>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530215 };
216
Mayank Ranacc0c5452013-01-29 16:41:53 +0530217 android_usb@fe8050c8 {
Mayank Rana55db0cb2012-10-15 16:50:06 +0530218 compatible = "qcom,android-usb";
Mayank Ranacc0c5452013-01-29 16:41:53 +0530219 reg = <0xfe8050c8 0xc8>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530220 };
221
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700222 sdcc1: qcom,sdcc@f9824000 {
223 cell-index = <1>; /* SDC1 eMMC slot */
224 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800225 reg = <0xf9824000 0x800>,
226 <0xf9824800 0x100>,
227 <0xf9804000 0x7000>;
228 reg-names = "core_mem", "dml_mem", "bam_mem";
229 interrupts = <0 123 0>, <0 137 0>;
230 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700231
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700232 vdd-supply = <&pm8110_l17>;
233 qcom,vdd-always-on;
234 qcom,vdd-lpm-sup;
235 qcom,vdd-voltage-level = <2900000 2900000>;
236 qcom,vdd-current-level = <9000 400000>;
237
238 vdd-io-supply = <&pm8110_l6>;
239 qcom,vdd-io-always-on;
240 qcom,vdd-io-lpm-sup;
241 qcom,vdd-io-voltage-level = <1800000 1800000>;
242 qcom,vdd-io-current-level = <9000 60000>;
243
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700244 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
245 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
Krishna Konda6c5d0f42013-04-12 16:44:26 -0700246 qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700247 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700248
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700249 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700250 qcom,sup-voltages = <2900 2900>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700251 qcom,bus-width = <8>;
252 qcom,nonremovable;
253 qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Venkat Gopalakrishnan587b2252013-04-05 12:16:50 -0700254
255 status = "disabled";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700256 };
257
258 sdcc2: qcom,sdcc@f98a4000 {
259 cell-index = <2>; /* SDC2 SD card slot */
260 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800261 reg = <0xf98a4000 0x800>,
262 <0xf98a4800 0x100>,
263 <0xf9884000 0x7000>;
264 reg-names = "core_mem", "dml_mem", "bam_mem";
265 interrupts = <0 125 0>, <0 220 0>;
266 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700267
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700268 vdd-supply = <&pm8110_l18>;
269 qcom,vdd-voltage-level = <2950000 2950000>;
270 qcom,vdd-current-level = <9000 400000>;
271
272 vdd-io-supply = <&pm8110_l21>;
273 qcom,vdd-io-voltage-level = <1800000 2950000>;
274 qcom,vdd-io-current-level = <9000 50000>;
275
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700276 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
277 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
Krishna Konda6c5d0f42013-04-12 16:44:26 -0700278 qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700279 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700280
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700281 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
282 qcom,sup-voltages = <2950 2950>;
283 qcom,bus-width = <4>;
284 qcom,xpc;
285 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
286 qcom,current-limit = <800>;
Venkat Gopalakrishnan587b2252013-04-05 12:16:50 -0700287
288 status = "disabled";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700289 };
290
Venkat Gopalakrishnana6ce5f22013-04-04 14:24:57 -0700291 sdhc_1: sdhci@f9824900 {
292 compatible = "qcom,sdhci-msm";
293 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
294 reg-names = "hc_mem", "core_mem";
295
296 interrupts = <0 123 0>, <0 138 0>;
297 interrupt-names = "hc_irq", "pwr_irq";
298
299 qcom,bus-width = <8>;
300 status = "disabled";
301 };
302
303 sdhc_2: sdhci@f98a4900 {
304 compatible = "qcom,sdhci-msm";
305 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
306 reg-names = "hc_mem", "core_mem";
307
308 interrupts = <0 125 0>, <0 221 0>;
309 interrupt-names = "hc_irq", "pwr_irq";
310
311 qcom,bus-width = <4>;
312 status = "disabled";
313 };
314
Yan He6c7304c2012-11-09 22:07:08 -0800315 qcom,sps {
316 compatible = "qcom,msm_sps";
317 qcom,device-type = <3>;
318 };
319
Jeff Hugo4e20fda2013-04-10 12:40:19 -0600320 qcom,smem@d900000 {
Jeff Hugo818d0f72012-11-05 14:19:28 -0700321 compatible = "qcom,smem";
Jeff Hugo4e20fda2013-04-10 12:40:19 -0600322 reg = <0xd900000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800323 <0xf9011000 0x1000>,
Jeff Hugo818d0f72012-11-05 14:19:28 -0700324 <0xfc428000 0x4000>;
325 reg-names = "smem", "irq-reg-base", "aux-mem1";
326
327 qcom,smd-modem {
328 compatible = "qcom,smd";
329 qcom,smd-edge = <0>;
330 qcom,smd-irq-offset = <0x8>;
331 qcom,smd-irq-bitmask = <0x1000>;
332 qcom,pil-string = "modem";
333 interrupts = <0 25 1>;
334 };
335
336 qcom,smsm-modem {
337 compatible = "qcom,smsm";
338 qcom,smsm-edge = <0>;
339 qcom,smsm-irq-offset = <0x8>;
340 qcom,smsm-irq-bitmask = <0x2000>;
341 interrupts = <0 26 1>;
342 };
343
344 qcom,smd-adsp {
345 compatible = "qcom,smd";
346 qcom,smd-edge = <1>;
347 qcom,smd-irq-offset = <0x8>;
348 qcom,smd-irq-bitmask = <0x100>;
349 qcom,pil-string = "adsp";
350 interrupts = <0 156 1>;
351 };
352
353 qcom,smsm-adsp {
354 compatible = "qcom,smsm";
355 qcom,smsm-edge = <1>;
356 qcom,smsm-irq-offset = <0x8>;
357 qcom,smsm-irq-bitmask = <0x200>;
358 interrupts = <0 157 1>;
359 };
360
361 qcom,smd-wcnss {
362 compatible = "qcom,smd";
363 qcom,smd-edge = <6>;
364 qcom,smd-irq-offset = <0x8>;
365 qcom,smd-irq-bitmask = <0x20000>;
366 qcom,pil-string = "wcnss";
367 interrupts = <0 142 1>;
368 };
369
370 qcom,smsm-wcnss {
371 compatible = "qcom,smsm";
372 qcom,smsm-edge = <6>;
373 qcom,smsm-irq-offset = <0x8>;
374 qcom,smsm-irq-bitmask = <0x80000>;
375 interrupts = <0 144 1>;
376 };
377
378 qcom,smd-rpm {
379 compatible = "qcom,smd";
380 qcom,smd-edge = <15>;
381 qcom,smd-irq-offset = <0x8>;
382 qcom,smd-irq-bitmask = <0x1>;
383 interrupts = <0 168 1>;
384 qcom,irq-no-suspend;
385 };
David Ng5a3cb232012-12-03 16:42:53 -0800386 };
Hanumant Singh4e334c82012-11-14 10:16:39 -0800387
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700388 rpm_bus: qcom,rpm-smd {
389 compatible = "qcom,rpm-smd";
390 rpm-channel-name = "rpm_requests";
391 rpm-channel-type = <15>; /* SMD_APPS_RPM */
Priyanka Mathur6e993c92013-03-20 11:17:27 -0700392 rpm-standalone;
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700393 };
394
Olav Haugan8340d932013-01-25 12:03:11 -0800395 qcom,msm-mem-hole {
396 compatible = "qcom,msm-mem-hole";
Olav Hauganfcc860e2013-04-06 10:56:06 -0700397 qcom,memblock-remove = <0x07B00000 0x6400000>; /* Address and Size of Hole */
Olav Haugan8340d932013-01-25 12:03:11 -0800398 };
399
Hanumant Singh4e334c82012-11-14 10:16:39 -0800400 qcom,wdt@f9017000 {
401 compatible = "qcom,msm-watchdog";
402 reg = <0xf9017000 0x1000>;
403 interrupts = <0 3 0>, <0 4 0>;
404 qcom,bark-time = <11000>;
405 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800406 qcom,ipi-ping;
Jeff Hugo818d0f72012-11-05 14:19:28 -0700407 };
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700408
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800409 qcom,acpuclk@f9011050 {
410 compatible = "qcom,acpuclk-a7";
411 reg = <0xf9011050 0x8>;
412 reg-names = "rcg_base";
Patrick Dalyf9451d22013-03-20 14:20:12 -0700413 a7_cpu-supply = <&apc_vreg_corner>;
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800414 };
415
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700416 spmi_bus: qcom,spmi@fc4c0000 {
417 cell-index = <0>;
418 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700419 reg-names = "core", "intr", "cnfg";
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700420 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700421 <0Xfc4cb000 0x1000>,
422 <0Xfc4ca000 0x1000>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700423 /* 190,ee0_krait_hlos_spmi_periph_irq */
424 /* 187,channel_0_krait_hlos_trans_done_irq */
425 interrupts = <0 190 0>, <0 187 0>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700426 qcom,pmic-arb-ee = <0>;
427 qcom,pmic-arb-channel = <0>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700428 };
429
Gilad Avidovf84f2792013-01-31 13:26:39 -0700430 i2c@f9925000 { /* BLSP-1 QUP-3 */
431 cell-index = <0>;
432 compatible = "qcom,i2c-qup";
433 #address-cells = <1>;
434 #size-cells = <0>;
435 reg-names = "qup_phys_addr";
436 reg = <0xf9925000 0x1000>;
437 interrupt-names = "qup_err_intr";
438 interrupts = <0 97 0>;
439 qcom,i2c-bus-freq = <100000>;
440 };
441
Gilad Avidovf58f1832013-01-09 17:31:28 -0700442
443 spi_0: spi@f9923000 { /* BLSP1 QUP1 */
444 compatible = "qcom,spi-qup-v2";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 reg-names = "spi_physical", "spi_bam_physical";
448 reg = <0xf9923000 0x1000>,
449 <0xf9904000 0xF000>;
450 interrupt-names = "spi_irq", "spi_bam_irq";
451 interrupts = <0 95 0>, <0 238 0>;
452 spi-max-frequency = <19200000>;
453
454 gpios = <&msmgpio 3 0>, /* CLK */
455 <&msmgpio 1 0>, /* MISO */
456 <&msmgpio 0 0>; /* MOSI */
457 cs-gpios = <&msmgpio 2 0>;
458
459 qcom,infinite-mode = <0>;
460 qcom,use-bam;
461 qcom,ver-reg-exists;
462 qcom,bam-consumer-pipe-index = <12>;
463 qcom,bam-producer-pipe-index = <13>;
464 };
465
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800466 qcom,pronto@fb21b000 {
467 compatible = "qcom,pil-pronto";
468 reg = <0xfb21b000 0x3000>,
469 <0xfc401700 0x4>,
470 <0xfd485300 0xc>;
471 reg-names = "pmu_base", "clk_base", "halt_base";
472 interrupts = <0 149 1>;
473 vdd_pronto_pll-supply = <&pm8110_l10>;
474
475 qcom,firmware-name = "wcnss";
Sameer Thalappil7abeb222013-04-02 11:13:42 -0700476
Sameer Thalappil4ba86302013-04-05 17:36:54 -0700477 /* GPIO inputs from wcnss */
Sameer Thalappil7abeb222013-04-02 11:13:42 -0700478 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
Sameer Thalappil4ba86302013-04-05 17:36:54 -0700479 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
Sameer Thalappil7abeb222013-04-02 11:13:42 -0700480
481 /* GPIO output to wcnss */
482 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800483 };
484
Sameer Thalappil1b65cd02013-04-03 16:42:34 -0700485 qcom,iris-fm {
486 compatible = "qcom,iris_fm";
487 };
488
Fred Oh92b18a02013-01-22 13:29:41 -0800489 sound {
490 compatible = "qcom,msm8x10-audio-codec";
491 qcom,model = "msm8x10-snd-card";
492 };
493
494 qcom,msm-pcm {
495 compatible = "qcom,msm-pcm-dsp";
496 };
497
498 qcom,msm-pcm-routing {
499 compatible = "qcom,msm-pcm-routing";
500 };
501
502 qcom,msm-pcm-lpa {
503 compatible = "qcom,msm-pcm-lpa";
504 };
505
506 qcom,msm-compr-dsp {
507 compatible = "qcom,msm-compr-dsp";
508 };
509
510 qcom,msm-voip-dsp {
511 compatible = "qcom,msm-voip-dsp";
512 };
513
514 qcom,msm-pcm-voice {
515 compatible = "qcom,msm-pcm-voice";
516 };
517
518 qcom,msm-stub-codec {
519 compatible = "qcom,msm-stub-codec";
520 };
521
522 qcom,msm-dai-fe {
523 compatible = "qcom,msm-dai-fe";
524 };
525
526 qcom,msm-pcm-afe {
527 compatible = "qcom,msm-pcm-afe";
528 };
529
530 qcom,msm-dai-mi2s {
531 compatible = "qcom,msm-dai-mi2s";
532 qcom,msm-dai-q6-mi2s-prim {
533 compatible = "qcom,msm-dai-q6-mi2s";
534 qcom,msm-dai-q6-mi2s-dev-id = <0>;
535 qcom,msm-mi2s-rx-lines = <1>;
536 qcom,msm-mi2s-tx-lines = <0>;
537 };
538
539 qcom,msm-dai-q6-mi2s-sec {
540 compatible = "qcom,msm-dai-q6-mi2s";
541 qcom,msm-dai-q6-mi2s-dev-id = <1>;
542 qcom,msm-mi2s-rx-lines = <0>;
543 qcom,msm-mi2s-tx-lines = <3>;
544 };
545 };
546
547 qcom,msm-dai-q6 {
548 compatible = "qcom,msm-dai-q6";
549 qcom,msm-dai-q6-bt-sco-rx {
550 compatible = "qcom,msm-dai-q6-dev";
551 qcom,msm-dai-q6-dev-id = <12288>;
552 };
553
554 qcom,msm-dai-q6-bt-sco-tx {
555 compatible = "qcom,msm-dai-q6-dev";
556 qcom,msm-dai-q6-dev-id = <12289>;
557 };
558
559 qcom,msm-dai-q6-int-fm-rx {
560 compatible = "qcom,msm-dai-q6-dev";
561 qcom,msm-dai-q6-dev-id = <12292>;
562 };
563
564 qcom,msm-dai-q6-int-fm-tx {
565 compatible = "qcom,msm-dai-q6-dev";
566 qcom,msm-dai-q6-dev-id = <12293>;
567 };
568
569 qcom,msm-dai-q6-be-afe-pcm-rx {
570 compatible = "qcom,msm-dai-q6-dev";
571 qcom,msm-dai-q6-dev-id = <224>;
572 };
573
574 qcom,msm-dai-q6-be-afe-pcm-tx {
575 compatible = "qcom,msm-dai-q6-dev";
576 qcom,msm-dai-q6-dev-id = <225>;
577 };
578
579 qcom,msm-dai-q6-afe-proxy-rx {
580 compatible = "qcom,msm-dai-q6-dev";
581 qcom,msm-dai-q6-dev-id = <241>;
582 };
583
584 qcom,msm-dai-q6-afe-proxy-tx {
585 compatible = "qcom,msm-dai-q6-dev";
586 qcom,msm-dai-q6-dev-id = <240>;
587 };
588 };
589
590 qcom,msm-pcm-hostless {
591 compatible = "qcom,msm-pcm-hostless";
592 };
593
Sameer Thalappil3928fef2013-04-08 11:51:15 -0700594 qcom,wcnss-wlan@fb000000 {
595 compatible = "qcom,wcnss_wlan";
Sameer Thalappilb2b93672013-04-18 17:00:46 -0700596 reg = <0xfb000000 0x280000>,
597 <0xf9011008 0x04>;
598 reg-names = "wcnss_mmio", "wcnss_fiq";
Sameer Thalappil3928fef2013-04-08 11:51:15 -0700599 interrupts = <0 145 0>, <0 146 0>;
600 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
601
602 qcom,pronto-vddmx-supply = <&pm8110_l3>;
603 qcom,pronto-vddcx-supply = <&pm8110_s1>;
604 qcom,pronto-vddpx-supply = <&pm8110_l6>;
605 qcom,iris-vddxo-supply = <&pm8110_l10>;
606 qcom,iris-vddrfa-supply = <&pm8110_l5>;
607 qcom,iris-vddpa-supply = <&pm8110_l16>;
608 qcom,iris-vdddig-supply = <&pm8110_l5>;
609
610 gpios = <&msmgpio 23 0>, <&msmgpio 24 0>, <&msmgpio 25 0>, <&msmgpio 26 0>, <&msmgpio 27 0>;
611 qcom,has_pronto_hw;
612 };
613
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800614 qcom,mss@fc880000 {
615 compatible = "qcom,pil-q6v5-mss";
616 reg = <0xfc880000 0x100>,
617 <0xfd485000 0x400>,
618 <0xfc820000 0x020>,
619 <0xfc401680 0x004>,
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800620 <0xfd485194 0x4>;
621 reg-names = "qdsp6_base", "halt_base", "rmb_base",
Matt Wagantall724b2bb2013-03-18 14:54:06 -0700622 "restart_reg", "cxrail_bhs_reg";
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800623
624 interrupts = <0 24 1>;
625 vdd_mss-supply = <&pm8110_s1>;
626 vdd_cx-supply = <&pm8110_s1_corner>;
627 vdd_mx-supply = <&pm8110_l3>;
628 vdd_pll-supply = <&pm8110_l10>;
629 qcom,vdd_pll = <1800000>;
630 qcom,is-loadable;
631 qcom,firmware-name = "mba";
632 qcom,pil-self-auth;
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700633
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800634 /* GPIO inputs from mss */
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700635 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800636 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700637
638 /* GPIO output to mss */
639 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800640 };
641
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800642 qcom,lpass@fe200000 {
643 compatible = "qcom,pil-q6v5-lpass";
644 reg = <0xfe200000 0x00100>,
Matt Wagantall015b50af2013-03-05 18:51:16 -0800645 <0xfd485100 0x00010>,
646 <0xfc4016c0 0x00004>;
647 reg-names = "qdsp6_base", "halt_base", "restart_reg";
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800648 interrupts = <0 162 1>;
Matt Wagantall6c515982013-01-29 14:58:43 -0800649 vdd_cx-supply = <&pm8110_s1_corner>;
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800650 qcom,firmware-name = "adsp";
Ravishankar Sarawadi2e8ac7d2013-03-28 15:23:30 -0700651
Ravishankar Sarawadiab203a82013-04-09 18:46:11 -0700652 /* GPIO inputs from lpass */
Ravishankar Sarawadi2e8ac7d2013-03-28 15:23:30 -0700653 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
Ravishankar Sarawadiab203a82013-04-09 18:46:11 -0700654 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
Ravishankar Sarawadi2e8ac7d2013-03-28 15:23:30 -0700655
656 /* GPIO output to lpass */
657 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800658 };
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700659
660 tsens: tsens@fc4a8000 {
661 compatible = "qcom,msm-tsens";
662 reg = <0xfc4a8000 0x2000>,
663 <0xfc4b8000 0x1000>;
664 reg-names = "tsens_physical", "tsens_eeprom_physical";
665 interrupts = <0 184 0>;
666 qcom,sensors = <2>;
667 qcom,slope = <2901 2846>;
Siddartha Mohanadossb2f48982013-03-28 13:51:38 -0700668 qcom,calib-mode = "fuse_map3";
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700669 qcom,calibration-less-mode;
Siddartha Mohanadoss0ca83312013-03-14 11:43:18 -0700670 qcom,tsens-local-init;
Siddartha Mohanadoss921f1f02013-04-04 16:30:03 -0700671 qcom,sensor-id = <0 5>;
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700672 };
673
Jennifer Liuf588d3a2013-04-05 10:11:48 -0700674 qcom,msm-thermal {
675 compatible = "qcom,msm-thermal";
676 qcom,sensor-id = <0>;
677 qcom,poll-ms = <250>;
678 qcom,limit-temp = <60>;
679 qcom,temp-hysteresis = <10>;
680 qcom,freq-step = <2>;
681 };
Jeff Hugoae4ab9f62013-04-08 13:43:08 -0600682
683 qcom,ipc-spinlock@fd484000 {
684 compatible = "qcom,ipc-spinlock-sfpb";
685 reg = <0xfd484000 0x400>;
686 qcom,num-locks = <8>;
687 };
Jeff Hugode2822a2013-04-08 14:09:38 -0600688
689 qcom,bam_dmux@fc834000 {
690 compatible = "qcom,bam_dmux";
691 reg = <0xfc834000 0x7000>;
692 interrupts = <0 29 1>;
693 };
Hariprasad Dhalinarasimha3a3e4e32013-04-14 16:18:30 -0700694
695 qcom,qseecom@7B00000 {
696 compatible = "qcom,qseecom";
697 reg = <0x7B00000 0x500000>;
698 reg-names = "secapp-region";
699 qcom,disk-encrypt-pipe-pair = <2>;
700 qcom,hlos-ce-hw-instance = <0>;
701 qcom,qsee-ce-hw-instance = <0>;
702 qcom,msm-bus,name = "qseecom-noc";
703 qcom,msm-bus,num-cases = <4>;
704 qcom,msm-bus,active-only = <0>;
705 qcom,msm-bus,num-paths = <1>;
706 qcom,msm-bus,vectors-KBps =
707 <55 512 0 0>,
708 <55 512 3936000 393600>,
709 <55 512 3936000 393600>,
710 <55 512 3936000 393600>;
711 };
Aparna Dase7cab2e2013-04-16 16:54:47 -0700712
Hariprasad Dhalinarasimhac8e0f312013-04-13 17:18:50 -0700713 qcom,msm-rng@f9bff000 {
714 compatible = "qcom,msm-rng";
715 reg = <0xf9bff000 0x200>;
716 qcom,msm-rng-iface-clk;
717 };
718
Aparna Dase7cab2e2013-04-16 16:54:47 -0700719 jtag_mm0: jtagmm@fc34c000 {
720 compatible = "qcom,jtag-mm";
721 reg = <0xfc34c000 0x1000>,
722 <0xfc340000 0x1000>;
723 reg-names = "etm-base","debug-base";
724 };
725
726 jtag_mm1: jtagmm@fc34d000 {
727 compatible = "qcom,jtag-mm";
728 reg = <0xfc34d000 0x1000>,
729 <0xfc342000 0x1000>;
730 reg-names = "etm-base","debug-base";
731 };
732
733 jtag_mm2: jtagmm@fc34e000 {
734 compatible = "qcom,jtag-mm";
735 reg = <0xfc34e000 0x1000>,
736 <0xfc344000 0x1000>;
737 reg-names = "etm-base","debug-base";
738 };
739
740 jtag_mm3: jtagmm@fc34f000 {
741 compatible = "qcom,jtag-mm";
742 reg = <0xfc34f000 0x1000>,
743 <0xfc346000 0x1000>;
744 reg-names = "etm-base","debug-base";
745 };
Hariprasad Dhalinarasimha9d3638a2013-04-13 22:42:11 -0700746
747 qcom,tz-log@fe805720 {
748 compatible = "qcom,tz-log";
749 reg = <0x0fe805720 0x1000>;
750 };
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700751};
David Collinsc6b34832012-10-24 12:57:57 -0700752
Matt Wagantall1bf56932012-11-29 15:03:29 -0800753&gdsc_vfe {
754 status = "ok";
755};
756
757&gdsc_oxili_cx {
758 status = "ok";
759};
760
Olav Haugan9c255522012-11-16 16:43:17 -0800761&lpass_iommu {
762 status = "ok";
763};
764
765&copss_iommu {
766 status = "ok";
767};
768
769&mdpe_iommu {
770 status = "ok";
771};
772
773&mdps_iommu {
774 status = "ok";
775};
776
777&gfx_iommu {
778 status = "ok";
779};
780
781&vfe_iommu {
782 status = "ok";
783};
784
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800785/include/ "msm8610-iommu-domains.dtsi"
Olav Haugan4bc4b692012-12-10 18:29:35 -0800786
Xiaozhe Shi350baa92013-04-09 18:13:50 -0700787/include/ "msm-pm8110-rpm-regulator.dtsi"
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700788/include/ "msm-pm8110.dtsi"
Xiaozhe Shi1581a7b2013-02-21 15:17:57 -0800789/include/ "msm8610-regulator.dtsi"
Siddartha Mohanadoss0f664a82013-03-11 22:52:01 -0700790
791&pm8110_vadc {
792 chan@0 {
793 label = "usb_in";
794 reg = <0>;
795 qcom,decimation = <0>;
796 qcom,pre-div-channel-scaling = <4>;
797 qcom,calibration-type = "absolute";
798 qcom,scale-function = <0>;
799 qcom,hw-settle-time = <0>;
800 qcom,fast-avg-setup = <0>;
801 };
802
803 chan@2 {
804 label = "vchg_sns";
805 reg = <2>;
806 qcom,decimation = <0>;
807 qcom,pre-div-channel-scaling = <3>;
808 qcom,calibration-type = "absolute";
809 qcom,scale-function = <0>;
810 qcom,hw-settle-time = <0>;
811 qcom,fast-avg-setup = <0>;
812 };
813
814 chan@5 {
815 label = "vcoin";
816 reg = <5>;
817 qcom,decimation = <0>;
818 qcom,pre-div-channel-scaling = <1>;
819 qcom,calibration-type = "absolute";
820 qcom,scale-function = <0>;
821 qcom,hw-settle-time = <0>;
822 qcom,fast-avg-setup = <0>;
823 };
824
825 chan@6 {
826 label = "vbat_sns";
827 reg = <6>;
828 qcom,decimation = <0>;
829 qcom,pre-div-channel-scaling = <1>;
830 qcom,calibration-type = "absolute";
831 qcom,scale-function = <0>;
832 qcom,hw-settle-time = <0>;
833 qcom,fast-avg-setup = <0>;
834 };
835
836 chan@7 {
837 label = "vph_pwr";
838 reg = <7>;
839 qcom,decimation = <0>;
840 qcom,pre-div-channel-scaling = <1>;
841 qcom,calibration-type = "absolute";
842 qcom,scale-function = <0>;
843 qcom,hw-settle-time = <0>;
844 qcom,fast-avg-setup = <0>;
845 };
846
847 chan@30 {
848 label = "batt_therm";
849 reg = <0x30>;
850 qcom,decimation = <0>;
851 qcom,pre-div-channel-scaling = <0>;
852 qcom,calibration-type = "ratiometric";
853 qcom,scale-function = <1>;
854 qcom,hw-settle-time = <2>;
855 qcom,fast-avg-setup = <0>;
856 };
857
858 chan@31 {
859 label = "batt_id";
860 reg = <0x31>;
861 qcom,decimation = <0>;
862 qcom,pre-div-channel-scaling = <0>;
863 qcom,calibration-type = "ratiometric";
864 qcom,scale-function = <0>;
865 qcom,hw-settle-time = <2>;
866 qcom,fast-avg-setup = <0>;
867 };
868
869 chan@b2 {
870 label = "xo_therm_pu2";
871 reg = <0xb2>;
872 qcom,decimation = <0>;
873 qcom,pre-div-channel-scaling = <0>;
874 qcom,calibration-type = "ratiometric";
875 qcom,scale-function = <4>;
876 qcom,hw-settle-time = <2>;
877 qcom,fast-avg-setup = <0>;
878 };
879};
880
881