Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 19 | #include <iostream> |
| 20 | |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 21 | #include "logging.h" |
| 22 | #include "stringprintf.h" |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 23 | #include "thread.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 24 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 25 | namespace art { |
| 26 | namespace arm { |
| 27 | |
| 28 | DisassemblerArm::DisassemblerArm() { |
| 29 | } |
| 30 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 31 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 32 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 33 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 34 | DumpArm(os, cur); |
| 35 | } |
| 36 | } else { |
| 37 | // remove thumb specifier bits |
| 38 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 39 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 40 | for (const uint8_t* cur = begin; cur < end;) { |
| 41 | cur += DumpThumb16(os, cur); |
| 42 | } |
| 43 | } |
| 44 | } |
| 45 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 46 | static const char* kConditionCodeNames[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 47 | "eq", // 0000 - equal |
| 48 | "ne", // 0001 - not-equal |
| 49 | "cs", // 0010 - carry-set, greater than, equal or unordered |
| 50 | "cc", // 0011 - carry-clear, less than |
| 51 | "mi", // 0100 - minus, negative |
| 52 | "pl", // 0101 - plus, positive or zero |
| 53 | "vs", // 0110 - overflow |
| 54 | "vc", // 0111 - no overflow |
| 55 | "hi", // 1000 - unsigned higher |
| 56 | "ls", // 1001 - unsigned lower or same |
| 57 | "ge", // 1010 - signed greater than or equal |
| 58 | "lt", // 1011 - signed less than |
| 59 | "gt", // 1100 - signed greater than |
| 60 | "le", // 1101 - signed less than or equal |
| 61 | "", // 1110 - always |
| 62 | "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 66 | if (cond < 15) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 67 | os << kConditionCodeNames[cond]; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 68 | } else { |
| 69 | os << "Unexpected condition: " << cond; |
| 70 | } |
| 71 | } |
| 72 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 73 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
| 74 | os << imm32 << " (" << reinterpret_cast<const void*>(instr_ptr + imm32) << ")"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 78 | return ptr[0] | (ptr[1] << 8); |
| 79 | } |
| 80 | |
| 81 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 82 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 83 | } |
| 84 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 85 | static const char* kDataProcessingOperations[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 86 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
| 87 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 90 | static const char* kThumbDataProcessingOperations[] = { |
| 91 | "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", |
| 92 | "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", |
| 93 | }; |
| 94 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 95 | struct ArmRegister { |
| 96 | ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 97 | ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 98 | uint32_t r; |
| 99 | }; |
| 100 | std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { |
| 101 | if (r.r == 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 102 | os << "sp"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 103 | } else if (r.r == 14) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 104 | os << "lr"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 105 | } else if (r.r == 15) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 106 | os << "pc"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 107 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 108 | os << "r" << r.r; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 109 | } |
| 110 | return os; |
| 111 | } |
| 112 | |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 113 | struct ThumbRegister : ArmRegister { |
| 114 | ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 115 | }; |
| 116 | |
| 117 | struct Rm { |
| 118 | Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} |
| 119 | uint32_t shift; |
| 120 | ArmRegister rm; |
| 121 | }; |
| 122 | std::ostream& operator<<(std::ostream& os, const Rm& r) { |
| 123 | os << r.rm; |
| 124 | if (r.shift != 0) { |
| 125 | os << "-shift-" << r.shift; // TODO |
| 126 | } |
| 127 | return os; |
| 128 | } |
| 129 | |
| 130 | struct Imm12 { |
| 131 | Imm12(uint32_t instruction) : rotate((instruction >> 8) & 0xf), imm(instruction & 0xff) {} |
| 132 | uint32_t rotate; |
| 133 | uint32_t imm; |
| 134 | }; |
| 135 | std::ostream& operator<<(std::ostream& os, const Imm12& rhs) { |
| 136 | uint32_t imm = (rhs.imm >> (2 * rhs.rotate)) | (rhs.imm << (32 - (2 * rhs.rotate))); |
| 137 | os << "#" << imm; |
| 138 | return os; |
| 139 | } |
| 140 | |
| 141 | struct RegisterList { |
| 142 | RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} |
| 143 | uint32_t register_list; |
| 144 | }; |
| 145 | std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { |
| 146 | if (rhs.register_list == 0) { |
| 147 | os << "<no register list?>"; |
| 148 | return os; |
| 149 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 150 | os << "{"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 151 | bool first = true; |
| 152 | for (size_t i = 0; i < 16; i++) { |
| 153 | if ((rhs.register_list & (1 << i)) != 0) { |
| 154 | if (first) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 155 | first = false; |
| 156 | } else { |
| 157 | os << ", "; |
| 158 | } |
| 159 | os << ArmRegister(i); |
| 160 | } |
| 161 | } |
| 162 | os << "}"; |
| 163 | return os; |
| 164 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 165 | |
| 166 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 167 | uint32_t instruction = ReadU32(instr_ptr); |
| 168 | uint32_t cond = (instruction >> 28) & 0xf; |
| 169 | uint32_t op1 = (instruction >> 25) & 0x7; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 170 | std::ostringstream opcode; |
| 171 | std::ostringstream args; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 172 | switch (op1) { |
| 173 | case 0: |
| 174 | case 1: // Data processing instructions. |
| 175 | { |
| 176 | if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 177 | opcode << (((instruction >> 5) & 1) ? "blx" : "bx"); |
| 178 | args << ArmRegister(instruction & 0xf); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 179 | break; |
| 180 | } |
| 181 | bool i = (instruction & (1 << 25)) != 0; |
| 182 | bool s = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 183 | opcode << kDataProcessingOperations[(instruction >> 21) & 0xf] |
| 184 | << kConditionCodeNames[cond] |
| 185 | << (s ? "s" : ""); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 186 | args << ArmRegister(instruction, 12) << ", "; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 187 | if (i) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 188 | args << ArmRegister(instruction, 16) << ", " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 189 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 190 | args << Rm(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 191 | } |
| 192 | } |
| 193 | break; |
| 194 | case 2: // Load/store word and unsigned byte. |
| 195 | { |
| 196 | bool p = (instruction & (1 << 24)) != 0; |
| 197 | bool b = (instruction & (1 << 22)) != 0; |
| 198 | bool w = (instruction & (1 << 21)) != 0; |
| 199 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 200 | opcode << (l ? "ldr" : "str") << (b ? "b" : "") << kConditionCodeNames[cond]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 201 | args << ArmRegister(instruction, 12) << ", "; |
| 202 | ArmRegister rn(instruction, 16); |
| 203 | if (rn.r == 0xf) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 204 | UNIMPLEMENTED(FATAL) << "literals"; |
| 205 | } else { |
| 206 | bool wback = !p || w; |
| 207 | if (p && !wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 208 | args << "[" << rn << ", " << Imm12(instruction) << "]"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 209 | } else if (p && wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 210 | args << "[" << rn << ", " << Imm12(instruction) << "]!"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 211 | } else if (!p && wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 212 | args << "[" << rn << "], " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 213 | } else { |
| 214 | LOG(FATAL) << p << " " << w; |
| 215 | } |
| 216 | } |
| 217 | } |
| 218 | break; |
| 219 | case 4: // Load/store multiple. |
| 220 | { |
| 221 | bool p = (instruction & (1 << 24)) != 0; |
| 222 | bool u = (instruction & (1 << 23)) != 0; |
| 223 | bool w = (instruction & (1 << 21)) != 0; |
| 224 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 225 | opcode << (l ? "ldm" : "stm") |
| 226 | << (u ? 'i' : 'd') |
| 227 | << (p ? 'b' : 'a') |
| 228 | << kConditionCodeNames[cond]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 229 | args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 230 | } |
| 231 | break; |
| 232 | default: |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 233 | opcode << "???"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 234 | break; |
| 235 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 236 | // TODO: a more complete ARM disassembler could generate wider opcodes. |
| 237 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instruction, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 241 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 242 | // |111|1 1|1000000|0000|1111110000000000| |
| 243 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 244 | // |---|---|-------|----|----------------| |
| 245 | // |332|2 2|2222222|1111|1111110000000000| |
| 246 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 247 | // |---|---|-------|----|----------------| |
| 248 | // |111|op1| op2 | | | |
| 249 | uint32_t op1 = (instr >> 27) & 3; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 250 | if (op1 == 0) { |
| 251 | return DumpThumb16(os, instr_ptr); |
| 252 | } |
| 253 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 254 | uint32_t op2 = (instr >> 20) & 0x7F; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 255 | std::ostringstream opcode; |
| 256 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 257 | switch (op1) { |
| 258 | case 0: |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 259 | break; |
| 260 | case 1: |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 261 | if ((op2 & 0x64) == 0) { // 00x x0xx |
| 262 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 263 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 264 | // |---|--|--|--|-|--|----|----------------| |
| 265 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 266 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 267 | // |---|--|--|--|-|--|----|----------------| |
| 268 | // |111|01|00|op|0|WL| Rn | | |
| 269 | // |111|01| op2 | | | |
| 270 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 271 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 272 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 273 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 274 | uint32_t op = (instr >> 23) & 3; |
| 275 | uint32_t W = (instr >> 21) & 1; |
| 276 | uint32_t L = (instr >> 20) & 1; |
| 277 | ArmRegister Rn(instr, 16); |
| 278 | if (op == 1 || op == 2) { |
| 279 | if (op == 1) { |
| 280 | if (L == 0) { |
| 281 | opcode << "stm"; |
| 282 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 283 | } else { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 284 | if (Rn.r != 13) { |
| 285 | opcode << "ldm"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 286 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 287 | } else { |
| 288 | opcode << "pop"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 289 | } |
| 290 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 291 | } else { |
| 292 | if (L == 0) { |
| 293 | if (Rn.r != 13) { |
| 294 | opcode << "stmdb"; |
| 295 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 296 | } else { |
| 297 | opcode << "push"; |
| 298 | } |
| 299 | } else { |
| 300 | opcode << "ldmdb"; |
| 301 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 302 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 303 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 304 | args << RegisterList(instr); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 305 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 306 | } else if ((op2 & 0x60) == 0x20) { // 01x xxxx |
| 307 | // Data-processing (shifted register) |
| 308 | // |111|1110|0000|0|0000|1111|1100|0000|0000| |
| 309 | // |5 3|2109|8765|4|3 0|5 |10 8|7 5 |3 0| |
| 310 | // |---|----|----|-|----|----|----|----|----| |
| 311 | // |332|2222|2222|2|1111|1111|1100|0000|0000| |
| 312 | // |1 9|8765|4321|0|9 6|5 |10 8|7 5 |3 0| |
| 313 | // |---|----|----|-|----|----|----|----|----| |
| 314 | // |111|0101| op3|S| Rn | | Rd | | Rm | |
| 315 | uint32_t op3 = (instr >> 21) & 0xF; |
| 316 | uint32_t S = (instr >> 20) & 1; |
| 317 | uint32_t Rn = (instr >> 16) & 0xF; |
| 318 | ArmRegister Rd(instr, 8); |
| 319 | ArmRegister Rm(instr, 0); |
| 320 | switch (op3) { |
| 321 | case 0x0: |
| 322 | if (Rn != 0xF) { |
| 323 | opcode << "and"; |
| 324 | } else { |
| 325 | opcode << "tst"; |
| 326 | S = 0; // don't print 's' |
| 327 | } |
| 328 | break; |
| 329 | case 0x1: opcode << "bic"; break; |
| 330 | case 0x2: |
| 331 | if (Rn != 0xF) { |
| 332 | opcode << "orr"; |
| 333 | } else { |
| 334 | opcode << "mov"; |
| 335 | } |
| 336 | break; |
| 337 | case 0x3: |
| 338 | if (Rn != 0xF) { |
| 339 | opcode << "orn"; |
| 340 | } else { |
| 341 | opcode << "mvn"; |
| 342 | } |
| 343 | break; |
| 344 | case 0x4: |
| 345 | if (Rn != 0xF) { |
| 346 | opcode << "eor"; |
| 347 | } else { |
| 348 | opcode << "teq"; |
| 349 | S = 0; // don't print 's' |
| 350 | } |
| 351 | break; |
| 352 | case 0x6: opcode << "pkh"; break; |
| 353 | case 0x8: |
| 354 | if (Rn != 0xF) { |
| 355 | opcode << "add"; |
| 356 | } else { |
| 357 | opcode << "cmn"; |
| 358 | S = 0; // don't print 's' |
| 359 | } |
| 360 | break; |
| 361 | case 0xA: opcode << "adc"; break; |
| 362 | case 0xB: opcode << "sbc"; break; |
| 363 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 364 | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 365 | if (S == 1) { |
| 366 | opcode << "s"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 367 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 368 | opcode << ".w"; |
| 369 | args << Rd << ", " << Rm; |
| 370 | } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx |
| 371 | // Co-processor instructions |
| 372 | // |111|1|11|000000|0000|1111|1100|000|0 |0000| |
| 373 | // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0| |
| 374 | // |---|-|--|------|----|----|----|---|---|----| |
| 375 | // |332|2|22|222222|1111|1111|1100|000|0 |0000| |
| 376 | // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0| |
| 377 | // |---|-|--|------|----|----|----|---|---|----| |
| 378 | // |111| |11| op3 | Rn | |copr| |op4| | |
| 379 | uint32_t op3 = (instr >> 20) & 0x3F; |
| 380 | uint32_t coproc = (instr >> 8) & 0xF; |
| 381 | uint32_t op4 = (instr >> 4) & 0x1; |
| 382 | if ((op3 & 0x30) == 0x20 && op4 == 0) { // 10 xxxx ... 0 |
| 383 | if ((coproc & 0xE) == 0xA) { |
| 384 | // VFP data-processing instructions |
| 385 | // |111|1|1100|0000|0000|1111|110|0|00 |0|0|0000| |
| 386 | // |5 3|2|1098|7654|3 0|54 2|10 |8|76 |5|4|3 0| |
| 387 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 388 | // |332|2|2222|2222|1111|1111|110|0|00 |0|0|0000| |
| 389 | // |1 9|8|7654|3210|9 6|54 2|109|8|76 |5|4|3 0| |
| 390 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 391 | // |111|T|1110|opc1|opc2| |101| |opc3| | | | |
| 392 | // 111 0 1110|1111 0100 1110 101 0 01 1 0 1001 - eef4ea69 |
| 393 | uint32_t opc1 = (instr >> 20) & 0xF; |
| 394 | uint32_t opc2 = (instr >> 16) & 0xF; |
| 395 | //uint32_t opc3 = (instr >> 6) & 0x3; |
| 396 | if ((opc1 & 0xB) == 0xB) { // 1x11 |
| 397 | // Other VFP data-processing instructions. |
| 398 | switch (opc2) { |
| 399 | case 0x4: case 0x5: { // Vector compare |
| 400 | // 1110 11101 D 11 0100 dddd 101 sE1M0 mmmm |
| 401 | uint32_t D = (instr >> 22) & 0x1; |
| 402 | uint32_t Vd = (instr >> 12) & 0xF; |
| 403 | uint32_t sz = (instr >> 8) & 1; |
| 404 | uint32_t E = (instr >> 7) & 1; |
| 405 | uint32_t M = (instr >> 5) & 1; |
| 406 | uint32_t Vm = instr & 0xF; |
| 407 | bool dp_operation = sz == 1; |
| 408 | opcode << (E == 0 ? "vcmp" : "vcmpe"); |
| 409 | opcode << (dp_operation ? ".f64" : ".f32"); |
| 410 | if (dp_operation) { |
| 411 | args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm); |
| 412 | } else { |
| 413 | args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M); |
| 414 | } |
| 415 | break; |
| 416 | } |
| 417 | } |
| 418 | } |
| 419 | } |
| 420 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 421 | } |
| 422 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 423 | case 2: |
| 424 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 425 | // Data-processing (modified immediate) |
| 426 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 427 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 428 | // |---|--|--|----|-|----|-|---|----|--------| |
| 429 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 430 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 431 | // |---|--|--|----|-|----|-|---|----|--------| |
| 432 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 433 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 434 | uint32_t i = (instr >> 26) & 1; |
| 435 | uint32_t op3 = (instr >> 21) & 0xF; |
| 436 | uint32_t S = (instr >> 20) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 437 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 438 | uint32_t imm3 = (instr >> 12) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 439 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 440 | uint32_t imm8 = instr & 0xFF; |
| 441 | int32_t imm32 = (i << 12) | (imm3 << 8) | imm8; |
| 442 | switch (op3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 443 | case 0x0: opcode << "and"; break; |
| 444 | case 0x1: opcode << "bic"; break; |
| 445 | case 0x2: opcode << "orr"; break; |
| 446 | case 0x3: opcode << "orn"; break; |
| 447 | case 0x4: opcode << "eor"; break; |
| 448 | case 0x8: opcode << "add"; break; |
| 449 | case 0xA: opcode << "adc"; break; |
| 450 | case 0xB: opcode << "sbc"; break; |
| 451 | case 0xD: opcode << "sub"; break; |
| 452 | case 0xE: opcode << "rsb"; break; |
| 453 | default: opcode << "UNKNOWN DPMI-" << op3; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 454 | } |
| 455 | if (S == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 456 | opcode << "s"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 457 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 458 | args << Rd << ", " << Rn << ", ThumbExpand(" << imm32 << ")"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 459 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 460 | // Data-processing (plain binary immediate) |
| 461 | // |111|11|10|00000|0000|1|111110000000000| |
| 462 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 463 | // |---|--|--|-----|----|-|---------------| |
| 464 | // |332|22|22|22222|1111|1|111110000000000| |
| 465 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 466 | // |---|--|--|-----|----|-|---------------| |
| 467 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 468 | uint32_t op3 = (instr >> 20) & 0x1F; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 469 | switch (op3) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 470 | case 0x00: { |
| 471 | ArmRegister Rd(instr, 8); |
| 472 | ArmRegister Rn(instr, 16); |
| 473 | uint32_t i = (instr >> 26) & 1; |
| 474 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 475 | uint32_t imm8 = instr & 0xFF; |
| 476 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
| 477 | if (Rn.r != 0xF) { |
| 478 | opcode << "addw"; |
| 479 | args << Rd << ", " << Rn << ", #" << imm12; |
| 480 | } else { |
| 481 | opcode << "adr"; |
| 482 | args << Rd << ", "; |
| 483 | DumpBranchTarget(args, instr_ptr + 4, imm12); |
| 484 | } |
| 485 | break; |
| 486 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 487 | case 0x04: { |
| 488 | // MOVW Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 489 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 490 | uint32_t i = (instr >> 26) & 1; |
| 491 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 492 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 493 | uint32_t Rn = (instr >> 16) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 494 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 495 | opcode << "movw"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 496 | args << Rd << ", #" << imm16; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 497 | break; |
| 498 | } |
| 499 | case 0x0A: { |
| 500 | // SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 501 | ArmRegister Rd(instr, 8); |
| 502 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 503 | uint32_t i = (instr >> 26) & 1; |
| 504 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 505 | uint32_t imm8 = instr & 0xFF; |
| 506 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 507 | opcode << "sub.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 508 | args << Rd << ", " << Rn << ", #" << imm12; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 509 | break; |
| 510 | } |
| 511 | default: |
| 512 | break; |
| 513 | } |
| 514 | } else { |
| 515 | // Branches and miscellaneous control |
| 516 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 517 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 518 | // |---|--|-------|----|-|---|----|--------| |
| 519 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 520 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 521 | // |---|--|-------|----|-|---|----|--------| |
| 522 | // |111|10| op2 | |1|op3|op4 | | |
| 523 | |
| 524 | uint32_t op3 = (instr >> 12) & 7; |
| 525 | //uint32_t op4 = (instr >> 8) & 0xF; |
| 526 | switch (op3) { |
| 527 | case 0: |
| 528 | if ((op2 & 0x38) != 0x38) { |
| 529 | // Conditional branch |
| 530 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 531 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 532 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 533 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 534 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 535 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 536 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 537 | uint32_t S = (instr >> 26) & 1; |
| 538 | uint32_t J2 = (instr >> 11) & 1; |
| 539 | uint32_t J1 = (instr >> 13) & 1; |
| 540 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 541 | uint32_t imm11 = instr & 0x7FF; |
| 542 | uint32_t cond = (instr >> 22) & 0xF; |
| 543 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 544 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 545 | opcode << "b"; |
| 546 | DumpCond(opcode, cond); |
| 547 | opcode << ".w"; |
| 548 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 549 | } |
| 550 | break; |
| 551 | case 2: |
| 552 | case 1: case 3: |
| 553 | break; |
| 554 | case 4: case 6: case 5: case 7: { |
| 555 | // BL, BLX (immediate) |
| 556 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 557 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 558 | // |---|--|-|----------|--|--|-|--|-----------| |
| 559 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 560 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 561 | // |---|--|-|----------|--|--|-|--|-----------| |
| 562 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 563 | uint32_t S = (instr >> 26) & 1; |
| 564 | uint32_t J2 = (instr >> 11) & 1; |
| 565 | uint32_t L = (instr >> 12) & 1; |
| 566 | uint32_t J1 = (instr >> 13) & 1; |
| 567 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 568 | uint32_t imm11 = instr & 0x7FF; |
| 569 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 570 | opcode << "bx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 571 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 572 | opcode << "blx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 573 | } |
| 574 | uint32_t I1 = ~(J1 ^ S); |
| 575 | uint32_t I2 = ~(J2 ^ S); |
| 576 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 577 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 578 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 579 | break; |
| 580 | } |
| 581 | } |
| 582 | } |
| 583 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 584 | case 3: |
| 585 | switch (op2) { |
| 586 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 587 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 588 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 589 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 590 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 591 | // |---|--|---|---|-|----|----|------|------| |
| 592 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 593 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 594 | // |---|--|---|---|-|----|----|------|------| |
| 595 | // |111|11|000|op3|0| | | op4 | | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 596 | uint32_t op3 = (instr >> 21) & 7; |
| 597 | //uint32_t op4 = (instr >> 6) & 0x3F; |
| 598 | switch (op3) { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 599 | case 0x0: case 0x4: { |
| 600 | // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii |
| 601 | // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 602 | ArmRegister Rn(instr, 16); |
| 603 | ArmRegister Rt(instr, 12); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 604 | opcode << "strb"; |
| 605 | if ((instr & 0x800) != 0) { |
| 606 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 607 | args << Rt << ", [" << Rn << ",#" << imm8 << "]"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 608 | } else { |
| 609 | uint32_t imm2 = (instr >> 4) & 3; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 610 | ArmRegister Rm(instr, 0); |
| 611 | args << Rt << ", [" << Rn << ", " << Rm; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 612 | if (imm2 != 0) { |
| 613 | args << ", " << "lsl #" << imm2; |
| 614 | } |
| 615 | args << "]"; |
| 616 | } |
| 617 | break; |
| 618 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 619 | case 0x2: case 0x6: { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 620 | ArmRegister Rn(instr, 16); |
| 621 | ArmRegister Rt(instr, 12); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 622 | if (op3 == 2) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 623 | if ((instr & 0x800) != 0) { |
| 624 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
| 625 | uint32_t P = (instr >> 10) & 1; |
| 626 | uint32_t U = (instr >> 9) & 1; |
| 627 | uint32_t W = (instr >> 8) & 1; |
| 628 | uint32_t imm8 = instr & 0xFF; |
| 629 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
| 630 | if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) { |
| 631 | opcode << "push"; |
| 632 | args << Rt; |
| 633 | } else if (Rn.r == 15 || (P == 0 && W == 0)) { |
| 634 | opcode << "UNDEFINED"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 635 | } else { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 636 | if (P == 1 && U == 1 && W == 0) { |
| 637 | opcode << "strt"; |
| 638 | } else { |
| 639 | opcode << "str"; |
| 640 | } |
| 641 | args << Rt << ", [" << Rn; |
| 642 | if (P == 0 && W == 1) { |
| 643 | args << "], #" << imm32; |
| 644 | } else { |
| 645 | args << ", #" << imm32 << "]"; |
| 646 | if (W == 1) { |
| 647 | args << "!"; |
| 648 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 649 | } |
| 650 | } |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 651 | } else { |
| 652 | // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm |
| 653 | ArmRegister Rn(instr, 16); |
| 654 | ArmRegister Rt(instr, 12); |
| 655 | ArmRegister Rm(instr, 0); |
| 656 | uint32_t imm2 = (instr >> 4) & 3; |
| 657 | opcode << "str.w"; |
| 658 | args << Rt << ", [" << Rn << ", " << Rm; |
| 659 | if (imm2 != 0) { |
| 660 | args << ", lsl #" << imm2; |
| 661 | } |
| 662 | args << "]"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 663 | } |
| 664 | } else if (op3 == 6) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 665 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 666 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 667 | opcode << "str.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 668 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 669 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 670 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 671 | } |
| 672 | } |
| 673 | |
| 674 | break; |
| 675 | } |
| 676 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
| 677 | // Load word |
| 678 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 679 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 680 | // |---|--|--|---|--|-|----|----|------|------| |
| 681 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 682 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 683 | // |---|--|--|---|--|-|----|----|------|------| |
| 684 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 685 | // |111|11| op2 | | | imm12 | |
| 686 | uint32_t op3 = (instr >> 23) & 3; |
| 687 | uint32_t op4 = (instr >> 6) & 0x3F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 688 | ArmRegister Rn(instr, 16); |
| 689 | ArmRegister Rt(instr, 12); |
| 690 | if (op3 == 1 || Rn.r == 15) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 691 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 692 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 693 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 694 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 695 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 696 | if (Rn.r == 9) { |
| 697 | args << " ; "; |
| 698 | Thread::DumpThreadOffset(args, imm12, 4); |
Ian Rogers | 5b9b1bc | 2012-04-09 22:51:43 -0700 | [diff] [blame] | 699 | } else if (Rn.r == 15) { |
| 700 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 701 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 702 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 703 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 704 | } else if (op4 == 0) { |
| 705 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 706 | uint32_t imm2 = (instr >> 4) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 707 | ArmRegister rm(instr, 0); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 708 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 709 | args << Rt << ", [" << Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 710 | if (imm2 != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 711 | args << ", lsl #" << imm2; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 712 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 713 | args << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 714 | } else { |
| 715 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 716 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 717 | opcode << "ldrt"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 718 | args << Rt << ", [" << Rn << ", #" << imm8 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 719 | } |
| 720 | break; |
| 721 | } |
| 722 | } |
| 723 | default: |
| 724 | break; |
| 725 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 726 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 727 | return 4; |
| 728 | } |
| 729 | |
| 730 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 731 | uint16_t instr = ReadU16(instr_ptr); |
| 732 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 733 | if (is_32bit) { |
| 734 | return DumpThumb32(os, instr_ptr); |
| 735 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 736 | std::ostringstream opcode; |
| 737 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 738 | uint16_t opcode1 = instr >> 10; |
| 739 | if (opcode1 < 0x10) { |
| 740 | // shift (immediate), add, subtract, move, and compare |
| 741 | uint16_t opcode2 = instr >> 9; |
| 742 | switch (opcode2) { |
| 743 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 744 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 745 | // Logical shift left - 00 000xx xxxxxxxxx |
| 746 | // Logical shift right - 00 001xx xxxxxxxxx |
| 747 | // Arithmetic shift right - 00 010xx xxxxxxxxx |
| 748 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 749 | ThumbRegister rm(instr, 3); |
| 750 | ThumbRegister Rd(instr, 7); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 751 | if (opcode2 <= 3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 752 | opcode << "lsls"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 753 | } else if (opcode2 <= 7) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 754 | opcode << "lsrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 755 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 756 | opcode << "asrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 757 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 758 | args << Rd << ", " << rm << ", #" << imm5; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 759 | break; |
| 760 | } |
| 761 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 762 | // Add register - 00 01100 mmm nnn ddd |
| 763 | // Sub register - 00 01101 mmm nnn ddd |
| 764 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 765 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 766 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 767 | ThumbRegister Rn(instr, 3); |
| 768 | ThumbRegister Rd(instr, 0); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 769 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 770 | opcode << "mov"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 771 | } else { |
| 772 | if ((opcode2 & 1) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 773 | opcode << "adds"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 774 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 775 | opcode << "subs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 776 | } |
| 777 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 778 | args << Rd << ", " << Rn; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 779 | if ((opcode2 & 2) == 0) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 780 | ArmRegister Rm(imm3_or_Rm); |
| 781 | args << ", " << Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 782 | } else if (imm3_or_Rm != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 783 | args << ", #" << imm3_or_Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 784 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 785 | break; |
| 786 | } |
| 787 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 788 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 789 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 790 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 791 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 792 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 793 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 794 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 795 | ThumbRegister Rn(instr, 8); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 796 | uint16_t imm8 = instr & 0xFF; |
| 797 | switch (opcode2 >> 2) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 798 | case 4: opcode << "movs"; break; |
| 799 | case 5: opcode << "cmp"; break; |
| 800 | case 6: opcode << "adds"; break; |
| 801 | case 7: opcode << "subs"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 802 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 803 | args << Rn << ", #" << imm8; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 804 | break; |
| 805 | } |
| 806 | default: |
| 807 | break; |
| 808 | } |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 809 | } else if (opcode1 == 0x10) { |
| 810 | // Data-processing |
| 811 | uint16_t opcode2 = (instr >> 6) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 812 | ThumbRegister rm(instr, 3); |
| 813 | ThumbRegister rdn(instr, 0); |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 814 | opcode << kThumbDataProcessingOperations[opcode2]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 815 | args << rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 816 | } else if (opcode1 == 0x11) { |
| 817 | // Special data instructions and branch and exchange |
| 818 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 819 | switch (opcode2) { |
| 820 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 821 | // Add low registers - 010001 0000 xxxxxx |
| 822 | // Add high registers - 010001 0001/001x xxxxxx |
| 823 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 824 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 825 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 826 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 827 | opcode << "add"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 828 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 829 | break; |
| 830 | } |
| 831 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 832 | // Move low registers - 010001 1000 xxxxxx |
| 833 | // Move high registers - 010001 1001/101x xxxxxx |
| 834 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 835 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 836 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 837 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 838 | opcode << "mov"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 839 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 840 | break; |
| 841 | } |
| 842 | case 0x5: case 0x6: case 0x7: { |
| 843 | // Compare high registers - 010001 0101/011x xxxxxx |
| 844 | uint16_t N = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 845 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 846 | uint16_t Rn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 847 | ArmRegister N_Rn((N << 3) | Rn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 848 | opcode << "cmp"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 849 | args << N_Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 850 | break; |
| 851 | } |
| 852 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 853 | // Branch and exchange - 010001 110x xxxxxx |
| 854 | // Branch with link and exchange - 010001 111x xxxxxx |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 855 | ArmRegister rm(instr, 3); |
| 856 | opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx"); |
| 857 | args << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 858 | break; |
| 859 | } |
| 860 | default: |
| 861 | break; |
| 862 | } |
| 863 | } else if ((instr & 0xF000) == 0xB000) { |
| 864 | // Miscellaneous 16-bit instructions |
| 865 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 866 | switch (opcode2) { |
| 867 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 868 | // Add immediate to SP - 1011 00000 ii iiiii |
| 869 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 870 | int imm7 = instr & 0x7F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 871 | opcode << ((opcode2 & 4) == 0 ? "add" : "sub"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 872 | args << "sp, sp, #" << (imm7 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 873 | break; |
| 874 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 875 | case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx |
| 876 | case 0x0C: case 0x0D: case 0x0E: case 0x0F: { |
| 877 | // CBNZ, CBZ |
| 878 | uint16_t op = (instr >> 11) & 1; |
| 879 | uint16_t i = (instr >> 9) & 1; |
| 880 | uint16_t imm5 = (instr >> 3) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 881 | ThumbRegister Rn(instr, 0); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 882 | opcode << (op != 0 ? "cbnz" : "cbz"); |
| 883 | uint32_t imm32 = (i << 7) | (imm5 << 1); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 884 | args << Rn << ", "; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 885 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
| 886 | break; |
| 887 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 888 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 889 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 890 | // If-Then, and hints |
| 891 | uint16_t opA = (instr >> 4) & 0xF; |
| 892 | uint16_t opB = instr & 0xF; |
| 893 | if (opB == 0) { |
| 894 | switch (opA) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 895 | case 0: opcode << "nop"; break; |
| 896 | case 1: opcode << "yield"; break; |
| 897 | case 2: opcode << "wfe"; break; |
| 898 | case 3: opcode << "sev"; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 899 | default: break; |
| 900 | } |
| 901 | } else { |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame^] | 902 | uint32_t first_cond = opA; |
| 903 | uint32_t mask = opB; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 904 | opcode << "it"; |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame^] | 905 | |
| 906 | // Flesh out the base "it" opcode with the specific collection of 't's and 'e's, |
| 907 | // and store up the actual condition codes we'll want to add to the next few opcodes. |
| 908 | size_t count = 3 - CTZ(mask); |
| 909 | it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself. |
| 910 | for (size_t i = 0; i < count; ++i) { |
| 911 | bool positive_cond = ((first_cond & 1) != 0); |
| 912 | bool positive_mask = ((mask & (1 << (3 - i))) != 0); |
| 913 | if (positive_mask == positive_cond) { |
| 914 | opcode << 't'; |
| 915 | it_conditions_[i] = kConditionCodeNames[first_cond]; |
| 916 | } else { |
| 917 | opcode << 'e'; |
| 918 | it_conditions_[i] = kConditionCodeNames[first_cond ^ 1]; |
| 919 | } |
| 920 | } |
| 921 | it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'. |
| 922 | |
| 923 | it_conditions_[count + 1] = ""; // No condition code for the IT itself... |
| 924 | DumpCond(args, first_cond); // ...because it's considered an argument. |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 925 | } |
| 926 | break; |
| 927 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 928 | default: |
| 929 | break; |
| 930 | } |
| 931 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 932 | ((instr & 0xE000) == 0x8000)) { |
| 933 | // Load/store single data item |
| 934 | uint16_t opA = instr >> 12; |
| 935 | //uint16_t opB = (instr >> 9) & 7; |
| 936 | switch (opA) { |
| 937 | case 0x6: { |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 938 | // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt |
| 939 | // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 940 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 941 | ThumbRegister Rn(instr, 3); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 942 | ThumbRegister Rt(instr, 0); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 943 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 944 | args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 945 | break; |
| 946 | } |
| 947 | case 0x9: { |
| 948 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 949 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 950 | uint16_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 951 | ThumbRegister Rt(instr, 8); |
| 952 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 953 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 954 | break; |
| 955 | } |
| 956 | default: |
| 957 | break; |
| 958 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 959 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 960 | uint16_t imm11 = instr & 0x7FFF; |
| 961 | int32_t imm32 = imm11 << 1; |
| 962 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 963 | opcode << "b"; |
| 964 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 965 | } |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame^] | 966 | |
| 967 | // Apply any IT-block conditions to the opcode if necessary. |
| 968 | if (!it_conditions_.empty()) { |
| 969 | opcode << it_conditions_.back(); |
| 970 | it_conditions_.pop_back(); |
| 971 | } |
| 972 | |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 973 | os << StringPrintf("\t\t\t%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 974 | } |
| 975 | return 2; |
| 976 | } |
| 977 | |
| 978 | } // namespace arm |
| 979 | } // namespace art |