Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/quick/mir_to_lir-inl.h" |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 19 | #include "dex/dataflow_iterator-inl.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 20 | #include "x86_lir.h" |
| 21 | |
| 22 | namespace art { |
| 23 | |
| 24 | /* This file contains codegen for the X86 ISA */ |
| 25 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 26 | LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | int opcode; |
| 28 | /* must be both DOUBLE or both not DOUBLE */ |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 29 | DCHECK(r_dest.IsFloat() || r_src.IsFloat()); |
| 30 | DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble()); |
| 31 | if (r_dest.IsDouble()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 32 | opcode = kX86MovsdRR; |
| 33 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 34 | if (r_dest.IsSingle()) { |
| 35 | if (r_src.IsSingle()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 36 | opcode = kX86MovssRR; |
| 37 | } else { // Fpr <- Gpr |
| 38 | opcode = kX86MovdxrRR; |
| 39 | } |
| 40 | } else { // Gpr <- Fpr |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 41 | DCHECK(r_src.IsSingle()) << "Raw: 0x" << std::hex << r_src.GetRawBits(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 42 | opcode = kX86MovdrxRR; |
| 43 | } |
| 44 | } |
| 45 | DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 46 | LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 47 | if (r_dest == r_src) { |
| 48 | res->flags.is_nop = true; |
| 49 | } |
| 50 | return res; |
| 51 | } |
| 52 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 53 | bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 54 | return true; |
| 55 | } |
| 56 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 57 | bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | return false; |
| 59 | } |
| 60 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 61 | bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 62 | return true; |
| 63 | } |
| 64 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 65 | bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 66 | return value == 0; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | /* |
| 70 | * Load a immediate using a shortcut if possible; otherwise |
| 71 | * grab from the per-translation literal pool. If target is |
| 72 | * a high register, build constant into a low register and copy. |
| 73 | * |
| 74 | * No additional register clobbering operation performed. Use this version when |
| 75 | * 1) r_dest is freshly returned from AllocTemp or |
| 76 | * 2) The codegen is under fixed register usage |
| 77 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 78 | LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { |
| 79 | RegStorage r_dest_save = r_dest; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 80 | if (r_dest.IsFloat()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 81 | if (value == 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 82 | return NewLIR2(kX86XorpsRR, r_dest.GetReg(), r_dest.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 83 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 84 | r_dest = AllocTemp(); |
| 85 | } |
| 86 | |
| 87 | LIR *res; |
| 88 | if (value == 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 89 | res = NewLIR2(kX86Xor32RR, r_dest.GetReg(), r_dest.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 90 | } else { |
| 91 | // Note, there is no byte immediate form of a 32 bit immediate move. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 92 | // 64-bit immediate is not supported by LIR structure |
| 93 | res = NewLIR2(kX86Mov32RI, r_dest.GetReg(), value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 94 | } |
| 95 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 96 | if (r_dest_save.IsFloat()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 97 | NewLIR2(kX86MovdxrRR, r_dest_save.GetReg(), r_dest.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 98 | FreeTemp(r_dest); |
| 99 | } |
| 100 | |
| 101 | return res; |
| 102 | } |
| 103 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 104 | LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 105 | LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 106 | res->target = target; |
| 107 | return res; |
| 108 | } |
| 109 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 110 | LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 111 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */, |
| 112 | X86ConditionEncoding(cc)); |
| 113 | branch->target = target; |
| 114 | return branch; |
| 115 | } |
| 116 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 117 | LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 118 | X86OpCode opcode = kX86Bkpt; |
| 119 | switch (op) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 120 | case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; |
| 121 | case kOpNot: opcode = r_dest_src.Is64Bit() ? kX86Not64R : kX86Not32R; break; |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 122 | case kOpRev: opcode = kX86Bswap32R; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 123 | case kOpBlx: opcode = kX86CallR; break; |
| 124 | default: |
| 125 | LOG(FATAL) << "Bad case in OpReg " << op; |
| 126 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 127 | return NewLIR1(opcode, r_dest_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 128 | } |
| 129 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 130 | LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 131 | X86OpCode opcode = kX86Bkpt; |
| 132 | bool byte_imm = IS_SIMM8(value); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 133 | DCHECK(!r_dest_src1.IsFloat()); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 134 | if (r_dest_src1.Is64Bit()) { |
| 135 | switch (op) { |
| 136 | case kOpAdd: opcode = byte_imm ? kX86Add64RI8 : kX86Add64RI; break; |
| 137 | case kOpSub: opcode = byte_imm ? kX86Sub64RI8 : kX86Sub64RI; break; |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 138 | case kOpLsl: opcode = kX86Sal64RI; break; |
| 139 | case kOpLsr: opcode = kX86Shr64RI; break; |
| 140 | case kOpAsr: opcode = kX86Sar64RI; break; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 141 | default: |
| 142 | LOG(FATAL) << "Bad case in OpRegImm (64-bit) " << op; |
| 143 | } |
| 144 | } else { |
| 145 | switch (op) { |
| 146 | case kOpLsl: opcode = kX86Sal32RI; break; |
| 147 | case kOpLsr: opcode = kX86Shr32RI; break; |
| 148 | case kOpAsr: opcode = kX86Sar32RI; break; |
| 149 | case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break; |
| 150 | case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break; |
| 151 | case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break; |
| 152 | // case kOpSbb: opcode = kX86Sbb32RI; break; |
| 153 | case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break; |
| 154 | case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break; |
| 155 | case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break; |
| 156 | case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break; |
| 157 | case kOpMov: |
| 158 | /* |
| 159 | * Moving the constant zero into register can be specialized as an xor of the register. |
| 160 | * However, that sets eflags while the move does not. For that reason here, always do |
| 161 | * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead. |
| 162 | */ |
| 163 | opcode = kX86Mov32RI; |
| 164 | break; |
| 165 | case kOpMul: |
| 166 | opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI; |
| 167 | return NewLIR3(opcode, r_dest_src1.GetReg(), r_dest_src1.GetReg(), value); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 168 | case kOp2Byte: |
| 169 | opcode = kX86Mov32RI; |
| 170 | value = static_cast<int8_t>(value); |
| 171 | break; |
| 172 | case kOp2Short: |
| 173 | opcode = kX86Mov32RI; |
| 174 | value = static_cast<int16_t>(value); |
| 175 | break; |
| 176 | case kOp2Char: |
| 177 | opcode = kX86Mov32RI; |
| 178 | value = static_cast<uint16_t>(value); |
| 179 | break; |
| 180 | case kOpNeg: |
| 181 | opcode = kX86Mov32RI; |
| 182 | value = -value; |
| 183 | break; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 184 | default: |
| 185 | LOG(FATAL) << "Bad case in OpRegImm " << op; |
| 186 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 187 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 188 | return NewLIR2(opcode, r_dest_src1.GetReg(), value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 189 | } |
| 190 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 191 | LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 192 | bool is64Bit = r_dest_src1.Is64Bit(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 193 | X86OpCode opcode = kX86Nop; |
| 194 | bool src2_must_be_cx = false; |
| 195 | switch (op) { |
| 196 | // X86 unary opcodes |
| 197 | case kOpMvn: |
| 198 | OpRegCopy(r_dest_src1, r_src2); |
| 199 | return OpReg(kOpNot, r_dest_src1); |
| 200 | case kOpNeg: |
| 201 | OpRegCopy(r_dest_src1, r_src2); |
| 202 | return OpReg(kOpNeg, r_dest_src1); |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 203 | case kOpRev: |
| 204 | OpRegCopy(r_dest_src1, r_src2); |
| 205 | return OpReg(kOpRev, r_dest_src1); |
| 206 | case kOpRevsh: |
| 207 | OpRegCopy(r_dest_src1, r_src2); |
| 208 | OpReg(kOpRev, r_dest_src1); |
| 209 | return OpRegImm(kOpAsr, r_dest_src1, 16); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 210 | // X86 binary opcodes |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 211 | case kOpSub: opcode = is64Bit ? kX86Sub64RR : kX86Sub32RR; break; |
| 212 | case kOpSbc: opcode = is64Bit ? kX86Sbb64RR : kX86Sbb32RR; break; |
| 213 | case kOpLsl: opcode = is64Bit ? kX86Sal64RC : kX86Sal32RC; src2_must_be_cx = true; break; |
| 214 | case kOpLsr: opcode = is64Bit ? kX86Shr64RC : kX86Shr32RC; src2_must_be_cx = true; break; |
| 215 | case kOpAsr: opcode = is64Bit ? kX86Sar64RC : kX86Sar32RC; src2_must_be_cx = true; break; |
| 216 | case kOpMov: opcode = is64Bit ? kX86Mov64RR : kX86Mov32RR; break; |
| 217 | case kOpCmp: opcode = is64Bit ? kX86Cmp64RR : kX86Cmp32RR; break; |
| 218 | case kOpAdd: opcode = is64Bit ? kX86Add64RR : kX86Add32RR; break; |
| 219 | case kOpAdc: opcode = is64Bit ? kX86Adc64RR : kX86Adc32RR; break; |
| 220 | case kOpAnd: opcode = is64Bit ? kX86And64RR : kX86And32RR; break; |
| 221 | case kOpOr: opcode = is64Bit ? kX86Or64RR : kX86Or32RR; break; |
| 222 | case kOpXor: opcode = is64Bit ? kX86Xor64RR : kX86Xor32RR; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 223 | case kOp2Byte: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 224 | // TODO: there are several instances of this check. A utility function perhaps? |
| 225 | // TODO: Similar to Arm's reg < 8 check. Perhaps add attribute checks to RegStorage? |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 226 | // Use shifts instead of a byte operand if the source can't be byte accessed. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 227 | if (r_src2.GetRegNum() >= rs_rX86_SP.GetRegNum()) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 228 | NewLIR2(is64Bit ? kX86Mov64RR : kX86Mov32RR, r_dest_src1.GetReg(), r_src2.GetReg()); |
| 229 | NewLIR2(is64Bit ? kX86Sal64RI : kX86Sal32RI, r_dest_src1.GetReg(), is64Bit ? 56 : 24); |
| 230 | return NewLIR2(is64Bit ? kX86Sar64RI : kX86Sar32RI, r_dest_src1.GetReg(), |
| 231 | is64Bit ? 56 : 24); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 232 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 233 | opcode = is64Bit ? kX86Bkpt : kX86Movsx8RR; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 234 | } |
| 235 | break; |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 236 | case kOp2Short: opcode = is64Bit ? kX86Bkpt : kX86Movsx16RR; break; |
| 237 | case kOp2Char: opcode = is64Bit ? kX86Bkpt : kX86Movzx16RR; break; |
| 238 | case kOpMul: opcode = is64Bit ? kX86Bkpt : kX86Imul32RR; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 239 | default: |
| 240 | LOG(FATAL) << "Bad case in OpRegReg " << op; |
| 241 | break; |
| 242 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 243 | CHECK(!src2_must_be_cx || r_src2.GetReg() == rs_rCX.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 244 | return NewLIR2(opcode, r_dest_src1.GetReg(), r_src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 245 | } |
| 246 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 247 | LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 248 | DCHECK(!r_base.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 249 | X86OpCode opcode = kX86Nop; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 250 | int dest = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 251 | switch (move_type) { |
| 252 | case kMov8GP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 253 | CHECK(!r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 254 | opcode = kX86Mov8RM; |
| 255 | break; |
| 256 | case kMov16GP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 257 | CHECK(!r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 258 | opcode = kX86Mov16RM; |
| 259 | break; |
| 260 | case kMov32GP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 261 | CHECK(!r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 262 | opcode = kX86Mov32RM; |
| 263 | break; |
| 264 | case kMov32FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 265 | CHECK(r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 266 | opcode = kX86MovssRM; |
| 267 | break; |
| 268 | case kMov64FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 269 | CHECK(r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 270 | opcode = kX86MovsdRM; |
| 271 | break; |
| 272 | case kMovU128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 273 | CHECK(r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 274 | opcode = kX86MovupsRM; |
| 275 | break; |
| 276 | case kMovA128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 277 | CHECK(r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 278 | opcode = kX86MovapsRM; |
| 279 | break; |
| 280 | case kMovLo128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 281 | CHECK(r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 282 | opcode = kX86MovlpsRM; |
| 283 | break; |
| 284 | case kMovHi128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 285 | CHECK(r_dest.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 286 | opcode = kX86MovhpsRM; |
| 287 | break; |
| 288 | case kMov64GP: |
| 289 | case kMovLo64FP: |
| 290 | case kMovHi64FP: |
| 291 | default: |
| 292 | LOG(FATAL) << "Bad case in OpMovRegMem"; |
| 293 | break; |
| 294 | } |
| 295 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 296 | return NewLIR3(opcode, dest, r_base.GetReg(), offset); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 297 | } |
| 298 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 299 | LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 300 | DCHECK(!r_base.IsFloat()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 301 | int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg(); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 302 | |
| 303 | X86OpCode opcode = kX86Nop; |
| 304 | switch (move_type) { |
| 305 | case kMov8GP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 306 | CHECK(!r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 307 | opcode = kX86Mov8MR; |
| 308 | break; |
| 309 | case kMov16GP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 310 | CHECK(!r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 311 | opcode = kX86Mov16MR; |
| 312 | break; |
| 313 | case kMov32GP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 314 | CHECK(!r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 315 | opcode = kX86Mov32MR; |
| 316 | break; |
| 317 | case kMov32FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 318 | CHECK(r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 319 | opcode = kX86MovssMR; |
| 320 | break; |
| 321 | case kMov64FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 322 | CHECK(r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 323 | opcode = kX86MovsdMR; |
| 324 | break; |
| 325 | case kMovU128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 326 | CHECK(r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 327 | opcode = kX86MovupsMR; |
| 328 | break; |
| 329 | case kMovA128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 330 | CHECK(r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 331 | opcode = kX86MovapsMR; |
| 332 | break; |
| 333 | case kMovLo128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 334 | CHECK(r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 335 | opcode = kX86MovlpsMR; |
| 336 | break; |
| 337 | case kMovHi128FP: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 338 | CHECK(r_src.IsFloat()); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 339 | opcode = kX86MovhpsMR; |
| 340 | break; |
| 341 | case kMov64GP: |
| 342 | case kMovLo64FP: |
| 343 | case kMovHi64FP: |
| 344 | default: |
| 345 | LOG(FATAL) << "Bad case in OpMovMemReg"; |
| 346 | break; |
| 347 | } |
| 348 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 349 | return NewLIR3(opcode, r_base.GetReg(), offset, src); |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 350 | } |
| 351 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 352 | LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 353 | // The only conditional reg to reg operation supported is Cmov |
| 354 | DCHECK_EQ(op, kOpCmov); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 355 | return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc)); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 356 | } |
| 357 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 358 | LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 359 | bool is64Bit = r_dest.Is64Bit(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 360 | X86OpCode opcode = kX86Nop; |
| 361 | switch (op) { |
| 362 | // X86 binary opcodes |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 363 | case kOpSub: opcode = is64Bit ? kX86Sub64RM : kX86Sub32RM; break; |
| 364 | case kOpMov: opcode = is64Bit ? kX86Mov64RM : kX86Mov32RM; break; |
| 365 | case kOpCmp: opcode = is64Bit ? kX86Cmp64RM : kX86Cmp32RM; break; |
| 366 | case kOpAdd: opcode = is64Bit ? kX86Add64RM : kX86Add32RM; break; |
| 367 | case kOpAnd: opcode = is64Bit ? kX86And64RM : kX86And32RM; break; |
| 368 | case kOpOr: opcode = is64Bit ? kX86Or64RM : kX86Or32RM; break; |
| 369 | case kOpXor: opcode = is64Bit ? kX86Xor64RM : kX86Xor32RM; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 370 | case kOp2Byte: opcode = kX86Movsx8RM; break; |
| 371 | case kOp2Short: opcode = kX86Movsx16RM; break; |
| 372 | case kOp2Char: opcode = kX86Movzx16RM; break; |
| 373 | case kOpMul: |
| 374 | default: |
| 375 | LOG(FATAL) << "Bad case in OpRegMem " << op; |
| 376 | break; |
| 377 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 378 | LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset); |
| 379 | if (r_base == rs_rX86_SP) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 380 | AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); |
| 381 | } |
| 382 | return l; |
| 383 | } |
| 384 | |
| 385 | LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { |
| 386 | DCHECK_NE(rl_dest.location, kLocPhysReg); |
| 387 | int displacement = SRegOffset(rl_dest.s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 388 | bool is64Bit = rl_dest.wide != 0; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 389 | X86OpCode opcode = kX86Nop; |
| 390 | switch (op) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 391 | case kOpSub: opcode = is64Bit ? kX86Sub64MR : kX86Sub32MR; break; |
| 392 | case kOpMov: opcode = is64Bit ? kX86Mov64MR : kX86Mov32MR; break; |
| 393 | case kOpCmp: opcode = is64Bit ? kX86Cmp64MR : kX86Cmp32MR; break; |
| 394 | case kOpAdd: opcode = is64Bit ? kX86Add64MR : kX86Add32MR; break; |
| 395 | case kOpAnd: opcode = is64Bit ? kX86And64MR : kX86And32MR; break; |
| 396 | case kOpOr: opcode = is64Bit ? kX86Or64MR : kX86Or32MR; break; |
| 397 | case kOpXor: opcode = is64Bit ? kX86Xor64MR : kX86Xor32MR; break; |
| 398 | case kOpLsl: opcode = is64Bit ? kX86Sal64MC : kX86Sal32MC; break; |
| 399 | case kOpLsr: opcode = is64Bit ? kX86Shr64MC : kX86Shr32MC; break; |
| 400 | case kOpAsr: opcode = is64Bit ? kX86Sar64MC : kX86Sar32MC; break; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 401 | default: |
| 402 | LOG(FATAL) << "Bad case in OpMemReg " << op; |
| 403 | break; |
| 404 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 405 | LIR *l = NewLIR3(opcode, rs_rX86_SP.GetReg(), displacement, r_value); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 406 | AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); |
| 407 | AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 408 | return l; |
| 409 | } |
| 410 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 411 | LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 412 | DCHECK_NE(rl_value.location, kLocPhysReg); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 413 | bool is64Bit = r_dest.Is64Bit(); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 414 | int displacement = SRegOffset(rl_value.s_reg_low); |
| 415 | X86OpCode opcode = kX86Nop; |
| 416 | switch (op) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 417 | case kOpSub: opcode = is64Bit ? kX86Sub64RM : kX86Sub32RM; break; |
| 418 | case kOpMov: opcode = is64Bit ? kX86Mov64RM : kX86Mov32RM; break; |
| 419 | case kOpCmp: opcode = is64Bit ? kX86Cmp64RM : kX86Cmp32RM; break; |
| 420 | case kOpAdd: opcode = is64Bit ? kX86Add64RM : kX86Add32RM; break; |
| 421 | case kOpAnd: opcode = is64Bit ? kX86And64RM : kX86And32RM; break; |
| 422 | case kOpOr: opcode = is64Bit ? kX86Or64RM : kX86Or32RM; break; |
| 423 | case kOpXor: opcode = is64Bit ? kX86Xor64RM : kX86Xor32RM; break; |
| 424 | case kOpMul: opcode = is64Bit ? kX86Bkpt : kX86Imul32RM; break; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 425 | default: |
| 426 | LOG(FATAL) << "Bad case in OpRegMem " << op; |
| 427 | break; |
| 428 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 429 | LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP.GetReg(), displacement); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 430 | AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 431 | return l; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 432 | } |
| 433 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 434 | LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, |
| 435 | RegStorage r_src2) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 436 | bool is64Bit = r_dest.Is64Bit(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 437 | if (r_dest != r_src1 && r_dest != r_src2) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 438 | if (op == kOpAdd) { // lea special case, except can't encode rbp as base |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 439 | if (r_src1 == r_src2) { |
| 440 | OpRegCopy(r_dest, r_src1); |
| 441 | return OpRegImm(kOpLsl, r_dest, 1); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 442 | } else if (r_src1 != rs_rBP) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 443 | return NewLIR5(is64Bit ? kX86Lea64RA : kX86Lea32RA, r_dest.GetReg(), |
| 444 | r_src1.GetReg() /* base */, r_src2.GetReg() /* index */, |
| 445 | 0 /* scale */, 0 /* disp */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 446 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 447 | return NewLIR5(is64Bit ? kX86Lea64RA : kX86Lea32RA, r_dest.GetReg(), |
| 448 | r_src2.GetReg() /* base */, r_src1.GetReg() /* index */, |
| 449 | 0 /* scale */, 0 /* disp */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 450 | } |
| 451 | } else { |
| 452 | OpRegCopy(r_dest, r_src1); |
| 453 | return OpRegReg(op, r_dest, r_src2); |
| 454 | } |
| 455 | } else if (r_dest == r_src1) { |
| 456 | return OpRegReg(op, r_dest, r_src2); |
| 457 | } else { // r_dest == r_src2 |
| 458 | switch (op) { |
| 459 | case kOpSub: // non-commutative |
| 460 | OpReg(kOpNeg, r_dest); |
| 461 | op = kOpAdd; |
| 462 | break; |
| 463 | case kOpSbc: |
| 464 | case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 465 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 466 | OpRegCopy(t_reg, r_src1); |
| 467 | OpRegReg(op, t_reg, r_src2); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 468 | LIR* res = OpRegCopyNoInsert(r_dest, t_reg); |
| 469 | AppendLIR(res); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 470 | FreeTemp(t_reg); |
| 471 | return res; |
| 472 | } |
| 473 | case kOpAdd: // commutative |
| 474 | case kOpOr: |
| 475 | case kOpAdc: |
| 476 | case kOpAnd: |
| 477 | case kOpXor: |
| 478 | break; |
| 479 | default: |
| 480 | LOG(FATAL) << "Bad case in OpRegRegReg " << op; |
| 481 | } |
| 482 | return OpRegReg(op, r_dest, r_src1); |
| 483 | } |
| 484 | } |
| 485 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 486 | LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 487 | if (op == kOpMul && !Gen64Bit()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 488 | X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 489 | return NewLIR3(opcode, r_dest.GetReg(), r_src.GetReg(), value); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 490 | } else if (op == kOpAnd && !Gen64Bit()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 491 | if (value == 0xFF && r_src.Low4()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 492 | return NewLIR2(kX86Movzx8RR, r_dest.GetReg(), r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 493 | } else if (value == 0xFFFF) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 494 | return NewLIR2(kX86Movzx16RR, r_dest.GetReg(), r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 495 | } |
| 496 | } |
| 497 | if (r_dest != r_src) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 498 | if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 499 | // TODO: fix bug in LEA encoding when disp == 0 |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 500 | return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r5sib_no_base /* base */, |
| 501 | r_src.GetReg() /* index */, value /* scale */, 0 /* disp */); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 502 | } else if (op == kOpAdd) { // lea add special case |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 503 | return NewLIR5(Gen64Bit() ? kX86Lea64RA : kX86Lea32RA, r_dest.GetReg(), |
| 504 | r_src.GetReg() /* base */, rs_rX86_SP.GetReg()/*r4sib_no_index*/ /* index */, |
| 505 | 0 /* scale */, value /* disp */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 506 | } |
| 507 | OpRegCopy(r_dest, r_src); |
| 508 | } |
| 509 | return OpRegImm(op, r_dest, value); |
| 510 | } |
| 511 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 512 | LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 513 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 514 | X86OpCode opcode = kX86Bkpt; |
| 515 | switch (op) { |
| 516 | case kOpBlx: opcode = kX86CallT; break; |
| 517 | case kOpBx: opcode = kX86JmpT; break; |
| 518 | default: |
| 519 | LOG(FATAL) << "Bad opcode: " << op; |
| 520 | break; |
| 521 | } |
| 522 | return NewLIR1(opcode, thread_offset.Int32Value()); |
| 523 | } |
| 524 | |
| 525 | LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) { |
| 526 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 527 | X86OpCode opcode = kX86Bkpt; |
| 528 | switch (op) { |
| 529 | case kOpBlx: opcode = kX86CallT; break; |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 530 | case kOpBx: opcode = kX86JmpT; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 531 | default: |
| 532 | LOG(FATAL) << "Bad opcode: " << op; |
| 533 | break; |
| 534 | } |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 535 | return NewLIR1(opcode, thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 536 | } |
| 537 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 538 | LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 539 | X86OpCode opcode = kX86Bkpt; |
| 540 | switch (op) { |
| 541 | case kOpBlx: opcode = kX86CallM; break; |
| 542 | default: |
| 543 | LOG(FATAL) << "Bad opcode: " << op; |
| 544 | break; |
| 545 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 546 | return NewLIR2(opcode, r_base.GetReg(), disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 547 | } |
| 548 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 549 | LIR* X86Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 550 | int32_t val_lo = Low32Bits(value); |
| 551 | int32_t val_hi = High32Bits(value); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 552 | int32_t low_reg_val = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 553 | LIR *res; |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 554 | bool is_fp = r_dest.IsFloat(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 555 | // TODO: clean this up once we fully recognize 64-bit storage containers. |
| 556 | if (is_fp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 557 | if (value == 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 558 | return NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 559 | } else if (base_of_code_ != nullptr) { |
| 560 | // We will load the value from the literal area. |
| 561 | LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); |
| 562 | if (data_target == NULL) { |
| 563 | data_target = AddWideData(&literal_list_, val_lo, val_hi); |
| 564 | } |
| 565 | |
| 566 | // Address the start of the method |
| 567 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 568 | if (rl_method.wide) { |
| 569 | rl_method = LoadValueWide(rl_method, kCoreReg); |
| 570 | } else { |
| 571 | rl_method = LoadValue(rl_method, kCoreReg); |
| 572 | } |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 573 | |
| 574 | // Load the proper value from the literal area. |
| 575 | // We don't know the proper offset for the value, so pick one that will force |
| 576 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 577 | // value. |
Mark Mendell | 0c52451 | 2014-05-27 15:52:21 -0400 | [diff] [blame] | 578 | res = LoadBaseDisp(rl_method.reg, 256 /* bogus */, RegStorage::FloatSolo64(low_reg_val), |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 579 | kDouble); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 580 | res->target = data_target; |
| 581 | res->flags.fixup = kFixupLoad; |
| 582 | SetMemRefType(res, true, kLiteral); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 583 | store_method_addr_used_ = true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 584 | } else { |
| 585 | if (val_lo == 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 586 | res = NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 587 | } else { |
Mark Mendell | d44f1a6 | 2014-06-03 16:05:37 -0400 | [diff] [blame] | 588 | res = LoadConstantNoClobber(RegStorage::FloatSolo32(low_reg_val), val_lo); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 589 | } |
| 590 | if (val_hi != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 591 | RegStorage r_dest_hi = AllocTempDouble(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 592 | LoadConstantNoClobber(r_dest_hi, val_hi); |
| 593 | NewLIR2(kX86PunpckldqRR, low_reg_val, r_dest_hi.GetReg()); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 594 | FreeTemp(r_dest_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 595 | } |
| 596 | } |
| 597 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 598 | if (r_dest.IsPair()) { |
| 599 | res = LoadConstantNoClobber(r_dest.GetLow(), val_lo); |
| 600 | LoadConstantNoClobber(r_dest.GetHigh(), val_hi); |
| 601 | } else { |
| 602 | // TODO(64) make int64_t value parameter of LoadConstantNoClobber |
| 603 | if (val_lo < 0) { |
| 604 | val_hi += 1; |
| 605 | } |
| 606 | res = LoadConstantNoClobber(RegStorage::Solo32(r_dest.GetReg()), val_hi); |
| 607 | NewLIR2(kX86Sal64RI, r_dest.GetReg(), 32); |
| 608 | if (val_lo != 0) { |
| 609 | NewLIR2(kX86Add64RI, r_dest.GetReg(), val_lo); |
| 610 | } |
| 611 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 612 | } |
| 613 | return res; |
| 614 | } |
| 615 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 616 | LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 617 | int displacement, RegStorage r_dest, OpSize size) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 618 | LIR *load = NULL; |
| 619 | LIR *load2 = NULL; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 620 | bool is_array = r_index.Valid(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 621 | bool pair = r_dest.IsPair(); |
| 622 | bool is64bit = ((size == k64) || (size == kDouble)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 623 | X86OpCode opcode = kX86Nop; |
| 624 | switch (size) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 625 | case k64: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 626 | case kDouble: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 627 | if (r_dest.IsFloat()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 628 | opcode = is_array ? kX86MovsdRA : kX86MovsdRM; |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 629 | } else if (!pair) { |
| 630 | opcode = is_array ? kX86Mov64RA : kX86Mov64RM; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 631 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 632 | opcode = is_array ? kX86Mov32RA : kX86Mov32RM; |
| 633 | } |
| 634 | // TODO: double store is to unaligned address |
| 635 | DCHECK_EQ((displacement & 0x3), 0); |
| 636 | break; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 637 | case kWord: |
| 638 | if (Gen64Bit()) { |
| 639 | opcode = is_array ? kX86Mov64RA : kX86Mov64RM; |
| 640 | CHECK_EQ(is_array, false); |
| 641 | CHECK_EQ(r_dest.IsFloat(), false); |
| 642 | break; |
| 643 | } // else fall-through to k32 case |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 644 | case k32: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 645 | case kSingle: |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 646 | case kReference: // TODO: update for reference decompression on 64-bit targets. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 647 | opcode = is_array ? kX86Mov32RA : kX86Mov32RM; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 648 | if (r_dest.IsFloat()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 649 | opcode = is_array ? kX86MovssRA : kX86MovssRM; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 650 | DCHECK(r_dest.IsFloat()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 651 | } |
| 652 | DCHECK_EQ((displacement & 0x3), 0); |
| 653 | break; |
| 654 | case kUnsignedHalf: |
| 655 | opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM; |
| 656 | DCHECK_EQ((displacement & 0x1), 0); |
| 657 | break; |
| 658 | case kSignedHalf: |
| 659 | opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM; |
| 660 | DCHECK_EQ((displacement & 0x1), 0); |
| 661 | break; |
| 662 | case kUnsignedByte: |
| 663 | opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM; |
| 664 | break; |
| 665 | case kSignedByte: |
| 666 | opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM; |
| 667 | break; |
| 668 | default: |
| 669 | LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; |
| 670 | } |
| 671 | |
| 672 | if (!is_array) { |
| 673 | if (!pair) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 674 | load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 675 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 676 | DCHECK(!r_dest.IsFloat()); // Make sure we're not still using a pair here. |
| 677 | if (r_base == r_dest.GetLow()) { |
| 678 | load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 679 | displacement + HIWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 680 | load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 681 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 682 | load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); |
| 683 | load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 684 | displacement + HIWORD_OFFSET); |
| 685 | } |
| 686 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 687 | if (r_base == rs_rX86_SP) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 688 | AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, |
| 689 | true /* is_load */, is64bit); |
| 690 | if (pair) { |
| 691 | AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, |
| 692 | true /* is_load */, is64bit); |
| 693 | } |
| 694 | } |
| 695 | } else { |
| 696 | if (!pair) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 697 | load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 698 | displacement + LOWORD_OFFSET); |
| 699 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 700 | DCHECK(!r_dest.IsFloat()); // Make sure we're not still using a pair here. |
| 701 | if (r_base == r_dest.GetLow()) { |
| 702 | if (r_dest.GetHigh() == r_index) { |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 703 | // We can't use either register for the first load. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 704 | RegStorage temp = AllocTemp(); |
| 705 | load2 = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 706 | displacement + HIWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 707 | load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 708 | displacement + LOWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 709 | OpRegCopy(r_dest.GetHigh(), temp); |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 710 | FreeTemp(temp); |
| 711 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 712 | load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 713 | displacement + HIWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 714 | load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 715 | displacement + LOWORD_OFFSET); |
| 716 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 717 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 718 | if (r_dest.GetLow() == r_index) { |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 719 | // We can't use either register for the first load. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 720 | RegStorage temp = AllocTemp(); |
| 721 | load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 722 | displacement + LOWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 723 | load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 724 | displacement + HIWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 725 | OpRegCopy(r_dest.GetLow(), temp); |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 726 | FreeTemp(temp); |
| 727 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 728 | load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 729 | displacement + LOWORD_OFFSET); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 730 | load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 731 | displacement + HIWORD_OFFSET); |
| 732 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 733 | } |
| 734 | } |
| 735 | } |
| 736 | |
| 737 | return load; |
| 738 | } |
| 739 | |
| 740 | /* Load value from base + scaled index. */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 741 | LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, |
| 742 | int scale, OpSize size) { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 743 | return LoadBaseIndexedDisp(r_base, r_index, scale, 0, r_dest, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 744 | } |
| 745 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 746 | LIR* X86Mir2Lir::LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, |
| 747 | OpSize size) { |
| 748 | // LoadBaseDisp() will emit correct insn for atomic load on x86 |
| 749 | // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). |
| 750 | return LoadBaseDisp(r_base, displacement, r_dest, size); |
| 751 | } |
| 752 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 753 | LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 754 | OpSize size) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 755 | return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_dest, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 756 | size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 757 | } |
| 758 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 759 | LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 760 | int displacement, RegStorage r_src, OpSize size) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 761 | LIR *store = NULL; |
| 762 | LIR *store2 = NULL; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 763 | bool is_array = r_index.Valid(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 764 | bool pair = r_src.IsPair(); |
| 765 | bool is64bit = (size == k64) || (size == kDouble); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 766 | X86OpCode opcode = kX86Nop; |
| 767 | switch (size) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 768 | case k64: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 769 | case kDouble: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 770 | if (r_src.IsFloat()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 771 | opcode = is_array ? kX86MovsdAR : kX86MovsdMR; |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 772 | } else if (!pair) { |
| 773 | opcode = is_array ? kX86Mov64AR : kX86Mov64MR; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 774 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 775 | opcode = is_array ? kX86Mov32AR : kX86Mov32MR; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 776 | } |
| 777 | // TODO: double store is to unaligned address |
| 778 | DCHECK_EQ((displacement & 0x3), 0); |
| 779 | break; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 780 | case kWord: |
| 781 | if (Gen64Bit()) { |
| 782 | opcode = is_array ? kX86Mov64AR : kX86Mov64MR; |
| 783 | CHECK_EQ(is_array, false); |
| 784 | CHECK_EQ(r_src.IsFloat(), false); |
| 785 | break; |
| 786 | } // else fall-through to k32 case |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 787 | case k32: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 788 | case kSingle: |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 789 | case kReference: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 790 | opcode = is_array ? kX86Mov32AR : kX86Mov32MR; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 791 | if (r_src.IsFloat()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 792 | opcode = is_array ? kX86MovssAR : kX86MovssMR; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 793 | DCHECK(r_src.IsSingle()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 794 | } |
| 795 | DCHECK_EQ((displacement & 0x3), 0); |
| 796 | break; |
| 797 | case kUnsignedHalf: |
| 798 | case kSignedHalf: |
| 799 | opcode = is_array ? kX86Mov16AR : kX86Mov16MR; |
| 800 | DCHECK_EQ((displacement & 0x1), 0); |
| 801 | break; |
| 802 | case kUnsignedByte: |
| 803 | case kSignedByte: |
| 804 | opcode = is_array ? kX86Mov8AR : kX86Mov8MR; |
| 805 | break; |
| 806 | default: |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 807 | LOG(FATAL) << "Bad case in StoreBaseIndexedDispBody"; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 808 | } |
| 809 | |
| 810 | if (!is_array) { |
| 811 | if (!pair) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 812 | store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 813 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 814 | DCHECK(!r_src.IsFloat()); // Make sure we're not still using a pair here. |
| 815 | store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetLowReg()); |
| 816 | store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 817 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 818 | if (r_base == rs_rX86_SP) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 819 | AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, |
| 820 | false /* is_load */, is64bit); |
| 821 | if (pair) { |
| 822 | AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, |
| 823 | false /* is_load */, is64bit); |
| 824 | } |
| 825 | } |
| 826 | } else { |
| 827 | if (!pair) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 828 | store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, |
| 829 | displacement + LOWORD_OFFSET, r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 830 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 831 | DCHECK(!r_src.IsFloat()); // Make sure we're not still using a pair here. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 832 | store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 833 | displacement + LOWORD_OFFSET, r_src.GetLowReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 834 | store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 835 | displacement + HIWORD_OFFSET, r_src.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 836 | } |
| 837 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 838 | return store; |
| 839 | } |
| 840 | |
| 841 | /* store value base base + scaled index. */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 842 | LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 843 | int scale, OpSize size) { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 844 | return StoreBaseIndexedDisp(r_base, r_index, scale, 0, r_src, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 845 | } |
| 846 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 847 | LIR* X86Mir2Lir::StoreBaseDispVolatile(RegStorage r_base, int displacement, |
| 848 | RegStorage r_src, OpSize size) { |
| 849 | // StoreBaseDisp() will emit correct insn for atomic store on x86 |
| 850 | // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). |
| 851 | return StoreBaseDisp(r_base, displacement, r_src, size); |
| 852 | } |
| 853 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 854 | LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, |
| 855 | RegStorage r_src, OpSize size) { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 856 | return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 857 | } |
| 858 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 859 | LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 860 | int offset, int check_value, LIR* target) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 861 | NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), offset, |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 862 | check_value); |
| 863 | LIR* branch = OpCondBranch(cond, target); |
| 864 | return branch; |
| 865 | } |
| 866 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 867 | void X86Mir2Lir::AnalyzeMIR() { |
| 868 | // Assume we don't need a pointer to the base of the code. |
| 869 | cu_->NewTimingSplit("X86 MIR Analysis"); |
| 870 | store_method_addr_ = false; |
| 871 | |
| 872 | // Walk the MIR looking for interesting items. |
| 873 | PreOrderDfsIterator iter(mir_graph_); |
| 874 | BasicBlock* curr_bb = iter.Next(); |
| 875 | while (curr_bb != NULL) { |
| 876 | AnalyzeBB(curr_bb); |
| 877 | curr_bb = iter.Next(); |
| 878 | } |
| 879 | |
| 880 | // Did we need a pointer to the method code? |
| 881 | if (store_method_addr_) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 882 | base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, Gen64Bit() == true); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 883 | } else { |
| 884 | base_of_code_ = nullptr; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) { |
| 889 | if (bb->block_type == kDead) { |
| 890 | // Ignore dead blocks |
| 891 | return; |
| 892 | } |
| 893 | |
| 894 | for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { |
| 895 | int opcode = mir->dalvikInsn.opcode; |
buzbee | 35ba7f3 | 2014-05-31 08:59:01 -0700 | [diff] [blame] | 896 | if (MIRGraph::IsPseudoMirOp(opcode)) { |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 897 | AnalyzeExtendedMIR(opcode, bb, mir); |
| 898 | } else { |
| 899 | AnalyzeMIR(opcode, bb, mir); |
| 900 | } |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | |
| 905 | void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) { |
| 906 | switch (opcode) { |
| 907 | // Instructions referencing doubles. |
| 908 | case kMirOpFusedCmplDouble: |
| 909 | case kMirOpFusedCmpgDouble: |
| 910 | AnalyzeFPInstruction(opcode, bb, mir); |
| 911 | break; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 912 | case kMirOpConstVector: |
| 913 | store_method_addr_ = true; |
| 914 | break; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 915 | default: |
| 916 | // Ignore the rest. |
| 917 | break; |
| 918 | } |
| 919 | } |
| 920 | |
| 921 | void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) { |
| 922 | // Looking for |
| 923 | // - Do we need a pointer to the code (used for packed switches and double lits)? |
| 924 | |
| 925 | switch (opcode) { |
| 926 | // Instructions referencing doubles. |
| 927 | case Instruction::CMPL_DOUBLE: |
| 928 | case Instruction::CMPG_DOUBLE: |
| 929 | case Instruction::NEG_DOUBLE: |
| 930 | case Instruction::ADD_DOUBLE: |
| 931 | case Instruction::SUB_DOUBLE: |
| 932 | case Instruction::MUL_DOUBLE: |
| 933 | case Instruction::DIV_DOUBLE: |
| 934 | case Instruction::REM_DOUBLE: |
| 935 | case Instruction::ADD_DOUBLE_2ADDR: |
| 936 | case Instruction::SUB_DOUBLE_2ADDR: |
| 937 | case Instruction::MUL_DOUBLE_2ADDR: |
| 938 | case Instruction::DIV_DOUBLE_2ADDR: |
| 939 | case Instruction::REM_DOUBLE_2ADDR: |
| 940 | AnalyzeFPInstruction(opcode, bb, mir); |
| 941 | break; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 942 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 943 | // Packed switches and array fills need a pointer to the base of the method. |
| 944 | case Instruction::FILL_ARRAY_DATA: |
| 945 | case Instruction::PACKED_SWITCH: |
| 946 | store_method_addr_ = true; |
| 947 | break; |
| 948 | default: |
| 949 | // Other instructions are not interesting yet. |
| 950 | break; |
| 951 | } |
| 952 | } |
| 953 | |
| 954 | void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) { |
| 955 | // Look at all the uses, and see if they are double constants. |
Jean Christophe Beyler | cc794c3 | 2014-05-02 09:34:13 -0700 | [diff] [blame] | 956 | uint64_t attrs = MIRGraph::GetDataFlowAttributes(static_cast<Instruction::Code>(opcode)); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 957 | int next_sreg = 0; |
| 958 | if (attrs & DF_UA) { |
| 959 | if (attrs & DF_A_WIDE) { |
| 960 | AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); |
| 961 | next_sreg += 2; |
| 962 | } else { |
| 963 | next_sreg++; |
| 964 | } |
| 965 | } |
| 966 | if (attrs & DF_UB) { |
| 967 | if (attrs & DF_B_WIDE) { |
| 968 | AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); |
| 969 | next_sreg += 2; |
| 970 | } else { |
| 971 | next_sreg++; |
| 972 | } |
| 973 | } |
| 974 | if (attrs & DF_UC) { |
| 975 | if (attrs & DF_C_WIDE) { |
| 976 | AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); |
| 977 | } |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) { |
| 982 | // If this is a double literal, we will want it in the literal pool. |
| 983 | if (use.is_const) { |
| 984 | store_method_addr_ = true; |
| 985 | } |
| 986 | } |
| 987 | |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 988 | RegLocation X86Mir2Lir::UpdateLocTyped(RegLocation loc, int reg_class) { |
| 989 | loc = UpdateLoc(loc); |
| 990 | if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) { |
| 991 | if (GetRegInfo(loc.reg)->IsTemp()) { |
| 992 | Clobber(loc.reg); |
| 993 | FreeTemp(loc.reg); |
| 994 | loc.reg = RegStorage::InvalidReg(); |
| 995 | loc.location = kLocDalvikFrame; |
| 996 | } |
| 997 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 998 | DCHECK(CheckCorePoolSanity()); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 999 | return loc; |
| 1000 | } |
| 1001 | |
| 1002 | RegLocation X86Mir2Lir::UpdateLocWideTyped(RegLocation loc, int reg_class) { |
| 1003 | loc = UpdateLocWide(loc); |
| 1004 | if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) { |
| 1005 | if (GetRegInfo(loc.reg)->IsTemp()) { |
| 1006 | Clobber(loc.reg); |
| 1007 | FreeTemp(loc.reg); |
| 1008 | loc.reg = RegStorage::InvalidReg(); |
| 1009 | loc.location = kLocDalvikFrame; |
| 1010 | } |
| 1011 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 1012 | DCHECK(CheckCorePoolSanity()); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1013 | return loc; |
| 1014 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1015 | } // namespace art |