blob: 2fed0dc337cf4c760ee2001b5b026d5c853d23b4 [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
115 [2] = "Reserved",
116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
132 [5 ... 7] = "reserved",
133};
134
135static char *transcoder_select[] = {
136 [0] = "Transcoder A",
137 [1] = "Transcoder B",
138 [2] = "Transcoder C",
139 [3] = "reserved",
140};
141
142static char *dp_port_width[] = {
143 [0] = "x1 mode",
144 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800145 [2] = "reserved",
146 [3] = "x4 mode",
147 [4 ... 7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800148};
149
Wu Fengguang12861a92011-11-12 11:12:47 +0800150static char *bits_per_sample[] = {
151 [0] = "reserved",
152 [1] = "16 bits",
153 [2] = "24 bits",
154 [3] = "32 bits",
155 [4] = "20 bits",
156 [5] = "reserved",
157};
158
159
Wu Fengguang020abdb2010-04-19 13:13:06 +0800160static void do_self_tests(void)
161{
162 if (BIT(1, 0) != 1)
163 exit(1);
164 if (BIT(0x80000000, 31) != 1)
165 exit(2);
166 if (BITS(0xc0000000, 31, 30) != 3)
167 exit(3);
168}
169
170/*
171 * EagleLake registers
172 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800173#define AUD_CONFIG 0x62000
174#define AUD_DEBUG 0x62010
175#define AUD_VID_DID 0x62020
176#define AUD_RID 0x62024
177#define AUD_SUBN_CNT 0x62028
178#define AUD_FUNC_GRP 0x62040
179#define AUD_SUBN_CNT2 0x62044
180#define AUD_GRP_CAP 0x62048
181#define AUD_PWRST 0x6204c
182#define AUD_SUPPWR 0x62050
183#define AUD_SID 0x62054
184#define AUD_OUT_CWCAP 0x62070
185#define AUD_OUT_PCMSIZE 0x62074
186#define AUD_OUT_STR 0x62078
187#define AUD_OUT_DIG_CNVT 0x6207c
188#define AUD_OUT_CH_STR 0x62080
189#define AUD_OUT_STR_DESC 0x62084
190#define AUD_PINW_CAP 0x620a0
191#define AUD_PIN_CAP 0x620a4
192#define AUD_PINW_CONNLNG 0x620a8
193#define AUD_PINW_CONNLST 0x620ac
194#define AUD_PINW_CNTR 0x620b0
195#define AUD_PINW_UNSOLRESP 0x620b8
196#define AUD_CNTL_ST 0x620b4
197#define AUD_PINW_CONFIG 0x620bc
198#define AUD_HDMIW_STATUS 0x620d4
199#define AUD_HDMIW_HDMIEDID 0x6210c
200#define AUD_HDMIW_INFOFR 0x62118
201#define AUD_CONV_CHCNT 0x62120
202#define AUD_CTS_ENABLE 0x62128
203
204#define VIDEO_DIP_CTL 0x61170
205#define VIDEO_DIP_ENABLE (1<<31)
206#define VIDEO_DIP_ENABLE_AVI (1<<21)
207#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
208#define VIDEO_DIP_ENABLE_SPD (1<<24)
209#define VIDEO_DIP_BUF_AVI (0<<19)
210#define VIDEO_DIP_BUF_VENDOR (1<<19)
211#define VIDEO_DIP_BUF_SPD (3<<19)
212#define VIDEO_DIP_TRANS_ONCE (0<<16)
213#define VIDEO_DIP_TRANS_1 (1<<16)
214#define VIDEO_DIP_TRANS_2 (2<<16)
215
216#define AUDIO_HOTPLUG_EN (1<<24)
217
218
Wu Fengguang020abdb2010-04-19 13:13:06 +0800219static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800220{
221 uint32_t dword;
222 int i;
223
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800224 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
225
226 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
227 dump_reg(SDVOB, "Digital Display Port B Control Register");
228 dump_reg(SDVOC, "Digital Display Port C Control Register");
229 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
230
231 dump_reg(AUD_CONFIG, "Audio Configuration");
232 dump_reg(AUD_DEBUG, "Audio Debug");
233 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
234 dump_reg(AUD_RID, "Audio Revision ID");
235 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
236 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
237 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
238 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
239 dump_reg(AUD_PWRST, "Audio Power State");
240 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
241 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
242 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
243 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
244 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
245 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
246 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
247 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
248 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
249 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
250 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
251 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
252 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
253 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
254 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
255 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
256 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
257 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
258 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
259 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
260 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
261
262 printf("\nDetails:\n\n");
263
264 dword = INREG(AUD_VID_DID);
265 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
266 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
267
268 dword = INREG(AUD_RID);
269 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
270 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
271 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
272 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
273
274 dword = INREG(SDVOB);
275 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
276 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
277 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
278 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
279 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
280
281 dword = INREG(SDVOC);
282 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
283 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
284 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
285 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
286 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
287
288 dword = INREG(PORT_HOTPLUG_EN);
289 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
290 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
291 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
292 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
293 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
294 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
295 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
296 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
297
298 dword = INREG(VIDEO_DIP_CTL);
299 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
300 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
301 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
302 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
303 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
304 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
305 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
306 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
307 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
308 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
309 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
310 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
311 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
312
313 dword = INREG(AUD_CONFIG);
314 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
315 OPNAME(pixel_clock, BITS(dword, 19, 16)));
316 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
317 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
318 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
319
320 dword = INREG(AUD_DEBUG);
321 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
322
323 dword = INREG(AUD_SUBN_CNT);
324 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
325 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
326
327 dword = INREG(AUD_SUBN_CNT2);
328 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
329 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
330
331 dword = INREG(AUD_FUNC_GRP);
332 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
333 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
334
335 dword = INREG(AUD_GRP_CAP);
336 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
337 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
338 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
339
340 dword = INREG(AUD_PWRST);
341 printf("AUD_PWRST device power state\t\t%s\n",
342 power_state[BITS(dword, 5, 4)]);
343 printf("AUD_PWRST device power state setting\t%s\n",
344 power_state[BITS(dword, 1, 0)]);
345
346 dword = INREG(AUD_SUPPWR);
347 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
348 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
349 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
350 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
351
352 dword = INREG(AUD_OUT_CWCAP);
353 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
354 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
355 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
356 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
357 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
358 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
359 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
360 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
361 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
362 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
363 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
364 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
365 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
366 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
367
368 dword = INREG(AUD_OUT_DIG_CNVT);
369 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
370 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
371 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
372 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
373 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
374 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
375 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
376 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
377 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
378
379 dword = INREG(AUD_OUT_CH_STR);
380 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
Wu Fengguang5032f682011-11-12 11:12:41 +0800381 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800382
383 dword = INREG(AUD_OUT_STR_DESC);
Wu Fengguang5032f682011-11-12 11:12:41 +0800384 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800385 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
386 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800387
388 dword = INREG(AUD_PINW_CAP);
389 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
390 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
Wu Fengguang5032f682011-11-12 11:12:41 +0800391 printf("AUD_PINW_CAP channel count\t\t%lu\n",
392 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800393 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
394 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
395 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
396 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
397 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
398 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
399 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
400 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
401 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
402 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
403 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
404
405
406 dword = INREG(AUD_PIN_CAP);
407 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
408 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
409 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
410 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
411
412 dword = INREG(AUD_PINW_CNTR);
413 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
414 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
415 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
416 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
417 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
418 BITS(dword, 2, 0),
419 OPNAME(stream_type, BITS(dword, 2, 0)));
420
421 dword = INREG(AUD_PINW_UNSOLRESP);
422 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
423
424 dword = INREG(AUD_CNTL_ST);
425 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
426 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
427 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
428 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
429 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
430 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
431 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
432 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
433 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
434 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
435 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
436 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
437 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
438 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
439 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
440
441 dword = INREG(AUD_HDMIW_STATUS);
442 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
443 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
444 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
445 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
446
447 dword = INREG(AUD_CONV_CHCNT);
448 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
449 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
450
451 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
452 for (i = 0; i < 8; i++) {
453 OUTREG(AUD_CONV_CHCNT, i);
454 dword = INREG(AUD_CONV_CHCNT);
455 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
456 }
457
458 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
459 dword = INREG(AUD_CNTL_ST);
460 dword &= ~BITMASK(20, 18);
461 dword &= ~BITMASK(3, 0);
462 OUTREG(AUD_CNTL_ST, dword);
463 for (i = 0; i < 8; i++)
464 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
465 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800466}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800467
Wu Fengguang020abdb2010-04-19 13:13:06 +0800468#undef AUD_RID
469#undef AUD_VID_DID
470#undef AUD_PWRST
471#undef AUD_OUT_CH_STR
472#undef AUD_HDMIW_STATUS
473
474/*
475 * IronLake registers
476 */
477#define AUD_CONFIG_A 0xE2000
478#define AUD_CONFIG_B 0xE2100
479#define AUD_CTS_ENABLE_A 0xE2028
480#define AUD_CTS_ENABLE_B 0xE2128
481#define AUD_MISC_CTRL_A 0xE2010
482#define AUD_MISC_CTRL_B 0xE2110
483#define AUD_VID_DID 0xE2020
484#define AUD_RID 0xE2024
485#define AUD_PWRST 0xE204C
486#define AUD_PORT_EN_HD_CFG 0xE207C
487#define AUD_OUT_DIG_CNVT_A 0xE2080
488#define AUD_OUT_DIG_CNVT_B 0xE2180
489#define AUD_OUT_CH_STR 0xE2088
490#define AUD_OUT_STR_DESC_A 0xE2084
491#define AUD_OUT_STR_DESC_B 0xE2184
492#define AUD_PINW_CONNLNG_LIST 0xE20A8
493#define AUD_PINW_CONNLNG_SEL 0xE20AC
494#define AUD_CNTL_ST_A 0xE20B4
495#define AUD_CNTL_ST_B 0xE21B4
496#define AUD_CNTL_ST2 0xE20C0
497#define AUD_HDMIW_STATUS 0xE20D4
498#define AUD_HDMIW_HDMIEDID_A 0xE2050
499#define AUD_HDMIW_HDMIEDID_B 0xE2150
500#define AUD_HDMIW_INFOFR_A 0xE2054
501#define AUD_HDMIW_INFOFR_B 0xE2154
502
503static void dump_ironlake(void)
504{
505 uint32_t dword;
506 int i;
507
508 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
509 dump_reg(HDMIC, "HDMI Port C Control");
510 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800511 dump_reg(PCH_DP_B, "DisplayPort B Control Register");
512 dump_reg(PCH_DP_C, "DisplayPort C Control Register");
513 dump_reg(PCH_DP_D, "DisplayPort D Control Register");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800514 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
515 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
516 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
517 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800518 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
519 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
520 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
521 dump_reg(AUD_RID, "Audio Revision ID");
522 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
523 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800524 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
525 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800526 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800527 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
528 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800529 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
530 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800531 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
532 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800533 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
534 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800535 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
536 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
537 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
538 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800539
540 printf("\nDetails:\n\n");
541
542 dword = INREG(AUD_VID_DID);
543 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
544 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
545
546 dword = INREG(AUD_RID);
547 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
548 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
549 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
550 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
551
552 dword = INREG(HDMIB);
553 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
554 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
555 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800556 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800557 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
558 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
559
560 dword = INREG(HDMIC);
561 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
562 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
563 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800564 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800565 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
566 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
567
568 dword = INREG(HDMID);
569 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
570 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
571 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
572 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
573 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
574 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
575
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800576 dword = INREG(PCH_DP_B);
577 printf("PCH_DP_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
578 printf("PCH_DP_B Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
579 printf("PCH_DP_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
580 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
581 printf("PCH_DP_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
582 printf("PCH_DP_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
583 printf("PCH_DP_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
584
585 dword = INREG(PCH_DP_C);
586 printf("PCH_DP_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
587 printf("PCH_DP_C Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
588 printf("PCH_DP_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
589 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
590 printf("PCH_DP_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
591 printf("PCH_DP_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
592 printf("PCH_DP_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
593
594 dword = INREG(PCH_DP_D);
595 printf("PCH_DP_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
596 printf("PCH_DP_D Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
597 printf("PCH_DP_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
598 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
599 printf("PCH_DP_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
600 printf("PCH_DP_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
601 printf("PCH_DP_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
602
Wu Fengguang020abdb2010-04-19 13:13:06 +0800603 dword = INREG(AUD_CONFIG_A);
604 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
605 OPNAME(pixel_clock, BITS(dword, 19, 16)));
606 dword = INREG(AUD_CONFIG_B);
607 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
608 OPNAME(pixel_clock, BITS(dword, 19, 16)));
609
610 dword = INREG(AUD_CTS_ENABLE_A);
611 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
612 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
613 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
614 dword = INREG(AUD_CTS_ENABLE_B);
615 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
616 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
617 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
618
619 dword = INREG(AUD_MISC_CTRL_A);
620 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
621 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
622 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
623 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
624 dword = INREG(AUD_MISC_CTRL_B);
625 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
626 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
627 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
628 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
629
630 dword = INREG(AUD_PWRST);
631 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
632 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
633 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
634 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
635 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
636 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
637 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
638 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
639 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
640 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
641 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
642 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
643
644 dword = INREG(AUD_PORT_EN_HD_CFG);
645 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
646 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
647 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
648 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
649 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
650 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
651 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
652 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
653 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
654 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
655
656 dword = INREG(AUD_OUT_DIG_CNVT_A);
657 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
658 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
659 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
660 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800661 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800662 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
663 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
664 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
665 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800666 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800667
668 dword = INREG(AUD_OUT_DIG_CNVT_B);
669 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
670 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
671 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
672 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800673 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800674 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
675 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
676 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
677 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800678 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800679
680 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
681 for (i = 0; i < 8; i++) {
682 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
683 dword = INREG(AUD_OUT_CH_STR);
684 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
685 1 + BITS(dword, 3, 0),
686 1 + BITS(dword, 7, 4),
687 1 + BITS(dword, 15, 12),
688 1 + BITS(dword, 23, 20));
689 }
690
691 dword = INREG(AUD_OUT_STR_DESC_A);
692 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800693 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800694 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
695 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800696 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
697
698 dword = INREG(AUD_OUT_STR_DESC_B);
699 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800700 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800701 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
702 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800703 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
704
705 dword = INREG(AUD_PINW_CONNLNG_SEL);
706 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
707 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
708 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
709
710 dword = INREG(AUD_CNTL_ST_A);
711 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
712 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
713 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800714 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800715 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
716 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
717 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
718 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
719 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
720
721 dword = INREG(AUD_CNTL_ST_B);
722 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
723 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
724 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800725 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800726 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
727 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
728 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
729 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
730 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
731
732 dword = INREG(AUD_CNTL_ST2);
733 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
734 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
735 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
736 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
737 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
738 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
739
740 dword = INREG(AUD_HDMIW_STATUS);
741 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
742 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
743 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
744 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
745 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
746 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
747
748 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
749 dword = INREG(AUD_CNTL_ST_A);
750 dword &= ~BITMASK(9, 5);
751 OUTREG(AUD_CNTL_ST_A, dword);
752 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
753 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
754 printf("\n");
755
756 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
757 dword = INREG(AUD_CNTL_ST_B);
758 dword &= ~BITMASK(9, 5);
759 OUTREG(AUD_CNTL_ST_B, dword);
760 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
761 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
762 printf("\n");
763
764 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
765 dword = INREG(AUD_CNTL_ST_A);
766 dword &= ~BITMASK(20, 18);
767 dword &= ~BITMASK(3, 0);
768 OUTREG(AUD_CNTL_ST_A, dword);
769 for (i = 0; i < 8; i++)
770 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
771 printf("\n");
772
773 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
774 dword = INREG(AUD_CNTL_ST_B);
775 dword &= ~BITMASK(20, 18);
776 dword &= ~BITMASK(3, 0);
777 OUTREG(AUD_CNTL_ST_B, dword);
778 for (i = 0; i < 8; i++)
779 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
780 printf("\n");
781
782}
783
784
785#undef AUD_CONFIG_A
786#undef AUD_MISC_CTRL_A
787#undef AUD_VID_DID
788#undef AUD_RID
789#undef AUD_CTS_ENABLE_A
790#undef AUD_PWRST
791#undef AUD_HDMIW_HDMIEDID_A
792#undef AUD_HDMIW_INFOFR_A
793#undef AUD_PORT_EN_HD_CFG
794#undef AUD_OUT_DIG_CNVT_A
795#undef AUD_OUT_STR_DESC_A
796#undef AUD_OUT_CH_STR
797#undef AUD_PINW_CONNLNG_LIST
798#undef AUD_CNTL_ST_A
799#undef AUD_HDMIW_STATUS
800#undef AUD_CONFIG_B
801#undef AUD_MISC_CTRL_B
802#undef AUD_CTS_ENABLE_B
803#undef AUD_HDMIW_HDMIEDID_B
804#undef AUD_HDMIW_INFOFR_B
805#undef AUD_OUT_DIG_CNVT_B
806#undef AUD_OUT_STR_DESC_B
807#undef AUD_CNTL_ST_B
808
809/*
810 * CougarPoint registers
811 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800812#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800813#define DP_CTL_C 0xE4200
814#define DP_AUX_CTL_C 0xE4210
815#define DP_AUX_TST_C 0xE4228
816#define SPORT_DDI_CRC_C 0xE4250
817#define SPORT_DDI_CRC_R 0xE4264
818#define DP_CTL_D 0xE4300
819#define DP_AUX_CTL_D 0xE4310
820#define DP_AUX_TST_D 0xE4328
821#define SPORT_DDI_CRC_CTL_D 0xE4350
822#define AUD_CONFIG_A 0xE5000
823#define AUD_MISC_CTRL_A 0xE5010
824#define AUD_VID_DID 0xE5020
825#define AUD_RID 0xE5024
826#define AUD_CTS_ENABLE_A 0xE5028
827#define AUD_PWRST 0xE504C
828#define AUD_HDMIW_HDMIEDID_A 0xE5050
829#define AUD_HDMIW_INFOFR_A 0xE5054
830#define AUD_PORT_EN_HD_CFG 0xE507C
831#define AUD_OUT_DIG_CNVT_A 0xE5080
832#define AUD_OUT_STR_DESC_A 0xE5084
833#define AUD_OUT_CH_STR 0xE5088
834#define AUD_PINW_CONNLNG_LIST 0xE50A8
835#define AUD_PINW_CONNLNG_SELA 0xE50AC
836#define AUD_CNTL_ST_A 0xE50B4
837#define AUD_CNTRL_ST2 0xE50C0
838#define AUD_CNTRL_ST3 0xE50C4
839#define AUD_HDMIW_STATUS 0xE50D4
840#define AUD_CONFIG_B 0xE5100
841#define AUD_MISC_CTRL_B 0xE5110
842#define AUD_CTS_ENABLE_B 0xE5128
843#define AUD_HDMIW_HDMIEDID_B 0xE5150
844#define AUD_HDMIW_INFOFR_B 0xE5154
845#define AUD_OUT_DIG_CNVT_B 0xE5180
846#define AUD_OUT_STR_DESC_B 0xE5184
847#define AUD_CNTL_ST_B 0xE51B4
848#define AUD_CONFIG_C 0xE5200
849#define AUD_MISC_CTRL_C 0xE5210
850#define AUD_CTS_ENABLE_C 0xE5228
851#define AUD_HDMIW_HDMIEDID_C 0xE5250
852#define AUD_HDMIW_INFOFR_C 0xE5254
853#define AUD_OUT_DIG_CNVT_C 0xE5280
854#define AUD_OUT_STR_DESC_C 0xE5284
855#define AUD_CNTL_ST_C 0xE52B4
856#define AUD_CONFIG_D 0xE5300
857#define AUD_MISC_CTRL_D 0xE5310
858#define AUD_CTS_ENABLE_D 0xE5328
859#define AUD_HDMIW_HDMIEDID_D 0xE5350
860#define AUD_HDMIW_INFOFR_D 0xE5354
861#define AUD_OUT_DIG_CNVT_D 0xE5380
862#define AUD_OUT_STR_DESC_D 0xE5384
863#define AUD_CNTL_ST_D 0xE53B4
864
865
866static void dump_cpt(void)
867{
868 uint32_t dword;
869 int i;
870
871 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
872 dump_reg(HDMIC, "HDMI Port C Control");
873 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguang97d20312011-11-12 11:12:45 +0800874 dump_reg(DP_CTL_B, "DisplayPort B Control");
875 dump_reg(DP_CTL_C, "DisplayPort C Control");
876 dump_reg(DP_CTL_D, "DisplayPort D Control");
877 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
878 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
879 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800880 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
881 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
882 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
883 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
884 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
885 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800886 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
887 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
888 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
889 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
890 dump_reg(AUD_RID, "Audio Revision ID");
891 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
892 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800893 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
894 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
895 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800896 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800897 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
898 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
899 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800900 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
901 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800902 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
903 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
904 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800905 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
906 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
907 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800908 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
909 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
910 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
911 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
912 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
913 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800914
915 printf("\nDetails:\n\n");
916
917 dword = INREG(AUD_VID_DID);
918 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
919 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
920
921 dword = INREG(AUD_RID);
922 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
923 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
924 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
925 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
926
927 dword = INREG(HDMIB);
928 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
929 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
930 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
931 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
932 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
933 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
934 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
935 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
936
937 dword = INREG(HDMIC);
938 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
939 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
940 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
941 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
942 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
943 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
944 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
945 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
946
947 dword = INREG(HDMID);
948 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
949 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
950 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
951 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
952 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
953 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
954 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
955 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
956
Wu Fengguang97d20312011-11-12 11:12:45 +0800957 dword = INREG(DP_CTL_B);
958 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
959 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800960 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800961 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
962 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
963 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800964
Wu Fengguang97d20312011-11-12 11:12:45 +0800965 dword = INREG(DP_CTL_C);
966 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
967 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800968 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800969 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
970 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
971 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800972
Wu Fengguang97d20312011-11-12 11:12:45 +0800973 dword = INREG(DP_CTL_D);
974 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
975 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800976 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800977 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
978 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
979 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800980
981 dword = INREG(AUD_CONFIG_A);
982 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
983 OPNAME(pixel_clock, BITS(dword, 19, 16)));
984 dword = INREG(AUD_CONFIG_B);
985 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
986 OPNAME(pixel_clock, BITS(dword, 19, 16)));
987 dword = INREG(AUD_CONFIG_C);
988 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
989 OPNAME(pixel_clock, BITS(dword, 19, 16)));
990
991 dword = INREG(AUD_CTS_ENABLE_A);
992 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
993 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
994 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
995 dword = INREG(AUD_CTS_ENABLE_B);
996 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
997 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
998 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
999 dword = INREG(AUD_CTS_ENABLE_C);
1000 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1001 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1002 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1003
1004 dword = INREG(AUD_MISC_CTRL_A);
1005 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1006 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1007 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1008 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1009 dword = INREG(AUD_MISC_CTRL_B);
1010 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1011 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1012 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1013 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1014 dword = INREG(AUD_MISC_CTRL_C);
1015 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1016 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1017 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1018 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1019
1020 dword = INREG(AUD_PWRST);
1021 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
1022 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
1023 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
1024 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
1025 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
1026 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
1027 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
1028 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
1029 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1030 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1031 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1032 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1033 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1034 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
1035
1036 dword = INREG(AUD_PORT_EN_HD_CFG);
1037 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1038 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1039 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1040 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1041 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1042 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1043 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1044 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1045 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1046 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1047 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1048 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
1049
1050 dword = INREG(AUD_OUT_DIG_CNVT_A);
1051 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1052 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1053 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1054 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001055 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001056 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1057 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1058 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1059 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1060 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1061
1062 dword = INREG(AUD_OUT_DIG_CNVT_B);
1063 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1064 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1065 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1066 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001067 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001068 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1069 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1070 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1071 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1072 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1073
1074 dword = INREG(AUD_OUT_DIG_CNVT_C);
1075 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1076 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1077 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1078 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001079 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001080 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1081 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1082 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1083 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1084 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1085
1086 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1087 for (i = 0; i < 8; i++) {
1088 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1089 dword = INREG(AUD_OUT_CH_STR);
1090 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1091 1 + BITS(dword, 3, 0),
1092 1 + BITS(dword, 7, 4),
1093 1 + BITS(dword, 15, 12),
1094 1 + BITS(dword, 23, 20));
1095 }
1096
1097 dword = INREG(AUD_OUT_STR_DESC_A);
1098 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001099 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001100 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1101 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001102 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1103
1104 dword = INREG(AUD_OUT_STR_DESC_B);
1105 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001106 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001107 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1108 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001109 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1110
1111 dword = INREG(AUD_OUT_STR_DESC_C);
1112 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001113 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001114 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1115 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001116 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1117
1118 dword = INREG(AUD_PINW_CONNLNG_SEL);
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001119 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1120 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1121 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001122
1123 dword = INREG(AUD_CNTL_ST_A);
1124 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1125 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001126 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1127 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001128 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1129 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1130 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1131 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1132 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1133
1134 dword = INREG(AUD_CNTL_ST_B);
1135 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1136 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001137 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1138 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001139 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1140 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1141 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1142 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1143 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1144
1145 dword = INREG(AUD_CNTL_ST_C);
1146 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1147 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001148 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1149 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001150 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1151 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1152 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1153 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1154 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1155
1156 dword = INREG(AUD_CNTRL_ST2);
1157 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1158 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1159 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1160 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1161 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1162 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1163
1164 dword = INREG(AUD_CNTRL_ST3);
1165 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1166 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1167 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1168 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1169 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1170 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1171 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1172 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1173 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1174
1175 dword = INREG(AUD_HDMIW_STATUS);
1176 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1177 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1178 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1179 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1180 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1181 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1182 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1183 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1184
1185 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1186 dword = INREG(AUD_CNTL_ST_A);
1187 dword &= ~BITMASK(9, 5);
1188 OUTREG(AUD_CNTL_ST_A, dword);
1189 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1190 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1191 printf("\n");
1192
1193 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1194 dword = INREG(AUD_CNTL_ST_B);
1195 dword &= ~BITMASK(9, 5);
1196 OUTREG(AUD_CNTL_ST_B, dword);
1197 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1198 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1199 printf("\n");
1200
1201 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1202 dword = INREG(AUD_CNTL_ST_C);
1203 dword &= ~BITMASK(9, 5);
1204 OUTREG(AUD_CNTL_ST_C, dword);
1205 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1206 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1207 printf("\n");
1208
1209 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1210 dword = INREG(AUD_CNTL_ST_A);
1211 dword &= ~BITMASK(20, 18);
1212 dword &= ~BITMASK(3, 0);
1213 OUTREG(AUD_CNTL_ST_A, dword);
1214 for (i = 0; i < 8; i++)
1215 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1216 printf("\n");
1217
1218 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1219 dword = INREG(AUD_CNTL_ST_B);
1220 dword &= ~BITMASK(20, 18);
1221 dword &= ~BITMASK(3, 0);
1222 OUTREG(AUD_CNTL_ST_B, dword);
1223 for (i = 0; i < 8; i++)
1224 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1225 printf("\n");
1226
1227 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1228 dword = INREG(AUD_CNTL_ST_C);
1229 dword &= ~BITMASK(20, 18);
1230 dword &= ~BITMASK(3, 0);
1231 OUTREG(AUD_CNTL_ST_C, dword);
1232 for (i = 0; i < 8; i++)
1233 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1234 printf("\n");
1235
1236}
1237
1238int main(int argc, char **argv)
1239{
1240 struct pci_device *pci_dev;
1241
1242 pci_dev = intel_get_pci_device();
1243 devid = pci_dev->device_id; /* XXX not true when mapping! */
1244
1245 do_self_tests();
1246
1247 if (argc == 2)
1248 intel_map_file(argv[1]);
1249 else
1250 intel_get_mmio(pci_dev);
1251
Wu Fengguang63e3c372011-11-12 11:12:44 +08001252 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001253 printf("%s audio registers:\n\n",
1254 IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001255 intel_check_pch();
1256 dump_cpt();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001257 } else if (IS_GEN5(devid)) {
1258 printf("Ironlake audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001259 dump_ironlake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001260 } else if (IS_G4X(devid)) {
1261 printf("G45 audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001262 dump_eaglelake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001263 }
Wu Fengguang020abdb2010-04-19 13:13:06 +08001264
1265 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001266}