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Arnold Schwaighofer92226dd2007-10-12 21:53:12 +00001//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
Evan Cheng0cc39452006-01-16 21:21:29 +000016#include "X86InstrBuilder.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000017#include "X86ISelLowering.h"
Evan Chenge8bd0a32006-06-06 23:30:24 +000018#include "X86MachineFunctionInfo.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000019#include "X86TargetMachine.h"
20#include "llvm/CallingConv.h"
Evan Cheng223547a2006-01-31 22:28:30 +000021#include "llvm/Constants.h"
Evan Cheng347d5f72006-04-28 21:29:37 +000022#include "llvm/DerivedTypes.h"
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000024#include "llvm/Function.h"
Evan Cheng6be2c582006-04-05 23:38:46 +000025#include "llvm/Intrinsics.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000026#include "llvm/ADT/BitVector.h"
Evan Cheng30b37b52006-03-13 23:18:16 +000027#include "llvm/ADT/VectorExtras.h"
28#include "llvm/Analysis/ScalarEvolutionExpressions.h"
Chris Lattner362e98a2007-02-27 04:43:02 +000029#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000030#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Cheng4a460802006-01-11 00:33:36 +000031#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Chenga844bde2008-02-02 04:07:54 +000033#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000034#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman69de1932008-02-06 22:27:42 +000035#include "llvm/CodeGen/PseudoSourceValue.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000036#include "llvm/CodeGen/SelectionDAG.h"
Evan Chengef6ffb12006-01-31 03:14:29 +000037#include "llvm/Support/MathExtras.h"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000038#include "llvm/Support/Debug.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000039#include "llvm/Target/TargetOptions.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000040#include "llvm/ADT/SmallSet.h"
Chris Lattner1a60aa72006-10-31 19:42:44 +000041#include "llvm/ADT/StringExtras.h"
Dale Johannesen22c39792008-02-22 22:17:59 +000042#include "llvm/ParamAttrsList.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000043using namespace llvm;
44
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000045X86TargetLowering::X86TargetLowering(TargetMachine &TM)
46 : TargetLowering(TM) {
Evan Cheng559806f2006-01-27 08:10:46 +000047 Subtarget = &TM.getSubtarget<X86Subtarget>();
Dale Johannesenf1fc3a82007-09-23 14:52:20 +000048 X86ScalarSSEf64 = Subtarget->hasSSE2();
49 X86ScalarSSEf32 = Subtarget->hasSSE1();
Evan Cheng25ab6902006-09-08 06:48:29 +000050 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000051
Chris Lattnerd43d00c2008-01-24 08:07:48 +000052 bool Fast = false;
Evan Cheng559806f2006-01-27 08:10:46 +000053
Anton Korobeynikov2365f512007-07-14 14:06:15 +000054 RegInfo = TM.getRegisterInfo();
55
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000056 // Set up the TargetLowering object.
57
58 // X86 is weird, it always uses i8 for shift amounts and setcc results.
59 setShiftAmountType(MVT::i8);
60 setSetCCResultType(MVT::i8);
61 setSetCCResultContents(ZeroOrOneSetCCResult);
Evan Cheng0b2afbd2006-01-25 09:15:17 +000062 setSchedulingPreference(SchedulingForRegPressure);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000063 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
Evan Cheng25ab6902006-09-08 06:48:29 +000064 setStackPointerRegisterToSaveRestore(X86StackPtr);
Evan Cheng714554d2006-03-16 21:47:42 +000065
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000066 if (Subtarget->isTargetDarwin()) {
Evan Chengdf57fa02006-03-17 20:31:41 +000067 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000068 setUseUnderscoreSetJmp(false);
69 setUseUnderscoreLongJmp(false);
Anton Korobeynikov317848f2007-01-03 11:43:14 +000070 } else if (Subtarget->isTargetMingw()) {
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000071 // MS runtime is weird: it exports _setjmp, but longjmp!
72 setUseUnderscoreSetJmp(true);
73 setUseUnderscoreLongJmp(false);
74 } else {
75 setUseUnderscoreSetJmp(true);
76 setUseUnderscoreLongJmp(true);
77 }
78
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000079 // Set up the register classes.
Evan Cheng069287d2006-05-16 07:21:53 +000080 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
81 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
82 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
Evan Cheng25ab6902006-09-08 06:48:29 +000083 if (Subtarget->is64Bit())
84 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000085
Duncan Sandsf9c98e62008-01-23 20:39:46 +000086 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
Evan Chengc5484282006-10-04 00:56:09 +000087
Chris Lattnerddf89562008-01-17 19:59:44 +000088 // We don't accept any truncstore of integer registers.
89 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
90 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
92 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
93 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
94 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
95
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000096 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
97 // operation.
98 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
99 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
Evan Cheng6892f282006-01-17 02:32:49 +0000101
Evan Cheng25ab6902006-09-08 06:48:29 +0000102 if (Subtarget->is64Bit()) {
103 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
Evan Cheng6892f282006-01-17 02:32:49 +0000104 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
Evan Cheng25ab6902006-09-08 06:48:29 +0000105 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000106 if (X86ScalarSSEf64)
Evan Cheng25ab6902006-09-08 06:48:29 +0000107 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
108 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
109 else
110 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
111 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000112
113 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
114 // this operation.
115 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
116 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000117 // SSE has no i16 to fp conversion, only i32
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000118 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000119 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000120 // f32 and f64 cases are Legal, f80 case is not
121 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
122 } else {
Evan Cheng5298bcc2006-02-17 07:01:52 +0000123 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
125 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000126
Dale Johannesen73328d12007-09-19 23:55:34 +0000127 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
128 // are Legal, f80 is custom lowered.
129 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
130 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
Evan Cheng6dab0532006-01-30 08:02:57 +0000131
Evan Cheng02568ff2006-01-30 22:13:22 +0000132 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
133 // this operation.
134 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
135 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
136
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000137 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000138 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000139 // f32 and f64 cases are Legal, f80 case is not
140 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000141 } else {
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000142 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000143 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000144 }
145
146 // Handle FP_TO_UINT by promoting the destination to a larger signed
147 // conversion.
148 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
149 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
151
Evan Cheng25ab6902006-09-08 06:48:29 +0000152 if (Subtarget->is64Bit()) {
153 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000154 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
Evan Cheng25ab6902006-09-08 06:48:29 +0000155 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000156 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
Evan Cheng25ab6902006-09-08 06:48:29 +0000157 // Expand FP_TO_UINT into a select.
158 // FIXME: We would like to use a Custom expander here eventually to do
159 // the optimal thing for SSE vs. the default expansion in the legalizer.
160 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
161 else
162 // With SSE3 we can use fisttpll to convert to a signed i64.
163 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
164 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000165
Chris Lattner399610a2006-12-05 18:22:22 +0000166 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000167 if (!X86ScalarSSEf64) {
Chris Lattnerf3597a12006-12-05 18:45:06 +0000168 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
169 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
170 }
Chris Lattner21f66852005-12-23 05:15:23 +0000171
Dan Gohmanb00ee212008-02-18 19:34:53 +0000172 // Scalar integer divide and remainder are lowered to use operations that
173 // produce two results, to match the available instructions. This exposes
174 // the two-result form to trivial CSE, which is able to combine x/y and x%y
175 // into a single instruction.
176 //
177 // Scalar integer multiply-high is also lowered to use two-result
178 // operations, to match the available instructions. However, plain multiply
179 // (low) operations are left as Legal, as there are single-result
180 // instructions for this in x86. Using the two-result multiply instructions
181 // when both high and low results are needed must be arranged by dagcombine.
Dan Gohman525178c2007-10-08 18:33:35 +0000182 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
183 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
184 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
185 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::SREM , MVT::i8 , Expand);
187 setOperationAction(ISD::UREM , MVT::i8 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000188 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
189 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
190 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
191 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::SREM , MVT::i16 , Expand);
193 setOperationAction(ISD::UREM , MVT::i16 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000194 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
195 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
196 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
197 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::SREM , MVT::i32 , Expand);
199 setOperationAction(ISD::UREM , MVT::i32 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000200 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
201 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
202 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
203 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::SREM , MVT::i64 , Expand);
205 setOperationAction(ISD::UREM , MVT::i64 , Expand);
Dan Gohmana37c9f72007-09-25 18:23:27 +0000206
Evan Chengc35497f2006-10-30 08:02:39 +0000207 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000208 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
Nate Begeman750ac1b2006-02-01 07:19:44 +0000209 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
210 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000211 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000212 if (Subtarget->is64Bit())
Christopher Lambc59e5212007-08-10 21:48:46 +0000213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
Chris Lattnerd1108222008-03-07 06:36:32 +0000218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
Chris Lattnerd1108222008-03-07 06:36:32 +0000220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
Dan Gohman1a024862008-01-31 00:41:03 +0000221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +0000222
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000236 }
237
Andrew Lenharthb873ff32005-11-20 21:41:10 +0000238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
Nate Begemand88fc032006-01-14 03:14:10 +0000239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
Nate Begeman35ef9132006-01-11 21:21:00 +0000240
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000244 // X86 wants to expand cmov itself.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
259 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000260 // X86 ret instruction may pop stack.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000261 setOperationAction(ISD::RET , MVT::Other, Custom);
Anton Korobeynikov2365f512007-07-14 14:06:15 +0000262 if (!Subtarget->is64Bit())
263 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
264
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000265 // Darwin ABI issue.
Evan Cheng7ccced62006-02-18 00:15:05 +0000266 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
Nate Begeman37efe672006-04-22 18:53:45 +0000267 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000268 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
Evan Cheng020d2e82006-02-23 20:41:18 +0000270 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000271 if (Subtarget->is64Bit()) {
272 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
273 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
274 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
275 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
276 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000277 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
Evan Cheng5298bcc2006-02-17 07:01:52 +0000278 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
279 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
280 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
Dan Gohman4c1fa612008-03-03 22:22:09 +0000281 if (Subtarget->is64Bit()) {
282 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
283 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
284 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
285 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000286 // X86 wants to expand memset / memcpy itself.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000287 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
288 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000289
Evan Cheng27b7db52008-03-08 00:58:38 +0000290 if (!Subtarget->hasSSE1())
291 setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
292
Andrew Lenharthd497d9f2008-02-16 14:46:26 +0000293 if (!Subtarget->hasSSE2())
294 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
295
Andrew Lenharth26ed8692008-03-01 21:52:34 +0000296 setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom);
297 setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom);
298 setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom);
Andrew Lenhartha76e2f02008-03-04 21:13:33 +0000299 setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom);
Andrew Lenharthd497d9f2008-02-16 14:46:26 +0000300
Evan Chenga844bde2008-02-02 04:07:54 +0000301 // Use the default ISD::LOCATION, ISD::DECLARE expansion.
Chris Lattnerf73bae12005-11-29 06:16:21 +0000302 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
Evan Cheng3c992d22006-03-07 02:02:57 +0000303 // FIXME - use subtarget debug flags
Anton Korobeynikovab4022f2006-10-31 08:31:24 +0000304 if (!Subtarget->isTargetDarwin() &&
305 !Subtarget->isTargetELF() &&
Anton Korobeynikov317848f2007-01-03 11:43:14 +0000306 !Subtarget->isTargetCygMing())
Jim Laskey1ee29252007-01-26 14:34:52 +0000307 setOperationAction(ISD::LABEL, MVT::Other, Expand);
Chris Lattnerf73bae12005-11-29 06:16:21 +0000308
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000309 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
310 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
311 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
312 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
313 if (Subtarget->is64Bit()) {
314 // FIXME: Verify
315 setExceptionPointerRegister(X86::RAX);
316 setExceptionSelectorRegister(X86::RDX);
317 } else {
318 setExceptionPointerRegister(X86::EAX);
319 setExceptionSelectorRegister(X86::EDX);
320 }
Anton Korobeynikov38252622007-09-03 00:36:06 +0000321 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000322
Duncan Sandsf7331b32007-09-11 14:10:23 +0000323 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
Duncan Sandsb116fac2007-07-27 20:02:49 +0000324
Chris Lattnerda68d302008-01-15 21:58:22 +0000325 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Anton Korobeynikov66fac792008-01-15 07:02:33 +0000326
Nate Begemanacc398c2006-01-25 18:21:52 +0000327 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
328 setOperationAction(ISD::VASTART , MVT::Other, Custom);
Nate Begemanacc398c2006-01-25 18:21:52 +0000329 setOperationAction(ISD::VAARG , MVT::Other, Expand);
Nate Begemanacc398c2006-01-25 18:21:52 +0000330 setOperationAction(ISD::VAEND , MVT::Other, Expand);
Evan Chengae642192007-03-02 23:16:35 +0000331 if (Subtarget->is64Bit())
332 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
333 else
334 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
335
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000336 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
Chris Lattnere1125522006-01-15 09:00:21 +0000337 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000338 if (Subtarget->is64Bit())
339 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +0000340 if (Subtarget->isTargetCygMing())
341 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
342 else
343 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
Chris Lattnerb99329e2006-01-13 02:42:53 +0000344
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000345 if (X86ScalarSSEf64) {
346 // f32 and f64 use SSE.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000347 // Set up the FP register classes.
Evan Cheng5ee4ccc2006-01-12 08:27:59 +0000348 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
349 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000350
Evan Cheng223547a2006-01-31 22:28:30 +0000351 // Use ANDPD to simulate FABS.
352 setOperationAction(ISD::FABS , MVT::f64, Custom);
353 setOperationAction(ISD::FABS , MVT::f32, Custom);
354
355 // Use XORP to simulate FNEG.
356 setOperationAction(ISD::FNEG , MVT::f64, Custom);
357 setOperationAction(ISD::FNEG , MVT::f32, Custom);
358
Evan Cheng68c47cb2007-01-05 07:55:56 +0000359 // Use ANDPD and ORPD to simulate FCOPYSIGN.
360 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
361 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
362
Evan Chengd25e9e82006-02-02 00:28:23 +0000363 // We don't support sin/cos/fmod
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000364 setOperationAction(ISD::FSIN , MVT::f64, Expand);
365 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000366 setOperationAction(ISD::FSIN , MVT::f32, Expand);
367 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000368
Chris Lattnera54aa942006-01-29 06:26:08 +0000369 // Expand FP immediates into loads from the stack, except for the special
370 // cases we handle.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000371 addLegalFPImmediate(APFloat(+0.0)); // xorpd
372 addLegalFPImmediate(APFloat(+0.0f)); // xorps
Dale Johannesen5411a392007-08-09 01:04:01 +0000373
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000374 // Floating truncations from f80 and extensions to f80 go through memory.
375 // If optimizing, we lie about this though and handle it in
376 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
377 if (Fast) {
378 setConvertAction(MVT::f32, MVT::f80, Expand);
379 setConvertAction(MVT::f64, MVT::f80, Expand);
380 setConvertAction(MVT::f80, MVT::f32, Expand);
381 setConvertAction(MVT::f80, MVT::f64, Expand);
382 }
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000383 } else if (X86ScalarSSEf32) {
384 // Use SSE for f32, x87 for f64.
385 // Set up the FP register classes.
386 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
387 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
388
389 // Use ANDPS to simulate FABS.
390 setOperationAction(ISD::FABS , MVT::f32, Custom);
391
392 // Use XORP to simulate FNEG.
393 setOperationAction(ISD::FNEG , MVT::f32, Custom);
394
395 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
396
397 // Use ANDPS and ORPS to simulate FCOPYSIGN.
398 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
399 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
400
401 // We don't support sin/cos/fmod
402 setOperationAction(ISD::FSIN , MVT::f32, Expand);
403 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000404
Nate Begemane1795842008-02-14 08:57:00 +0000405 // Special cases we handle for FP constants.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000406 addLegalFPImmediate(APFloat(+0.0f)); // xorps
407 addLegalFPImmediate(APFloat(+0.0)); // FLD0
408 addLegalFPImmediate(APFloat(+1.0)); // FLD1
409 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
410 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
411
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000412 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
413 // this though and handle it in InstructionSelectPreprocess so that
414 // dagcombine2 can hack on these.
415 if (Fast) {
416 setConvertAction(MVT::f32, MVT::f64, Expand);
417 setConvertAction(MVT::f32, MVT::f80, Expand);
418 setConvertAction(MVT::f80, MVT::f32, Expand);
419 setConvertAction(MVT::f64, MVT::f32, Expand);
420 // And x87->x87 truncations also.
421 setConvertAction(MVT::f80, MVT::f64, Expand);
422 }
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000423
424 if (!UnsafeFPMath) {
425 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
426 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
427 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000428 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000429 // f32 and f64 in x87.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000430 // Set up the FP register classes.
Dale Johannesen849f2142007-07-03 00:53:03 +0000431 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
432 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000433
Evan Cheng68c47cb2007-01-05 07:55:56 +0000434 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
Dale Johannesen849f2142007-07-03 00:53:03 +0000435 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
Evan Cheng68c47cb2007-01-05 07:55:56 +0000436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
Dale Johannesen5411a392007-08-09 01:04:01 +0000438
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000439 // Floating truncations go through memory. If optimizing, we lie about
440 // this though and handle it in InstructionSelectPreprocess so that
441 // dagcombine2 can hack on these.
442 if (Fast) {
443 setConvertAction(MVT::f80, MVT::f32, Expand);
444 setConvertAction(MVT::f64, MVT::f32, Expand);
445 setConvertAction(MVT::f80, MVT::f64, Expand);
446 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000447
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000448 if (!UnsafeFPMath) {
449 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
450 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
451 }
Dale Johannesenf04afdb2007-08-30 00:23:21 +0000452 addLegalFPImmediate(APFloat(+0.0)); // FLD0
453 addLegalFPImmediate(APFloat(+1.0)); // FLD1
454 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
455 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000456 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
457 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
458 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
459 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000460 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000461
Dale Johannesen59a58732007-08-05 18:49:15 +0000462 // Long double always uses X87.
463 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000464 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
Chris Lattner71d07a02008-01-27 06:19:31 +0000466 {
Chris Lattner71d07a02008-01-27 06:19:31 +0000467 APFloat TmpFlt(+0.0);
468 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
469 addLegalFPImmediate(TmpFlt); // FLD0
470 TmpFlt.changeSign();
471 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
472 APFloat TmpFlt2(+1.0);
473 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
474 addLegalFPImmediate(TmpFlt2); // FLD1
475 TmpFlt2.changeSign();
476 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
477 }
478
Dale Johannesen2f429012007-09-26 21:10:55 +0000479 if (!UnsafeFPMath) {
480 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
481 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
482 }
Dale Johannesen59a58732007-08-05 18:49:15 +0000483
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000484 // Always use a library call for pow.
485 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
486 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
487 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
488
Evan Chengd30bf012006-03-01 01:11:20 +0000489 // First set operation action for all vector types to expand. Then we
490 // will selectively turn on ones that can be effectively codegen'd.
Dan Gohmanfa0f77d2007-05-18 18:44:07 +0000491 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
492 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
Evan Chengd30bf012006-03-01 01:11:20 +0000493 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
494 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000495 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
Evan Chenga72cb0e2007-06-29 00:18:15 +0000496 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000497 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000498 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000499 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
500 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
501 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
502 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
503 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
504 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000505 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
Evan Chengb067a1e2006-03-31 19:22:53 +0000506 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
Chris Lattner9b3bd462006-03-21 20:51:05 +0000507 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
Evan Chengb067a1e2006-03-31 19:22:53 +0000508 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
Dan Gohman20382522007-07-10 00:05:58 +0000509 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
510 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
511 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
512 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
513 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
514 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
515 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000516 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
517 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
518 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
519 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000520 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
Dan Gohmanf0d00892007-10-12 14:09:42 +0000521 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
522 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
523 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
Dan Gohman89081322007-12-12 22:21:26 +0000524 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
525 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
526 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
527 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
528 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
529 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000530 }
531
Evan Chenga88973f2006-03-22 19:22:18 +0000532 if (Subtarget->hasMMX()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000533 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
534 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
535 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000536 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000537
Evan Chengd30bf012006-03-01 01:11:20 +0000538 // FIXME: add MMX packed arithmetics
Bill Wendlingbc9bffa2007-03-07 05:43:18 +0000539
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000540 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
541 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
542 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
Chris Lattner6c284d72007-04-12 04:14:49 +0000543 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000544
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000545 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
546 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
547 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
Dale Johannesen8d26e592007-10-30 01:18:38 +0000548 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000549
Bill Wendling74027e92007-03-15 21:24:36 +0000550 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
551 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
552
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000553 setOperationAction(ISD::AND, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000554 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000555 setOperationAction(ISD::AND, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000556 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
557 setOperationAction(ISD::AND, MVT::v2i32, Promote);
558 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
559 setOperationAction(ISD::AND, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000560
561 setOperationAction(ISD::OR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000562 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000563 setOperationAction(ISD::OR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000564 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
565 setOperationAction(ISD::OR, MVT::v2i32, Promote);
566 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
567 setOperationAction(ISD::OR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000568
569 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000570 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000571 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000572 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
573 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
574 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
575 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000576
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000577 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000578 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000579 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000580 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
581 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
582 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
583 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000584
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000585 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
586 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
587 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
588 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
Bill Wendlinga348c562007-03-22 18:42:45 +0000589
590 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
591 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
592 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000593 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
Bill Wendling826f36f2007-03-28 00:57:11 +0000594
595 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
596 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
Bill Wendling2f9bb1a2007-04-24 21:16:55 +0000597 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000598 }
599
Evan Chenga88973f2006-03-22 19:22:18 +0000600 if (Subtarget->hasSSE1()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000601 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
602
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000603 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
604 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
605 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
606 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000607 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
608 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000609 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
610 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
611 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
Evan Cheng11e15b32006-04-03 20:53:28 +0000612 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000613 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000614 }
615
Evan Chenga88973f2006-03-22 19:22:18 +0000616 if (Subtarget->hasSSE2()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000617 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
618 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
619 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
620 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
621 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
622
Evan Chengf7c378e2006-04-10 07:23:14 +0000623 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
624 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
625 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000626 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000627 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
628 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
629 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000630 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
Evan Chengf9989842006-04-13 05:10:25 +0000631 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000632 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
633 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
634 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
635 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000636 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
637 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000638
Evan Chengf7c378e2006-04-10 07:23:14 +0000639 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
640 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
Evan Chengb067a1e2006-03-31 19:22:53 +0000641 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000642 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000643 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000644
Evan Cheng2c3ae372006-04-12 21:21:57 +0000645 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
646 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
Nate Begeman844e0f92007-12-11 01:41:33 +0000647 // Do not attempt to custom lower non-power-of-2 vectors
648 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
649 continue;
Evan Cheng2c3ae372006-04-12 21:21:57 +0000650 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
651 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
652 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
653 }
654 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
655 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
656 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
657 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000659 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000660 if (Subtarget->is64Bit()) {
661 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
Dale Johannesen25f1d082007-10-31 00:32:36 +0000662 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000663 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000664
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000665 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
Evan Cheng2c3ae372006-04-12 21:21:57 +0000666 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
667 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
668 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
669 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
670 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
671 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
672 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
Evan Cheng91b740d2006-04-12 17:12:36 +0000673 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
674 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000675 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
676 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
Evan Chengf7c378e2006-04-10 07:23:14 +0000677 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000678
Chris Lattnerddf89562008-01-17 19:59:44 +0000679 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000680
Evan Cheng2c3ae372006-04-12 21:21:57 +0000681 // Custom lower v2i64 and v2f64 selects.
682 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
Evan Cheng91b740d2006-04-12 17:12:36 +0000683 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000684 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000685 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000686 }
Nate Begeman14d12ca2008-02-11 04:19:36 +0000687
688 if (Subtarget->hasSSE41()) {
689 // FIXME: Do we need to handle scalar-to-vector here?
690 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
691
692 // i8 and i16 vectors are custom , because the source register and source
693 // source memory operand types are not the same width. f32 vectors are
694 // custom since the immediate controlling the insert encodes additional
695 // information.
696 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
698 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
699 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
700
701 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
702 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
703 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
704 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
705
706 if (Subtarget->is64Bit()) {
Nate Begemancdd1eec2008-02-12 22:51:28 +0000707 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
708 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000709 }
710 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000711
Evan Cheng6be2c582006-04-05 23:38:46 +0000712 // We want to custom lower some of our intrinsics.
713 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
714
Evan Cheng206ee9d2006-07-07 08:33:52 +0000715 // We have target-specific dag combine patterns for the following nodes:
716 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
Chris Lattner83e6c992006-10-04 06:57:07 +0000717 setTargetDAGCombine(ISD::SELECT);
Chris Lattner149a4e52008-02-22 02:09:43 +0000718 setTargetDAGCombine(ISD::STORE);
Evan Cheng206ee9d2006-07-07 08:33:52 +0000719
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000720 computeRegisterProperties();
721
Evan Cheng87ed7162006-02-14 08:25:08 +0000722 // FIXME: These should be based on subtarget info. Plus, the values should
723 // be smaller when we are in optimizing for size mode.
Evan Chenga03a5dc2006-02-14 08:38:30 +0000724 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
725 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
726 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000727 allowUnalignedMemoryAccesses = true; // x86 supports it!
Evan Chengfb8075d2008-02-28 00:43:03 +0000728 setPrefLoopAlignment(16);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000729}
730
Evan Cheng29286502008-01-23 23:17:41 +0000731/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
732/// the desired ByVal argument alignment.
733static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
734 if (MaxAlign == 16)
735 return;
736 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
737 if (VTy->getBitWidth() == 128)
738 MaxAlign = 16;
Evan Cheng29286502008-01-23 23:17:41 +0000739 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
740 unsigned EltAlign = 0;
741 getMaxByValAlign(ATy->getElementType(), EltAlign);
742 if (EltAlign > MaxAlign)
743 MaxAlign = EltAlign;
744 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
745 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
746 unsigned EltAlign = 0;
747 getMaxByValAlign(STy->getElementType(i), EltAlign);
748 if (EltAlign > MaxAlign)
749 MaxAlign = EltAlign;
750 if (MaxAlign == 16)
751 break;
752 }
753 }
754 return;
755}
756
757/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
758/// function arguments in the caller parameter area. For X86, aggregates
Dale Johannesen0c191872008-02-08 19:48:20 +0000759/// that contain SSE vectors are placed at 16-byte boundaries while the rest
760/// are at 4-byte boundaries.
Evan Cheng29286502008-01-23 23:17:41 +0000761unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
762 if (Subtarget->is64Bit())
763 return getTargetData()->getABITypeAlignment(Ty);
764 unsigned Align = 4;
Dale Johannesen0c191872008-02-08 19:48:20 +0000765 if (Subtarget->hasSSE1())
766 getMaxByValAlign(Ty, Align);
Evan Cheng29286502008-01-23 23:17:41 +0000767 return Align;
768}
Chris Lattner2b02a442007-02-25 08:29:00 +0000769
Evan Chengcc415862007-11-09 01:32:10 +0000770/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
771/// jumptable.
772SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
773 SelectionDAG &DAG) const {
774 if (usesGlobalOffsetTable())
775 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
776 if (!Subtarget->isPICStyleRIPRel())
777 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
778 return Table;
779}
780
Chris Lattner2b02a442007-02-25 08:29:00 +0000781//===----------------------------------------------------------------------===//
782// Return Value Calling Convention Implementation
783//===----------------------------------------------------------------------===//
784
Chris Lattner59ed56b2007-02-28 04:55:35 +0000785#include "X86GenCallingConv.inc"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000786
787/// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it
788/// exists skip possible ISD:TokenFactor.
789static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) {
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000790 if (Chain.getOpcode() == X86ISD::TAILCALL) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000791 return Chain;
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000792 } else if (Chain.getOpcode() == ISD::TokenFactor) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000793 if (Chain.getNumOperands() &&
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000794 Chain.getOperand(0).getOpcode() == X86ISD::TAILCALL)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000795 return Chain.getOperand(0);
796 }
797 return Chain;
798}
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000799
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000800/// LowerRET - Lower an ISD::RET node.
801SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
802 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
803
Chris Lattner9774c912007-02-27 05:28:59 +0000804 SmallVector<CCValAssign, 16> RVLocs;
805 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
Chris Lattner52387be2007-06-19 00:13:10 +0000806 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
807 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
Chris Lattnere32bbf62007-02-28 07:09:55 +0000808 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000809
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000810 // If this is the first return lowered for this function, add the regs to the
811 // liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +0000812 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Chris Lattner9774c912007-02-27 05:28:59 +0000813 for (unsigned i = 0; i != RVLocs.size(); ++i)
814 if (RVLocs[i].isRegLoc())
Chris Lattner84bc5422007-12-31 04:13:23 +0000815 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000816 }
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000817 SDOperand Chain = Op.getOperand(0);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000818
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000819 // Handle tail call return.
820 Chain = GetPossiblePreceedingTailCall(Chain);
821 if (Chain.getOpcode() == X86ISD::TAILCALL) {
822 SDOperand TailCall = Chain;
823 SDOperand TargetAddress = TailCall.getOperand(1);
824 SDOperand StackAdjustment = TailCall.getOperand(2);
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000825 assert(((TargetAddress.getOpcode() == ISD::Register &&
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000826 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
827 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
828 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
829 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
830 "Expecting an global address, external symbol, or register");
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000831 assert(StackAdjustment.getOpcode() == ISD::Constant &&
832 "Expecting a const value");
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000833
834 SmallVector<SDOperand,8> Operands;
835 Operands.push_back(Chain.getOperand(0));
836 Operands.push_back(TargetAddress);
837 Operands.push_back(StackAdjustment);
838 // Copy registers used by the call. Last operand is a flag so it is not
839 // copied.
Arnold Schwaighofer448175f2007-10-16 09:05:00 +0000840 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000841 Operands.push_back(Chain.getOperand(i));
842 }
Arnold Schwaighofer448175f2007-10-16 09:05:00 +0000843 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
844 Operands.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000845 }
846
847 // Regular return.
848 SDOperand Flag;
849
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000850 // Copy the result values into the output registers.
Chris Lattner9774c912007-02-27 05:28:59 +0000851 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
852 RVLocs[0].getLocReg() != X86::ST0) {
853 for (unsigned i = 0; i != RVLocs.size(); ++i) {
854 CCValAssign &VA = RVLocs[i];
855 assert(VA.isRegLoc() && "Can only return in registers!");
856 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
857 Flag);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000858 Flag = Chain.getValue(1);
859 }
860 } else {
861 // We need to handle a destination of ST0 specially, because it isn't really
862 // a register.
863 SDOperand Value = Op.getOperand(1);
864
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000865 // an XMM register onto the fp-stack. Do this with an FP_EXTEND to f80.
866 // This will get legalized into a load/store if it can't get optimized away.
867 if (isScalarFPTypeInSSEReg(RVLocs[0].getValVT()))
868 Value = DAG.getNode(ISD::FP_EXTEND, MVT::f80, Value);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000869
870 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
871 SDOperand Ops[] = { Chain, Value };
872 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
873 Flag = Chain.getValue(1);
874 }
875
876 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
877 if (Flag.Val)
878 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
879 else
880 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
881}
882
883
Chris Lattner3085e152007-02-25 08:59:22 +0000884/// LowerCallResult - Lower the result values of an ISD::CALL into the
885/// appropriate copies out of appropriate physical registers. This assumes that
886/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
887/// being lowered. The returns a SDNode with the same number of values as the
888/// ISD::CALL.
889SDNode *X86TargetLowering::
890LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
891 unsigned CallingConv, SelectionDAG &DAG) {
Chris Lattnere32bbf62007-02-28 07:09:55 +0000892
893 // Assign locations to each value returned by this call.
Chris Lattner9774c912007-02-27 05:28:59 +0000894 SmallVector<CCValAssign, 16> RVLocs;
Chris Lattner52387be2007-06-19 00:13:10 +0000895 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
896 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
Chris Lattnere32bbf62007-02-28 07:09:55 +0000897 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
898
Chris Lattnere32bbf62007-02-28 07:09:55 +0000899 SmallVector<SDOperand, 8> ResultVals;
Chris Lattner3085e152007-02-25 08:59:22 +0000900
901 // Copy all of the result registers out of their specified physreg.
Chris Lattner9774c912007-02-27 05:28:59 +0000902 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
903 for (unsigned i = 0; i != RVLocs.size(); ++i) {
904 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
905 RVLocs[i].getValVT(), InFlag).getValue(1);
Chris Lattner3085e152007-02-25 08:59:22 +0000906 InFlag = Chain.getValue(2);
907 ResultVals.push_back(Chain.getValue(0));
908 }
909 } else {
910 // Copies from the FP stack are special, as ST0 isn't a valid register
911 // before the fp stackifier runs.
912
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000913 // Copy ST0 into an RFP register with FP_GET_RESULT. If this will end up
914 // in an SSE register, copy it out as F80 and do a truncate, otherwise use
915 // the specified value type.
916 MVT::ValueType GetResultTy = RVLocs[0].getValVT();
917 if (isScalarFPTypeInSSEReg(GetResultTy))
918 GetResultTy = MVT::f80;
919 SDVTList Tys = DAG.getVTList(GetResultTy, MVT::Other, MVT::Flag);
920
Chris Lattner3085e152007-02-25 08:59:22 +0000921 SDOperand GROps[] = { Chain, InFlag };
922 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
923 Chain = RetVal.getValue(1);
924 InFlag = RetVal.getValue(2);
Chris Lattner112dedc2007-12-29 06:41:28 +0000925
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000926 // If we want the result in an SSE register, use an FP_TRUNCATE to get it
927 // there.
928 if (GetResultTy != RVLocs[0].getValVT())
929 RetVal = DAG.getNode(ISD::FP_ROUND, RVLocs[0].getValVT(), RetVal,
930 // This truncation won't change the value.
931 DAG.getIntPtrConstant(1));
932
Chris Lattner3085e152007-02-25 08:59:22 +0000933 ResultVals.push_back(RetVal);
934 }
935
936 // Merge everything together with a MERGE_VALUES node.
937 ResultVals.push_back(Chain);
938 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
939 &ResultVals[0], ResultVals.size()).Val;
Chris Lattner2b02a442007-02-25 08:29:00 +0000940}
941
Evan Cheng0d9e9762008-01-29 19:34:22 +0000942/// LowerCallResultToTwo64BitRegs - Lower the result values of an x86-64
943/// ISD::CALL where the results are known to be in two 64-bit registers,
944/// e.g. XMM0 and XMM1. This simplify store the two values back to the
945/// fixed stack slot allocated for StructRet.
946SDNode *X86TargetLowering::
947LowerCallResultToTwo64BitRegs(SDOperand Chain, SDOperand InFlag,
948 SDNode *TheCall, unsigned Reg1, unsigned Reg2,
949 MVT::ValueType VT, SelectionDAG &DAG) {
950 SDOperand RetVal1 = DAG.getCopyFromReg(Chain, Reg1, VT, InFlag);
951 Chain = RetVal1.getValue(1);
952 InFlag = RetVal1.getValue(2);
953 SDOperand RetVal2 = DAG.getCopyFromReg(Chain, Reg2, VT, InFlag);
954 Chain = RetVal2.getValue(1);
955 InFlag = RetVal2.getValue(2);
956 SDOperand FIN = TheCall->getOperand(5);
957 Chain = DAG.getStore(Chain, RetVal1, FIN, NULL, 0);
958 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
959 Chain = DAG.getStore(Chain, RetVal2, FIN, NULL, 0);
960 return Chain.Val;
961}
962
963/// LowerCallResultToTwoX87Regs - Lower the result values of an x86-64 ISD::CALL
964/// where the results are known to be in ST0 and ST1.
965SDNode *X86TargetLowering::
966LowerCallResultToTwoX87Regs(SDOperand Chain, SDOperand InFlag,
967 SDNode *TheCall, SelectionDAG &DAG) {
968 SmallVector<SDOperand, 8> ResultVals;
969 const MVT::ValueType VTs[] = { MVT::f80, MVT::f80, MVT::Other, MVT::Flag };
970 SDVTList Tys = DAG.getVTList(VTs, 4);
971 SDOperand Ops[] = { Chain, InFlag };
972 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT2, Tys, Ops, 2);
973 Chain = RetVal.getValue(2);
974 SDOperand FIN = TheCall->getOperand(5);
975 Chain = DAG.getStore(Chain, RetVal.getValue(1), FIN, NULL, 0);
976 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(16));
977 Chain = DAG.getStore(Chain, RetVal, FIN, NULL, 0);
978 return Chain.Val;
979}
Chris Lattner2b02a442007-02-25 08:29:00 +0000980
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000981//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000982// C & StdCall & Fast Calling Convention implementation
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000983//===----------------------------------------------------------------------===//
Anton Korobeynikovb10308e2007-01-28 13:31:35 +0000984// StdCall calling convention seems to be standard for many Windows' API
985// routines and around. It differs from C calling convention just a little:
986// callee should clean up the stack, not caller. Symbols should be also
987// decorated in some fancy way :) It doesn't support any vector arguments.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000988// For info on fast calling convention see Fast Calling Convention (tail call)
989// implementation LowerX86_32FastCCCallTo.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000990
Evan Cheng85e38002006-04-27 05:35:28 +0000991/// AddLiveIn - This helper function adds the specified physical register to the
992/// MachineFunction as a live in value. It also creates a corresponding virtual
993/// register for it.
994static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
Anton Korobeynikovb10308e2007-01-28 13:31:35 +0000995 const TargetRegisterClass *RC) {
Evan Cheng85e38002006-04-27 05:35:28 +0000996 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000997 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
998 MF.getRegInfo().addLiveIn(PReg, VReg);
Evan Cheng85e38002006-04-27 05:35:28 +0000999 return VReg;
1000}
1001
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001002/// CallIsStructReturn - Determines whether a CALL node uses struct return
1003/// semantics.
Gordon Henriksen86737662008-01-05 16:56:59 +00001004static bool CallIsStructReturn(SDOperand Op) {
1005 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1006 if (!NumOps)
1007 return false;
1008
1009 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(6));
1010 return Flags->getValue() & ISD::ParamFlags::StructReturn;
1011}
1012
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001013/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1014/// return semantics.
Gordon Henriksen86737662008-01-05 16:56:59 +00001015static bool ArgsAreStructReturn(SDOperand Op) {
1016 unsigned NumArgs = Op.Val->getNumValues() - 1;
1017 if (!NumArgs)
1018 return false;
1019
1020 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(3));
1021 return Flags->getValue() & ISD::ParamFlags::StructReturn;
1022}
1023
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001024/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires the
1025/// callee to pop its own arguments. Callee pop is necessary to support tail
1026/// calls.
Gordon Henriksen86737662008-01-05 16:56:59 +00001027bool X86TargetLowering::IsCalleePop(SDOperand Op) {
1028 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1029 if (IsVarArg)
1030 return false;
1031
1032 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1033 default:
1034 return false;
1035 case CallingConv::X86_StdCall:
1036 return !Subtarget->is64Bit();
1037 case CallingConv::X86_FastCall:
1038 return !Subtarget->is64Bit();
1039 case CallingConv::Fast:
1040 return PerformTailCallOpt;
1041 }
1042}
1043
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001044/// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1045/// FORMAL_ARGUMENTS node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001046CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
1047 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1048
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00001049 if (Subtarget->is64Bit()) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001050 if (CC == CallingConv::Fast && PerformTailCallOpt)
1051 return CC_X86_64_TailCall;
1052 else
1053 return CC_X86_64_C;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00001054 }
1055
Gordon Henriksen86737662008-01-05 16:56:59 +00001056 if (CC == CallingConv::X86_FastCall)
1057 return CC_X86_32_FastCall;
1058 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1059 return CC_X86_32_TailCall;
1060 else
1061 return CC_X86_32_C;
1062}
1063
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001064/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1065/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001066NameDecorationStyle
1067X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1068 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1069 if (CC == CallingConv::X86_FastCall)
1070 return FastCall;
1071 else if (CC == CallingConv::X86_StdCall)
1072 return StdCall;
1073 return None;
1074}
1075
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001076/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
1077/// possibly be overwritten when lowering the outgoing arguments in a tail
1078/// call. Currently the implementation of this call is very conservative and
1079/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
1080/// virtual registers would be overwritten by direct lowering.
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001081static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
1082 MachineFrameInfo * MFI) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001083 RegisterSDNode * OpReg = NULL;
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001084 FrameIndexSDNode * FrameIdxNode = NULL;
1085 int FrameIdx = 0;
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001086 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
1087 (Op.getOpcode()== ISD::CopyFromReg &&
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001088 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
1089 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
1090 (Op.getOpcode() == ISD::LOAD &&
1091 (FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op.getOperand(1))) &&
1092 (MFI->isFixedObjectIndex((FrameIdx = FrameIdxNode->getIndex()))) &&
1093 (MFI->getObjectOffset(FrameIdx) >= 0)))
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001094 return true;
1095 return false;
1096}
1097
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001098/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1099/// in a register before calling.
1100bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1101 return !IsTailCall && !Is64Bit &&
1102 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1103 Subtarget->isPICStyleGOT();
1104}
1105
1106
1107/// CallRequiresFnAddressInReg - Check whether the call requires the function
1108/// address to be loaded in a register.
1109bool
1110X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1111 return !Is64Bit && IsTailCall &&
1112 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1113 Subtarget->isPICStyleGOT();
1114}
1115
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001116/// CopyTailCallClobberedArgumentsToVRegs - Create virtual registers for all
1117/// arguments to force loading and guarantee that arguments sourcing from
1118/// incomming parameters are not overwriting each other.
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001119static SDOperand
1120CopyTailCallClobberedArgumentsToVRegs(SDOperand Chain,
1121 SmallVector<std::pair<unsigned, SDOperand>, 8> &TailCallClobberedVRegs,
1122 SelectionDAG &DAG,
1123 MachineFunction &MF,
1124 const TargetLowering * TL) {
1125
1126 SDOperand InFlag;
1127 for (unsigned i = 0, e = TailCallClobberedVRegs.size(); i != e; i++) {
1128 SDOperand Arg = TailCallClobberedVRegs[i].second;
1129 unsigned Idx = TailCallClobberedVRegs[i].first;
1130 unsigned VReg =
1131 MF.getRegInfo().
1132 createVirtualRegister(TL->getRegClassFor(Arg.getValueType()));
1133 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
1134 InFlag = Chain.getValue(1);
1135 Arg = DAG.getCopyFromReg(Chain, VReg, Arg.getValueType(), InFlag);
1136 TailCallClobberedVRegs[i] = std::make_pair(Idx, Arg);
1137 Chain = Arg.getValue(1);
1138 InFlag = Arg.getValue(2);
1139 }
1140 return Chain;
1141}
1142
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001143/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1144/// by "Src" to address "Dst" with size and alignment information specified by
1145/// the specific parameter attribute. The copy will be passed as a byval function
1146/// parameter.
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001147static SDOperand
Evan Cheng8e5712b2008-01-12 01:08:07 +00001148CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1149 unsigned Flags, SelectionDAG &DAG) {
1150 unsigned Align = 1 <<
1151 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1152 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001153 ISD::ParamFlags::ByValSizeOffs;
Evan Cheng8e5712b2008-01-12 01:08:07 +00001154 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1155 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001156 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32);
Evan Cheng8e5712b2008-01-12 01:08:07 +00001157 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001158}
1159
Rafael Espindola7effac52007-09-14 15:48:13 +00001160SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1161 const CCValAssign &VA,
1162 MachineFrameInfo *MFI,
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001163 unsigned CC,
Rafael Espindola7effac52007-09-14 15:48:13 +00001164 SDOperand Root, unsigned i) {
1165 // Create the nodes corresponding to a load from this parameter slot.
Evan Chenge70bb592008-01-10 02:24:25 +00001166 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001167 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
Evan Chenge70bb592008-01-10 02:24:25 +00001168 bool isByVal = Flags & ISD::ParamFlags::ByVal;
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001169 bool isImmutable = !AlwaysUseMutable && !isByVal;
Evan Chenge70bb592008-01-10 02:24:25 +00001170
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001171 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1172 // changed with more analysis.
1173 // In case of tail call optimization mark all arguments mutable. Since they
1174 // could be overwritten by lowering of arguments in case of a tail call.
Rafael Espindola7effac52007-09-14 15:48:13 +00001175 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001176 VA.getLocMemOffset(), isImmutable);
Rafael Espindola7effac52007-09-14 15:48:13 +00001177 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
Evan Chenge70bb592008-01-10 02:24:25 +00001178 if (isByVal)
Rafael Espindola7effac52007-09-14 15:48:13 +00001179 return FIN;
Dan Gohman69de1932008-02-06 22:27:42 +00001180 return DAG.getLoad(VA.getValVT(), Root, FIN,
Dan Gohman3069b872008-02-07 18:41:25 +00001181 PseudoSourceValue::getFixedStack(), FI);
Rafael Espindola7effac52007-09-14 15:48:13 +00001182}
1183
Gordon Henriksen86737662008-01-05 16:56:59 +00001184SDOperand
1185X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng1bc78042006-04-26 01:20:17 +00001186 MachineFunction &MF = DAG.getMachineFunction();
Gordon Henriksen86737662008-01-05 16:56:59 +00001187 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1188
1189 const Function* Fn = MF.getFunction();
1190 if (Fn->hasExternalLinkage() &&
1191 Subtarget->isTargetCygMing() &&
1192 Fn->getName() == "main")
1193 FuncInfo->setForceFramePointer(true);
1194
1195 // Decorate the function name.
1196 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1197
Evan Cheng1bc78042006-04-26 01:20:17 +00001198 MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng25caf632006-05-23 21:06:34 +00001199 SDOperand Root = Op.getOperand(0);
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001200 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001201 unsigned CC = MF.getFunction()->getCallingConv();
Gordon Henriksen86737662008-01-05 16:56:59 +00001202 bool Is64Bit = Subtarget->is64Bit();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001203
1204 assert(!(isVarArg && CC == CallingConv::Fast) &&
1205 "Var args not supported with calling convention fastcc");
1206
Chris Lattner638402b2007-02-28 07:00:42 +00001207 // Assign locations to all of the incoming arguments.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001208 SmallVector<CCValAssign, 16> ArgLocs;
Gordon Henriksenae636f82008-01-03 16:47:34 +00001209 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Gordon Henriksen86737662008-01-05 16:56:59 +00001210 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001211
Chris Lattnerf39f7712007-02-28 05:46:49 +00001212 SmallVector<SDOperand, 8> ArgValues;
1213 unsigned LastVal = ~0U;
1214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1215 CCValAssign &VA = ArgLocs[i];
1216 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1217 // places.
1218 assert(VA.getValNo() != LastVal &&
1219 "Don't support value assigned to multiple locs yet");
1220 LastVal = VA.getValNo();
1221
1222 if (VA.isRegLoc()) {
1223 MVT::ValueType RegVT = VA.getLocVT();
1224 TargetRegisterClass *RC;
1225 if (RegVT == MVT::i32)
1226 RC = X86::GR32RegisterClass;
Gordon Henriksen86737662008-01-05 16:56:59 +00001227 else if (Is64Bit && RegVT == MVT::i64)
1228 RC = X86::GR64RegisterClass;
Dale Johannesene672af12008-02-05 20:46:33 +00001229 else if (RegVT == MVT::f32)
Gordon Henriksen86737662008-01-05 16:56:59 +00001230 RC = X86::FR32RegisterClass;
Dale Johannesene672af12008-02-05 20:46:33 +00001231 else if (RegVT == MVT::f64)
Gordon Henriksen86737662008-01-05 16:56:59 +00001232 RC = X86::FR64RegisterClass;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001233 else {
1234 assert(MVT::isVector(RegVT));
Gordon Henriksen86737662008-01-05 16:56:59 +00001235 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
1236 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1237 RegVT = MVT::i64;
1238 } else
1239 RC = X86::VR128RegisterClass;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001240 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001241
Chris Lattner82932a52007-03-02 05:12:29 +00001242 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1243 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
Chris Lattnerf39f7712007-02-28 05:46:49 +00001244
1245 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1246 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1247 // right size.
1248 if (VA.getLocInfo() == CCValAssign::SExt)
1249 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1250 DAG.getValueType(VA.getValVT()));
1251 else if (VA.getLocInfo() == CCValAssign::ZExt)
1252 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1253 DAG.getValueType(VA.getValVT()));
1254
1255 if (VA.getLocInfo() != CCValAssign::Full)
1256 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1257
Gordon Henriksen86737662008-01-05 16:56:59 +00001258 // Handle MMX values passed in GPRs.
1259 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1260 MVT::getSizeInBits(RegVT) == 64)
1261 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1262
Chris Lattnerf39f7712007-02-28 05:46:49 +00001263 ArgValues.push_back(ArgValue);
1264 } else {
1265 assert(VA.isMemLoc());
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001266 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
Evan Cheng1bc78042006-04-26 01:20:17 +00001267 }
Evan Cheng1bc78042006-04-26 01:20:17 +00001268 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001269
Chris Lattnerf39f7712007-02-28 05:46:49 +00001270 unsigned StackSize = CCInfo.getNextStackOffset();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001271 // align stack specially for tail calls
Gordon Henriksenae636f82008-01-03 16:47:34 +00001272 if (CC == CallingConv::Fast)
1273 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
Evan Cheng25caf632006-05-23 21:06:34 +00001274
Evan Cheng1bc78042006-04-26 01:20:17 +00001275 // If the function takes variable number of arguments, make a frame index for
1276 // the start of the first vararg value... for expansion of llvm.va_start.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001277 if (isVarArg) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001278 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1279 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1280 }
1281 if (Is64Bit) {
1282 static const unsigned GPR64ArgRegs[] = {
1283 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1284 };
1285 static const unsigned XMMArgRegs[] = {
1286 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1287 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1288 };
1289
1290 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1291 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1292
1293 // For X86-64, if there are vararg parameters that are passed via
1294 // registers, then we must store them to their spots on the stack so they
1295 // may be loaded by deferencing the result of va_next.
1296 VarArgsGPOffset = NumIntRegs * 8;
1297 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1298 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1299
1300 // Store the integer parameter registers.
1301 SmallVector<SDOperand, 8> MemOps;
1302 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1303 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001304 DAG.getIntPtrConstant(VarArgsGPOffset));
Gordon Henriksen86737662008-01-05 16:56:59 +00001305 for (; NumIntRegs != 6; ++NumIntRegs) {
1306 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1307 X86::GR64RegisterClass);
1308 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
Dan Gohman69de1932008-02-06 22:27:42 +00001309 SDOperand Store =
1310 DAG.getStore(Val.getValue(1), Val, FIN,
Dan Gohman3069b872008-02-07 18:41:25 +00001311 PseudoSourceValue::getFixedStack(),
Dan Gohman69de1932008-02-06 22:27:42 +00001312 RegSaveFrameIndex);
Gordon Henriksen86737662008-01-05 16:56:59 +00001313 MemOps.push_back(Store);
1314 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001315 DAG.getIntPtrConstant(8));
Gordon Henriksen86737662008-01-05 16:56:59 +00001316 }
1317
1318 // Now store the XMM (fp + vector) parameter registers.
1319 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001320 DAG.getIntPtrConstant(VarArgsFPOffset));
Gordon Henriksen86737662008-01-05 16:56:59 +00001321 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1322 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1323 X86::VR128RegisterClass);
1324 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
Dan Gohman69de1932008-02-06 22:27:42 +00001325 SDOperand Store =
1326 DAG.getStore(Val.getValue(1), Val, FIN,
Dan Gohman3069b872008-02-07 18:41:25 +00001327 PseudoSourceValue::getFixedStack(),
Dan Gohman69de1932008-02-06 22:27:42 +00001328 RegSaveFrameIndex);
Gordon Henriksen86737662008-01-05 16:56:59 +00001329 MemOps.push_back(Store);
1330 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001331 DAG.getIntPtrConstant(16));
Gordon Henriksen86737662008-01-05 16:56:59 +00001332 }
1333 if (!MemOps.empty())
1334 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1335 &MemOps[0], MemOps.size());
1336 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001337 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001338
1339 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1340 // arguments and the arguments after the retaddr has been pushed are
1341 // aligned.
1342 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1343 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1344 (StackSize & 7) == 0)
1345 StackSize += 4;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001346
Gordon Henriksenae636f82008-01-03 16:47:34 +00001347 ArgValues.push_back(Root);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001348
Gordon Henriksen86737662008-01-05 16:56:59 +00001349 // Some CCs need callee pop.
1350 if (IsCalleePop(Op)) {
1351 BytesToPopOnReturn = StackSize; // Callee pops everything.
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001352 BytesCallerReserves = 0;
1353 } else {
Anton Korobeynikov1d9bacc2007-03-06 08:12:33 +00001354 BytesToPopOnReturn = 0; // Callee pops nothing.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001355 // If this is an sret function, the return should pop the hidden pointer.
Gordon Henriksen86737662008-01-05 16:56:59 +00001356 if (!Is64Bit && ArgsAreStructReturn(Op))
Chris Lattnerf39f7712007-02-28 05:46:49 +00001357 BytesToPopOnReturn = 4;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001358 BytesCallerReserves = StackSize;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001359 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001360
Gordon Henriksen86737662008-01-05 16:56:59 +00001361 if (!Is64Bit) {
1362 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1363 if (CC == CallingConv::X86_FastCall)
1364 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1365 }
Evan Cheng25caf632006-05-23 21:06:34 +00001366
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001367 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
Evan Cheng1bc78042006-04-26 01:20:17 +00001368
Evan Cheng25caf632006-05-23 21:06:34 +00001369 // Return the new list of results.
Chris Lattner5a88b832007-02-25 07:10:00 +00001370 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
Chris Lattner14dd4c92007-02-26 07:50:02 +00001371 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001372}
1373
Evan Chengdffbd832008-01-10 00:09:10 +00001374SDOperand
1375X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1376 const SDOperand &StackPtr,
1377 const CCValAssign &VA,
1378 SDOperand Chain,
1379 SDOperand Arg) {
Dan Gohman4fdad172008-02-07 16:28:05 +00001380 unsigned LocMemOffset = VA.getLocMemOffset();
1381 SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset);
Evan Chengdffbd832008-01-10 00:09:10 +00001382 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1383 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1384 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1385 if (Flags & ISD::ParamFlags::ByVal) {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001386 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
Evan Chengdffbd832008-01-10 00:09:10 +00001387 }
Dan Gohman4fdad172008-02-07 16:28:05 +00001388 return DAG.getStore(Chain, Arg, PtrOff,
Dan Gohman3069b872008-02-07 18:41:25 +00001389 PseudoSourceValue::getStack(), LocMemOffset);
Evan Chengdffbd832008-01-10 00:09:10 +00001390}
1391
Evan Cheng0d9e9762008-01-29 19:34:22 +00001392/// ClassifyX86_64SRetCallReturn - Classify how to implement a x86-64
1393/// struct return call to the specified function. X86-64 ABI specifies
1394/// some SRet calls are actually returned in registers. Since current
1395/// LLVM cannot represent multi-value calls, they are represent as
1396/// calls where the results are passed in a hidden struct provided by
1397/// the caller. This function examines the type of the struct to
1398/// determine the correct way to implement the call.
1399X86::X86_64SRet
1400X86TargetLowering::ClassifyX86_64SRetCallReturn(const Function *Fn) {
1401 // FIXME: Disabled for now.
1402 return X86::InMemory;
1403
1404 const PointerType *PTy = cast<PointerType>(Fn->arg_begin()->getType());
1405 const Type *RTy = PTy->getElementType();
1406 unsigned Size = getTargetData()->getABITypeSize(RTy);
1407 if (Size != 16 && Size != 32)
1408 return X86::InMemory;
1409
1410 if (Size == 32) {
1411 const StructType *STy = dyn_cast<StructType>(RTy);
1412 if (!STy) return X86::InMemory;
1413 if (STy->getNumElements() == 2 &&
1414 STy->getElementType(0) == Type::X86_FP80Ty &&
1415 STy->getElementType(1) == Type::X86_FP80Ty)
1416 return X86::InX87;
1417 }
1418
1419 bool AllFP = true;
1420 for (Type::subtype_iterator I = RTy->subtype_begin(), E = RTy->subtype_end();
1421 I != E; ++I) {
1422 const Type *STy = I->get();
1423 if (!STy->isFPOrFPVector()) {
1424 AllFP = false;
1425 break;
1426 }
1427 }
1428
1429 if (AllFP)
1430 return X86::InSSE;
1431 return X86::InGPR64;
1432}
1433
1434void X86TargetLowering::X86_64AnalyzeSRetCallOperands(SDNode *TheCall,
1435 CCAssignFn *Fn,
1436 CCState &CCInfo) {
1437 unsigned NumOps = (TheCall->getNumOperands() - 5) / 2;
1438 for (unsigned i = 1; i != NumOps; ++i) {
1439 MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType();
1440 SDOperand FlagOp = TheCall->getOperand(5+2*i+1);
1441 unsigned ArgFlags =cast<ConstantSDNode>(FlagOp)->getValue();
1442 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) {
1443 cerr << "Call operand #" << i << " has unhandled type "
1444 << MVT::getValueTypeString(ArgVT) << "\n";
1445 abort();
1446 }
1447 }
1448}
1449
Gordon Henriksen86737662008-01-05 16:56:59 +00001450SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1451 MachineFunction &MF = DAG.getMachineFunction();
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001452 MachineFrameInfo * MFI = MF.getFrameInfo();
Evan Cheng32fe1032006-05-25 00:59:30 +00001453 SDOperand Chain = Op.getOperand(0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001454 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001455 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
Gordon Henriksen86737662008-01-05 16:56:59 +00001456 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1457 && CC == CallingConv::Fast && PerformTailCallOpt;
Evan Cheng32fe1032006-05-25 00:59:30 +00001458 SDOperand Callee = Op.getOperand(4);
Gordon Henriksen86737662008-01-05 16:56:59 +00001459 bool Is64Bit = Subtarget->is64Bit();
Evan Cheng0d9e9762008-01-29 19:34:22 +00001460 bool IsStructRet = CallIsStructReturn(Op);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001461
1462 assert(!(isVarArg && CC == CallingConv::Fast) &&
1463 "Var args not supported with calling convention fastcc");
1464
Chris Lattner638402b2007-02-28 07:00:42 +00001465 // Analyze operands of the call, assigning locations to each operand.
Chris Lattner423c5f42007-02-28 05:31:48 +00001466 SmallVector<CCValAssign, 16> ArgLocs;
Chris Lattner52387be2007-06-19 00:13:10 +00001467 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Evan Cheng0d9e9762008-01-29 19:34:22 +00001468 CCAssignFn *CCFn = CCAssignFnForNode(Op);
1469
1470 X86::X86_64SRet SRetMethod = X86::InMemory;
1471 if (Is64Bit && IsStructRet)
1472 // FIXME: We can't figure out type of the sret structure for indirect
1473 // calls. We need to copy more information from CallSite to the ISD::CALL
1474 // node.
1475 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1476 SRetMethod =
1477 ClassifyX86_64SRetCallReturn(dyn_cast<Function>(G->getGlobal()));
1478
1479 // UGLY HACK! For x86-64, some 128-bit aggregates are returns in a pair of
1480 // registers. Unfortunately, llvm does not support i128 yet so we pretend it's
1481 // a sret call.
1482 if (SRetMethod != X86::InMemory)
1483 X86_64AnalyzeSRetCallOperands(Op.Val, CCFn, CCInfo);
1484 else
1485 CCInfo.AnalyzeCallOperands(Op.Val, CCFn);
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001486
Chris Lattner423c5f42007-02-28 05:31:48 +00001487 // Get a count of how many bytes are to be pushed on the stack.
1488 unsigned NumBytes = CCInfo.getNextStackOffset();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001489 if (CC == CallingConv::Fast)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001490 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001491
Gordon Henriksen86737662008-01-05 16:56:59 +00001492 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1493 // arguments and the arguments after the retaddr has been pushed are aligned.
1494 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1495 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1496 (NumBytes & 7) == 0)
1497 NumBytes += 4;
1498
1499 int FPDiff = 0;
1500 if (IsTailCall) {
1501 // Lower arguments at fp - stackoffset + fpdiff.
1502 unsigned NumBytesCallerPushed =
1503 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1504 FPDiff = NumBytesCallerPushed - NumBytes;
1505
1506 // Set the delta of movement of the returnaddr stackslot.
1507 // But only set if delta is greater than previous delta.
1508 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1509 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1510 }
1511
Chris Lattner0bd48932008-01-17 07:00:52 +00001512 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001513
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001514 SDOperand RetAddrFrIdx;
Gordon Henriksen86737662008-01-05 16:56:59 +00001515 if (IsTailCall) {
1516 // Adjust the Return address stack slot.
1517 if (FPDiff) {
1518 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1519 RetAddrFrIdx = getReturnAddressFrameIndex(DAG);
1520 // Load the "old" Return address.
1521 RetAddrFrIdx =
1522 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001523 Chain = SDOperand(RetAddrFrIdx.Val, 1);
1524 }
1525 }
1526
Chris Lattner5a88b832007-02-25 07:10:00 +00001527 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001528 SmallVector<std::pair<unsigned, SDOperand>, 8> TailCallClobberedVRegs;
Chris Lattner5a88b832007-02-25 07:10:00 +00001529 SmallVector<SDOperand, 8> MemOpChains;
Evan Cheng32fe1032006-05-25 00:59:30 +00001530
Chris Lattner423c5f42007-02-28 05:31:48 +00001531 SDOperand StackPtr;
Chris Lattner423c5f42007-02-28 05:31:48 +00001532
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001533 // Walk the register/memloc assignments, inserting copies/loads. For tail
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001534 // calls, remember all arguments for later special lowering.
Chris Lattner423c5f42007-02-28 05:31:48 +00001535 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1536 CCValAssign &VA = ArgLocs[i];
1537 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001538
Chris Lattner423c5f42007-02-28 05:31:48 +00001539 // Promote the value if needed.
1540 switch (VA.getLocInfo()) {
1541 default: assert(0 && "Unknown loc info!");
1542 case CCValAssign::Full: break;
1543 case CCValAssign::SExt:
1544 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1545 break;
1546 case CCValAssign::ZExt:
1547 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1548 break;
1549 case CCValAssign::AExt:
1550 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1551 break;
Evan Cheng6b5783d2006-05-25 18:56:34 +00001552 }
Chris Lattner423c5f42007-02-28 05:31:48 +00001553
1554 if (VA.isRegLoc()) {
1555 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1556 } else {
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001557 if (!IsTailCall) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001558 assert(VA.isMemLoc());
1559 if (StackPtr.Val == 0)
1560 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1561
1562 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1563 Arg));
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001564 } else if (IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
1565 TailCallClobberedVRegs.push_back(std::make_pair(i,Arg));
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001566 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001567 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001568 }
Chris Lattnerc0bdf342007-02-28 05:39:26 +00001569
Evan Cheng32fe1032006-05-25 00:59:30 +00001570 if (!MemOpChains.empty())
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001571 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1572 &MemOpChains[0], MemOpChains.size());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001573
Evan Cheng347d5f72006-04-28 21:29:37 +00001574 // Build a sequence of copy-to-reg nodes chained together with token chain
1575 // and flag operands which copy the outgoing args into registers.
1576 SDOperand InFlag;
Evan Cheng32fe1032006-05-25 00:59:30 +00001577 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1578 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1579 InFlag);
Evan Cheng347d5f72006-04-28 21:29:37 +00001580 InFlag = Chain.getValue(1);
1581 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001582
Evan Chengf4684712007-02-21 21:18:14 +00001583 // ELF / PIC requires GOT in the EBX register before function calls via PLT
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001584 // GOT pointer.
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001585 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1586 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1587 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1588 InFlag);
1589 InFlag = Chain.getValue(1);
1590 }
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001591 // If we are tail calling and generating PIC/GOT style code load the address
1592 // of the callee into ecx. The value in ecx is used as target of the tail
1593 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1594 // calls on PIC/GOT architectures. Normally we would just put the address of
1595 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1596 // restored (since ebx is callee saved) before jumping to the target@PLT.
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001597 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001598 // Note: The actual moving to ecx is done further down.
1599 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1600 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1601 !G->getGlobal()->hasProtectedVisibility())
1602 Callee = LowerGlobalAddress(Callee, DAG);
1603 else if (isa<ExternalSymbolSDNode>(Callee))
1604 Callee = LowerExternalSymbol(Callee,DAG);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00001605 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001606
Gordon Henriksen86737662008-01-05 16:56:59 +00001607 if (Is64Bit && isVarArg) {
1608 // From AMD64 ABI document:
1609 // For calls that may call functions that use varargs or stdargs
1610 // (prototype-less calls or calls to functions containing ellipsis (...) in
1611 // the declaration) %al is used as hidden argument to specify the number
1612 // of SSE registers used. The contents of %al do not need to match exactly
1613 // the number of registers, but must be an ubound on the number of SSE
1614 // registers used and is in the range 0 - 8 inclusive.
1615
1616 // Count the number of XMM registers allocated.
1617 static const unsigned XMMArgRegs[] = {
1618 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1619 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1620 };
1621 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1622
1623 Chain = DAG.getCopyToReg(Chain, X86::AL,
1624 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1625 InFlag = Chain.getValue(1);
1626 }
1627
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001628
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001629 // For tail calls lower the arguments to the 'real' stack slot.
Gordon Henriksen86737662008-01-05 16:56:59 +00001630 if (IsTailCall) {
1631 SmallVector<SDOperand, 8> MemOpChains2;
Gordon Henriksen86737662008-01-05 16:56:59 +00001632 SDOperand FIN;
1633 int FI = 0;
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001634 // Do not flag preceeding copytoreg stuff together with the following stuff.
1635 InFlag = SDOperand();
1636
1637 Chain = CopyTailCallClobberedArgumentsToVRegs(Chain, TailCallClobberedVRegs,
1638 DAG, MF, this);
1639
Gordon Henriksen86737662008-01-05 16:56:59 +00001640 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1641 CCValAssign &VA = ArgLocs[i];
1642 if (!VA.isRegLoc()) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001643 assert(VA.isMemLoc());
1644 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
Gordon Henriksen86737662008-01-05 16:56:59 +00001645 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1646 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
Gordon Henriksen86737662008-01-05 16:56:59 +00001647 // Create frame index.
1648 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1649 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1650 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1651 FIN = DAG.getFrameIndex(FI, MVT::i32);
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001652
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001653 // Find virtual register for this argument.
1654 bool Found=false;
1655 for (unsigned idx=0, e= TailCallClobberedVRegs.size(); idx < e; idx++)
1656 if (TailCallClobberedVRegs[idx].first==i) {
1657 Arg = TailCallClobberedVRegs[idx].second;
1658 Found=true;
1659 break;
1660 }
1661 assert(IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)==false ||
1662 (Found==true && "No corresponding Argument was found"));
1663
Gordon Henriksen86737662008-01-05 16:56:59 +00001664 if (Flags & ISD::ParamFlags::ByVal) {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001665 // Copy relative to framepointer.
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001666 MemOpChains2.push_back(CreateCopyOfByValArgument(Arg, FIN, Chain,
Evan Cheng8e5712b2008-01-12 01:08:07 +00001667 Flags, DAG));
Gordon Henriksen86737662008-01-05 16:56:59 +00001668 } else {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001669 // Store relative to framepointer.
Dan Gohman69de1932008-02-06 22:27:42 +00001670 MemOpChains2.push_back(
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001671 DAG.getStore(Chain, Arg, FIN,
Dan Gohman3069b872008-02-07 18:41:25 +00001672 PseudoSourceValue::getFixedStack(), FI));
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001673 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001674 }
1675 }
1676
1677 if (!MemOpChains2.empty())
1678 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
Arnold Schwaighofer719eb022008-01-11 14:34:56 +00001679 &MemOpChains2[0], MemOpChains2.size());
Gordon Henriksen86737662008-01-05 16:56:59 +00001680
1681 // Store the return address to the appropriate stack slot.
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001682 if (FPDiff) {
1683 // Calculate the new stack slot for the return address.
1684 int SlotSize = Is64Bit ? 8 : 4;
1685 int NewReturnAddrFI =
1686 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1687 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1688 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1689 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1690 PseudoSourceValue::getFixedStack(), NewReturnAddrFI);
1691 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001692 }
1693
Evan Cheng32fe1032006-05-25 00:59:30 +00001694 // If the callee is a GlobalAddress node (quite common, every direct call is)
1695 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
Anton Korobeynikova5986852006-11-20 10:46:14 +00001696 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00001697 // We should use extra load for direct calls to dllimported functions in
1698 // non-JIT mode.
Gordon Henriksen86737662008-01-05 16:56:59 +00001699 if ((IsTailCall || !Is64Bit ||
1700 getTargetMachine().getCodeModel() != CodeModel::Large)
1701 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1702 getTargetMachine(), true))
Anton Korobeynikova5986852006-11-20 10:46:14 +00001703 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
Gordon Henriksenae636f82008-01-03 16:47:34 +00001704 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001705 if (IsTailCall || !Is64Bit ||
1706 getTargetMachine().getCodeModel() != CodeModel::Large)
1707 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1708 } else if (IsTailCall) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001709 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1710
1711 Chain = DAG.getCopyToReg(Chain,
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001712 DAG.getRegister(Opc, getPointerTy()),
Gordon Henriksen86737662008-01-05 16:56:59 +00001713 Callee,InFlag);
1714 Callee = DAG.getRegister(Opc, getPointerTy());
1715 // Add register as live out.
1716 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001717 }
1718
Chris Lattnerd96d0722007-02-25 06:40:16 +00001719 // Returns a chain & a flag for retval copy to use.
1720 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner5a88b832007-02-25 07:10:00 +00001721 SmallVector<SDOperand, 8> Ops;
Gordon Henriksen86737662008-01-05 16:56:59 +00001722
1723 if (IsTailCall) {
1724 Ops.push_back(Chain);
Chris Lattner0bd48932008-01-17 07:00:52 +00001725 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1726 Ops.push_back(DAG.getIntPtrConstant(0));
Gordon Henriksen86737662008-01-05 16:56:59 +00001727 if (InFlag.Val)
1728 Ops.push_back(InFlag);
1729 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1730 InFlag = Chain.getValue(1);
1731
1732 // Returns a chain & a flag for retval copy to use.
1733 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1734 Ops.clear();
1735 }
1736
Nate Begeman4c5dcf52006-02-17 00:03:04 +00001737 Ops.push_back(Chain);
1738 Ops.push_back(Callee);
Evan Chengb69d1132006-06-14 18:17:40 +00001739
Gordon Henriksen86737662008-01-05 16:56:59 +00001740 if (IsTailCall)
1741 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
Evan Chengf4684712007-02-21 21:18:14 +00001742
1743 // Add an implicit use GOT pointer in EBX.
Gordon Henriksen86737662008-01-05 16:56:59 +00001744 if (!IsTailCall && !Is64Bit &&
1745 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Evan Chengf4684712007-02-21 21:18:14 +00001746 Subtarget->isPICStyleGOT())
1747 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
Gordon Henriksenae636f82008-01-03 16:47:34 +00001748
Gordon Henriksen86737662008-01-05 16:56:59 +00001749 // Add argument registers to the end of the list so that they are known live
1750 // into the call.
Evan Cheng9b449442008-01-07 23:08:23 +00001751 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1752 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1753 RegsToPass[i].second.getValueType()));
Gordon Henriksen86737662008-01-05 16:56:59 +00001754
Evan Cheng347d5f72006-04-28 21:29:37 +00001755 if (InFlag.Val)
1756 Ops.push_back(InFlag);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001757
Gordon Henriksen86737662008-01-05 16:56:59 +00001758 if (IsTailCall) {
1759 assert(InFlag.Val &&
1760 "Flag must be set. Depend on flag being set in LowerRET");
1761 Chain = DAG.getNode(X86ISD::TAILCALL,
1762 Op.Val->getVTList(), &Ops[0], Ops.size());
1763
1764 return SDOperand(Chain.Val, Op.ResNo);
1765 }
1766
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001767 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
Evan Cheng347d5f72006-04-28 21:29:37 +00001768 InFlag = Chain.getValue(1);
Evan Chengd90eb7f2006-01-05 00:27:02 +00001769
Chris Lattner2d297092006-05-23 18:50:38 +00001770 // Create the CALLSEQ_END node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001771 unsigned NumBytesForCalleeToPush;
1772 if (IsCalleePop(Op))
1773 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
Evan Cheng0d9e9762008-01-29 19:34:22 +00001774 else if (!Is64Bit && IsStructRet)
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001775 // If this is is a call to a struct-return function, the callee
1776 // pops the hidden struct pointer, so we have to push it back.
1777 // This is common for Darwin/X86, Linux & Mingw32 targets.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001778 NumBytesForCalleeToPush = 4;
Gordon Henriksen86737662008-01-05 16:56:59 +00001779 else
Gordon Henriksenae636f82008-01-03 16:47:34 +00001780 NumBytesForCalleeToPush = 0; // Callee pops nothing.
Gordon Henriksen86737662008-01-05 16:56:59 +00001781
Gordon Henriksenae636f82008-01-03 16:47:34 +00001782 // Returns a flag for retval copy to use.
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001783 Chain = DAG.getCALLSEQ_END(Chain,
Chris Lattner0bd48932008-01-17 07:00:52 +00001784 DAG.getIntPtrConstant(NumBytes),
1785 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001786 InFlag);
Chris Lattner3085e152007-02-25 08:59:22 +00001787 InFlag = Chain.getValue(1);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001788
Chris Lattner3085e152007-02-25 08:59:22 +00001789 // Handle result values, copying them out of physregs into vregs that we
1790 // return.
Evan Cheng0d9e9762008-01-29 19:34:22 +00001791 switch (SRetMethod) {
1792 default:
1793 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1794 case X86::InGPR64:
1795 return SDOperand(LowerCallResultToTwo64BitRegs(Chain, InFlag, Op.Val,
1796 X86::RAX, X86::RDX,
1797 MVT::i64, DAG), Op.ResNo);
1798 case X86::InSSE:
1799 return SDOperand(LowerCallResultToTwo64BitRegs(Chain, InFlag, Op.Val,
1800 X86::XMM0, X86::XMM1,
1801 MVT::f64, DAG), Op.ResNo);
1802 case X86::InX87:
1803 return SDOperand(LowerCallResultToTwoX87Regs(Chain, InFlag, Op.Val, DAG),
1804 Op.ResNo);
1805 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001806}
1807
Evan Cheng25ab6902006-09-08 06:48:29 +00001808
1809//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001810// Fast Calling Convention (tail call) implementation
1811//===----------------------------------------------------------------------===//
1812
1813// Like std call, callee cleans arguments, convention except that ECX is
1814// reserved for storing the tail called function address. Only 2 registers are
1815// free for argument passing (inreg). Tail call optimization is performed
1816// provided:
1817// * tailcallopt is enabled
1818// * caller/callee are fastcc
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001819// On X86_64 architecture with GOT-style position independent code only local
1820// (within module) calls are supported at the moment.
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001821// To keep the stack aligned according to platform abi the function
1822// GetAlignedArgumentStackSize ensures that argument delta is always multiples
1823// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001824// If a tail called function callee has more arguments than the caller the
1825// caller needs to make sure that there is room to move the RETADDR to. This is
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001826// achieved by reserving an area the size of the argument delta right after the
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001827// original REtADDR, but before the saved framepointer or the spilled registers
1828// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1829// stack layout:
1830// arg1
1831// arg2
1832// RETADDR
1833// [ new RETADDR
1834// move area ]
1835// (possible EBP)
1836// ESI
1837// EDI
1838// local1 ..
1839
1840/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1841/// for a 16 byte align requirement.
1842unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1843 SelectionDAG& DAG) {
1844 if (PerformTailCallOpt) {
1845 MachineFunction &MF = DAG.getMachineFunction();
1846 const TargetMachine &TM = MF.getTarget();
1847 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1848 unsigned StackAlignment = TFI.getStackAlignment();
1849 uint64_t AlignMask = StackAlignment - 1;
1850 int64_t Offset = StackSize;
1851 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1852 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1853 // Number smaller than 12 so just add the difference.
1854 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1855 } else {
1856 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1857 Offset = ((~AlignMask) & Offset) + StackAlignment +
1858 (StackAlignment-SlotSize);
1859 }
1860 StackSize = Offset;
1861 }
1862 return StackSize;
1863}
1864
1865/// IsEligibleForTailCallElimination - Check to see whether the next instruction
Evan Cheng9df7dc52007-11-02 01:26:22 +00001866/// following the call is a return. A function is eligible if caller/callee
1867/// calling conventions match, currently only fastcc supports tail calls, and
1868/// the function CALL is immediatly followed by a RET.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001869bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1870 SDOperand Ret,
1871 SelectionDAG& DAG) const {
Evan Cheng9df7dc52007-11-02 01:26:22 +00001872 if (!PerformTailCallOpt)
1873 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001874
1875 // Check whether CALL node immediatly preceeds the RET node and whether the
1876 // return uses the result of the node or is a void return.
Evan Cheng9df7dc52007-11-02 01:26:22 +00001877 unsigned NumOps = Ret.getNumOperands();
1878 if ((NumOps == 1 &&
1879 (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
1880 Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
Evan Chenga9d641e2007-11-02 17:45:40 +00001881 (NumOps > 1 &&
Evan Cheng9df7dc52007-11-02 01:26:22 +00001882 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
1883 Ret.getOperand(1) == SDOperand(Call.Val,0))) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001884 MachineFunction &MF = DAG.getMachineFunction();
1885 unsigned CallerCC = MF.getFunction()->getCallingConv();
1886 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1887 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1888 SDOperand Callee = Call.getOperand(4);
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001889 // On x86/32Bit PIC/GOT tail calls are supported.
Evan Cheng9df7dc52007-11-02 01:26:22 +00001890 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001891 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
Evan Cheng9df7dc52007-11-02 01:26:22 +00001892 return true;
1893
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001894 // Can only do local tail calls (in same module, hidden or protected) on
1895 // x86_64 PIC/GOT at the moment.
Gordon Henriksen86737662008-01-05 16:56:59 +00001896 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1897 return G->getGlobal()->hasHiddenVisibility()
1898 || G->getGlobal()->hasProtectedVisibility();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001899 }
1900 }
Evan Cheng9df7dc52007-11-02 01:26:22 +00001901
1902 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001903}
1904
Chris Lattnerfcf1a3d2007-02-28 06:10:12 +00001905//===----------------------------------------------------------------------===//
1906// Other Lowering Hooks
1907//===----------------------------------------------------------------------===//
1908
1909
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001910SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001911 MachineFunction &MF = DAG.getMachineFunction();
1912 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1913 int ReturnAddrIndex = FuncInfo->getRAIndex();
1914
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001915 if (ReturnAddrIndex == 0) {
1916 // Set up a frame object for the return address.
Evan Cheng25ab6902006-09-08 06:48:29 +00001917 if (Subtarget->is64Bit())
1918 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1919 else
1920 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001921
1922 FuncInfo->setRAIndex(ReturnAddrIndex);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001923 }
1924
Evan Cheng25ab6902006-09-08 06:48:29 +00001925 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001926}
1927
1928
1929
Evan Cheng6dfa9992006-01-30 23:41:35 +00001930/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1931/// specific condition code. It returns a false if it cannot do a direct
Chris Lattnerf9570512006-09-13 03:22:10 +00001932/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1933/// needed.
Evan Cheng6be2c582006-04-05 23:38:46 +00001934static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
Chris Lattnerf9570512006-09-13 03:22:10 +00001935 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1936 SelectionDAG &DAG) {
Chris Lattner7fbe9722006-10-20 17:42:20 +00001937 X86CC = X86::COND_INVALID;
Evan Chengd9558e02006-01-06 00:43:03 +00001938 if (!isFP) {
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001939 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1940 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1941 // X > -1 -> X == 0, jump !sign.
1942 RHS = DAG.getConstant(0, RHS.getValueType());
Chris Lattner7fbe9722006-10-20 17:42:20 +00001943 X86CC = X86::COND_NS;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001944 return true;
1945 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1946 // X < 0 -> X == 0, jump on sign.
Chris Lattner7fbe9722006-10-20 17:42:20 +00001947 X86CC = X86::COND_S;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001948 return true;
Dan Gohman5f6913c2007-09-17 14:49:27 +00001949 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1950 // X < 1 -> X <= 0
1951 RHS = DAG.getConstant(0, RHS.getValueType());
1952 X86CC = X86::COND_LE;
1953 return true;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001954 }
Chris Lattnerf9570512006-09-13 03:22:10 +00001955 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001956
Evan Chengd9558e02006-01-06 00:43:03 +00001957 switch (SetCCOpcode) {
1958 default: break;
Chris Lattner7fbe9722006-10-20 17:42:20 +00001959 case ISD::SETEQ: X86CC = X86::COND_E; break;
1960 case ISD::SETGT: X86CC = X86::COND_G; break;
1961 case ISD::SETGE: X86CC = X86::COND_GE; break;
1962 case ISD::SETLT: X86CC = X86::COND_L; break;
1963 case ISD::SETLE: X86CC = X86::COND_LE; break;
1964 case ISD::SETNE: X86CC = X86::COND_NE; break;
1965 case ISD::SETULT: X86CC = X86::COND_B; break;
1966 case ISD::SETUGT: X86CC = X86::COND_A; break;
1967 case ISD::SETULE: X86CC = X86::COND_BE; break;
1968 case ISD::SETUGE: X86CC = X86::COND_AE; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001969 }
1970 } else {
1971 // On a floating point condition, the flags are set as follows:
1972 // ZF PF CF op
1973 // 0 | 0 | 0 | X > Y
1974 // 0 | 0 | 1 | X < Y
1975 // 1 | 0 | 0 | X == Y
1976 // 1 | 1 | 1 | unordered
Chris Lattnerf9570512006-09-13 03:22:10 +00001977 bool Flip = false;
Evan Chengd9558e02006-01-06 00:43:03 +00001978 switch (SetCCOpcode) {
1979 default: break;
1980 case ISD::SETUEQ:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001981 case ISD::SETEQ: X86CC = X86::COND_E; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001982 case ISD::SETOLT: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001983 case ISD::SETOGT:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001984 case ISD::SETGT: X86CC = X86::COND_A; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001985 case ISD::SETOLE: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001986 case ISD::SETOGE:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001987 case ISD::SETGE: X86CC = X86::COND_AE; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001988 case ISD::SETUGT: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001989 case ISD::SETULT:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001990 case ISD::SETLT: X86CC = X86::COND_B; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001991 case ISD::SETUGE: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001992 case ISD::SETULE:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001993 case ISD::SETLE: X86CC = X86::COND_BE; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001994 case ISD::SETONE:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001995 case ISD::SETNE: X86CC = X86::COND_NE; break;
1996 case ISD::SETUO: X86CC = X86::COND_P; break;
1997 case ISD::SETO: X86CC = X86::COND_NP; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001998 }
Chris Lattnerf9570512006-09-13 03:22:10 +00001999 if (Flip)
2000 std::swap(LHS, RHS);
Evan Chengd9558e02006-01-06 00:43:03 +00002001 }
Evan Cheng6dfa9992006-01-30 23:41:35 +00002002
Chris Lattner7fbe9722006-10-20 17:42:20 +00002003 return X86CC != X86::COND_INVALID;
Evan Chengd9558e02006-01-06 00:43:03 +00002004}
2005
Evan Cheng4a460802006-01-11 00:33:36 +00002006/// hasFPCMov - is there a floating point cmov for the specific X86 condition
2007/// code. Current x86 isa includes the following FP cmov instructions:
Evan Chengaaca22c2006-01-10 20:26:56 +00002008/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Evan Cheng4a460802006-01-11 00:33:36 +00002009static bool hasFPCMov(unsigned X86CC) {
Evan Chengaaca22c2006-01-10 20:26:56 +00002010 switch (X86CC) {
2011 default:
2012 return false;
Chris Lattner7fbe9722006-10-20 17:42:20 +00002013 case X86::COND_B:
2014 case X86::COND_BE:
2015 case X86::COND_E:
2016 case X86::COND_P:
2017 case X86::COND_A:
2018 case X86::COND_AE:
2019 case X86::COND_NE:
2020 case X86::COND_NP:
Evan Chengaaca22c2006-01-10 20:26:56 +00002021 return true;
2022 }
2023}
2024
Evan Cheng5ced1d82006-04-06 23:23:56 +00002025/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
Evan Chengc5cdff22006-04-07 21:53:05 +00002026/// true if Op is undef or if its value falls within the specified range (L, H].
Evan Cheng5ced1d82006-04-06 23:23:56 +00002027static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
2028 if (Op.getOpcode() == ISD::UNDEF)
2029 return true;
2030
2031 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
Evan Chengc5cdff22006-04-07 21:53:05 +00002032 return (Val >= Low && Val < Hi);
2033}
2034
2035/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2036/// true if Op is undef or if its value equal to the specified value.
2037static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
2038 if (Op.getOpcode() == ISD::UNDEF)
2039 return true;
2040 return cast<ConstantSDNode>(Op)->getValue() == Val;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002041}
2042
Evan Cheng0188ecb2006-03-22 18:59:22 +00002043/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2044/// specifies a shuffle of elements that is suitable for input to PSHUFD.
2045bool X86::isPSHUFDMask(SDNode *N) {
2046 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2047
Dan Gohman7f55fcb2007-08-02 21:17:01 +00002048 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
Evan Cheng0188ecb2006-03-22 18:59:22 +00002049 return false;
2050
2051 // Check if the value doesn't reference the second vector.
Evan Cheng506d3df2006-03-29 23:07:14 +00002052 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002053 SDOperand Arg = N->getOperand(i);
2054 if (Arg.getOpcode() == ISD::UNDEF) continue;
2055 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohman7f55fcb2007-08-02 21:17:01 +00002056 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
Evan Cheng506d3df2006-03-29 23:07:14 +00002057 return false;
2058 }
2059
2060 return true;
2061}
2062
2063/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Chengc21a0532006-04-05 01:47:37 +00002064/// specifies a shuffle of elements that is suitable for input to PSHUFHW.
Evan Cheng506d3df2006-03-29 23:07:14 +00002065bool X86::isPSHUFHWMask(SDNode *N) {
2066 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2067
2068 if (N->getNumOperands() != 8)
2069 return false;
2070
2071 // Lower quadword copied in order.
2072 for (unsigned i = 0; i != 4; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002073 SDOperand Arg = N->getOperand(i);
2074 if (Arg.getOpcode() == ISD::UNDEF) continue;
2075 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2076 if (cast<ConstantSDNode>(Arg)->getValue() != i)
Evan Cheng506d3df2006-03-29 23:07:14 +00002077 return false;
2078 }
2079
2080 // Upper quadword shuffled.
2081 for (unsigned i = 4; i != 8; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002082 SDOperand Arg = N->getOperand(i);
2083 if (Arg.getOpcode() == ISD::UNDEF) continue;
2084 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2085 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002086 if (Val < 4 || Val > 7)
2087 return false;
2088 }
2089
2090 return true;
2091}
2092
2093/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Chengc21a0532006-04-05 01:47:37 +00002094/// specifies a shuffle of elements that is suitable for input to PSHUFLW.
Evan Cheng506d3df2006-03-29 23:07:14 +00002095bool X86::isPSHUFLWMask(SDNode *N) {
2096 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2097
2098 if (N->getNumOperands() != 8)
2099 return false;
2100
2101 // Upper quadword copied in order.
Evan Chengc5cdff22006-04-07 21:53:05 +00002102 for (unsigned i = 4; i != 8; ++i)
2103 if (!isUndefOrEqual(N->getOperand(i), i))
Evan Cheng506d3df2006-03-29 23:07:14 +00002104 return false;
Evan Cheng506d3df2006-03-29 23:07:14 +00002105
2106 // Lower quadword shuffled.
Evan Chengc5cdff22006-04-07 21:53:05 +00002107 for (unsigned i = 0; i != 4; ++i)
2108 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
Evan Cheng506d3df2006-03-29 23:07:14 +00002109 return false;
Evan Cheng0188ecb2006-03-22 18:59:22 +00002110
2111 return true;
2112}
2113
Evan Cheng14aed5e2006-03-24 01:18:28 +00002114/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2115/// specifies a shuffle of elements that is suitable for input to SHUFP*.
Chris Lattner5a88b832007-02-25 07:10:00 +00002116static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
Evan Cheng39623da2006-04-20 08:58:49 +00002117 if (NumElems != 2 && NumElems != 4) return false;
Evan Cheng14aed5e2006-03-24 01:18:28 +00002118
Evan Cheng39623da2006-04-20 08:58:49 +00002119 unsigned Half = NumElems / 2;
2120 for (unsigned i = 0; i < Half; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00002121 if (!isUndefOrInRange(Elems[i], 0, NumElems))
Evan Cheng39623da2006-04-20 08:58:49 +00002122 return false;
2123 for (unsigned i = Half; i < NumElems; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00002124 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
Evan Cheng39623da2006-04-20 08:58:49 +00002125 return false;
Evan Cheng14aed5e2006-03-24 01:18:28 +00002126
2127 return true;
2128}
2129
Evan Cheng39623da2006-04-20 08:58:49 +00002130bool X86::isSHUFPMask(SDNode *N) {
2131 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002132 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002133}
2134
Evan Cheng213d2cf2007-05-17 18:45:50 +00002135/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
Evan Cheng39623da2006-04-20 08:58:49 +00002136/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2137/// half elements to come from vector 1 (which would equal the dest.) and
2138/// the upper half to come from vector 2.
Chris Lattner5a88b832007-02-25 07:10:00 +00002139static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
2140 if (NumOps != 2 && NumOps != 4) return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002141
Chris Lattner5a88b832007-02-25 07:10:00 +00002142 unsigned Half = NumOps / 2;
Evan Cheng39623da2006-04-20 08:58:49 +00002143 for (unsigned i = 0; i < Half; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00002144 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
Evan Cheng39623da2006-04-20 08:58:49 +00002145 return false;
Chris Lattner5a88b832007-02-25 07:10:00 +00002146 for (unsigned i = Half; i < NumOps; ++i)
2147 if (!isUndefOrInRange(Ops[i], 0, NumOps))
Evan Cheng39623da2006-04-20 08:58:49 +00002148 return false;
2149 return true;
2150}
2151
2152static bool isCommutedSHUFP(SDNode *N) {
2153 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002154 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002155}
2156
Evan Cheng2c0dbd02006-03-24 02:58:06 +00002157/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2158/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2159bool X86::isMOVHLPSMask(SDNode *N) {
2160 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2161
Evan Cheng2064a2b2006-03-28 06:50:32 +00002162 if (N->getNumOperands() != 4)
Evan Cheng2c0dbd02006-03-24 02:58:06 +00002163 return false;
2164
Evan Cheng2064a2b2006-03-28 06:50:32 +00002165 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
Evan Chengc5cdff22006-04-07 21:53:05 +00002166 return isUndefOrEqual(N->getOperand(0), 6) &&
2167 isUndefOrEqual(N->getOperand(1), 7) &&
2168 isUndefOrEqual(N->getOperand(2), 2) &&
2169 isUndefOrEqual(N->getOperand(3), 3);
Evan Cheng2064a2b2006-03-28 06:50:32 +00002170}
2171
Evan Cheng6e56e2c2006-11-07 22:14:24 +00002172/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2173/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2174/// <2, 3, 2, 3>
2175bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2176 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2177
2178 if (N->getNumOperands() != 4)
2179 return false;
2180
2181 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2182 return isUndefOrEqual(N->getOperand(0), 2) &&
2183 isUndefOrEqual(N->getOperand(1), 3) &&
2184 isUndefOrEqual(N->getOperand(2), 2) &&
2185 isUndefOrEqual(N->getOperand(3), 3);
2186}
2187
Evan Cheng5ced1d82006-04-06 23:23:56 +00002188/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2189/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2190bool X86::isMOVLPMask(SDNode *N) {
2191 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2192
2193 unsigned NumElems = N->getNumOperands();
2194 if (NumElems != 2 && NumElems != 4)
2195 return false;
2196
Evan Chengc5cdff22006-04-07 21:53:05 +00002197 for (unsigned i = 0; i < NumElems/2; ++i)
2198 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2199 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002200
Evan Chengc5cdff22006-04-07 21:53:05 +00002201 for (unsigned i = NumElems/2; i < NumElems; ++i)
2202 if (!isUndefOrEqual(N->getOperand(i), i))
2203 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002204
2205 return true;
2206}
2207
2208/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Cheng533a0aa2006-04-19 20:35:22 +00002209/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2210/// and MOVLHPS.
Evan Cheng5ced1d82006-04-06 23:23:56 +00002211bool X86::isMOVHPMask(SDNode *N) {
2212 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2213
2214 unsigned NumElems = N->getNumOperands();
2215 if (NumElems != 2 && NumElems != 4)
2216 return false;
2217
Evan Chengc5cdff22006-04-07 21:53:05 +00002218 for (unsigned i = 0; i < NumElems/2; ++i)
2219 if (!isUndefOrEqual(N->getOperand(i), i))
2220 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002221
2222 for (unsigned i = 0; i < NumElems/2; ++i) {
2223 SDOperand Arg = N->getOperand(i + NumElems/2);
Evan Chengc5cdff22006-04-07 21:53:05 +00002224 if (!isUndefOrEqual(Arg, i + NumElems))
2225 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002226 }
2227
2228 return true;
2229}
2230
Evan Cheng0038e592006-03-28 00:39:58 +00002231/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2232/// specifies a shuffle of elements that is suitable for input to UNPCKL.
Chris Lattner5a88b832007-02-25 07:10:00 +00002233bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
2234 bool V2IsSplat = false) {
2235 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng0038e592006-03-28 00:39:58 +00002236 return false;
2237
Chris Lattner5a88b832007-02-25 07:10:00 +00002238 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2239 SDOperand BitI = Elts[i];
2240 SDOperand BitI1 = Elts[i+1];
Evan Chengc5cdff22006-04-07 21:53:05 +00002241 if (!isUndefOrEqual(BitI, j))
2242 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002243 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002244 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002245 return false;
2246 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002247 if (!isUndefOrEqual(BitI1, j + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002248 return false;
2249 }
Evan Cheng0038e592006-03-28 00:39:58 +00002250 }
2251
2252 return true;
2253}
2254
Evan Cheng39623da2006-04-20 08:58:49 +00002255bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2256 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002257 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002258}
2259
Evan Cheng4fcb9222006-03-28 02:43:26 +00002260/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2261/// specifies a shuffle of elements that is suitable for input to UNPCKH.
Chris Lattner5a88b832007-02-25 07:10:00 +00002262bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2263 bool V2IsSplat = false) {
2264 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng4fcb9222006-03-28 02:43:26 +00002265 return false;
2266
Chris Lattner5a88b832007-02-25 07:10:00 +00002267 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2268 SDOperand BitI = Elts[i];
2269 SDOperand BitI1 = Elts[i+1];
2270 if (!isUndefOrEqual(BitI, j + NumElts/2))
Evan Chengc5cdff22006-04-07 21:53:05 +00002271 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002272 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002273 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002274 return false;
2275 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002276 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002277 return false;
2278 }
Evan Cheng4fcb9222006-03-28 02:43:26 +00002279 }
2280
2281 return true;
2282}
2283
Evan Cheng39623da2006-04-20 08:58:49 +00002284bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2285 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002286 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002287}
2288
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002289/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2290/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2291/// <0, 0, 1, 1>
2292bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2293 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2294
2295 unsigned NumElems = N->getNumOperands();
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002296 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002297 return false;
2298
2299 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2300 SDOperand BitI = N->getOperand(i);
2301 SDOperand BitI1 = N->getOperand(i+1);
2302
Evan Chengc5cdff22006-04-07 21:53:05 +00002303 if (!isUndefOrEqual(BitI, j))
2304 return false;
2305 if (!isUndefOrEqual(BitI1, j))
2306 return false;
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002307 }
2308
2309 return true;
2310}
2311
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002312/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2313/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2314/// <2, 2, 3, 3>
2315bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2316 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2317
2318 unsigned NumElems = N->getNumOperands();
2319 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2320 return false;
2321
2322 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2323 SDOperand BitI = N->getOperand(i);
2324 SDOperand BitI1 = N->getOperand(i + 1);
2325
2326 if (!isUndefOrEqual(BitI, j))
2327 return false;
2328 if (!isUndefOrEqual(BitI1, j))
2329 return false;
2330 }
2331
2332 return true;
2333}
2334
Evan Cheng017dcc62006-04-21 01:05:10 +00002335/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2336/// specifies a shuffle of elements that is suitable for input to MOVSS,
2337/// MOVSD, and MOVD, i.e. setting the lowest element.
Chris Lattner5a88b832007-02-25 07:10:00 +00002338static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
Evan Cheng10762102007-12-06 22:14:22 +00002339 if (NumElts != 2 && NumElts != 4)
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002340 return false;
2341
Chris Lattner5a88b832007-02-25 07:10:00 +00002342 if (!isUndefOrEqual(Elts[0], NumElts))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002343 return false;
2344
Chris Lattner5a88b832007-02-25 07:10:00 +00002345 for (unsigned i = 1; i < NumElts; ++i) {
2346 if (!isUndefOrEqual(Elts[i], i))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002347 return false;
2348 }
2349
2350 return true;
2351}
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002352
Evan Cheng017dcc62006-04-21 01:05:10 +00002353bool X86::isMOVLMask(SDNode *N) {
Evan Cheng39623da2006-04-20 08:58:49 +00002354 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002355 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002356}
2357
Evan Cheng017dcc62006-04-21 01:05:10 +00002358/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2359/// of what x86 movss want. X86 movs requires the lowest element to be lowest
Evan Cheng39623da2006-04-20 08:58:49 +00002360/// element of vector 2 and the other elements to come from vector 1 in order.
Chris Lattner5a88b832007-02-25 07:10:00 +00002361static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2362 bool V2IsSplat = false,
Evan Cheng8cf723d2006-09-08 01:50:06 +00002363 bool V2IsUndef = false) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002364 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
Evan Cheng39623da2006-04-20 08:58:49 +00002365 return false;
2366
2367 if (!isUndefOrEqual(Ops[0], 0))
2368 return false;
2369
Chris Lattner5a88b832007-02-25 07:10:00 +00002370 for (unsigned i = 1; i < NumOps; ++i) {
Evan Cheng39623da2006-04-20 08:58:49 +00002371 SDOperand Arg = Ops[i];
Chris Lattner5a88b832007-02-25 07:10:00 +00002372 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2373 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2374 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
Evan Cheng8cf723d2006-09-08 01:50:06 +00002375 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002376 }
2377
2378 return true;
2379}
2380
Evan Cheng8cf723d2006-09-08 01:50:06 +00002381static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2382 bool V2IsUndef = false) {
Evan Cheng39623da2006-04-20 08:58:49 +00002383 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002384 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2385 V2IsSplat, V2IsUndef);
Evan Cheng39623da2006-04-20 08:58:49 +00002386}
2387
Evan Chengd9539472006-04-14 21:59:03 +00002388/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2389/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2390bool X86::isMOVSHDUPMask(SDNode *N) {
2391 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2392
2393 if (N->getNumOperands() != 4)
2394 return false;
2395
2396 // Expect 1, 1, 3, 3
2397 for (unsigned i = 0; i < 2; ++i) {
2398 SDOperand Arg = N->getOperand(i);
2399 if (Arg.getOpcode() == ISD::UNDEF) continue;
2400 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2401 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2402 if (Val != 1) return false;
2403 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002404
2405 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002406 for (unsigned i = 2; i < 4; ++i) {
2407 SDOperand Arg = N->getOperand(i);
2408 if (Arg.getOpcode() == ISD::UNDEF) continue;
2409 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2410 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2411 if (Val != 3) return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002412 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002413 }
Evan Cheng39fc1452006-04-15 03:13:24 +00002414
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002415 // Don't use movshdup if it can be done with a shufps.
2416 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002417}
2418
2419/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2420/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2421bool X86::isMOVSLDUPMask(SDNode *N) {
2422 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2423
2424 if (N->getNumOperands() != 4)
2425 return false;
2426
2427 // Expect 0, 0, 2, 2
2428 for (unsigned i = 0; i < 2; ++i) {
2429 SDOperand Arg = N->getOperand(i);
2430 if (Arg.getOpcode() == ISD::UNDEF) continue;
2431 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2432 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2433 if (Val != 0) return false;
2434 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002435
2436 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002437 for (unsigned i = 2; i < 4; ++i) {
2438 SDOperand Arg = N->getOperand(i);
2439 if (Arg.getOpcode() == ISD::UNDEF) continue;
2440 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2441 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2442 if (Val != 2) return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002443 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002444 }
Evan Cheng39fc1452006-04-15 03:13:24 +00002445
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002446 // Don't use movshdup if it can be done with a shufps.
2447 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002448}
2449
Evan Cheng49892af2007-06-19 00:02:56 +00002450/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2451/// specifies a identity operation on the LHS or RHS.
2452static bool isIdentityMask(SDNode *N, bool RHS = false) {
2453 unsigned NumElems = N->getNumOperands();
2454 for (unsigned i = 0; i < NumElems; ++i)
2455 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2456 return false;
2457 return true;
2458}
2459
Evan Chengb9df0ca2006-03-22 02:53:00 +00002460/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2461/// a splat of a single element.
Evan Chengc575ca22006-04-17 20:43:08 +00002462static bool isSplatMask(SDNode *N) {
Evan Chengb9df0ca2006-03-22 02:53:00 +00002463 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2464
Evan Chengb9df0ca2006-03-22 02:53:00 +00002465 // This is a splat operation if each element of the permute is the same, and
2466 // if the value doesn't reference the second vector.
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002467 unsigned NumElems = N->getNumOperands();
2468 SDOperand ElementBase;
2469 unsigned i = 0;
2470 for (; i != NumElems; ++i) {
2471 SDOperand Elt = N->getOperand(i);
Reid Spencer3ed469c2006-11-02 20:25:50 +00002472 if (isa<ConstantSDNode>(Elt)) {
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002473 ElementBase = Elt;
2474 break;
2475 }
2476 }
2477
2478 if (!ElementBase.Val)
2479 return false;
2480
2481 for (; i != NumElems; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002482 SDOperand Arg = N->getOperand(i);
2483 if (Arg.getOpcode() == ISD::UNDEF) continue;
2484 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002485 if (Arg != ElementBase) return false;
Evan Chengb9df0ca2006-03-22 02:53:00 +00002486 }
2487
2488 // Make sure it is a splat of the first vector operand.
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002489 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
Evan Chengb9df0ca2006-03-22 02:53:00 +00002490}
2491
Evan Chengc575ca22006-04-17 20:43:08 +00002492/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2493/// a splat of a single element and it's a 2 or 4 element mask.
2494bool X86::isSplatMask(SDNode *N) {
2495 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2496
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002497 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
Evan Chengc575ca22006-04-17 20:43:08 +00002498 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2499 return false;
2500 return ::isSplatMask(N);
2501}
2502
Evan Chengf686d9b2006-10-27 21:08:32 +00002503/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2504/// specifies a splat of zero element.
2505bool X86::isSplatLoMask(SDNode *N) {
2506 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2507
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002508 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
Evan Chengf686d9b2006-10-27 21:08:32 +00002509 if (!isUndefOrEqual(N->getOperand(i), 0))
2510 return false;
2511 return true;
2512}
2513
Evan Cheng63d33002006-03-22 08:01:21 +00002514/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2515/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2516/// instructions.
2517unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
Evan Chengb9df0ca2006-03-22 02:53:00 +00002518 unsigned NumOperands = N->getNumOperands();
2519 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2520 unsigned Mask = 0;
Evan Cheng36b27f32006-03-28 23:41:33 +00002521 for (unsigned i = 0; i < NumOperands; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002522 unsigned Val = 0;
2523 SDOperand Arg = N->getOperand(NumOperands-i-1);
2524 if (Arg.getOpcode() != ISD::UNDEF)
2525 Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng14aed5e2006-03-24 01:18:28 +00002526 if (Val >= NumOperands) Val -= NumOperands;
Evan Cheng63d33002006-03-22 08:01:21 +00002527 Mask |= Val;
Evan Cheng36b27f32006-03-28 23:41:33 +00002528 if (i != NumOperands - 1)
2529 Mask <<= Shift;
2530 }
Evan Cheng63d33002006-03-22 08:01:21 +00002531
2532 return Mask;
2533}
2534
Evan Cheng506d3df2006-03-29 23:07:14 +00002535/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2536/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2537/// instructions.
2538unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2539 unsigned Mask = 0;
2540 // 8 nodes, but we only care about the last 4.
2541 for (unsigned i = 7; i >= 4; --i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002542 unsigned Val = 0;
2543 SDOperand Arg = N->getOperand(i);
2544 if (Arg.getOpcode() != ISD::UNDEF)
2545 Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002546 Mask |= (Val - 4);
2547 if (i != 4)
2548 Mask <<= 2;
2549 }
2550
2551 return Mask;
2552}
2553
2554/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2555/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2556/// instructions.
2557unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2558 unsigned Mask = 0;
2559 // 8 nodes, but we only care about the first 4.
2560 for (int i = 3; i >= 0; --i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002561 unsigned Val = 0;
2562 SDOperand Arg = N->getOperand(i);
2563 if (Arg.getOpcode() != ISD::UNDEF)
2564 Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002565 Mask |= Val;
2566 if (i != 0)
2567 Mask <<= 2;
2568 }
2569
2570 return Mask;
2571}
2572
Evan Chengc21a0532006-04-05 01:47:37 +00002573/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2574/// specifies a 8 element shuffle that can be broken into a pair of
2575/// PSHUFHW and PSHUFLW.
2576static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2577 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2578
2579 if (N->getNumOperands() != 8)
2580 return false;
2581
2582 // Lower quadword shuffled.
2583 for (unsigned i = 0; i != 4; ++i) {
2584 SDOperand Arg = N->getOperand(i);
2585 if (Arg.getOpcode() == ISD::UNDEF) continue;
2586 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2587 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00002588 if (Val >= 4)
Evan Chengc21a0532006-04-05 01:47:37 +00002589 return false;
2590 }
2591
2592 // Upper quadword shuffled.
2593 for (unsigned i = 4; i != 8; ++i) {
2594 SDOperand Arg = N->getOperand(i);
2595 if (Arg.getOpcode() == ISD::UNDEF) continue;
2596 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2597 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2598 if (Val < 4 || Val > 7)
2599 return false;
2600 }
2601
2602 return true;
2603}
2604
Chris Lattner8a594482007-11-25 00:24:49 +00002605/// CommuteVectorShuffle - Swap vector_shuffle operands as well as
Evan Cheng5ced1d82006-04-06 23:23:56 +00002606/// values in ther permute mask.
Evan Cheng9eca5e82006-10-25 21:49:50 +00002607static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2608 SDOperand &V2, SDOperand &Mask,
2609 SelectionDAG &DAG) {
Evan Cheng5ced1d82006-04-06 23:23:56 +00002610 MVT::ValueType VT = Op.getValueType();
2611 MVT::ValueType MaskVT = Mask.getValueType();
Dan Gohman51eaa862007-06-14 22:58:02 +00002612 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002613 unsigned NumElems = Mask.getNumOperands();
Chris Lattner5a88b832007-02-25 07:10:00 +00002614 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002615
2616 for (unsigned i = 0; i != NumElems; ++i) {
2617 SDOperand Arg = Mask.getOperand(i);
Evan Cheng80d428c2006-04-19 22:48:17 +00002618 if (Arg.getOpcode() == ISD::UNDEF) {
2619 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2620 continue;
2621 }
Evan Cheng5ced1d82006-04-06 23:23:56 +00002622 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2623 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2624 if (Val < NumElems)
2625 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2626 else
2627 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2628 }
2629
Evan Cheng9eca5e82006-10-25 21:49:50 +00002630 std::swap(V1, V2);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002631 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
Evan Cheng9eca5e82006-10-25 21:49:50 +00002632 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002633}
2634
Evan Cheng779ccea2007-12-07 21:30:01 +00002635/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2636/// the two vector operands have swapped position.
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002637static
2638SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2639 MVT::ValueType MaskVT = Mask.getValueType();
2640 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2641 unsigned NumElems = Mask.getNumOperands();
2642 SmallVector<SDOperand, 8> MaskVec;
2643 for (unsigned i = 0; i != NumElems; ++i) {
2644 SDOperand Arg = Mask.getOperand(i);
2645 if (Arg.getOpcode() == ISD::UNDEF) {
2646 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2647 continue;
2648 }
2649 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2650 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2651 if (Val < NumElems)
2652 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2653 else
2654 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2655 }
2656 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2657}
2658
2659
Evan Cheng533a0aa2006-04-19 20:35:22 +00002660/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2661/// match movhlps. The lower half elements should come from upper half of
2662/// V1 (and in order), and the upper half elements should come from the upper
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002663/// half of V2 (and in order).
Evan Cheng533a0aa2006-04-19 20:35:22 +00002664static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2665 unsigned NumElems = Mask->getNumOperands();
2666 if (NumElems != 4)
2667 return false;
2668 for (unsigned i = 0, e = 2; i != e; ++i)
2669 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2670 return false;
2671 for (unsigned i = 2; i != 4; ++i)
2672 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2673 return false;
2674 return true;
2675}
2676
Evan Cheng5ced1d82006-04-06 23:23:56 +00002677/// isScalarLoadToVector - Returns true if the node is a scalar load that
2678/// is promoted to a vector.
Evan Cheng533a0aa2006-04-19 20:35:22 +00002679static inline bool isScalarLoadToVector(SDNode *N) {
2680 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2681 N = N->getOperand(0).Val;
Evan Cheng466685d2006-10-09 20:57:25 +00002682 return ISD::isNON_EXTLoad(N);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002683 }
2684 return false;
2685}
2686
Evan Cheng533a0aa2006-04-19 20:35:22 +00002687/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2688/// match movlp{s|d}. The lower half elements should come from lower half of
2689/// V1 (and in order), and the upper half elements should come from the upper
2690/// half of V2 (and in order). And since V1 will become the source of the
2691/// MOVLP, it must be either a vector load or a scalar load to vector.
Evan Cheng23425f52006-10-09 21:39:25 +00002692static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
Evan Cheng466685d2006-10-09 20:57:25 +00002693 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002694 return false;
Evan Cheng23425f52006-10-09 21:39:25 +00002695 // Is V2 is a vector load, don't do this transformation. We will try to use
2696 // load folding shufps op.
2697 if (ISD::isNON_EXTLoad(V2))
2698 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002699
Evan Cheng533a0aa2006-04-19 20:35:22 +00002700 unsigned NumElems = Mask->getNumOperands();
2701 if (NumElems != 2 && NumElems != 4)
2702 return false;
2703 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2704 if (!isUndefOrEqual(Mask->getOperand(i), i))
2705 return false;
2706 for (unsigned i = NumElems/2; i != NumElems; ++i)
2707 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2708 return false;
2709 return true;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002710}
2711
Evan Cheng39623da2006-04-20 08:58:49 +00002712/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2713/// all the same.
2714static bool isSplatVector(SDNode *N) {
2715 if (N->getOpcode() != ISD::BUILD_VECTOR)
2716 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002717
Evan Cheng39623da2006-04-20 08:58:49 +00002718 SDOperand SplatValue = N->getOperand(0);
2719 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2720 if (N->getOperand(i) != SplatValue)
Evan Cheng5ced1d82006-04-06 23:23:56 +00002721 return false;
2722 return true;
2723}
2724
Evan Cheng8cf723d2006-09-08 01:50:06 +00002725/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2726/// to an undef.
2727static bool isUndefShuffle(SDNode *N) {
Evan Cheng213d2cf2007-05-17 18:45:50 +00002728 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
Evan Cheng8cf723d2006-09-08 01:50:06 +00002729 return false;
2730
2731 SDOperand V1 = N->getOperand(0);
2732 SDOperand V2 = N->getOperand(1);
2733 SDOperand Mask = N->getOperand(2);
2734 unsigned NumElems = Mask.getNumOperands();
2735 for (unsigned i = 0; i != NumElems; ++i) {
2736 SDOperand Arg = Mask.getOperand(i);
2737 if (Arg.getOpcode() != ISD::UNDEF) {
2738 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2739 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2740 return false;
2741 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2742 return false;
2743 }
2744 }
2745 return true;
2746}
2747
Evan Cheng213d2cf2007-05-17 18:45:50 +00002748/// isZeroNode - Returns true if Elt is a constant zero or a floating point
2749/// constant +0.0.
2750static inline bool isZeroNode(SDOperand Elt) {
2751 return ((isa<ConstantSDNode>(Elt) &&
2752 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2753 (isa<ConstantFPSDNode>(Elt) &&
Dale Johanneseneaf08942007-08-31 04:03:46 +00002754 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
Evan Cheng213d2cf2007-05-17 18:45:50 +00002755}
2756
2757/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2758/// to an zero vector.
2759static bool isZeroShuffle(SDNode *N) {
2760 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2761 return false;
2762
2763 SDOperand V1 = N->getOperand(0);
2764 SDOperand V2 = N->getOperand(1);
2765 SDOperand Mask = N->getOperand(2);
2766 unsigned NumElems = Mask.getNumOperands();
2767 for (unsigned i = 0; i != NumElems; ++i) {
2768 SDOperand Arg = Mask.getOperand(i);
Chris Lattner8a594482007-11-25 00:24:49 +00002769 if (Arg.getOpcode() == ISD::UNDEF)
2770 continue;
2771
2772 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2773 if (Idx < NumElems) {
2774 unsigned Opc = V1.Val->getOpcode();
2775 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2776 continue;
2777 if (Opc != ISD::BUILD_VECTOR ||
2778 !isZeroNode(V1.Val->getOperand(Idx)))
2779 return false;
2780 } else if (Idx >= NumElems) {
2781 unsigned Opc = V2.Val->getOpcode();
2782 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2783 continue;
2784 if (Opc != ISD::BUILD_VECTOR ||
2785 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2786 return false;
Evan Cheng213d2cf2007-05-17 18:45:50 +00002787 }
2788 }
2789 return true;
2790}
2791
2792/// getZeroVector - Returns a vector of specified type with all zero elements.
2793///
2794static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2795 assert(MVT::isVector(VT) && "Expected a vector type");
Chris Lattner8a594482007-11-25 00:24:49 +00002796
2797 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2798 // type. This ensures they get CSE'd.
2799 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2800 SDOperand Vec;
2801 if (MVT::getSizeInBits(VT) == 64) // MMX
2802 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2803 else // SSE
2804 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2805 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
Evan Cheng213d2cf2007-05-17 18:45:50 +00002806}
2807
Chris Lattner8a594482007-11-25 00:24:49 +00002808/// getOnesVector - Returns a vector of specified type with all bits set.
2809///
2810static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2811 assert(MVT::isVector(VT) && "Expected a vector type");
2812
2813 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2814 // type. This ensures they get CSE'd.
2815 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2816 SDOperand Vec;
2817 if (MVT::getSizeInBits(VT) == 64) // MMX
2818 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2819 else // SSE
2820 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2821 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2822}
2823
2824
Evan Cheng39623da2006-04-20 08:58:49 +00002825/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2826/// that point to V2 points to its first element.
2827static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2828 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2829
2830 bool Changed = false;
Chris Lattner5a88b832007-02-25 07:10:00 +00002831 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002832 unsigned NumElems = Mask.getNumOperands();
2833 for (unsigned i = 0; i != NumElems; ++i) {
2834 SDOperand Arg = Mask.getOperand(i);
2835 if (Arg.getOpcode() != ISD::UNDEF) {
2836 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2837 if (Val > NumElems) {
2838 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2839 Changed = true;
2840 }
2841 }
2842 MaskVec.push_back(Arg);
2843 }
2844
2845 if (Changed)
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002846 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2847 &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002848 return Mask;
2849}
2850
Evan Cheng017dcc62006-04-21 01:05:10 +00002851/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2852/// operation of specified width.
2853static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
Evan Cheng39623da2006-04-20 08:58:49 +00002854 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002855 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
Evan Cheng39623da2006-04-20 08:58:49 +00002856
Chris Lattner5a88b832007-02-25 07:10:00 +00002857 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002858 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2859 for (unsigned i = 1; i != NumElems; ++i)
2860 MaskVec.push_back(DAG.getConstant(i, BaseVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002861 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002862}
2863
Evan Chengc575ca22006-04-17 20:43:08 +00002864/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2865/// of specified width.
2866static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2867 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002868 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00002869 SmallVector<SDOperand, 8> MaskVec;
Evan Chengc575ca22006-04-17 20:43:08 +00002870 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2871 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2872 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2873 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002874 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Chengc575ca22006-04-17 20:43:08 +00002875}
2876
Evan Cheng39623da2006-04-20 08:58:49 +00002877/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2878/// of specified width.
2879static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2880 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002881 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
Evan Cheng39623da2006-04-20 08:58:49 +00002882 unsigned Half = NumElems/2;
Chris Lattner5a88b832007-02-25 07:10:00 +00002883 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002884 for (unsigned i = 0; i != Half; ++i) {
2885 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2886 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2887 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002888 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002889}
2890
Chris Lattner62098042008-03-09 01:05:04 +00002891/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2892/// element #0 of a vector with the specified index, leaving the rest of the
2893/// elements in place.
2894static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2895 SelectionDAG &DAG) {
2896 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2897 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2898 SmallVector<SDOperand, 8> MaskVec;
2899 // Element #0 of the result gets the elt we are replacing.
2900 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2901 for (unsigned i = 1; i != NumElems; ++i)
2902 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2903 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2904}
2905
Evan Chengc575ca22006-04-17 20:43:08 +00002906/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2907///
2908static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2909 SDOperand V1 = Op.getOperand(0);
Evan Cheng017dcc62006-04-21 01:05:10 +00002910 SDOperand Mask = Op.getOperand(2);
Evan Chengc575ca22006-04-17 20:43:08 +00002911 MVT::ValueType VT = Op.getValueType();
Evan Cheng017dcc62006-04-21 01:05:10 +00002912 unsigned NumElems = Mask.getNumOperands();
2913 Mask = getUnpacklMask(NumElems, DAG);
Evan Chengc575ca22006-04-17 20:43:08 +00002914 while (NumElems != 4) {
Evan Cheng017dcc62006-04-21 01:05:10 +00002915 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
Evan Chengc575ca22006-04-17 20:43:08 +00002916 NumElems >>= 1;
2917 }
2918 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2919
Chris Lattner8a594482007-11-25 00:24:49 +00002920 Mask = getZeroVector(MVT::v4i32, DAG);
Evan Chengc575ca22006-04-17 20:43:08 +00002921 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
Evan Cheng017dcc62006-04-21 01:05:10 +00002922 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
Evan Chengc575ca22006-04-17 20:43:08 +00002923 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2924}
2925
Evan Chengba05f722006-04-21 23:03:30 +00002926/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
Chris Lattner8a594482007-11-25 00:24:49 +00002927/// vector of zero or undef vector. This produces a shuffle where the low
2928/// element of V2 is swizzled into the zero/undef vector, landing at element
2929/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
Chris Lattner62098042008-03-09 01:05:04 +00002930static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx,
Evan Chengba05f722006-04-21 23:03:30 +00002931 bool isZero, SelectionDAG &DAG) {
Chris Lattner62098042008-03-09 01:05:04 +00002932 MVT::ValueType VT = V2.getValueType();
Evan Chengba05f722006-04-21 23:03:30 +00002933 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
Chris Lattner62098042008-03-09 01:05:04 +00002934 unsigned NumElems = MVT::getVectorNumElements(V2.getValueType());
Evan Cheng017dcc62006-04-21 01:05:10 +00002935 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002936 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
Chris Lattner8a594482007-11-25 00:24:49 +00002937 SmallVector<SDOperand, 16> MaskVec;
2938 for (unsigned i = 0; i != NumElems; ++i)
2939 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2940 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2941 else
2942 MaskVec.push_back(DAG.getConstant(i, EVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002943 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2944 &MaskVec[0], MaskVec.size());
Evan Chengba05f722006-04-21 23:03:30 +00002945 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
Evan Cheng017dcc62006-04-21 01:05:10 +00002946}
2947
Evan Chengc78d3b42006-04-24 18:01:45 +00002948/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2949///
2950static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2951 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00002952 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00002953 if (NumNonZero > 8)
2954 return SDOperand();
2955
2956 SDOperand V(0, 0);
2957 bool First = true;
2958 for (unsigned i = 0; i < 16; ++i) {
2959 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2960 if (ThisIsNonZero && First) {
2961 if (NumZero)
2962 V = getZeroVector(MVT::v8i16, DAG);
2963 else
2964 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2965 First = false;
2966 }
2967
2968 if ((i & 1) != 0) {
2969 SDOperand ThisElt(0, 0), LastElt(0, 0);
2970 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2971 if (LastIsNonZero) {
2972 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2973 }
2974 if (ThisIsNonZero) {
2975 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2976 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2977 ThisElt, DAG.getConstant(8, MVT::i8));
2978 if (LastIsNonZero)
2979 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2980 } else
2981 ThisElt = LastElt;
2982
2983 if (ThisElt.Val)
2984 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
Chris Lattner0bd48932008-01-17 07:00:52 +00002985 DAG.getIntPtrConstant(i/2));
Evan Chengc78d3b42006-04-24 18:01:45 +00002986 }
2987 }
2988
2989 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2990}
2991
Bill Wendlinga348c562007-03-22 18:42:45 +00002992/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
Evan Chengc78d3b42006-04-24 18:01:45 +00002993///
2994static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2995 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00002996 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00002997 if (NumNonZero > 4)
2998 return SDOperand();
2999
3000 SDOperand V(0, 0);
3001 bool First = true;
3002 for (unsigned i = 0; i < 8; ++i) {
3003 bool isNonZero = (NonZeros & (1 << i)) != 0;
3004 if (isNonZero) {
3005 if (First) {
3006 if (NumZero)
3007 V = getZeroVector(MVT::v8i16, DAG);
3008 else
3009 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3010 First = false;
3011 }
3012 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
Chris Lattner0bd48932008-01-17 07:00:52 +00003013 DAG.getIntPtrConstant(i));
Evan Chengc78d3b42006-04-24 18:01:45 +00003014 }
3015 }
3016
3017 return V;
3018}
3019
Evan Cheng0db9fe62006-04-25 20:13:52 +00003020SDOperand
3021X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner8a594482007-11-25 00:24:49 +00003022 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3023 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
3024 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3025 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3026 // eliminated on x86-32 hosts.
3027 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3028 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003029
Chris Lattner8a594482007-11-25 00:24:49 +00003030 if (ISD::isBuildVectorAllOnes(Op.Val))
3031 return getOnesVector(Op.getValueType(), DAG);
3032 return getZeroVector(Op.getValueType(), DAG);
3033 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003034
3035 MVT::ValueType VT = Op.getValueType();
Dan Gohman51eaa862007-06-14 22:58:02 +00003036 MVT::ValueType EVT = MVT::getVectorElementType(VT);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003037 unsigned EVTBits = MVT::getSizeInBits(EVT);
3038
3039 unsigned NumElems = Op.getNumOperands();
3040 unsigned NumZero = 0;
3041 unsigned NumNonZero = 0;
3042 unsigned NonZeros = 0;
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003043 bool IsAllConstants = true;
Evan Cheng14b32e12007-12-11 01:46:18 +00003044 SmallSet<SDOperand, 8> Values;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003045 for (unsigned i = 0; i < NumElems; ++i) {
3046 SDOperand Elt = Op.getOperand(i);
Evan Chengdb2d5242007-12-12 06:45:40 +00003047 if (Elt.getOpcode() == ISD::UNDEF)
3048 continue;
3049 Values.insert(Elt);
3050 if (Elt.getOpcode() != ISD::Constant &&
3051 Elt.getOpcode() != ISD::ConstantFP)
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003052 IsAllConstants = false;
Evan Chengdb2d5242007-12-12 06:45:40 +00003053 if (isZeroNode(Elt))
3054 NumZero++;
3055 else {
3056 NonZeros |= (1 << i);
3057 NumNonZero++;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003058 }
3059 }
3060
Dan Gohman7f321562007-06-25 16:23:39 +00003061 if (NumNonZero == 0) {
Chris Lattner8a594482007-11-25 00:24:49 +00003062 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3063 return DAG.getNode(ISD::UNDEF, VT);
Dan Gohman7f321562007-06-25 16:23:39 +00003064 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003065
Chris Lattner67f453a2008-03-09 05:42:06 +00003066 // Special case for single non-zero, non-undef, element.
Evan Chengdb2d5242007-12-12 06:45:40 +00003067 if (NumNonZero == 1 && NumElems <= 4) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003068 unsigned Idx = CountTrailingZeros_32(NonZeros);
3069 SDOperand Item = Op.getOperand(Idx);
Chris Lattner19f79692008-03-08 22:59:52 +00003070
Chris Lattner62098042008-03-09 01:05:04 +00003071 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3072 // the value are obviously zero, truncate the value to i32 and do the
3073 // insertion that way. Only do this if the value is non-constant or if the
3074 // value is a constant being inserted into element 0. It is cheaper to do
3075 // a constant pool load than it is to do a movd + shuffle.
3076 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3077 (!IsAllConstants || Idx == 0)) {
3078 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3079 // Handle MMX and SSE both.
3080 MVT::ValueType VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3081 MVT::ValueType VecElts = VT == MVT::v2i64 ? 4 : 2;
3082
3083 // Truncate the value (which may itself be a constant) to i32, and
3084 // convert it to a vector with movd (S2V+shuffle to zero extend).
3085 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3086 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3087 Item = getShuffleVectorZeroOrUndef(Item, 0, true, DAG);
3088
3089 // Now we have our 32-bit value zero extended in the low element of
3090 // a vector. If Idx != 0, swizzle it into place.
3091 if (Idx != 0) {
3092 SDOperand Ops[] = {
3093 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3094 getSwapEltZeroMask(VecElts, Idx, DAG)
3095 };
3096 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3097 }
3098 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3099 }
3100 }
3101
Chris Lattner19f79692008-03-08 22:59:52 +00003102 // If we have a constant or non-constant insertion into the low element of
3103 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3104 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3105 // depending on what the source datatype is. Because we can only get here
3106 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3107 if (Idx == 0 &&
3108 // Don't do this for i64 values on x86-32.
3109 (EVT != MVT::i64 || Subtarget->is64Bit())) {
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003110 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003111 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
Chris Lattner62098042008-03-09 01:05:04 +00003112 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG);
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003113 }
3114
3115 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
Evan Chengdb2d5242007-12-12 06:45:40 +00003116 return SDOperand();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003117
Chris Lattner19f79692008-03-08 22:59:52 +00003118 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3119 // is a non-constant being inserted into an element other than the low one,
3120 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3121 // movd/movss) to move this into the low element, then shuffle it into
3122 // place.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003123 if (EVTBits == 32) {
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003124 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3125
Evan Cheng0db9fe62006-04-25 20:13:52 +00003126 // Turn it into a shuffle of zero and zero-extended scalar to vector.
Chris Lattner62098042008-03-09 01:05:04 +00003127 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003128 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00003129 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00003130 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003131 for (unsigned i = 0; i < NumElems; i++)
3132 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003133 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3134 &MaskVec[0], MaskVec.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003135 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3136 DAG.getNode(ISD::UNDEF, VT), Mask);
3137 }
3138 }
3139
Chris Lattner67f453a2008-03-09 05:42:06 +00003140 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3141 if (Values.size() == 1)
3142 return SDOperand();
3143
Dan Gohmana3941172007-07-24 22:55:08 +00003144 // A vector full of immediates; various special cases are already
3145 // handled, so this is best done with a single constant-pool load.
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003146 if (IsAllConstants)
Dan Gohmana3941172007-07-24 22:55:08 +00003147 return SDOperand();
3148
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003149 // Let legalizer expand 2-wide build_vectors.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003150 if (EVTBits == 64)
3151 return SDOperand();
3152
3153 // If element VT is < 32 bits, convert it to inserts into a zero vector.
Bill Wendling826f36f2007-03-28 00:57:11 +00003154 if (EVTBits == 8 && NumElems == 16) {
Evan Cheng25ab6902006-09-08 06:48:29 +00003155 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3156 *this);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003157 if (V.Val) return V;
3158 }
3159
Bill Wendling826f36f2007-03-28 00:57:11 +00003160 if (EVTBits == 16 && NumElems == 8) {
Evan Cheng25ab6902006-09-08 06:48:29 +00003161 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3162 *this);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003163 if (V.Val) return V;
3164 }
3165
3166 // If element VT is == 32 bits, turn it into a number of shuffles.
Chris Lattner5a88b832007-02-25 07:10:00 +00003167 SmallVector<SDOperand, 8> V;
3168 V.resize(NumElems);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003169 if (NumElems == 4 && NumZero > 0) {
3170 for (unsigned i = 0; i < 4; ++i) {
3171 bool isZero = !(NonZeros & (1 << i));
3172 if (isZero)
3173 V[i] = getZeroVector(VT, DAG);
3174 else
3175 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3176 }
3177
3178 for (unsigned i = 0; i < 2; ++i) {
3179 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3180 default: break;
3181 case 0:
3182 V[i] = V[i*2]; // Must be a zero vector.
3183 break;
3184 case 1:
3185 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3186 getMOVLMask(NumElems, DAG));
3187 break;
3188 case 2:
3189 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3190 getMOVLMask(NumElems, DAG));
3191 break;
3192 case 3:
3193 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3194 getUnpacklMask(NumElems, DAG));
3195 break;
3196 }
3197 }
3198
Evan Cheng069287d2006-05-16 07:21:53 +00003199 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003200 // clears the upper bits.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003201 // FIXME: we can do the same for v4f32 case when we know both parts of
3202 // the lower half come from scalar_to_vector (loadf32). We should do
3203 // that in post legalizer dag combiner with target specific hooks.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003204 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
Evan Cheng0db9fe62006-04-25 20:13:52 +00003205 return V[0];
3206 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00003207 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00003208 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003209 bool Reverse = (NonZeros & 0x3) == 2;
3210 for (unsigned i = 0; i < 2; ++i)
3211 if (Reverse)
3212 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3213 else
3214 MaskVec.push_back(DAG.getConstant(i, EVT));
3215 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3216 for (unsigned i = 0; i < 2; ++i)
3217 if (Reverse)
3218 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3219 else
3220 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
Chris Lattnere2199452006-08-11 17:38:39 +00003221 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3222 &MaskVec[0], MaskVec.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003223 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3224 }
3225
3226 if (Values.size() > 2) {
3227 // Expand into a number of unpckl*.
3228 // e.g. for v4f32
3229 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3230 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3231 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3232 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3233 for (unsigned i = 0; i < NumElems; ++i)
3234 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3235 NumElems >>= 1;
3236 while (NumElems != 0) {
3237 for (unsigned i = 0; i < NumElems; ++i)
3238 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3239 UnpckMask);
3240 NumElems >>= 1;
3241 }
3242 return V[0];
3243 }
3244
3245 return SDOperand();
3246}
3247
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003248static
3249SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
3250 SDOperand PermMask, SelectionDAG &DAG,
3251 TargetLowering &TLI) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003252 SDOperand NewV;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003253 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
3254 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
Evan Cheng14b32e12007-12-11 01:46:18 +00003255 MVT::ValueType PtrVT = TLI.getPointerTy();
3256 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
3257 PermMask.Val->op_end());
3258
3259 // First record which half of which vector the low elements come from.
3260 SmallVector<unsigned, 4> LowQuad(4);
3261 for (unsigned i = 0; i < 4; ++i) {
3262 SDOperand Elt = MaskElts[i];
3263 if (Elt.getOpcode() == ISD::UNDEF)
3264 continue;
3265 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3266 int QuadIdx = EltIdx / 4;
3267 ++LowQuad[QuadIdx];
3268 }
3269 int BestLowQuad = -1;
3270 unsigned MaxQuad = 1;
3271 for (unsigned i = 0; i < 4; ++i) {
3272 if (LowQuad[i] > MaxQuad) {
3273 BestLowQuad = i;
3274 MaxQuad = LowQuad[i];
3275 }
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003276 }
3277
Evan Cheng14b32e12007-12-11 01:46:18 +00003278 // Record which half of which vector the high elements come from.
3279 SmallVector<unsigned, 4> HighQuad(4);
3280 for (unsigned i = 4; i < 8; ++i) {
3281 SDOperand Elt = MaskElts[i];
3282 if (Elt.getOpcode() == ISD::UNDEF)
3283 continue;
3284 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3285 int QuadIdx = EltIdx / 4;
3286 ++HighQuad[QuadIdx];
3287 }
3288 int BestHighQuad = -1;
3289 MaxQuad = 1;
3290 for (unsigned i = 0; i < 4; ++i) {
3291 if (HighQuad[i] > MaxQuad) {
3292 BestHighQuad = i;
3293 MaxQuad = HighQuad[i];
3294 }
3295 }
3296
3297 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3298 if (BestLowQuad != -1 || BestHighQuad != -1) {
3299 // First sort the 4 chunks in order using shufpd.
3300 SmallVector<SDOperand, 8> MaskVec;
3301 if (BestLowQuad != -1)
3302 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3303 else
3304 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3305 if (BestHighQuad != -1)
3306 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3307 else
3308 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3309 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3310 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3311 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3312 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3313 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3314
3315 // Now sort high and low parts separately.
3316 BitVector InOrder(8);
3317 if (BestLowQuad != -1) {
3318 // Sort lower half in order using PSHUFLW.
3319 MaskVec.clear();
3320 bool AnyOutOrder = false;
3321 for (unsigned i = 0; i != 4; ++i) {
3322 SDOperand Elt = MaskElts[i];
3323 if (Elt.getOpcode() == ISD::UNDEF) {
3324 MaskVec.push_back(Elt);
3325 InOrder.set(i);
3326 } else {
3327 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3328 if (EltIdx != i)
3329 AnyOutOrder = true;
3330 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3331 // If this element is in the right place after this shuffle, then
3332 // remember it.
3333 if ((int)(EltIdx / 4) == BestLowQuad)
3334 InOrder.set(i);
3335 }
3336 }
3337 if (AnyOutOrder) {
3338 for (unsigned i = 4; i != 8; ++i)
3339 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3340 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3341 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3342 }
3343 }
3344
3345 if (BestHighQuad != -1) {
3346 // Sort high half in order using PSHUFHW if possible.
3347 MaskVec.clear();
3348 for (unsigned i = 0; i != 4; ++i)
3349 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3350 bool AnyOutOrder = false;
3351 for (unsigned i = 4; i != 8; ++i) {
3352 SDOperand Elt = MaskElts[i];
3353 if (Elt.getOpcode() == ISD::UNDEF) {
3354 MaskVec.push_back(Elt);
3355 InOrder.set(i);
3356 } else {
3357 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3358 if (EltIdx != i)
3359 AnyOutOrder = true;
3360 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3361 // If this element is in the right place after this shuffle, then
3362 // remember it.
3363 if ((int)(EltIdx / 4) == BestHighQuad)
3364 InOrder.set(i);
3365 }
3366 }
3367 if (AnyOutOrder) {
3368 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3369 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3370 }
3371 }
3372
3373 // The other elements are put in the right place using pextrw and pinsrw.
3374 for (unsigned i = 0; i != 8; ++i) {
3375 if (InOrder[i])
3376 continue;
3377 SDOperand Elt = MaskElts[i];
3378 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3379 if (EltIdx == i)
3380 continue;
3381 SDOperand ExtOp = (EltIdx < 8)
3382 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3383 DAG.getConstant(EltIdx, PtrVT))
3384 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3385 DAG.getConstant(EltIdx - 8, PtrVT));
3386 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3387 DAG.getConstant(i, PtrVT));
3388 }
3389 return NewV;
3390 }
3391
3392 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3393 ///as few as possible.
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003394 // First, let's find out how many elements are already in the right order.
3395 unsigned V1InOrder = 0;
3396 unsigned V1FromV1 = 0;
3397 unsigned V2InOrder = 0;
3398 unsigned V2FromV2 = 0;
Evan Cheng14b32e12007-12-11 01:46:18 +00003399 SmallVector<SDOperand, 8> V1Elts;
3400 SmallVector<SDOperand, 8> V2Elts;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003401 for (unsigned i = 0; i < 8; ++i) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003402 SDOperand Elt = MaskElts[i];
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003403 if (Elt.getOpcode() == ISD::UNDEF) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003404 V1Elts.push_back(Elt);
3405 V2Elts.push_back(Elt);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003406 ++V1InOrder;
3407 ++V2InOrder;
Evan Cheng14b32e12007-12-11 01:46:18 +00003408 continue;
3409 }
3410 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3411 if (EltIdx == i) {
3412 V1Elts.push_back(Elt);
3413 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3414 ++V1InOrder;
3415 } else if (EltIdx == i+8) {
3416 V1Elts.push_back(Elt);
3417 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3418 ++V2InOrder;
3419 } else if (EltIdx < 8) {
3420 V1Elts.push_back(Elt);
3421 ++V1FromV1;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003422 } else {
Evan Cheng14b32e12007-12-11 01:46:18 +00003423 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3424 ++V2FromV2;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003425 }
3426 }
3427
3428 if (V2InOrder > V1InOrder) {
3429 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3430 std::swap(V1, V2);
3431 std::swap(V1Elts, V2Elts);
3432 std::swap(V1FromV1, V2FromV2);
3433 }
3434
Evan Cheng14b32e12007-12-11 01:46:18 +00003435 if ((V1FromV1 + V1InOrder) != 8) {
3436 // Some elements are from V2.
3437 if (V1FromV1) {
3438 // If there are elements that are from V1 but out of place,
3439 // then first sort them in place
3440 SmallVector<SDOperand, 8> MaskVec;
3441 for (unsigned i = 0; i < 8; ++i) {
3442 SDOperand Elt = V1Elts[i];
3443 if (Elt.getOpcode() == ISD::UNDEF) {
3444 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3445 continue;
3446 }
3447 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3448 if (EltIdx >= 8)
3449 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3450 else
3451 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3452 }
3453 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3454 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003455 }
Evan Cheng14b32e12007-12-11 01:46:18 +00003456
3457 NewV = V1;
3458 for (unsigned i = 0; i < 8; ++i) {
3459 SDOperand Elt = V1Elts[i];
3460 if (Elt.getOpcode() == ISD::UNDEF)
3461 continue;
3462 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3463 if (EltIdx < 8)
3464 continue;
3465 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3466 DAG.getConstant(EltIdx - 8, PtrVT));
3467 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3468 DAG.getConstant(i, PtrVT));
3469 }
3470 return NewV;
3471 } else {
3472 // All elements are from V1.
3473 NewV = V1;
3474 for (unsigned i = 0; i < 8; ++i) {
3475 SDOperand Elt = V1Elts[i];
3476 if (Elt.getOpcode() == ISD::UNDEF)
3477 continue;
3478 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3479 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3480 DAG.getConstant(EltIdx, PtrVT));
3481 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3482 DAG.getConstant(i, PtrVT));
3483 }
3484 return NewV;
3485 }
3486}
3487
Evan Cheng7a831ce2007-12-15 03:00:47 +00003488/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3489/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3490/// done when every pair / quad of shuffle mask elements point to elements in
3491/// the right sequence. e.g.
Evan Cheng14b32e12007-12-11 01:46:18 +00003492/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3493static
Evan Cheng7a831ce2007-12-15 03:00:47 +00003494SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3495 MVT::ValueType VT,
Evan Cheng14b32e12007-12-11 01:46:18 +00003496 SDOperand PermMask, SelectionDAG &DAG,
3497 TargetLowering &TLI) {
3498 unsigned NumElems = PermMask.getNumOperands();
Evan Cheng7a831ce2007-12-15 03:00:47 +00003499 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3500 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3501 MVT::ValueType NewVT = MaskVT;
3502 switch (VT) {
3503 case MVT::v4f32: NewVT = MVT::v2f64; break;
3504 case MVT::v4i32: NewVT = MVT::v2i64; break;
3505 case MVT::v8i16: NewVT = MVT::v4i32; break;
3506 case MVT::v16i8: NewVT = MVT::v4i32; break;
3507 default: assert(false && "Unexpected!");
3508 }
3509
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003510 if (NewWidth == 2) {
Evan Cheng7a831ce2007-12-15 03:00:47 +00003511 if (MVT::isInteger(VT))
3512 NewVT = MVT::v2i64;
3513 else
3514 NewVT = MVT::v2f64;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003515 }
Evan Cheng7a831ce2007-12-15 03:00:47 +00003516 unsigned Scale = NumElems / NewWidth;
3517 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng14b32e12007-12-11 01:46:18 +00003518 for (unsigned i = 0; i < NumElems; i += Scale) {
3519 unsigned StartIdx = ~0U;
3520 for (unsigned j = 0; j < Scale; ++j) {
3521 SDOperand Elt = PermMask.getOperand(i+j);
3522 if (Elt.getOpcode() == ISD::UNDEF)
3523 continue;
3524 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3525 if (StartIdx == ~0U)
3526 StartIdx = EltIdx - (EltIdx % Scale);
3527 if (EltIdx != StartIdx + j)
3528 return SDOperand();
3529 }
3530 if (StartIdx == ~0U)
3531 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3532 else
3533 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003534 }
3535
Evan Cheng7a831ce2007-12-15 03:00:47 +00003536 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3537 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3538 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3539 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3540 &MaskVec[0], MaskVec.size()));
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003541}
3542
Evan Cheng0db9fe62006-04-25 20:13:52 +00003543SDOperand
3544X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3545 SDOperand V1 = Op.getOperand(0);
3546 SDOperand V2 = Op.getOperand(1);
3547 SDOperand PermMask = Op.getOperand(2);
3548 MVT::ValueType VT = Op.getValueType();
3549 unsigned NumElems = PermMask.getNumOperands();
3550 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3551 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
Evan Chengd9b8e402006-10-16 06:36:00 +00003552 bool V1IsSplat = false;
3553 bool V2IsSplat = false;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003554
Evan Cheng8cf723d2006-09-08 01:50:06 +00003555 if (isUndefShuffle(Op.Val))
3556 return DAG.getNode(ISD::UNDEF, VT);
3557
Evan Cheng213d2cf2007-05-17 18:45:50 +00003558 if (isZeroShuffle(Op.Val))
3559 return getZeroVector(VT, DAG);
3560
Evan Cheng49892af2007-06-19 00:02:56 +00003561 if (isIdentityMask(PermMask.Val))
3562 return V1;
3563 else if (isIdentityMask(PermMask.Val, true))
3564 return V2;
3565
Evan Cheng0db9fe62006-04-25 20:13:52 +00003566 if (isSplatMask(PermMask.Val)) {
3567 if (NumElems <= 4) return Op;
3568 // Promote it to a v4i32 splat.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003569 return PromoteSplat(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003570 }
3571
Evan Cheng7a831ce2007-12-15 03:00:47 +00003572 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3573 // do it!
3574 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3575 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3576 if (NewOp.Val)
3577 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3578 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3579 // FIXME: Figure out a cleaner way to do this.
3580 // Try to make use of movq to zero out the top part.
3581 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3582 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3583 if (NewOp.Val) {
3584 SDOperand NewV1 = NewOp.getOperand(0);
3585 SDOperand NewV2 = NewOp.getOperand(1);
3586 SDOperand NewMask = NewOp.getOperand(2);
3587 if (isCommutedMOVL(NewMask.Val, true, false)) {
3588 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3589 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(),
3590 NewV1, NewV2, getMOVLMask(2, DAG));
3591 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3592 }
3593 }
3594 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3595 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3596 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3597 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3598 }
3599 }
3600
Evan Cheng9bbbb982006-10-25 20:48:19 +00003601 if (X86::isMOVLMask(PermMask.Val))
3602 return (V1IsUndef) ? V2 : Op;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003603
Evan Cheng9bbbb982006-10-25 20:48:19 +00003604 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3605 X86::isMOVSLDUPMask(PermMask.Val) ||
3606 X86::isMOVHLPSMask(PermMask.Val) ||
3607 X86::isMOVHPMask(PermMask.Val) ||
3608 X86::isMOVLPMask(PermMask.Val))
3609 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003610
Evan Cheng9bbbb982006-10-25 20:48:19 +00003611 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3612 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
Evan Cheng9eca5e82006-10-25 21:49:50 +00003613 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003614
Evan Cheng9eca5e82006-10-25 21:49:50 +00003615 bool Commuted = false;
Chris Lattner8a594482007-11-25 00:24:49 +00003616 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3617 // 1,1,1,1 -> v8i16 though.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003618 V1IsSplat = isSplatVector(V1.Val);
3619 V2IsSplat = isSplatVector(V2.Val);
Chris Lattner8a594482007-11-25 00:24:49 +00003620
3621 // Canonicalize the splat or undef, if present, to be on the RHS.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003622 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
Evan Cheng9eca5e82006-10-25 21:49:50 +00003623 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00003624 std::swap(V1IsSplat, V2IsSplat);
3625 std::swap(V1IsUndef, V2IsUndef);
Evan Cheng9eca5e82006-10-25 21:49:50 +00003626 Commuted = true;
Evan Cheng9bbbb982006-10-25 20:48:19 +00003627 }
3628
Evan Cheng7a831ce2007-12-15 03:00:47 +00003629 // FIXME: Figure out a cleaner way to do this.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003630 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3631 if (V2IsUndef) return V1;
Evan Cheng9eca5e82006-10-25 21:49:50 +00003632 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00003633 if (V2IsSplat) {
3634 // V2 is a splat, so the mask may be malformed. That is, it may point
3635 // to any V2 element. The instruction selectior won't like this. Get
3636 // a corrected mask and commute to form a proper MOVS{S|D}.
3637 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3638 if (NewMask.Val != PermMask.Val)
3639 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003640 }
Evan Cheng9bbbb982006-10-25 20:48:19 +00003641 return Op;
Evan Chengd9b8e402006-10-16 06:36:00 +00003642 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003643
Evan Chengd9b8e402006-10-16 06:36:00 +00003644 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003645 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
Evan Chengd9b8e402006-10-16 06:36:00 +00003646 X86::isUNPCKLMask(PermMask.Val) ||
3647 X86::isUNPCKHMask(PermMask.Val))
3648 return Op;
Evan Chenge1113032006-10-04 18:33:38 +00003649
Evan Cheng9bbbb982006-10-25 20:48:19 +00003650 if (V2IsSplat) {
3651 // Normalize mask so all entries that point to V2 points to its first
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003652 // element then try to match unpck{h|l} again. If match, return a
Evan Cheng9bbbb982006-10-25 20:48:19 +00003653 // new vector_shuffle with the corrected mask.
3654 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3655 if (NewMask.Val != PermMask.Val) {
3656 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3657 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3658 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3659 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3660 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3661 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003662 }
3663 }
3664 }
3665
3666 // Normalize the node to match x86 shuffle ops if needed
Evan Cheng9eca5e82006-10-25 21:49:50 +00003667 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3668 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3669
3670 if (Commuted) {
3671 // Commute is back and try unpck* again.
3672 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3673 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003674 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
Evan Cheng9eca5e82006-10-25 21:49:50 +00003675 X86::isUNPCKLMask(PermMask.Val) ||
3676 X86::isUNPCKHMask(PermMask.Val))
3677 return Op;
3678 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003679
3680 // If VT is integer, try PSHUF* first, then SHUFP*.
3681 if (MVT::isInteger(VT)) {
Dan Gohman7f55fcb2007-08-02 21:17:01 +00003682 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
3683 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3684 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
3685 X86::isPSHUFDMask(PermMask.Val)) ||
Evan Cheng0db9fe62006-04-25 20:13:52 +00003686 X86::isPSHUFHWMask(PermMask.Val) ||
3687 X86::isPSHUFLWMask(PermMask.Val)) {
3688 if (V2.getOpcode() != ISD::UNDEF)
3689 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3690 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3691 return Op;
3692 }
3693
Chris Lattner07c70cd2007-05-17 17:13:13 +00003694 if (X86::isSHUFPMask(PermMask.Val) &&
3695 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003696 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003697 } else {
3698 // Floating point cases in the other order.
3699 if (X86::isSHUFPMask(PermMask.Val))
3700 return Op;
3701 if (X86::isPSHUFDMask(PermMask.Val) ||
3702 X86::isPSHUFHWMask(PermMask.Val) ||
3703 X86::isPSHUFLWMask(PermMask.Val)) {
3704 if (V2.getOpcode() != ISD::UNDEF)
3705 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3706 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3707 return Op;
3708 }
3709 }
3710
Evan Cheng14b32e12007-12-11 01:46:18 +00003711 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3712 if (VT == MVT::v8i16) {
3713 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3714 if (NewOp.Val)
3715 return NewOp;
3716 }
3717
3718 // Handle all 4 wide cases with a number of shuffles.
3719 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003720 // Don't do this for MMX.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003721 MVT::ValueType MaskVT = PermMask.getValueType();
Dan Gohman51eaa862007-06-14 22:58:02 +00003722 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00003723 SmallVector<std::pair<int, int>, 8> Locs;
Evan Cheng43f3bd32006-04-28 07:03:38 +00003724 Locs.reserve(NumElems);
Evan Cheng14b32e12007-12-11 01:46:18 +00003725 SmallVector<SDOperand, 8> Mask1(NumElems,
3726 DAG.getNode(ISD::UNDEF, MaskEVT));
3727 SmallVector<SDOperand, 8> Mask2(NumElems,
3728 DAG.getNode(ISD::UNDEF, MaskEVT));
Evan Cheng43f3bd32006-04-28 07:03:38 +00003729 unsigned NumHi = 0;
3730 unsigned NumLo = 0;
3731 // If no more than two elements come from either vector. This can be
3732 // implemented with two shuffles. First shuffle gather the elements.
3733 // The second shuffle, which takes the first shuffle as both of its
3734 // vector operands, put the elements into the right order.
3735 for (unsigned i = 0; i != NumElems; ++i) {
3736 SDOperand Elt = PermMask.getOperand(i);
3737 if (Elt.getOpcode() == ISD::UNDEF) {
3738 Locs[i] = std::make_pair(-1, -1);
3739 } else {
3740 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3741 if (Val < NumElems) {
3742 Locs[i] = std::make_pair(0, NumLo);
3743 Mask1[NumLo] = Elt;
3744 NumLo++;
3745 } else {
3746 Locs[i] = std::make_pair(1, NumHi);
3747 if (2+NumHi < NumElems)
3748 Mask1[2+NumHi] = Elt;
3749 NumHi++;
3750 }
3751 }
3752 }
3753 if (NumLo <= 2 && NumHi <= 2) {
3754 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Chris Lattnere2199452006-08-11 17:38:39 +00003755 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3756 &Mask1[0], Mask1.size()));
Evan Cheng43f3bd32006-04-28 07:03:38 +00003757 for (unsigned i = 0; i != NumElems; ++i) {
3758 if (Locs[i].first == -1)
3759 continue;
3760 else {
3761 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3762 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3763 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3764 }
3765 }
3766
3767 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
Chris Lattnere2199452006-08-11 17:38:39 +00003768 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3769 &Mask2[0], Mask2.size()));
Evan Cheng43f3bd32006-04-28 07:03:38 +00003770 }
3771
3772 // Break it into (shuffle shuffle_hi, shuffle_lo).
3773 Locs.clear();
Chris Lattner5a88b832007-02-25 07:10:00 +00003774 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3775 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3776 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003777 unsigned MaskIdx = 0;
3778 unsigned LoIdx = 0;
3779 unsigned HiIdx = NumElems/2;
3780 for (unsigned i = 0; i != NumElems; ++i) {
3781 if (i == NumElems/2) {
3782 MaskPtr = &HiMask;
3783 MaskIdx = 1;
3784 LoIdx = 0;
3785 HiIdx = NumElems/2;
3786 }
3787 SDOperand Elt = PermMask.getOperand(i);
3788 if (Elt.getOpcode() == ISD::UNDEF) {
3789 Locs[i] = std::make_pair(-1, -1);
3790 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3791 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3792 (*MaskPtr)[LoIdx] = Elt;
3793 LoIdx++;
3794 } else {
3795 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3796 (*MaskPtr)[HiIdx] = Elt;
3797 HiIdx++;
3798 }
3799 }
3800
Chris Lattner8c0c10c2006-05-16 06:45:34 +00003801 SDOperand LoShuffle =
3802 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Chris Lattnere2199452006-08-11 17:38:39 +00003803 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3804 &LoMask[0], LoMask.size()));
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003805 SDOperand HiShuffle =
Chris Lattner8c0c10c2006-05-16 06:45:34 +00003806 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Chris Lattnere2199452006-08-11 17:38:39 +00003807 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3808 &HiMask[0], HiMask.size()));
Chris Lattner5a88b832007-02-25 07:10:00 +00003809 SmallVector<SDOperand, 8> MaskOps;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003810 for (unsigned i = 0; i != NumElems; ++i) {
3811 if (Locs[i].first == -1) {
3812 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3813 } else {
3814 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3815 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3816 }
3817 }
3818 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
Chris Lattnere2199452006-08-11 17:38:39 +00003819 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3820 &MaskOps[0], MaskOps.size()));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003821 }
3822
3823 return SDOperand();
3824}
3825
3826SDOperand
Nate Begeman14d12ca2008-02-11 04:19:36 +00003827X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
3828 SelectionDAG &DAG) {
3829 MVT::ValueType VT = Op.getValueType();
3830 if (MVT::getSizeInBits(VT) == 8) {
3831 SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
3832 Op.getOperand(0), Op.getOperand(1));
3833 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3834 DAG.getValueType(VT));
3835 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3836 } else if (MVT::getSizeInBits(VT) == 16) {
3837 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
3838 Op.getOperand(0), Op.getOperand(1));
3839 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3840 DAG.getValueType(VT));
3841 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3842 }
3843 return SDOperand();
3844}
3845
3846
3847SDOperand
Evan Cheng0db9fe62006-04-25 20:13:52 +00003848X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3849 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3850 return SDOperand();
3851
Nate Begeman14d12ca2008-02-11 04:19:36 +00003852 if (Subtarget->hasSSE41())
3853 return LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
3854
Evan Cheng0db9fe62006-04-25 20:13:52 +00003855 MVT::ValueType VT = Op.getValueType();
3856 // TODO: handle v16i8.
3857 if (MVT::getSizeInBits(VT) == 16) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003858 SDOperand Vec = Op.getOperand(0);
3859 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3860 if (Idx == 0)
3861 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3862 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3863 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3864 Op.getOperand(1)));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003865 // Transform it so it match pextrw which produces a 32-bit result.
3866 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3867 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3868 Op.getOperand(0), Op.getOperand(1));
3869 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3870 DAG.getValueType(VT));
3871 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3872 } else if (MVT::getSizeInBits(VT) == 32) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003873 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3874 if (Idx == 0)
3875 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003876 // SHUFPS the element to the lowest double word, then movss.
3877 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
Chris Lattner5a88b832007-02-25 07:10:00 +00003878 SmallVector<SDOperand, 8> IdxVec;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003879 IdxVec.
3880 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3881 IdxVec.
3882 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3883 IdxVec.
3884 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3885 IdxVec.
3886 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
Chris Lattnere2199452006-08-11 17:38:39 +00003887 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3888 &IdxVec[0], IdxVec.size());
Evan Cheng14b32e12007-12-11 01:46:18 +00003889 SDOperand Vec = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003890 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Evan Cheng6e56e2c2006-11-07 22:14:24 +00003891 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003892 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
Chris Lattner0bd48932008-01-17 07:00:52 +00003893 DAG.getIntPtrConstant(0));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003894 } else if (MVT::getSizeInBits(VT) == 64) {
Nate Begeman14d12ca2008-02-11 04:19:36 +00003895 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
3896 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
3897 // to match extract_elt for f64.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003898 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3899 if (Idx == 0)
3900 return Op;
3901
3902 // UNPCKHPD the element to the lowest double word, then movsd.
3903 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3904 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3905 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
Chris Lattner5a88b832007-02-25 07:10:00 +00003906 SmallVector<SDOperand, 8> IdxVec;
Dan Gohman51eaa862007-06-14 22:58:02 +00003907 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003908 IdxVec.
3909 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
Chris Lattnere2199452006-08-11 17:38:39 +00003910 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3911 &IdxVec[0], IdxVec.size());
Evan Cheng14b32e12007-12-11 01:46:18 +00003912 SDOperand Vec = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003913 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3914 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3915 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
Chris Lattner0bd48932008-01-17 07:00:52 +00003916 DAG.getIntPtrConstant(0));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003917 }
3918
3919 return SDOperand();
3920}
3921
3922SDOperand
Nate Begeman14d12ca2008-02-11 04:19:36 +00003923X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){
3924 MVT::ValueType VT = Op.getValueType();
3925 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3926
3927 SDOperand N0 = Op.getOperand(0);
3928 SDOperand N1 = Op.getOperand(1);
3929 SDOperand N2 = Op.getOperand(2);
3930
3931 if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) {
3932 unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB
3933 : X86ISD::PINSRW;
3934 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
3935 // argument.
3936 if (N1.getValueType() != MVT::i32)
3937 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3938 if (N2.getValueType() != MVT::i32)
3939 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
3940 return DAG.getNode(Opc, VT, N0, N1, N2);
3941 } else if (EVT == MVT::f32) {
3942 // Bits [7:6] of the constant are the source select. This will always be
3943 // zero here. The DAG Combiner may combine an extract_elt index into these
3944 // bits. For example (insert (extract, 3), 2) could be matched by putting
3945 // the '3' into bits [7:6] of X86ISD::INSERTPS.
3946 // Bits [5:4] of the constant are the destination select. This is the
3947 // value of the incoming immediate.
3948 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
3949 // combine either bitwise AND or insert of float 0.0 to set these bits.
3950 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
3951 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
3952 }
3953 return SDOperand();
3954}
3955
3956SDOperand
Evan Cheng0db9fe62006-04-25 20:13:52 +00003957X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003958 MVT::ValueType VT = Op.getValueType();
Evan Cheng794405e2007-12-12 07:55:34 +00003959 MVT::ValueType EVT = MVT::getVectorElementType(VT);
Nate Begeman14d12ca2008-02-11 04:19:36 +00003960
3961 if (Subtarget->hasSSE41())
3962 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
3963
Evan Cheng794405e2007-12-12 07:55:34 +00003964 if (EVT == MVT::i8)
3965 return SDOperand();
3966
Evan Cheng0db9fe62006-04-25 20:13:52 +00003967 SDOperand N0 = Op.getOperand(0);
3968 SDOperand N1 = Op.getOperand(1);
3969 SDOperand N2 = Op.getOperand(2);
Evan Cheng794405e2007-12-12 07:55:34 +00003970
3971 if (MVT::getSizeInBits(EVT) == 16) {
3972 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3973 // as its second argument.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003974 if (N1.getValueType() != MVT::i32)
3975 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3976 if (N2.getValueType() != MVT::i32)
Chris Lattner0bd48932008-01-17 07:00:52 +00003977 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003978 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003979 }
Nate Begeman219f67f2008-01-05 20:51:30 +00003980 return SDOperand();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003981}
3982
3983SDOperand
3984X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3985 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
Evan Chengefec7512008-02-18 23:04:32 +00003986 MVT::ValueType VT = MVT::v2i32;
3987 switch (Op.getValueType()) {
3988 default: break;
3989 case MVT::v16i8:
3990 case MVT::v8i16:
3991 VT = MVT::v4i32;
3992 break;
3993 }
3994 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
3995 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003996}
3997
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003998// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
Evan Cheng0db9fe62006-04-25 20:13:52 +00003999// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4000// one of the above mentioned nodes. It has to be wrapped because otherwise
4001// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4002// be used to form addressing mode. These wrapped nodes will be selected
4003// into MOV32ri.
4004SDOperand
4005X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
4006 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Evan Chengd0ff02c2006-11-29 23:19:46 +00004007 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
4008 getPointerTy(),
4009 CP->getAlignment());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00004010 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004011 // With PIC, the address is actually $g + Offset.
4012 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4013 !Subtarget->isPICStyleRIPRel()) {
4014 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4015 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4016 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004017 }
4018
4019 return Result;
4020}
4021
4022SDOperand
4023X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
4024 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Evan Chengd0ff02c2006-11-29 23:19:46 +00004025 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
Evan Chenga844bde2008-02-02 04:07:54 +00004026 // If it's a debug information descriptor, don't mess with it.
4027 if (DAG.isVerifiedDebugInfoDesc(Op))
4028 return Result;
Evan Cheng19f2ffc2006-12-05 04:01:03 +00004029 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004030 // With PIC, the address is actually $g + Offset.
4031 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4032 !Subtarget->isPICStyleRIPRel()) {
4033 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4034 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4035 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004036 }
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00004037
4038 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4039 // load the value at address GV, not the value of GV itself. This means that
4040 // the GlobalAddress must be in the base or index register of the address, not
4041 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004042 // The same applies for external symbols during PIC codegen
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00004043 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
Dan Gohman69de1932008-02-06 22:27:42 +00004044 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
Dan Gohman3069b872008-02-07 18:41:25 +00004045 PseudoSourceValue::getGOT(), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004046
4047 return Result;
4048}
4049
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004050// Lower ISD::GlobalTLSAddress using the "general dynamic" model
4051static SDOperand
4052LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4053 const MVT::ValueType PtrVT) {
4054 SDOperand InFlag;
4055 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4056 DAG.getNode(X86ISD::GlobalBaseReg,
4057 PtrVT), InFlag);
4058 InFlag = Chain.getValue(1);
4059
4060 // emit leal symbol@TLSGD(,%ebx,1), %eax
4061 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4062 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4063 GA->getValueType(0),
4064 GA->getOffset());
4065 SDOperand Ops[] = { Chain, TGA, InFlag };
4066 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4067 InFlag = Result.getValue(2);
4068 Chain = Result.getValue(1);
4069
4070 // call ___tls_get_addr. This function receives its argument in
4071 // the register EAX.
4072 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4073 InFlag = Chain.getValue(1);
4074
4075 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4076 SDOperand Ops1[] = { Chain,
4077 DAG.getTargetExternalSymbol("___tls_get_addr",
4078 PtrVT),
4079 DAG.getRegister(X86::EAX, PtrVT),
4080 DAG.getRegister(X86::EBX, PtrVT),
4081 InFlag };
4082 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4083 InFlag = Chain.getValue(1);
4084
4085 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4086}
4087
4088// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4089// "local exec" model.
4090static SDOperand
4091LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4092 const MVT::ValueType PtrVT) {
4093 // Get the Thread Pointer
4094 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4095 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4096 // exec)
4097 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4098 GA->getValueType(0),
4099 GA->getOffset());
4100 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00004101
4102 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
Dan Gohman69de1932008-02-06 22:27:42 +00004103 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
Dan Gohman3069b872008-02-07 18:41:25 +00004104 PseudoSourceValue::getGOT(), 0);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00004105
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004106 // The address of the thread local variable is the add of the thread
4107 // pointer with the offset of the variable.
4108 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4109}
4110
4111SDOperand
4112X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
4113 // TODO: implement the "local dynamic" model
Lauro Ramos Venancio2c5c1112007-04-21 20:56:26 +00004114 // TODO: implement the "initial exec"model for pic executables
4115 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
4116 "TLS not implemented for non-ELF and 64-bit targets");
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004117 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4118 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4119 // otherwise use the "Local Exec"TLS Model
4120 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4121 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
4122 else
4123 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4124}
4125
Evan Cheng0db9fe62006-04-25 20:13:52 +00004126SDOperand
4127X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
4128 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
Evan Chengd0ff02c2006-11-29 23:19:46 +00004129 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00004130 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004131 // With PIC, the address is actually $g + Offset.
4132 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4133 !Subtarget->isPICStyleRIPRel()) {
4134 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4135 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4136 Result);
4137 }
4138
4139 return Result;
4140}
4141
4142SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
4143 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4144 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4145 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4146 // With PIC, the address is actually $g + Offset.
4147 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4148 !Subtarget->isPICStyleRIPRel()) {
4149 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4150 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4151 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004152 }
4153
4154 return Result;
4155}
4156
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004157/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4158/// take a 2 x i32 value to shift plus a shift amount.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004159SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004160 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4161 MVT::ValueType VT = Op.getValueType();
4162 unsigned VTBits = MVT::getSizeInBits(VT);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004163 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4164 SDOperand ShOpLo = Op.getOperand(0);
4165 SDOperand ShOpHi = Op.getOperand(1);
4166 SDOperand ShAmt = Op.getOperand(2);
4167 SDOperand Tmp1 = isSRA ?
Dan Gohman4c1fa612008-03-03 22:22:09 +00004168 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4169 DAG.getConstant(0, VT);
Evan Chenge3413162006-01-09 18:33:28 +00004170
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004171 SDOperand Tmp2, Tmp3;
4172 if (Op.getOpcode() == ISD::SHL_PARTS) {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004173 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4174 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004175 } else {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004176 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4177 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004178 }
Evan Chenge3413162006-01-09 18:33:28 +00004179
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004180 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4181 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
Dan Gohman4c1fa612008-03-03 22:22:09 +00004182 DAG.getConstant(VTBits, MVT::i8));
4183 SDOperand Cond = DAG.getNode(X86ISD::CMP, VT,
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004184 AndNode, DAG.getConstant(0, MVT::i8));
Evan Chenge3413162006-01-09 18:33:28 +00004185
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004186 SDOperand Hi, Lo;
4187 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Dan Gohman4c1fa612008-03-03 22:22:09 +00004188 VTs = DAG.getNodeValueTypes(VT, MVT::Flag);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004189 SmallVector<SDOperand, 4> Ops;
4190 if (Op.getOpcode() == ISD::SHL_PARTS) {
4191 Ops.push_back(Tmp2);
4192 Ops.push_back(Tmp3);
4193 Ops.push_back(CC);
4194 Ops.push_back(Cond);
Dan Gohman4c1fa612008-03-03 22:22:09 +00004195 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
Evan Chenge3413162006-01-09 18:33:28 +00004196
Evan Chenge3413162006-01-09 18:33:28 +00004197 Ops.clear();
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004198 Ops.push_back(Tmp3);
4199 Ops.push_back(Tmp1);
4200 Ops.push_back(CC);
4201 Ops.push_back(Cond);
Dan Gohman4c1fa612008-03-03 22:22:09 +00004202 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004203 } else {
4204 Ops.push_back(Tmp2);
4205 Ops.push_back(Tmp3);
4206 Ops.push_back(CC);
4207 Ops.push_back(Cond);
Dan Gohman4c1fa612008-03-03 22:22:09 +00004208 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004209
4210 Ops.clear();
4211 Ops.push_back(Tmp3);
4212 Ops.push_back(Tmp1);
4213 Ops.push_back(CC);
4214 Ops.push_back(Cond);
Dan Gohman4c1fa612008-03-03 22:22:09 +00004215 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004216 }
4217
Dan Gohman4c1fa612008-03-03 22:22:09 +00004218 VTs = DAG.getNodeValueTypes(VT, VT);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004219 Ops.clear();
4220 Ops.push_back(Lo);
4221 Ops.push_back(Hi);
4222 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004223}
Evan Chenga3195e82006-01-12 22:54:21 +00004224
Evan Cheng0db9fe62006-04-25 20:13:52 +00004225SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004226 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
Chris Lattnerb09916b2008-02-27 05:57:41 +00004227 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
4228 "Unknown SINT_TO_FP to lower!");
4229
4230 // These are really Legal; caller falls through into that case.
4231 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4232 return SDOperand();
4233 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4234 Subtarget->is64Bit())
4235 return SDOperand();
4236
Evan Cheng0db9fe62006-04-25 20:13:52 +00004237 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
4238 MachineFunction &MF = DAG.getMachineFunction();
4239 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4240 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Evan Cheng786225a2006-10-05 23:01:46 +00004241 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
Dan Gohman69de1932008-02-06 22:27:42 +00004242 StackSlot,
Dan Gohman3069b872008-02-07 18:41:25 +00004243 PseudoSourceValue::getFixedStack(),
Dan Gohman69de1932008-02-06 22:27:42 +00004244 SSFI);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004245
4246 // Build the FILD
Chris Lattner5a88b832007-02-25 07:10:00 +00004247 SDVTList Tys;
Chris Lattner78631162008-01-16 06:24:21 +00004248 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004249 if (useSSE)
Chris Lattner5a88b832007-02-25 07:10:00 +00004250 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4251 else
Dale Johannesen849f2142007-07-03 00:53:03 +00004252 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
Chris Lattner5a88b832007-02-25 07:10:00 +00004253 SmallVector<SDOperand, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004254 Ops.push_back(Chain);
4255 Ops.push_back(StackSlot);
4256 Ops.push_back(DAG.getValueType(SrcVT));
Chris Lattnerb09916b2008-02-27 05:57:41 +00004257 SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4258 Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004259
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004260 if (useSSE) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004261 Chain = Result.getValue(1);
4262 SDOperand InFlag = Result.getValue(2);
4263
4264 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4265 // shouldn't be necessary except that RFP cannot be live across
4266 // multiple blocks. When stackifier is fixed, they can be uncoupled.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004267 MachineFunction &MF = DAG.getMachineFunction();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004268 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004269 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Chris Lattner5a88b832007-02-25 07:10:00 +00004270 Tys = DAG.getVTList(MVT::Other);
4271 SmallVector<SDOperand, 8> Ops;
Evan Chenga3195e82006-01-12 22:54:21 +00004272 Ops.push_back(Chain);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004273 Ops.push_back(Result);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004274 Ops.push_back(StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004275 Ops.push_back(DAG.getValueType(Op.getValueType()));
4276 Ops.push_back(InFlag);
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004277 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
Dan Gohman69de1932008-02-06 22:27:42 +00004278 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
Dan Gohman3069b872008-02-07 18:41:25 +00004279 PseudoSourceValue::getFixedStack(), SSFI);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004280 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004281
Evan Cheng0db9fe62006-04-25 20:13:52 +00004282 return Result;
4283}
4284
Chris Lattner27a6c732007-11-24 07:07:01 +00004285std::pair<SDOperand,SDOperand> X86TargetLowering::
4286FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004287 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
4288 "Unknown FP_TO_SINT to lower!");
Evan Cheng0db9fe62006-04-25 20:13:52 +00004289
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004290 // These are really Legal.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00004291 if (Op.getValueType() == MVT::i32 &&
Chris Lattner78631162008-01-16 06:24:21 +00004292 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
Chris Lattner27a6c732007-11-24 07:07:01 +00004293 return std::make_pair(SDOperand(), SDOperand());
Dale Johannesen73328d12007-09-19 23:55:34 +00004294 if (Subtarget->is64Bit() &&
4295 Op.getValueType() == MVT::i64 &&
4296 Op.getOperand(0).getValueType() != MVT::f80)
Chris Lattner27a6c732007-11-24 07:07:01 +00004297 return std::make_pair(SDOperand(), SDOperand());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004298
Evan Cheng87c89352007-10-15 20:11:21 +00004299 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4300 // stack slot.
4301 MachineFunction &MF = DAG.getMachineFunction();
4302 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
4303 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4304 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004305 unsigned Opc;
4306 switch (Op.getValueType()) {
Chris Lattner27a6c732007-11-24 07:07:01 +00004307 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4308 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4309 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4310 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004311 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004312
Evan Cheng0db9fe62006-04-25 20:13:52 +00004313 SDOperand Chain = DAG.getEntryNode();
4314 SDOperand Value = Op.getOperand(0);
Chris Lattner78631162008-01-16 06:24:21 +00004315 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004316 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Dan Gohman69de1932008-02-06 22:27:42 +00004317 Chain = DAG.getStore(Chain, Value, StackSlot,
Dan Gohman3069b872008-02-07 18:41:25 +00004318 PseudoSourceValue::getFixedStack(), SSFI);
Dale Johannesen849f2142007-07-03 00:53:03 +00004319 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
Chris Lattner5a88b832007-02-25 07:10:00 +00004320 SDOperand Ops[] = {
4321 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4322 };
4323 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004324 Chain = Value.getValue(1);
4325 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4326 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4327 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004328
Evan Cheng0db9fe62006-04-25 20:13:52 +00004329 // Build the FP_TO_INT*_IN_MEM
Chris Lattner5a88b832007-02-25 07:10:00 +00004330 SDOperand Ops[] = { Chain, Value, StackSlot };
4331 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
Evan Chengd9558e02006-01-06 00:43:03 +00004332
Chris Lattner27a6c732007-11-24 07:07:01 +00004333 return std::make_pair(FIST, StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004334}
4335
Chris Lattner27a6c732007-11-24 07:07:01 +00004336SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner27a6c732007-11-24 07:07:01 +00004337 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
4338 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4339 if (FIST.Val == 0) return SDOperand();
4340
4341 // Load the result.
4342 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4343}
4344
4345SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4346 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
4347 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4348 if (FIST.Val == 0) return 0;
4349
4350 // Return an i64 load from the stack slot.
4351 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
4352
4353 // Use a MERGE_VALUES node to drop the chain result value.
4354 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
4355}
4356
Evan Cheng0db9fe62006-04-25 20:13:52 +00004357SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
4358 MVT::ValueType VT = Op.getValueType();
Dan Gohman20382522007-07-10 00:05:58 +00004359 MVT::ValueType EltVT = VT;
4360 if (MVT::isVector(VT))
4361 EltVT = MVT::getVectorElementType(VT);
4362 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004363 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00004364 if (EltVT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004365 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
Dan Gohman20382522007-07-10 00:05:58 +00004366 CV.push_back(C);
4367 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004368 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004369 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
Dan Gohman20382522007-07-10 00:05:58 +00004370 CV.push_back(C);
4371 CV.push_back(C);
4372 CV.push_back(C);
4373 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004374 }
Dan Gohmand3006222007-07-27 17:16:43 +00004375 Constant *C = ConstantVector::get(CV);
4376 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
Dan Gohman69de1932008-02-06 22:27:42 +00004377 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004378 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004379 false, 16);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004380 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4381}
4382
4383SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4384 MVT::ValueType VT = Op.getValueType();
Dan Gohman20382522007-07-10 00:05:58 +00004385 MVT::ValueType EltVT = VT;
Evan Chengd4d01b72007-07-19 23:36:01 +00004386 unsigned EltNum = 1;
4387 if (MVT::isVector(VT)) {
Dan Gohman20382522007-07-10 00:05:58 +00004388 EltVT = MVT::getVectorElementType(VT);
Evan Chengd4d01b72007-07-19 23:36:01 +00004389 EltNum = MVT::getVectorNumElements(VT);
4390 }
Dan Gohman20382522007-07-10 00:05:58 +00004391 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004392 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00004393 if (EltVT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004394 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
Dan Gohman20382522007-07-10 00:05:58 +00004395 CV.push_back(C);
4396 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004397 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004398 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
Dan Gohman20382522007-07-10 00:05:58 +00004399 CV.push_back(C);
4400 CV.push_back(C);
4401 CV.push_back(C);
4402 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004403 }
Dan Gohmand3006222007-07-27 17:16:43 +00004404 Constant *C = ConstantVector::get(CV);
4405 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
Dan Gohman69de1932008-02-06 22:27:42 +00004406 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004407 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004408 false, 16);
Evan Chengd4d01b72007-07-19 23:36:01 +00004409 if (MVT::isVector(VT)) {
Evan Chengd4d01b72007-07-19 23:36:01 +00004410 return DAG.getNode(ISD::BIT_CONVERT, VT,
4411 DAG.getNode(ISD::XOR, MVT::v2i64,
4412 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4413 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4414 } else {
Evan Chengd4d01b72007-07-19 23:36:01 +00004415 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4416 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004417}
4418
Evan Cheng68c47cb2007-01-05 07:55:56 +00004419SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng73d6cf12007-01-05 21:37:56 +00004420 SDOperand Op0 = Op.getOperand(0);
4421 SDOperand Op1 = Op.getOperand(1);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004422 MVT::ValueType VT = Op.getValueType();
Evan Cheng73d6cf12007-01-05 21:37:56 +00004423 MVT::ValueType SrcVT = Op1.getValueType();
Evan Cheng68c47cb2007-01-05 07:55:56 +00004424 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004425
4426 // If second operand is smaller, extend it first.
4427 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4428 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4429 SrcVT = VT;
Dale Johannesen43421b32007-09-06 18:13:44 +00004430 SrcTy = MVT::getTypeForValueType(SrcVT);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004431 }
Dale Johannesen61c7ef32007-10-21 01:07:44 +00004432 // And if it is bigger, shrink it first.
4433 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
Chris Lattner0bd48932008-01-17 07:00:52 +00004434 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
Dale Johannesen61c7ef32007-10-21 01:07:44 +00004435 SrcVT = VT;
4436 SrcTy = MVT::getTypeForValueType(SrcVT);
4437 }
4438
4439 // At this point the operands and the result should have the same
4440 // type, and that won't be f80 since that is not custom lowered.
Evan Cheng73d6cf12007-01-05 21:37:56 +00004441
Evan Cheng68c47cb2007-01-05 07:55:56 +00004442 // First get the sign bit of second operand.
4443 std::vector<Constant*> CV;
4444 if (SrcVT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004445 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
4446 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004447 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004448 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
4449 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4450 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4451 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004452 }
Dan Gohmand3006222007-07-27 17:16:43 +00004453 Constant *C = ConstantVector::get(CV);
4454 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
Dan Gohman69de1932008-02-06 22:27:42 +00004455 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004456 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004457 false, 16);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004458 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004459
4460 // Shift sign bit right or left if the two operands have different types.
4461 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4462 // Op0 is MVT::f32, Op1 is MVT::f64.
4463 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4464 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4465 DAG.getConstant(32, MVT::i32));
4466 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4467 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
Chris Lattner0bd48932008-01-17 07:00:52 +00004468 DAG.getIntPtrConstant(0));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004469 }
4470
Evan Cheng73d6cf12007-01-05 21:37:56 +00004471 // Clear first operand sign bit.
4472 CV.clear();
4473 if (VT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004474 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
4475 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00004476 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004477 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
4478 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4479 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4480 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00004481 }
Dan Gohmand3006222007-07-27 17:16:43 +00004482 C = ConstantVector::get(CV);
4483 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
Dan Gohman69de1932008-02-06 22:27:42 +00004484 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004485 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004486 false, 16);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004487 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4488
4489 // Or the value with the sign bit.
4490 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004491}
4492
Evan Chenge5f62042007-09-29 00:00:36 +00004493SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0488db92007-09-25 01:57:46 +00004494 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
Evan Cheng1a35edb2007-09-26 00:45:55 +00004495 SDOperand Cond;
Evan Cheng0488db92007-09-25 01:57:46 +00004496 SDOperand Op0 = Op.getOperand(0);
4497 SDOperand Op1 = Op.getOperand(1);
4498 SDOperand CC = Op.getOperand(2);
4499 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4500 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4501 unsigned X86CC;
4502
Evan Cheng0488db92007-09-25 01:57:46 +00004503 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
Evan Cheng1a35edb2007-09-26 00:45:55 +00004504 Op0, Op1, DAG)) {
Evan Chenge5f62042007-09-29 00:00:36 +00004505 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4506 return DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004507 DAG.getConstant(X86CC, MVT::i8), Cond);
Evan Cheng1a35edb2007-09-26 00:45:55 +00004508 }
Evan Cheng0488db92007-09-25 01:57:46 +00004509
4510 assert(isFP && "Illegal integer SetCC!");
4511
Evan Chenge5f62042007-09-29 00:00:36 +00004512 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
Evan Cheng0488db92007-09-25 01:57:46 +00004513 switch (SetCCOpcode) {
4514 default: assert(false && "Illegal floating point SetCC!");
4515 case ISD::SETOEQ: { // !PF & ZF
Evan Chenge5f62042007-09-29 00:00:36 +00004516 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004517 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004518 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004519 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4520 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4521 }
4522 case ISD::SETUNE: { // PF | !ZF
Evan Chenge5f62042007-09-29 00:00:36 +00004523 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004524 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004525 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004526 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4527 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4528 }
4529 }
4530}
4531
4532
Evan Cheng0db9fe62006-04-25 20:13:52 +00004533SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00004534 bool addTest = true;
Evan Cheng734503b2006-09-11 02:19:56 +00004535 SDOperand Cond = Op.getOperand(0);
4536 SDOperand CC;
Evan Cheng9bba8942006-01-26 02:13:10 +00004537
Evan Cheng734503b2006-09-11 02:19:56 +00004538 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00004539 Cond = LowerSETCC(Cond, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00004540
Evan Cheng3f41d662007-10-08 22:16:29 +00004541 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4542 // setting operand in place of the X86ISD::SETCC.
Evan Cheng734503b2006-09-11 02:19:56 +00004543 if (Cond.getOpcode() == X86ISD::SETCC) {
4544 CC = Cond.getOperand(0);
4545
Evan Cheng734503b2006-09-11 02:19:56 +00004546 SDOperand Cmp = Cond.getOperand(1);
4547 unsigned Opc = Cmp.getOpcode();
Evan Cheng3f41d662007-10-08 22:16:29 +00004548 MVT::ValueType VT = Op.getValueType();
Chris Lattner1956d152008-01-16 06:19:45 +00004549
Evan Cheng3f41d662007-10-08 22:16:29 +00004550 bool IllegalFPCMov = false;
Chris Lattner1956d152008-01-16 06:19:45 +00004551 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
Chris Lattner78631162008-01-16 06:24:21 +00004552 !isScalarFPTypeInSSEReg(VT)) // FPStack?
Evan Cheng3f41d662007-10-08 22:16:29 +00004553 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
Chris Lattner1956d152008-01-16 06:19:45 +00004554
Evan Chenge5f62042007-09-29 00:00:36 +00004555 if ((Opc == X86ISD::CMP ||
4556 Opc == X86ISD::COMI ||
4557 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
Evan Cheng3f41d662007-10-08 22:16:29 +00004558 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00004559 addTest = false;
4560 }
4561 }
4562
4563 if (addTest) {
4564 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Evan Cheng3f41d662007-10-08 22:16:29 +00004565 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
Evan Cheng0488db92007-09-25 01:57:46 +00004566 }
4567
4568 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4569 MVT::Flag);
4570 SmallVector<SDOperand, 4> Ops;
4571 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4572 // condition is true.
4573 Ops.push_back(Op.getOperand(2));
4574 Ops.push_back(Op.getOperand(1));
4575 Ops.push_back(CC);
4576 Ops.push_back(Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004577 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
Evan Cheng0488db92007-09-25 01:57:46 +00004578}
4579
Evan Cheng0db9fe62006-04-25 20:13:52 +00004580SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00004581 bool addTest = true;
4582 SDOperand Chain = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004583 SDOperand Cond = Op.getOperand(1);
4584 SDOperand Dest = Op.getOperand(2);
4585 SDOperand CC;
Evan Cheng734503b2006-09-11 02:19:56 +00004586
Evan Cheng0db9fe62006-04-25 20:13:52 +00004587 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00004588 Cond = LowerSETCC(Cond, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004589
Evan Cheng3f41d662007-10-08 22:16:29 +00004590 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4591 // setting operand in place of the X86ISD::SETCC.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004592 if (Cond.getOpcode() == X86ISD::SETCC) {
Evan Cheng734503b2006-09-11 02:19:56 +00004593 CC = Cond.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004594
Evan Cheng734503b2006-09-11 02:19:56 +00004595 SDOperand Cmp = Cond.getOperand(1);
4596 unsigned Opc = Cmp.getOpcode();
Evan Chenge5f62042007-09-29 00:00:36 +00004597 if (Opc == X86ISD::CMP ||
4598 Opc == X86ISD::COMI ||
4599 Opc == X86ISD::UCOMI) {
Evan Cheng3f41d662007-10-08 22:16:29 +00004600 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00004601 addTest = false;
4602 }
4603 }
4604
4605 if (addTest) {
4606 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Evan Chenge5f62042007-09-29 00:00:36 +00004607 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
Evan Cheng0488db92007-09-25 01:57:46 +00004608 }
Evan Chenge5f62042007-09-29 00:00:36 +00004609 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
Evan Cheng0488db92007-09-25 01:57:46 +00004610 Chain, Op.getOperand(2), CC, Cond);
4611}
4612
Anton Korobeynikove060b532007-04-17 19:34:00 +00004613
4614// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4615// Calls to _alloca is needed to probe the stack when allocating more than 4k
4616// bytes in one go. Touching the stack at 4K increments is necessary to ensure
4617// that the guard pages used by the OS virtual memory manager are allocated in
4618// correct sequence.
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004619SDOperand
4620X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4621 SelectionDAG &DAG) {
Anton Korobeynikove060b532007-04-17 19:34:00 +00004622 assert(Subtarget->isTargetCygMing() &&
4623 "This should be used only on Cygwin/Mingw targets");
4624
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004625 // Get the inputs.
4626 SDOperand Chain = Op.getOperand(0);
4627 SDOperand Size = Op.getOperand(1);
4628 // FIXME: Ensure alignment here
4629
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004630 SDOperand Flag;
4631
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004632 MVT::ValueType IntPtr = getPointerTy();
Chris Lattner0bd48932008-01-17 07:00:52 +00004633 MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004634
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004635 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4636 Flag = Chain.getValue(1);
4637
4638 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4639 SDOperand Ops[] = { Chain,
4640 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4641 DAG.getRegister(X86::EAX, IntPtr),
4642 Flag };
4643 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4644 Flag = Chain.getValue(1);
4645
4646 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004647
4648 std::vector<MVT::ValueType> Tys;
4649 Tys.push_back(SPTy);
4650 Tys.push_back(MVT::Other);
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004651 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4652 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004653}
4654
Evan Cheng0db9fe62006-04-25 20:13:52 +00004655SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4656 SDOperand InFlag(0, 0);
4657 SDOperand Chain = Op.getOperand(0);
4658 unsigned Align =
4659 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4660 if (Align == 0) Align = 1;
4661
4662 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
Rafael Espindola6b83b5d2007-08-27 10:18:20 +00004663 // If not DWORD aligned or size is more than the threshold, call memset.
Rafael Espindola44c82652007-08-27 17:48:26 +00004664 // The libc version is likely to be faster for these cases. It can use the
4665 // address value and run time information about the CPU.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004666 if ((Align & 3) != 0 ||
Rafael Espindolafc05f402007-10-31 11:52:06 +00004667 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004668 MVT::ValueType IntPtr = getPointerTy();
Owen Andersona69571c2006-05-03 01:29:57 +00004669 const Type *IntPtrTy = getTargetData()->getIntPtrType();
Reid Spencer47857812006-12-31 05:55:36 +00004670 TargetLowering::ArgListTy Args;
4671 TargetLowering::ArgListEntry Entry;
4672 Entry.Node = Op.getOperand(1);
4673 Entry.Ty = IntPtrTy;
Reid Spencer47857812006-12-31 05:55:36 +00004674 Args.push_back(Entry);
Reid Spenceraff93872007-01-03 17:24:59 +00004675 // Extend the unsigned i8 argument to be an int value for the call.
Reid Spencer47857812006-12-31 05:55:36 +00004676 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4677 Entry.Ty = IntPtrTy;
Reid Spencer47857812006-12-31 05:55:36 +00004678 Args.push_back(Entry);
4679 Entry.Node = Op.getOperand(3);
4680 Args.push_back(Entry);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004681 std::pair<SDOperand,SDOperand> CallResult =
Duncan Sands00fee652008-02-14 17:28:50 +00004682 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
4683 false, DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004684 return CallResult.second;
Evan Cheng48090aa2006-03-21 23:01:21 +00004685 }
Evan Chengb9df0ca2006-03-22 02:53:00 +00004686
Evan Cheng0db9fe62006-04-25 20:13:52 +00004687 MVT::ValueType AVT;
4688 SDOperand Count;
4689 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4690 unsigned BytesLeft = 0;
4691 bool TwoRepStos = false;
4692 if (ValC) {
4693 unsigned ValReg;
Evan Cheng25ab6902006-09-08 06:48:29 +00004694 uint64_t Val = ValC->getValue() & 255;
Evan Cheng5ced1d82006-04-06 23:23:56 +00004695
Evan Cheng0db9fe62006-04-25 20:13:52 +00004696 // If the value is a constant, then we can potentially use larger sets.
4697 switch (Align & 3) {
4698 case 2: // WORD aligned
4699 AVT = MVT::i16;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004700 ValReg = X86::AX;
Evan Cheng25ab6902006-09-08 06:48:29 +00004701 Val = (Val << 8) | Val;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004702 break;
Evan Cheng25ab6902006-09-08 06:48:29 +00004703 case 0: // DWORD aligned
Evan Cheng0db9fe62006-04-25 20:13:52 +00004704 AVT = MVT::i32;
Evan Cheng25ab6902006-09-08 06:48:29 +00004705 ValReg = X86::EAX;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004706 Val = (Val << 8) | Val;
4707 Val = (Val << 16) | Val;
Evan Cheng25ab6902006-09-08 06:48:29 +00004708 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4709 AVT = MVT::i64;
4710 ValReg = X86::RAX;
4711 Val = (Val << 32) | Val;
4712 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004713 break;
4714 default: // Byte aligned
4715 AVT = MVT::i8;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004716 ValReg = X86::AL;
Evan Cheng25ab6902006-09-08 06:48:29 +00004717 Count = Op.getOperand(3);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004718 break;
Evan Cheng80d428c2006-04-19 22:48:17 +00004719 }
4720
Evan Cheng25ab6902006-09-08 06:48:29 +00004721 if (AVT > MVT::i8) {
4722 if (I) {
4723 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
Chris Lattner0bd48932008-01-17 07:00:52 +00004724 Count = DAG.getIntPtrConstant(I->getValue() / UBytes);
Evan Cheng25ab6902006-09-08 06:48:29 +00004725 BytesLeft = I->getValue() % UBytes;
4726 } else {
4727 assert(AVT >= MVT::i32 &&
4728 "Do not use rep;stos if not at least DWORD aligned");
4729 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4730 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4731 TwoRepStos = true;
4732 }
4733 }
4734
Evan Cheng0db9fe62006-04-25 20:13:52 +00004735 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4736 InFlag);
4737 InFlag = Chain.getValue(1);
4738 } else {
4739 AVT = MVT::i8;
4740 Count = Op.getOperand(3);
4741 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4742 InFlag = Chain.getValue(1);
Evan Chengb9df0ca2006-03-22 02:53:00 +00004743 }
Evan Chengc78d3b42006-04-24 18:01:45 +00004744
Evan Cheng25ab6902006-09-08 06:48:29 +00004745 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4746 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004747 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00004748 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4749 Op.getOperand(1), InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004750 InFlag = Chain.getValue(1);
Evan Chenga0b3afb2006-03-27 07:00:16 +00004751
Chris Lattnerd96d0722007-02-25 06:40:16 +00004752 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner5a88b832007-02-25 07:10:00 +00004753 SmallVector<SDOperand, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004754 Ops.push_back(Chain);
4755 Ops.push_back(DAG.getValueType(AVT));
4756 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00004757 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
Evan Chengc78d3b42006-04-24 18:01:45 +00004758
Evan Cheng0db9fe62006-04-25 20:13:52 +00004759 if (TwoRepStos) {
4760 InFlag = Chain.getValue(1);
4761 Count = Op.getOperand(3);
4762 MVT::ValueType CVT = Count.getValueType();
4763 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
Evan Cheng25ab6902006-09-08 06:48:29 +00004764 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4765 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4766 Left, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004767 InFlag = Chain.getValue(1);
Chris Lattnerd96d0722007-02-25 06:40:16 +00004768 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004769 Ops.clear();
4770 Ops.push_back(Chain);
4771 Ops.push_back(DAG.getValueType(MVT::i8));
4772 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00004773 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004774 } else if (BytesLeft) {
Evan Cheng25ab6902006-09-08 06:48:29 +00004775 // Issue stores for the last 1 - 7 bytes.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004776 SDOperand Value;
4777 unsigned Val = ValC->getValue() & 255;
4778 unsigned Offset = I->getValue() - BytesLeft;
4779 SDOperand DstAddr = Op.getOperand(1);
4780 MVT::ValueType AddrVT = DstAddr.getValueType();
Evan Cheng25ab6902006-09-08 06:48:29 +00004781 if (BytesLeft >= 4) {
4782 Val = (Val << 8) | Val;
4783 Val = (Val << 16) | Val;
4784 Value = DAG.getConstant(Val, MVT::i32);
Evan Cheng786225a2006-10-05 23:01:46 +00004785 Chain = DAG.getStore(Chain, Value,
4786 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4787 DAG.getConstant(Offset, AddrVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004788 NULL, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004789 BytesLeft -= 4;
4790 Offset += 4;
4791 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004792 if (BytesLeft >= 2) {
4793 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
Evan Cheng786225a2006-10-05 23:01:46 +00004794 Chain = DAG.getStore(Chain, Value,
4795 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4796 DAG.getConstant(Offset, AddrVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004797 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004798 BytesLeft -= 2;
4799 Offset += 2;
Evan Cheng386031a2006-03-24 07:29:27 +00004800 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004801 if (BytesLeft == 1) {
4802 Value = DAG.getConstant(Val, MVT::i8);
Evan Cheng786225a2006-10-05 23:01:46 +00004803 Chain = DAG.getStore(Chain, Value,
4804 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4805 DAG.getConstant(Offset, AddrVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004806 NULL, 0);
Evan Chengba05f722006-04-21 23:03:30 +00004807 }
Evan Cheng386031a2006-03-24 07:29:27 +00004808 }
Evan Cheng11e15b32006-04-03 20:53:28 +00004809
Evan Cheng0db9fe62006-04-25 20:13:52 +00004810 return Chain;
4811}
Evan Cheng11e15b32006-04-03 20:53:28 +00004812
Rafael Espindola068317b2007-09-28 12:53:01 +00004813SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
4814 SDOperand Dest,
4815 SDOperand Source,
4816 unsigned Size,
4817 unsigned Align,
4818 SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004819 MVT::ValueType AVT;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004820 unsigned BytesLeft = 0;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004821 switch (Align & 3) {
4822 case 2: // WORD aligned
4823 AVT = MVT::i16;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004824 break;
Evan Cheng25ab6902006-09-08 06:48:29 +00004825 case 0: // DWORD aligned
Evan Cheng0db9fe62006-04-25 20:13:52 +00004826 AVT = MVT::i32;
Evan Cheng25ab6902006-09-08 06:48:29 +00004827 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4828 AVT = MVT::i64;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004829 break;
4830 default: // Byte aligned
4831 AVT = MVT::i8;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004832 break;
4833 }
4834
Rafael Espindola068317b2007-09-28 12:53:01 +00004835 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
Chris Lattner0bd48932008-01-17 07:00:52 +00004836 SDOperand Count = DAG.getIntPtrConstant(Size / UBytes);
Rafael Espindola068317b2007-09-28 12:53:01 +00004837 BytesLeft = Size % UBytes;
Evan Cheng25ab6902006-09-08 06:48:29 +00004838
Evan Cheng0db9fe62006-04-25 20:13:52 +00004839 SDOperand InFlag(0, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004840 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4841 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004842 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00004843 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
Rafael Espindola068317b2007-09-28 12:53:01 +00004844 Dest, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004845 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00004846 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
Rafael Espindola068317b2007-09-28 12:53:01 +00004847 Source, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004848 InFlag = Chain.getValue(1);
4849
Chris Lattnerd96d0722007-02-25 06:40:16 +00004850 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner5a88b832007-02-25 07:10:00 +00004851 SmallVector<SDOperand, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004852 Ops.push_back(Chain);
4853 Ops.push_back(DAG.getValueType(AVT));
4854 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00004855 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004856
Rafael Espindola068317b2007-09-28 12:53:01 +00004857 if (BytesLeft) {
Evan Cheng25ab6902006-09-08 06:48:29 +00004858 // Issue loads and stores for the last 1 - 7 bytes.
Rafael Espindola068317b2007-09-28 12:53:01 +00004859 unsigned Offset = Size - BytesLeft;
4860 SDOperand DstAddr = Dest;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004861 MVT::ValueType DstVT = DstAddr.getValueType();
Rafael Espindola068317b2007-09-28 12:53:01 +00004862 SDOperand SrcAddr = Source;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004863 MVT::ValueType SrcVT = SrcAddr.getValueType();
4864 SDOperand Value;
Evan Cheng25ab6902006-09-08 06:48:29 +00004865 if (BytesLeft >= 4) {
4866 Value = DAG.getLoad(MVT::i32, Chain,
4867 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4868 DAG.getConstant(Offset, SrcVT)),
Evan Cheng466685d2006-10-09 20:57:25 +00004869 NULL, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004870 Chain = Value.getValue(1);
Evan Cheng786225a2006-10-05 23:01:46 +00004871 Chain = DAG.getStore(Chain, Value,
4872 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4873 DAG.getConstant(Offset, DstVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004874 NULL, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004875 BytesLeft -= 4;
4876 Offset += 4;
4877 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004878 if (BytesLeft >= 2) {
4879 Value = DAG.getLoad(MVT::i16, Chain,
4880 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4881 DAG.getConstant(Offset, SrcVT)),
Evan Cheng466685d2006-10-09 20:57:25 +00004882 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004883 Chain = Value.getValue(1);
Evan Cheng786225a2006-10-05 23:01:46 +00004884 Chain = DAG.getStore(Chain, Value,
4885 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4886 DAG.getConstant(Offset, DstVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004887 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004888 BytesLeft -= 2;
4889 Offset += 2;
Evan Chengb067a1e2006-03-31 19:22:53 +00004890 }
4891
Evan Cheng0db9fe62006-04-25 20:13:52 +00004892 if (BytesLeft == 1) {
4893 Value = DAG.getLoad(MVT::i8, Chain,
4894 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4895 DAG.getConstant(Offset, SrcVT)),
Evan Cheng466685d2006-10-09 20:57:25 +00004896 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004897 Chain = Value.getValue(1);
Evan Cheng786225a2006-10-05 23:01:46 +00004898 Chain = DAG.getStore(Chain, Value,
4899 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4900 DAG.getConstant(Offset, DstVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004901 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004902 }
Evan Chengb067a1e2006-03-31 19:22:53 +00004903 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004904
4905 return Chain;
4906}
4907
Chris Lattner27a6c732007-11-24 07:07:01 +00004908/// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4909SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
Chris Lattnerd96d0722007-02-25 06:40:16 +00004910 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner27a6c732007-11-24 07:07:01 +00004911 SDOperand TheChain = N->getOperand(0);
4912 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
Evan Cheng3fa9dff2006-11-29 08:28:13 +00004913 if (Subtarget->is64Bit()) {
Chris Lattner27a6c732007-11-24 07:07:01 +00004914 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4915 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4916 MVT::i64, rax.getValue(2));
4917 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
Evan Cheng3fa9dff2006-11-29 08:28:13 +00004918 DAG.getConstant(32, MVT::i8));
Chris Lattner5a88b832007-02-25 07:10:00 +00004919 SDOperand Ops[] = {
Chris Lattner27a6c732007-11-24 07:07:01 +00004920 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
Chris Lattner5a88b832007-02-25 07:10:00 +00004921 };
Chris Lattnerd96d0722007-02-25 06:40:16 +00004922
4923 Tys = DAG.getVTList(MVT::i64, MVT::Other);
Chris Lattner27a6c732007-11-24 07:07:01 +00004924 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
Evan Cheng3fa9dff2006-11-29 08:28:13 +00004925 }
Chris Lattner5a88b832007-02-25 07:10:00 +00004926
Chris Lattner27a6c732007-11-24 07:07:01 +00004927 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4928 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4929 MVT::i32, eax.getValue(2));
4930 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4931 SDOperand Ops[] = { eax, edx };
4932 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4933
4934 // Use a MERGE_VALUES to return the value and chain.
4935 Ops[1] = edx.getValue(1);
4936 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4937 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004938}
4939
4940SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman69de1932008-02-06 22:27:42 +00004941 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Evan Cheng8b2794a2006-10-13 21:14:26 +00004942
Evan Cheng25ab6902006-09-08 06:48:29 +00004943 if (!Subtarget->is64Bit()) {
4944 // vastart just stores the address of the VarArgsFrameIndex slot into the
4945 // memory location argument.
4946 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Dan Gohman69de1932008-02-06 22:27:42 +00004947 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004948 }
4949
4950 // __va_list_tag:
4951 // gp_offset (0 - 6 * 8)
4952 // fp_offset (48 - 48 + 8 * 16)
4953 // overflow_arg_area (point to parameters coming in memory).
4954 // reg_save_area
Chris Lattner5a88b832007-02-25 07:10:00 +00004955 SmallVector<SDOperand, 8> MemOps;
Evan Cheng25ab6902006-09-08 06:48:29 +00004956 SDOperand FIN = Op.getOperand(1);
4957 // Store gp_offset
Evan Cheng786225a2006-10-05 23:01:46 +00004958 SDOperand Store = DAG.getStore(Op.getOperand(0),
4959 DAG.getConstant(VarArgsGPOffset, MVT::i32),
Dan Gohman69de1932008-02-06 22:27:42 +00004960 FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004961 MemOps.push_back(Store);
4962
4963 // Store fp_offset
Chris Lattner0bd48932008-01-17 07:00:52 +00004964 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
Evan Cheng786225a2006-10-05 23:01:46 +00004965 Store = DAG.getStore(Op.getOperand(0),
4966 DAG.getConstant(VarArgsFPOffset, MVT::i32),
Dan Gohman69de1932008-02-06 22:27:42 +00004967 FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004968 MemOps.push_back(Store);
4969
4970 // Store ptr to overflow_arg_area
Chris Lattner0bd48932008-01-17 07:00:52 +00004971 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
Evan Cheng25ab6902006-09-08 06:48:29 +00004972 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Dan Gohman69de1932008-02-06 22:27:42 +00004973 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004974 MemOps.push_back(Store);
4975
4976 // Store ptr to reg_save_area.
Chris Lattner0bd48932008-01-17 07:00:52 +00004977 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
Evan Cheng25ab6902006-09-08 06:48:29 +00004978 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Dan Gohman69de1932008-02-06 22:27:42 +00004979 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004980 MemOps.push_back(Store);
4981 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004982}
4983
Evan Chengae642192007-03-02 23:16:35 +00004984SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4985 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4986 SDOperand Chain = Op.getOperand(0);
4987 SDOperand DstPtr = Op.getOperand(1);
4988 SDOperand SrcPtr = Op.getOperand(2);
Dan Gohman69de1932008-02-06 22:27:42 +00004989 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4990 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
Evan Chengae642192007-03-02 23:16:35 +00004991
Dan Gohman69de1932008-02-06 22:27:42 +00004992 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0);
Evan Chengae642192007-03-02 23:16:35 +00004993 Chain = SrcPtr.getValue(1);
4994 for (unsigned i = 0; i < 3; ++i) {
Dan Gohman69de1932008-02-06 22:27:42 +00004995 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0);
Evan Chengae642192007-03-02 23:16:35 +00004996 Chain = Val.getValue(1);
Dan Gohman69de1932008-02-06 22:27:42 +00004997 Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0);
Evan Chengae642192007-03-02 23:16:35 +00004998 if (i == 2)
4999 break;
5000 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
Chris Lattner0bd48932008-01-17 07:00:52 +00005001 DAG.getIntPtrConstant(8));
Evan Chengae642192007-03-02 23:16:35 +00005002 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
Chris Lattner0bd48932008-01-17 07:00:52 +00005003 DAG.getIntPtrConstant(8));
Evan Chengae642192007-03-02 23:16:35 +00005004 }
5005 return Chain;
5006}
5007
Evan Cheng0db9fe62006-04-25 20:13:52 +00005008SDOperand
5009X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
5010 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
5011 switch (IntNo) {
5012 default: return SDOperand(); // Don't custom lower most intrinsics.
Evan Cheng6be2c582006-04-05 23:38:46 +00005013 // Comparison intrinsics.
Evan Cheng0db9fe62006-04-25 20:13:52 +00005014 case Intrinsic::x86_sse_comieq_ss:
5015 case Intrinsic::x86_sse_comilt_ss:
5016 case Intrinsic::x86_sse_comile_ss:
5017 case Intrinsic::x86_sse_comigt_ss:
5018 case Intrinsic::x86_sse_comige_ss:
5019 case Intrinsic::x86_sse_comineq_ss:
5020 case Intrinsic::x86_sse_ucomieq_ss:
5021 case Intrinsic::x86_sse_ucomilt_ss:
5022 case Intrinsic::x86_sse_ucomile_ss:
5023 case Intrinsic::x86_sse_ucomigt_ss:
5024 case Intrinsic::x86_sse_ucomige_ss:
5025 case Intrinsic::x86_sse_ucomineq_ss:
5026 case Intrinsic::x86_sse2_comieq_sd:
5027 case Intrinsic::x86_sse2_comilt_sd:
5028 case Intrinsic::x86_sse2_comile_sd:
5029 case Intrinsic::x86_sse2_comigt_sd:
5030 case Intrinsic::x86_sse2_comige_sd:
5031 case Intrinsic::x86_sse2_comineq_sd:
5032 case Intrinsic::x86_sse2_ucomieq_sd:
5033 case Intrinsic::x86_sse2_ucomilt_sd:
5034 case Intrinsic::x86_sse2_ucomile_sd:
5035 case Intrinsic::x86_sse2_ucomigt_sd:
5036 case Intrinsic::x86_sse2_ucomige_sd:
5037 case Intrinsic::x86_sse2_ucomineq_sd: {
5038 unsigned Opc = 0;
5039 ISD::CondCode CC = ISD::SETCC_INVALID;
5040 switch (IntNo) {
5041 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005042 case Intrinsic::x86_sse_comieq_ss:
5043 case Intrinsic::x86_sse2_comieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005044 Opc = X86ISD::COMI;
5045 CC = ISD::SETEQ;
5046 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00005047 case Intrinsic::x86_sse_comilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005048 case Intrinsic::x86_sse2_comilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005049 Opc = X86ISD::COMI;
5050 CC = ISD::SETLT;
5051 break;
5052 case Intrinsic::x86_sse_comile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005053 case Intrinsic::x86_sse2_comile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005054 Opc = X86ISD::COMI;
5055 CC = ISD::SETLE;
5056 break;
5057 case Intrinsic::x86_sse_comigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005058 case Intrinsic::x86_sse2_comigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005059 Opc = X86ISD::COMI;
5060 CC = ISD::SETGT;
5061 break;
5062 case Intrinsic::x86_sse_comige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005063 case Intrinsic::x86_sse2_comige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005064 Opc = X86ISD::COMI;
5065 CC = ISD::SETGE;
5066 break;
5067 case Intrinsic::x86_sse_comineq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005068 case Intrinsic::x86_sse2_comineq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005069 Opc = X86ISD::COMI;
5070 CC = ISD::SETNE;
5071 break;
5072 case Intrinsic::x86_sse_ucomieq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005073 case Intrinsic::x86_sse2_ucomieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005074 Opc = X86ISD::UCOMI;
5075 CC = ISD::SETEQ;
5076 break;
5077 case Intrinsic::x86_sse_ucomilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005078 case Intrinsic::x86_sse2_ucomilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005079 Opc = X86ISD::UCOMI;
5080 CC = ISD::SETLT;
5081 break;
5082 case Intrinsic::x86_sse_ucomile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005083 case Intrinsic::x86_sse2_ucomile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005084 Opc = X86ISD::UCOMI;
5085 CC = ISD::SETLE;
5086 break;
5087 case Intrinsic::x86_sse_ucomigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005088 case Intrinsic::x86_sse2_ucomigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005089 Opc = X86ISD::UCOMI;
5090 CC = ISD::SETGT;
5091 break;
5092 case Intrinsic::x86_sse_ucomige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005093 case Intrinsic::x86_sse2_ucomige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005094 Opc = X86ISD::UCOMI;
5095 CC = ISD::SETGE;
5096 break;
5097 case Intrinsic::x86_sse_ucomineq_ss:
5098 case Intrinsic::x86_sse2_ucomineq_sd:
5099 Opc = X86ISD::UCOMI;
5100 CC = ISD::SETNE;
5101 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00005102 }
Evan Cheng734503b2006-09-11 02:19:56 +00005103
Evan Cheng0db9fe62006-04-25 20:13:52 +00005104 unsigned X86CC;
Chris Lattnerf9570512006-09-13 03:22:10 +00005105 SDOperand LHS = Op.getOperand(1);
5106 SDOperand RHS = Op.getOperand(2);
5107 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00005108
Evan Chenge5f62042007-09-29 00:00:36 +00005109 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5110 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5111 DAG.getConstant(X86CC, MVT::i8), Cond);
5112 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
Evan Cheng6be2c582006-04-05 23:38:46 +00005113 }
Evan Cheng38bcbaf2005-12-23 07:31:11 +00005114 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00005115}
Evan Cheng72261582005-12-20 06:22:03 +00005116
Nate Begemanbcc5f362007-01-29 22:58:52 +00005117SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
5118 // Depths > 0 not supported yet!
5119 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5120 return SDOperand();
5121
5122 // Just load the return address
5123 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5124 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5125}
5126
5127SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
5128 // Depths > 0 not supported yet!
5129 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5130 return SDOperand();
5131
5132 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5133 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
Chris Lattner0bd48932008-01-17 07:00:52 +00005134 DAG.getIntPtrConstant(4));
Nate Begemanbcc5f362007-01-29 22:58:52 +00005135}
5136
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005137SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
5138 SelectionDAG &DAG) {
5139 // Is not yet supported on x86-64
5140 if (Subtarget->is64Bit())
5141 return SDOperand();
5142
Chris Lattner0bd48932008-01-17 07:00:52 +00005143 return DAG.getIntPtrConstant(8);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005144}
5145
5146SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
5147{
5148 assert(!Subtarget->is64Bit() &&
5149 "Lowering of eh_return builtin is not supported yet on x86-64");
5150
5151 MachineFunction &MF = DAG.getMachineFunction();
5152 SDOperand Chain = Op.getOperand(0);
5153 SDOperand Offset = Op.getOperand(1);
5154 SDOperand Handler = Op.getOperand(2);
5155
5156 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
5157 getPointerTy());
5158
5159 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
Chris Lattner0bd48932008-01-17 07:00:52 +00005160 DAG.getIntPtrConstant(-4UL));
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005161 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5162 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5163 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
Chris Lattner84bc5422007-12-31 04:13:23 +00005164 MF.getRegInfo().addLiveOut(X86::ECX);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005165
5166 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
5167 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
5168}
5169
Duncan Sandsb116fac2007-07-27 20:02:49 +00005170SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
5171 SelectionDAG &DAG) {
5172 SDOperand Root = Op.getOperand(0);
5173 SDOperand Trmp = Op.getOperand(1); // trampoline
5174 SDOperand FPtr = Op.getOperand(2); // nested function
5175 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
5176
Dan Gohman69de1932008-02-06 22:27:42 +00005177 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
Duncan Sandsb116fac2007-07-27 20:02:49 +00005178
Duncan Sands339e14f2008-01-16 22:55:25 +00005179 const X86InstrInfo *TII =
5180 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5181
Duncan Sandsb116fac2007-07-27 20:02:49 +00005182 if (Subtarget->is64Bit()) {
Duncan Sands339e14f2008-01-16 22:55:25 +00005183 SDOperand OutChains[6];
5184
5185 // Large code-model.
5186
5187 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5188 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5189
5190 const unsigned char N86R10 =
Dan Gohman60783302008-02-08 03:29:40 +00005191 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
Duncan Sands339e14f2008-01-16 22:55:25 +00005192 const unsigned char N86R11 =
Dan Gohman60783302008-02-08 03:29:40 +00005193 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
Duncan Sands339e14f2008-01-16 22:55:25 +00005194
5195 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5196
5197 // Load the pointer to the nested function into R11.
5198 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5199 SDOperand Addr = Trmp;
5200 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005201 TrmpAddr, 0);
Duncan Sands339e14f2008-01-16 22:55:25 +00005202
5203 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
Dan Gohman69de1932008-02-06 22:27:42 +00005204 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
Duncan Sands339e14f2008-01-16 22:55:25 +00005205
5206 // Load the 'nest' parameter value into R10.
5207 // R10 is specified in X86CallingConv.td
5208 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5209 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5210 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005211 TrmpAddr, 10);
Duncan Sands339e14f2008-01-16 22:55:25 +00005212
5213 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
Dan Gohman69de1932008-02-06 22:27:42 +00005214 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
Duncan Sands339e14f2008-01-16 22:55:25 +00005215
5216 // Jump to the nested function.
5217 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5218 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5219 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005220 TrmpAddr, 20);
Duncan Sands339e14f2008-01-16 22:55:25 +00005221
5222 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5223 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5224 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005225 TrmpAddr, 22);
Duncan Sands339e14f2008-01-16 22:55:25 +00005226
5227 SDOperand Ops[] =
5228 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5229 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005230 } else {
Dan Gohmanbbfb9c52008-01-31 01:01:48 +00005231 const Function *Func =
Duncan Sandsb116fac2007-07-27 20:02:49 +00005232 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5233 unsigned CC = Func->getCallingConv();
Duncan Sandsee465742007-08-29 19:01:20 +00005234 unsigned NestReg;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005235
5236 switch (CC) {
5237 default:
5238 assert(0 && "Unsupported calling convention");
5239 case CallingConv::C:
Duncan Sandsb116fac2007-07-27 20:02:49 +00005240 case CallingConv::X86_StdCall: {
5241 // Pass 'nest' parameter in ECX.
5242 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00005243 NestReg = X86::ECX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005244
5245 // Check that ECX wasn't needed by an 'inreg' parameter.
5246 const FunctionType *FTy = Func->getFunctionType();
Duncan Sandsdc024672007-11-27 13:23:08 +00005247 const ParamAttrsList *Attrs = Func->getParamAttrs();
Duncan Sandsb116fac2007-07-27 20:02:49 +00005248
5249 if (Attrs && !Func->isVarArg()) {
5250 unsigned InRegCount = 0;
5251 unsigned Idx = 1;
5252
5253 for (FunctionType::param_iterator I = FTy->param_begin(),
5254 E = FTy->param_end(); I != E; ++I, ++Idx)
5255 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
5256 // FIXME: should only count parameters that are lowered to integers.
5257 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
5258
5259 if (InRegCount > 2) {
5260 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5261 abort();
5262 }
5263 }
5264 break;
5265 }
5266 case CallingConv::X86_FastCall:
5267 // Pass 'nest' parameter in EAX.
5268 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00005269 NestReg = X86::EAX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005270 break;
5271 }
5272
5273 SDOperand OutChains[4];
5274 SDOperand Addr, Disp;
5275
5276 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5277 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5278
Duncan Sands339e14f2008-01-16 22:55:25 +00005279 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5280 const unsigned char N86Reg =
Dan Gohman60783302008-02-08 03:29:40 +00005281 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
Duncan Sandsee465742007-08-29 19:01:20 +00005282 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Dan Gohman69de1932008-02-06 22:27:42 +00005283 Trmp, TrmpAddr, 0);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005284
5285 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
Dan Gohman69de1932008-02-06 22:27:42 +00005286 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005287
Duncan Sands339e14f2008-01-16 22:55:25 +00005288 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005289 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5290 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005291 TrmpAddr, 5, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005292
5293 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
Dan Gohman69de1932008-02-06 22:27:42 +00005294 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005295
Duncan Sandsf7331b32007-09-11 14:10:23 +00005296 SDOperand Ops[] =
5297 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5298 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005299 }
5300}
5301
Dan Gohman1a024862008-01-31 00:41:03 +00005302SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005303 /*
5304 The rounding mode is in bits 11:10 of FPSR, and has the following
5305 settings:
5306 00 Round to nearest
5307 01 Round to -inf
5308 10 Round to +inf
5309 11 Round to 0
5310
5311 FLT_ROUNDS, on the other hand, expects the following:
5312 -1 Undefined
5313 0 Round to 0
5314 1 Round to nearest
5315 2 Round to +inf
5316 3 Round to -inf
5317
5318 To perform the conversion, we do:
5319 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5320 */
5321
5322 MachineFunction &MF = DAG.getMachineFunction();
5323 const TargetMachine &TM = MF.getTarget();
5324 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5325 unsigned StackAlignment = TFI.getStackAlignment();
5326 MVT::ValueType VT = Op.getValueType();
5327
5328 // Save FP Control Word to stack slot
5329 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5330 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5331
5332 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5333 DAG.getEntryNode(), StackSlot);
5334
5335 // Load FP Control Word from stack slot
5336 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5337
5338 // Transform as necessary
5339 SDOperand CWD1 =
5340 DAG.getNode(ISD::SRL, MVT::i16,
5341 DAG.getNode(ISD::AND, MVT::i16,
5342 CWD, DAG.getConstant(0x800, MVT::i16)),
5343 DAG.getConstant(11, MVT::i8));
5344 SDOperand CWD2 =
5345 DAG.getNode(ISD::SRL, MVT::i16,
5346 DAG.getNode(ISD::AND, MVT::i16,
5347 CWD, DAG.getConstant(0x400, MVT::i16)),
5348 DAG.getConstant(9, MVT::i8));
5349
5350 SDOperand RetVal =
5351 DAG.getNode(ISD::AND, MVT::i16,
5352 DAG.getNode(ISD::ADD, MVT::i16,
5353 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5354 DAG.getConstant(1, MVT::i16)),
5355 DAG.getConstant(3, MVT::i16));
5356
5357
5358 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
5359 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5360}
5361
Evan Cheng18efe262007-12-14 02:13:44 +00005362SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
5363 MVT::ValueType VT = Op.getValueType();
5364 MVT::ValueType OpVT = VT;
5365 unsigned NumBits = MVT::getSizeInBits(VT);
5366
5367 Op = Op.getOperand(0);
5368 if (VT == MVT::i8) {
Evan Cheng152804e2007-12-14 08:30:15 +00005369 // Zero extend to i32 since there is not an i8 bsr.
Evan Cheng18efe262007-12-14 02:13:44 +00005370 OpVT = MVT::i32;
5371 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5372 }
Evan Cheng18efe262007-12-14 02:13:44 +00005373
Evan Cheng152804e2007-12-14 08:30:15 +00005374 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5375 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5376 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5377
5378 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5379 SmallVector<SDOperand, 4> Ops;
5380 Ops.push_back(Op);
5381 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5382 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5383 Ops.push_back(Op.getValue(1));
5384 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5385
5386 // Finally xor with NumBits-1.
5387 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5388
Evan Cheng18efe262007-12-14 02:13:44 +00005389 if (VT == MVT::i8)
5390 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5391 return Op;
5392}
5393
5394SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5395 MVT::ValueType VT = Op.getValueType();
5396 MVT::ValueType OpVT = VT;
Evan Cheng152804e2007-12-14 08:30:15 +00005397 unsigned NumBits = MVT::getSizeInBits(VT);
Evan Cheng18efe262007-12-14 02:13:44 +00005398
5399 Op = Op.getOperand(0);
5400 if (VT == MVT::i8) {
5401 OpVT = MVT::i32;
5402 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5403 }
Evan Cheng152804e2007-12-14 08:30:15 +00005404
5405 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5406 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5407 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5408
5409 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5410 SmallVector<SDOperand, 4> Ops;
5411 Ops.push_back(Op);
5412 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5413 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5414 Ops.push_back(Op.getValue(1));
5415 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5416
Evan Cheng18efe262007-12-14 02:13:44 +00005417 if (VT == MVT::i8)
5418 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5419 return Op;
5420}
5421
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005422SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) {
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005423 MVT::ValueType T = cast<AtomicSDNode>(Op.Val)->getVT();
Andrew Lenhartha76e2f02008-03-04 21:13:33 +00005424 unsigned Reg = 0;
5425 unsigned size = 0;
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005426 switch(T) {
5427 case MVT::i8: Reg = X86::AL; size = 1; break;
5428 case MVT::i16: Reg = X86::AX; size = 2; break;
5429 case MVT::i32: Reg = X86::EAX; size = 4; break;
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005430 case MVT::i64:
5431 if (Subtarget->is64Bit()) {
5432 Reg = X86::RAX; size = 8;
5433 } else //Should go away when LowerType stuff lands
5434 return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0);
5435 break;
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005436 };
5437 SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
Andrew Lenharthce1105d2008-03-01 22:27:48 +00005438 Op.getOperand(3), SDOperand());
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005439 SDOperand Ops[] = { cpIn.getValue(0),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005440 Op.getOperand(1),
5441 Op.getOperand(2),
5442 DAG.getTargetConstant(size, MVT::i8),
5443 cpIn.getValue(1) };
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005444 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5445 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5446 SDOperand cpOut =
5447 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5448 return cpOut;
5449}
5450
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005451SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) {
5452 MVT::ValueType T = cast<AtomicSDNode>(Op)->getVT();
5453 assert (T == MVT::i64 && "Only know how to expand i64 CAS");
5454 SDOperand cpInL, cpInH;
5455 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5456 DAG.getConstant(0, MVT::i32));
5457 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5458 DAG.getConstant(1, MVT::i32));
5459 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5460 cpInL, SDOperand());
5461 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5462 cpInH, cpInL.getValue(1));
5463 SDOperand swapInL, swapInH;
5464 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5465 DAG.getConstant(0, MVT::i32));
5466 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5467 DAG.getConstant(1, MVT::i32));
5468 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5469 swapInL, cpInH.getValue(1));
5470 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5471 swapInH, swapInL.getValue(1));
5472 SDOperand Ops[] = { swapInH.getValue(0),
5473 Op->getOperand(1),
5474 swapInH.getValue(1)};
5475 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5476 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5477 SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5478 Result.getValue(1));
5479 SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5480 cpOutL.getValue(2));
5481 SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5482 SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5483 Tys = DAG.getVTList(MVT::i64, MVT::Other);
5484 return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val;
5485}
5486
Evan Cheng0db9fe62006-04-25 20:13:52 +00005487/// LowerOperation - Provide custom lowering hooks for some operations.
5488///
5489SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5490 switch (Op.getOpcode()) {
5491 default: assert(0 && "Should not custom lower this!");
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005492 case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005493 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5494 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5495 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5496 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5497 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5498 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5499 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00005500 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005501 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5502 case ISD::SHL_PARTS:
5503 case ISD::SRA_PARTS:
5504 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5505 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5506 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5507 case ISD::FABS: return LowerFABS(Op, DAG);
5508 case ISD::FNEG: return LowerFNEG(Op, DAG);
Evan Cheng68c47cb2007-01-05 07:55:56 +00005509 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Evan Chenge5f62042007-09-29 00:00:36 +00005510 case ISD::SETCC: return LowerSETCC(Op, DAG);
5511 case ISD::SELECT: return LowerSELECT(Op, DAG);
5512 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005513 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Evan Cheng32fe1032006-05-25 00:59:30 +00005514 case ISD::CALL: return LowerCALL(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005515 case ISD::RET: return LowerRET(Op, DAG);
Evan Cheng1bc78042006-04-26 01:20:17 +00005516 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005517 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
5518 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005519 case ISD::VASTART: return LowerVASTART(Op, DAG);
Evan Chengae642192007-03-02 23:16:35 +00005520 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005521 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00005522 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5523 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005524 case ISD::FRAME_TO_ARGS_OFFSET:
5525 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005526 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005527 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005528 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
Dan Gohman1a024862008-01-31 00:41:03 +00005529 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Evan Cheng18efe262007-12-14 02:13:44 +00005530 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5531 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
Chris Lattner27a6c732007-11-24 07:07:01 +00005532
5533 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5534 case ISD::READCYCLECOUNTER:
5535 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005536 }
Chris Lattner27a6c732007-11-24 07:07:01 +00005537}
5538
5539/// ExpandOperation - Provide custom lowering hooks for expanding operations.
5540SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5541 switch (N->getOpcode()) {
5542 default: assert(0 && "Should not custom lower this!");
5543 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5544 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005545 case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG);
Chris Lattner27a6c732007-11-24 07:07:01 +00005546 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00005547}
5548
Evan Cheng72261582005-12-20 06:22:03 +00005549const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5550 switch (Opcode) {
5551 default: return NULL;
Evan Cheng18efe262007-12-14 02:13:44 +00005552 case X86ISD::BSF: return "X86ISD::BSF";
5553 case X86ISD::BSR: return "X86ISD::BSR";
Evan Chenge3413162006-01-09 18:33:28 +00005554 case X86ISD::SHLD: return "X86ISD::SHLD";
5555 case X86ISD::SHRD: return "X86ISD::SHRD";
Evan Chengef6ffb12006-01-31 03:14:29 +00005556 case X86ISD::FAND: return "X86ISD::FAND";
Evan Cheng68c47cb2007-01-05 07:55:56 +00005557 case X86ISD::FOR: return "X86ISD::FOR";
Evan Cheng223547a2006-01-31 22:28:30 +00005558 case X86ISD::FXOR: return "X86ISD::FXOR";
Evan Cheng68c47cb2007-01-05 07:55:56 +00005559 case X86ISD::FSRL: return "X86ISD::FSRL";
Evan Chenga3195e82006-01-12 22:54:21 +00005560 case X86ISD::FILD: return "X86ISD::FILD";
Evan Chenge3de85b2006-02-04 02:20:30 +00005561 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
Evan Cheng72261582005-12-20 06:22:03 +00005562 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5563 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5564 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
Evan Chengb077b842005-12-21 02:39:21 +00005565 case X86ISD::FLD: return "X86ISD::FLD";
Evan Chengd90eb7f2006-01-05 00:27:02 +00005566 case X86ISD::FST: return "X86ISD::FST";
5567 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
Evan Cheng0d9e9762008-01-29 19:34:22 +00005568 case X86ISD::FP_GET_RESULT2: return "X86ISD::FP_GET_RESULT2";
Evan Chengb077b842005-12-21 02:39:21 +00005569 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
Evan Cheng72261582005-12-20 06:22:03 +00005570 case X86ISD::CALL: return "X86ISD::CALL";
5571 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5572 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5573 case X86ISD::CMP: return "X86ISD::CMP";
Evan Cheng6be2c582006-04-05 23:38:46 +00005574 case X86ISD::COMI: return "X86ISD::COMI";
5575 case X86ISD::UCOMI: return "X86ISD::UCOMI";
Evan Chengd5781fc2005-12-21 20:21:51 +00005576 case X86ISD::SETCC: return "X86ISD::SETCC";
Evan Cheng72261582005-12-20 06:22:03 +00005577 case X86ISD::CMOV: return "X86ISD::CMOV";
5578 case X86ISD::BRCOND: return "X86ISD::BRCOND";
Evan Chengb077b842005-12-21 02:39:21 +00005579 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
Evan Cheng8df346b2006-03-04 01:12:00 +00005580 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5581 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
Evan Cheng7ccced62006-02-18 00:15:05 +00005582 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
Evan Cheng020d2e82006-02-23 20:41:18 +00005583 case X86ISD::Wrapper: return "X86ISD::Wrapper";
Nate Begeman14d12ca2008-02-11 04:19:36 +00005584 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
Evan Chengb067a1e2006-03-31 19:22:53 +00005585 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
Nate Begeman14d12ca2008-02-11 04:19:36 +00005586 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
5587 case X86ISD::PINSRB: return "X86ISD::PINSRB";
Evan Cheng653159f2006-03-31 21:55:24 +00005588 case X86ISD::PINSRW: return "X86ISD::PINSRW";
Evan Cheng8ca29322006-11-10 21:43:37 +00005589 case X86ISD::FMAX: return "X86ISD::FMAX";
5590 case X86ISD::FMIN: return "X86ISD::FMIN";
Dan Gohman20382522007-07-10 00:05:58 +00005591 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5592 case X86ISD::FRCP: return "X86ISD::FRCP";
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00005593 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5594 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005595 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005596 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005597 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005598 case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG";
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005599 case X86ISD::LCMPXCHG8_DAG: return "x86ISD::LCMPXCHG8_DAG";
Evan Cheng72261582005-12-20 06:22:03 +00005600 }
5601}
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005602
Chris Lattnerc9addb72007-03-30 23:15:24 +00005603// isLegalAddressingMode - Return true if the addressing mode represented
5604// by AM is legal for this target, for a load/store of the specified type.
5605bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5606 const Type *Ty) const {
5607 // X86 supports extremely general addressing modes.
5608
5609 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5610 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5611 return false;
5612
5613 if (AM.BaseGV) {
Evan Cheng52787842007-08-01 23:46:47 +00005614 // We can only fold this if we don't need an extra load.
Chris Lattnerc9addb72007-03-30 23:15:24 +00005615 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5616 return false;
Evan Cheng52787842007-08-01 23:46:47 +00005617
5618 // X86-64 only supports addr of globals in small code model.
5619 if (Subtarget->is64Bit()) {
5620 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5621 return false;
5622 // If lower 4G is not available, then we must use rip-relative addressing.
5623 if (AM.BaseOffs || AM.Scale > 1)
5624 return false;
5625 }
Chris Lattnerc9addb72007-03-30 23:15:24 +00005626 }
5627
5628 switch (AM.Scale) {
5629 case 0:
5630 case 1:
5631 case 2:
5632 case 4:
5633 case 8:
5634 // These scales always work.
5635 break;
5636 case 3:
5637 case 5:
5638 case 9:
5639 // These scales are formed with basereg+scalereg. Only accept if there is
5640 // no basereg yet.
5641 if (AM.HasBaseReg)
5642 return false;
5643 break;
5644 default: // Other stuff never works.
5645 return false;
5646 }
5647
5648 return true;
5649}
5650
5651
Evan Cheng2bd122c2007-10-26 01:56:11 +00005652bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5653 if (!Ty1->isInteger() || !Ty2->isInteger())
5654 return false;
Evan Chenge127a732007-10-29 07:57:50 +00005655 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5656 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5657 if (NumBits1 <= NumBits2)
5658 return false;
5659 return Subtarget->is64Bit() || NumBits1 < 64;
Evan Cheng2bd122c2007-10-26 01:56:11 +00005660}
5661
Evan Cheng3c3ddb32007-10-29 19:58:20 +00005662bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5663 MVT::ValueType VT2) const {
5664 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5665 return false;
5666 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5667 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5668 if (NumBits1 <= NumBits2)
5669 return false;
5670 return Subtarget->is64Bit() || NumBits1 < 64;
5671}
Evan Cheng2bd122c2007-10-26 01:56:11 +00005672
Evan Cheng60c07e12006-07-05 22:17:51 +00005673/// isShuffleMaskLegal - Targets can use this to indicate that they only
5674/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5675/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5676/// are assumed to be legal.
5677bool
5678X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5679 // Only do shuffles on 128-bit vector types for now.
5680 if (MVT::getSizeInBits(VT) == 64) return false;
5681 return (Mask.Val->getNumOperands() <= 4 ||
Evan Cheng49892af2007-06-19 00:02:56 +00005682 isIdentityMask(Mask.Val) ||
5683 isIdentityMask(Mask.Val, true) ||
Evan Cheng60c07e12006-07-05 22:17:51 +00005684 isSplatMask(Mask.Val) ||
5685 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5686 X86::isUNPCKLMask(Mask.Val) ||
Evan Cheng49892af2007-06-19 00:02:56 +00005687 X86::isUNPCKHMask(Mask.Val) ||
Evan Cheng60c07e12006-07-05 22:17:51 +00005688 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
Evan Cheng49892af2007-06-19 00:02:56 +00005689 X86::isUNPCKH_v_undef_Mask(Mask.Val));
Evan Cheng60c07e12006-07-05 22:17:51 +00005690}
5691
5692bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5693 MVT::ValueType EVT,
5694 SelectionDAG &DAG) const {
5695 unsigned NumElts = BVOps.size();
5696 // Only do shuffles on 128-bit vector types for now.
5697 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5698 if (NumElts == 2) return true;
5699 if (NumElts == 4) {
Chris Lattner5a88b832007-02-25 07:10:00 +00005700 return (isMOVLMask(&BVOps[0], 4) ||
5701 isCommutedMOVL(&BVOps[0], 4, true) ||
5702 isSHUFPMask(&BVOps[0], 4) ||
5703 isCommutedSHUFP(&BVOps[0], 4));
Evan Cheng60c07e12006-07-05 22:17:51 +00005704 }
5705 return false;
5706}
5707
5708//===----------------------------------------------------------------------===//
5709// X86 Scheduler Hooks
5710//===----------------------------------------------------------------------===//
5711
5712MachineBasicBlock *
Evan Chengff9b3732008-01-30 18:18:23 +00005713X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5714 MachineBasicBlock *BB) {
Evan Chengc0f64ff2006-11-27 23:37:22 +00005715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Evan Cheng60c07e12006-07-05 22:17:51 +00005716 switch (MI->getOpcode()) {
5717 default: assert(false && "Unexpected instr type to insert");
5718 case X86::CMOV_FR32:
5719 case X86::CMOV_FR64:
5720 case X86::CMOV_V4F32:
5721 case X86::CMOV_V2F64:
Evan Chenge5f62042007-09-29 00:00:36 +00005722 case X86::CMOV_V2I64: {
Evan Cheng60c07e12006-07-05 22:17:51 +00005723 // To "insert" a SELECT_CC instruction, we actually have to insert the
5724 // diamond control-flow pattern. The incoming instruction knows the
5725 // destination vreg to set, the condition code register to branch on, the
5726 // true/false values to select between, and a branch opcode to use.
5727 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5728 ilist<MachineBasicBlock>::iterator It = BB;
5729 ++It;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005730
Evan Cheng60c07e12006-07-05 22:17:51 +00005731 // thisMBB:
5732 // ...
5733 // TrueVal = ...
5734 // cmpTY ccX, r1, r2
5735 // bCC copy1MBB
5736 // fallthrough --> copy0MBB
5737 MachineBasicBlock *thisMBB = BB;
5738 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5739 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005740 unsigned Opc =
Chris Lattner7fbe9722006-10-20 17:42:20 +00005741 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
Evan Chengc0f64ff2006-11-27 23:37:22 +00005742 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
Evan Cheng60c07e12006-07-05 22:17:51 +00005743 MachineFunction *F = BB->getParent();
5744 F->getBasicBlockList().insert(It, copy0MBB);
5745 F->getBasicBlockList().insert(It, sinkMBB);
5746 // Update machine-CFG edges by first adding all successors of the current
5747 // block to the new block which will contain the Phi node for the select.
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005748 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
Evan Cheng60c07e12006-07-05 22:17:51 +00005749 e = BB->succ_end(); i != e; ++i)
5750 sinkMBB->addSuccessor(*i);
5751 // Next, remove all successors of the current block, and add the true
5752 // and fallthrough blocks as its successors.
5753 while(!BB->succ_empty())
5754 BB->removeSuccessor(BB->succ_begin());
5755 BB->addSuccessor(copy0MBB);
5756 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005757
Evan Cheng60c07e12006-07-05 22:17:51 +00005758 // copy0MBB:
5759 // %FalseValue = ...
5760 // # fallthrough to sinkMBB
5761 BB = copy0MBB;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005762
Evan Cheng60c07e12006-07-05 22:17:51 +00005763 // Update machine-CFG edges
5764 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005765
Evan Cheng60c07e12006-07-05 22:17:51 +00005766 // sinkMBB:
5767 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5768 // ...
5769 BB = sinkMBB;
Evan Chengc0f64ff2006-11-27 23:37:22 +00005770 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
Evan Cheng60c07e12006-07-05 22:17:51 +00005771 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5772 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5773
5774 delete MI; // The pseudo instruction is gone now.
5775 return BB;
5776 }
5777
Dale Johannesen849f2142007-07-03 00:53:03 +00005778 case X86::FP32_TO_INT16_IN_MEM:
5779 case X86::FP32_TO_INT32_IN_MEM:
5780 case X86::FP32_TO_INT64_IN_MEM:
5781 case X86::FP64_TO_INT16_IN_MEM:
5782 case X86::FP64_TO_INT32_IN_MEM:
Dale Johannesena996d522007-08-07 01:17:37 +00005783 case X86::FP64_TO_INT64_IN_MEM:
5784 case X86::FP80_TO_INT16_IN_MEM:
5785 case X86::FP80_TO_INT32_IN_MEM:
5786 case X86::FP80_TO_INT64_IN_MEM: {
Evan Cheng60c07e12006-07-05 22:17:51 +00005787 // Change the floating point control register to use "round towards zero"
5788 // mode when truncating to an integer value.
5789 MachineFunction *F = BB->getParent();
5790 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
Evan Chengc0f64ff2006-11-27 23:37:22 +00005791 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005792
5793 // Load the old value of the high byte of the control word...
5794 unsigned OldCW =
Chris Lattner84bc5422007-12-31 04:13:23 +00005795 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
Evan Chengc0f64ff2006-11-27 23:37:22 +00005796 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005797
5798 // Set the high part to be round to zero...
Evan Chengc0f64ff2006-11-27 23:37:22 +00005799 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5800 .addImm(0xC7F);
Evan Cheng60c07e12006-07-05 22:17:51 +00005801
5802 // Reload the modified control word now...
Evan Chengc0f64ff2006-11-27 23:37:22 +00005803 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005804
5805 // Restore the memory image of control word to original value
Evan Chengc0f64ff2006-11-27 23:37:22 +00005806 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5807 .addReg(OldCW);
Evan Cheng60c07e12006-07-05 22:17:51 +00005808
5809 // Get the X86 opcode to use.
5810 unsigned Opc;
5811 switch (MI->getOpcode()) {
5812 default: assert(0 && "illegal opcode!");
Dale Johannesene377d4d2007-07-04 21:07:47 +00005813 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
5814 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
5815 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
5816 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
5817 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5818 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
Dale Johannesena996d522007-08-07 01:17:37 +00005819 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5820 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5821 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
Evan Cheng60c07e12006-07-05 22:17:51 +00005822 }
5823
5824 X86AddressMode AM;
5825 MachineOperand &Op = MI->getOperand(0);
5826 if (Op.isRegister()) {
5827 AM.BaseType = X86AddressMode::RegBase;
5828 AM.Base.Reg = Op.getReg();
5829 } else {
5830 AM.BaseType = X86AddressMode::FrameIndexBase;
Chris Lattner8aa797a2007-12-30 23:10:15 +00005831 AM.Base.FrameIndex = Op.getIndex();
Evan Cheng60c07e12006-07-05 22:17:51 +00005832 }
5833 Op = MI->getOperand(1);
5834 if (Op.isImmediate())
Chris Lattner7fbe9722006-10-20 17:42:20 +00005835 AM.Scale = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00005836 Op = MI->getOperand(2);
5837 if (Op.isImmediate())
Chris Lattner7fbe9722006-10-20 17:42:20 +00005838 AM.IndexReg = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00005839 Op = MI->getOperand(3);
5840 if (Op.isGlobalAddress()) {
5841 AM.GV = Op.getGlobal();
5842 } else {
Chris Lattner7fbe9722006-10-20 17:42:20 +00005843 AM.Disp = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00005844 }
Evan Chengc0f64ff2006-11-27 23:37:22 +00005845 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5846 .addReg(MI->getOperand(4).getReg());
Evan Cheng60c07e12006-07-05 22:17:51 +00005847
5848 // Reload the original control word now.
Evan Chengc0f64ff2006-11-27 23:37:22 +00005849 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005850
5851 delete MI; // The pseudo instruction is gone now.
5852 return BB;
5853 }
5854 }
5855}
5856
5857//===----------------------------------------------------------------------===//
5858// X86 Optimization Hooks
5859//===----------------------------------------------------------------------===//
5860
Nate Begeman368e18d2006-02-16 21:11:51 +00005861void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
Dan Gohman977a76f2008-02-13 22:28:48 +00005862 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00005863 APInt &KnownZero,
5864 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00005865 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +00005866 unsigned Depth) const {
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005867 unsigned Opc = Op.getOpcode();
Evan Cheng865f0602006-04-05 06:11:20 +00005868 assert((Opc >= ISD::BUILTIN_OP_END ||
5869 Opc == ISD::INTRINSIC_WO_CHAIN ||
5870 Opc == ISD::INTRINSIC_W_CHAIN ||
5871 Opc == ISD::INTRINSIC_VOID) &&
5872 "Should use MaskedValueIsZero if you don't know whether Op"
5873 " is a target node!");
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005874
Dan Gohmanf4f92f52008-02-13 23:07:24 +00005875 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005876 switch (Opc) {
Evan Cheng865f0602006-04-05 06:11:20 +00005877 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005878 case X86ISD::SETCC:
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00005879 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
5880 Mask.getBitWidth() - 1);
Nate Begeman368e18d2006-02-16 21:11:51 +00005881 break;
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005882 }
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005883}
Chris Lattner259e97c2006-01-31 19:43:35 +00005884
Evan Cheng206ee9d2006-07-07 08:33:52 +00005885/// getShuffleScalarElt - Returns the scalar element that will make up the ith
5886/// element of the result of the vector shuffle.
5887static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5888 MVT::ValueType VT = N->getValueType(0);
5889 SDOperand PermMask = N->getOperand(2);
5890 unsigned NumElems = PermMask.getNumOperands();
5891 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5892 i %= NumElems;
5893 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5894 return (i == 0)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005895 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
Evan Cheng206ee9d2006-07-07 08:33:52 +00005896 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5897 SDOperand Idx = PermMask.getOperand(i);
5898 if (Idx.getOpcode() == ISD::UNDEF)
Dan Gohman51eaa862007-06-14 22:58:02 +00005899 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
Evan Cheng206ee9d2006-07-07 08:33:52 +00005900 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5901 }
5902 return SDOperand();
5903}
5904
5905/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5906/// node is a GlobalAddress + an offset.
5907static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
Evan Cheng0085a282006-11-30 21:55:46 +00005908 unsigned Opc = N->getOpcode();
Evan Cheng19f2ffc2006-12-05 04:01:03 +00005909 if (Opc == X86ISD::Wrapper) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005910 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5911 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5912 return true;
5913 }
Evan Cheng0085a282006-11-30 21:55:46 +00005914 } else if (Opc == ISD::ADD) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005915 SDOperand N1 = N->getOperand(0);
5916 SDOperand N2 = N->getOperand(1);
5917 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5918 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5919 if (V) {
5920 Offset += V->getSignExtended();
5921 return true;
5922 }
5923 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5924 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5925 if (V) {
5926 Offset += V->getSignExtended();
5927 return true;
5928 }
5929 }
5930 }
5931 return false;
5932}
5933
5934/// isConsecutiveLoad - Returns true if N is loading from an address of Base
5935/// + Dist * Size.
5936static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5937 MachineFrameInfo *MFI) {
5938 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5939 return false;
5940
5941 SDOperand Loc = N->getOperand(1);
5942 SDOperand BaseLoc = Base->getOperand(1);
5943 if (Loc.getOpcode() == ISD::FrameIndex) {
5944 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5945 return false;
Dan Gohman275769a2007-07-23 20:24:29 +00005946 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5947 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
Evan Cheng206ee9d2006-07-07 08:33:52 +00005948 int FS = MFI->getObjectSize(FI);
5949 int BFS = MFI->getObjectSize(BFI);
5950 if (FS != BFS || FS != Size) return false;
5951 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5952 } else {
5953 GlobalValue *GV1 = NULL;
5954 GlobalValue *GV2 = NULL;
5955 int64_t Offset1 = 0;
5956 int64_t Offset2 = 0;
5957 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5958 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5959 if (isGA1 && isGA2 && GV1 == GV2)
5960 return Offset1 == (Offset2 + Dist*Size);
5961 }
5962
5963 return false;
5964}
5965
Evan Cheng1e60c092006-07-10 21:37:44 +00005966static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5967 const X86Subtarget *Subtarget) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005968 GlobalValue *GV;
Nick Lewycky916a9f02008-02-02 08:29:58 +00005969 int64_t Offset = 0;
Evan Cheng206ee9d2006-07-07 08:33:52 +00005970 if (isGAPlusOffset(Base, GV, Offset))
5971 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
Chris Lattnerba96fbc2008-01-26 20:07:42 +00005972 // DAG combine handles the stack object case.
Evan Cheng206ee9d2006-07-07 08:33:52 +00005973 return false;
5974}
5975
5976
5977/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5978/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5979/// if the load addresses are consecutive, non-overlapping, and in the right
5980/// order.
Evan Cheng1e60c092006-07-10 21:37:44 +00005981static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5982 const X86Subtarget *Subtarget) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005983 MachineFunction &MF = DAG.getMachineFunction();
5984 MachineFrameInfo *MFI = MF.getFrameInfo();
5985 MVT::ValueType VT = N->getValueType(0);
Dan Gohman51eaa862007-06-14 22:58:02 +00005986 MVT::ValueType EVT = MVT::getVectorElementType(VT);
Evan Cheng206ee9d2006-07-07 08:33:52 +00005987 SDOperand PermMask = N->getOperand(2);
5988 int NumElems = (int)PermMask.getNumOperands();
5989 SDNode *Base = NULL;
5990 for (int i = 0; i < NumElems; ++i) {
5991 SDOperand Idx = PermMask.getOperand(i);
5992 if (Idx.getOpcode() == ISD::UNDEF) {
5993 if (!Base) return SDOperand();
5994 } else {
5995 SDOperand Arg =
5996 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
Evan Cheng466685d2006-10-09 20:57:25 +00005997 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
Evan Cheng206ee9d2006-07-07 08:33:52 +00005998 return SDOperand();
5999 if (!Base)
6000 Base = Arg.Val;
6001 else if (!isConsecutiveLoad(Arg.Val, Base,
6002 i, MVT::getSizeInBits(EVT)/8,MFI))
6003 return SDOperand();
6004 }
6005 }
6006
Evan Cheng1e60c092006-07-10 21:37:44 +00006007 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
Dan Gohmand3006222007-07-27 17:16:43 +00006008 LoadSDNode *LD = cast<LoadSDNode>(Base);
Evan Cheng466685d2006-10-09 20:57:25 +00006009 if (isAlign16) {
Evan Cheng466685d2006-10-09 20:57:25 +00006010 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
Dan Gohmand3006222007-07-27 17:16:43 +00006011 LD->getSrcValueOffset(), LD->isVolatile());
Evan Cheng466685d2006-10-09 20:57:25 +00006012 } else {
Dan Gohmand3006222007-07-27 17:16:43 +00006013 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6014 LD->getSrcValueOffset(), LD->isVolatile(),
6015 LD->getAlignment());
Evan Cheng311ace02006-08-11 07:35:45 +00006016 }
Evan Cheng206ee9d2006-07-07 08:33:52 +00006017}
6018
Chris Lattner83e6c992006-10-04 06:57:07 +00006019/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6020static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6021 const X86Subtarget *Subtarget) {
6022 SDOperand Cond = N->getOperand(0);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006023
Chris Lattner83e6c992006-10-04 06:57:07 +00006024 // If we have SSE[12] support, try to form min/max nodes.
6025 if (Subtarget->hasSSE2() &&
6026 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6027 if (Cond.getOpcode() == ISD::SETCC) {
6028 // Get the LHS/RHS of the select.
6029 SDOperand LHS = N->getOperand(1);
6030 SDOperand RHS = N->getOperand(2);
6031 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006032
Evan Cheng8ca29322006-11-10 21:43:37 +00006033 unsigned Opcode = 0;
Chris Lattner83e6c992006-10-04 06:57:07 +00006034 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
Chris Lattner1907a7b2006-10-05 04:11:26 +00006035 switch (CC) {
6036 default: break;
6037 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6038 case ISD::SETULE:
6039 case ISD::SETLE:
6040 if (!UnsafeFPMath) break;
6041 // FALL THROUGH.
6042 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6043 case ISD::SETLT:
Evan Cheng8ca29322006-11-10 21:43:37 +00006044 Opcode = X86ISD::FMIN;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006045 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006046
Chris Lattner1907a7b2006-10-05 04:11:26 +00006047 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6048 case ISD::SETUGT:
6049 case ISD::SETGT:
6050 if (!UnsafeFPMath) break;
6051 // FALL THROUGH.
6052 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6053 case ISD::SETGE:
Evan Cheng8ca29322006-11-10 21:43:37 +00006054 Opcode = X86ISD::FMAX;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006055 break;
6056 }
Chris Lattner83e6c992006-10-04 06:57:07 +00006057 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
Chris Lattner1907a7b2006-10-05 04:11:26 +00006058 switch (CC) {
6059 default: break;
6060 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6061 case ISD::SETUGT:
6062 case ISD::SETGT:
6063 if (!UnsafeFPMath) break;
6064 // FALL THROUGH.
6065 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6066 case ISD::SETGE:
Evan Cheng8ca29322006-11-10 21:43:37 +00006067 Opcode = X86ISD::FMIN;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006068 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006069
Chris Lattner1907a7b2006-10-05 04:11:26 +00006070 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6071 case ISD::SETULE:
6072 case ISD::SETLE:
6073 if (!UnsafeFPMath) break;
6074 // FALL THROUGH.
6075 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6076 case ISD::SETLT:
Evan Cheng8ca29322006-11-10 21:43:37 +00006077 Opcode = X86ISD::FMAX;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006078 break;
6079 }
Chris Lattner83e6c992006-10-04 06:57:07 +00006080 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006081
Evan Cheng8ca29322006-11-10 21:43:37 +00006082 if (Opcode)
6083 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
Chris Lattner83e6c992006-10-04 06:57:07 +00006084 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006085
Chris Lattner83e6c992006-10-04 06:57:07 +00006086 }
6087
6088 return SDOperand();
6089}
6090
Chris Lattner149a4e52008-02-22 02:09:43 +00006091/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6092static SDOperand PerformSTORECombine(StoreSDNode *St, SelectionDAG &DAG,
6093 const X86Subtarget *Subtarget) {
6094 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6095 // the FP state in cases where an emms may be missing.
Dale Johannesen079f2a62008-02-25 19:20:14 +00006096 // A preferable solution to the general problem is to figure out the right
6097 // places to insert EMMS. This qualifies as a quick hack.
Chris Lattner149a4e52008-02-22 02:09:43 +00006098 if (MVT::isVector(St->getValue().getValueType()) &&
6099 MVT::getSizeInBits(St->getValue().getValueType()) == 64 &&
Dale Johannesen079f2a62008-02-25 19:20:14 +00006100 isa<LoadSDNode>(St->getValue()) &&
6101 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6102 St->getChain().hasOneUse() && !St->isVolatile()) {
Dale Johannesen14e2ea92008-02-25 22:29:22 +00006103 SDNode* LdVal = St->getValue().Val;
Dale Johannesen079f2a62008-02-25 19:20:14 +00006104 LoadSDNode *Ld = 0;
6105 int TokenFactorIndex = -1;
6106 SmallVector<SDOperand, 8> Ops;
6107 SDNode* ChainVal = St->getChain().Val;
6108 // Must be a store of a load. We currently handle two cases: the load
6109 // is a direct child, and it's under an intervening TokenFactor. It is
6110 // possible to dig deeper under nested TokenFactors.
Dale Johannesen14e2ea92008-02-25 22:29:22 +00006111 if (ChainVal == LdVal)
Dale Johannesen079f2a62008-02-25 19:20:14 +00006112 Ld = cast<LoadSDNode>(St->getChain());
6113 else if (St->getValue().hasOneUse() &&
6114 ChainVal->getOpcode() == ISD::TokenFactor) {
6115 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
Dale Johannesen14e2ea92008-02-25 22:29:22 +00006116 if (ChainVal->getOperand(i).Val == LdVal) {
Dale Johannesen079f2a62008-02-25 19:20:14 +00006117 TokenFactorIndex = i;
6118 Ld = cast<LoadSDNode>(St->getValue());
6119 } else
6120 Ops.push_back(ChainVal->getOperand(i));
6121 }
6122 }
6123 if (Ld) {
6124 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6125 if (Subtarget->is64Bit()) {
6126 SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6127 Ld->getBasePtr(), Ld->getSrcValue(),
6128 Ld->getSrcValueOffset(), Ld->isVolatile(),
6129 Ld->getAlignment());
6130 SDOperand NewChain = NewLd.getValue(1);
6131 if (TokenFactorIndex != -1) {
6132 Ops.push_back(NewLd);
6133 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6134 Ops.size());
6135 }
6136 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6137 St->getSrcValue(), St->getSrcValueOffset(),
6138 St->isVolatile(), St->getAlignment());
6139 }
6140
6141 // Otherwise, lower to two 32-bit copies.
6142 SDOperand LoAddr = Ld->getBasePtr();
6143 SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6144 DAG.getConstant(MVT::i32, 4));
6145
6146 SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6147 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6148 Ld->isVolatile(), Ld->getAlignment());
6149 SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6150 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6151 Ld->isVolatile(),
6152 MinAlign(Ld->getAlignment(), 4));
6153
6154 SDOperand NewChain = LoLd.getValue(1);
6155 if (TokenFactorIndex != -1) {
6156 Ops.push_back(LoLd);
6157 Ops.push_back(HiLd);
6158 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6159 Ops.size());
6160 }
6161
6162 LoAddr = St->getBasePtr();
6163 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6164 DAG.getConstant(MVT::i32, 4));
6165
6166 SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
Chris Lattner149a4e52008-02-22 02:09:43 +00006167 St->getSrcValue(), St->getSrcValueOffset(),
6168 St->isVolatile(), St->getAlignment());
Dale Johannesen079f2a62008-02-25 19:20:14 +00006169 SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6170 St->getSrcValue(), St->getSrcValueOffset()+4,
6171 St->isVolatile(),
6172 MinAlign(St->getAlignment(), 4));
6173 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
Chris Lattner149a4e52008-02-22 02:09:43 +00006174 }
Chris Lattner149a4e52008-02-22 02:09:43 +00006175 }
6176 return SDOperand();
6177}
6178
Chris Lattner6cf73262008-01-25 06:14:17 +00006179/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6180/// X86ISD::FXOR nodes.
Chris Lattneraf723b92008-01-25 05:46:26 +00006181static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
Chris Lattner6cf73262008-01-25 06:14:17 +00006182 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6183 // F[X]OR(0.0, x) -> x
6184 // F[X]OR(x, 0.0) -> x
Chris Lattneraf723b92008-01-25 05:46:26 +00006185 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6186 if (C->getValueAPF().isPosZero())
6187 return N->getOperand(1);
6188 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6189 if (C->getValueAPF().isPosZero())
6190 return N->getOperand(0);
6191 return SDOperand();
6192}
6193
6194/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6195static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6196 // FAND(0.0, x) -> 0.0
6197 // FAND(x, 0.0) -> 0.0
6198 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6199 if (C->getValueAPF().isPosZero())
6200 return N->getOperand(0);
6201 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6202 if (C->getValueAPF().isPosZero())
6203 return N->getOperand(1);
6204 return SDOperand();
6205}
6206
Chris Lattner83e6c992006-10-04 06:57:07 +00006207
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006208SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
Evan Cheng206ee9d2006-07-07 08:33:52 +00006209 DAGCombinerInfo &DCI) const {
Evan Cheng206ee9d2006-07-07 08:33:52 +00006210 SelectionDAG &DAG = DCI.DAG;
6211 switch (N->getOpcode()) {
6212 default: break;
Chris Lattneraf723b92008-01-25 05:46:26 +00006213 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget);
6214 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
Chris Lattner149a4e52008-02-22 02:09:43 +00006215 case ISD::STORE:
6216 return PerformSTORECombine(cast<StoreSDNode>(N), DAG, Subtarget);
Chris Lattner6cf73262008-01-25 06:14:17 +00006217 case X86ISD::FXOR:
Chris Lattneraf723b92008-01-25 05:46:26 +00006218 case X86ISD::FOR: return PerformFORCombine(N, DAG);
6219 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
Evan Cheng206ee9d2006-07-07 08:33:52 +00006220 }
6221
6222 return SDOperand();
6223}
6224
Evan Cheng60c07e12006-07-05 22:17:51 +00006225//===----------------------------------------------------------------------===//
6226// X86 Inline Assembly Support
6227//===----------------------------------------------------------------------===//
6228
Chris Lattnerf4dff842006-07-11 02:54:03 +00006229/// getConstraintType - Given a constraint letter, return the type of
6230/// constraint it is for this target.
6231X86TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00006232X86TargetLowering::getConstraintType(const std::string &Constraint) const {
6233 if (Constraint.size() == 1) {
6234 switch (Constraint[0]) {
6235 case 'A':
6236 case 'r':
6237 case 'R':
6238 case 'l':
6239 case 'q':
6240 case 'Q':
6241 case 'x':
6242 case 'Y':
6243 return C_RegisterClass;
6244 default:
6245 break;
6246 }
Chris Lattnerf4dff842006-07-11 02:54:03 +00006247 }
Chris Lattner4234f572007-03-25 02:14:49 +00006248 return TargetLowering::getConstraintType(Constraint);
Chris Lattnerf4dff842006-07-11 02:54:03 +00006249}
6250
Dale Johannesenba2a0b92008-01-29 02:21:21 +00006251/// LowerXConstraint - try to replace an X constraint, which matches anything,
6252/// with another that has more specific requirements based on the type of the
6253/// corresponding operand.
6254void X86TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
6255 std::string& s) const {
6256 if (MVT::isFloatingPoint(ConstraintVT)) {
6257 if (Subtarget->hasSSE2())
6258 s = "Y";
6259 else if (Subtarget->hasSSE1())
6260 s = "x";
6261 else
6262 s = "f";
6263 } else
6264 return TargetLowering::lowerXConstraint(ConstraintVT, s);
6265}
6266
Chris Lattner48884cd2007-08-25 00:47:38 +00006267/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6268/// vector. If it is invalid, don't add anything to Ops.
6269void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
6270 char Constraint,
6271 std::vector<SDOperand>&Ops,
6272 SelectionDAG &DAG) {
6273 SDOperand Result(0, 0);
6274
Chris Lattner22aaf1d2006-10-31 20:13:11 +00006275 switch (Constraint) {
6276 default: break;
Devang Patel84f7fd22007-03-17 00:13:28 +00006277 case 'I':
Chris Lattner188b9fe2007-03-25 01:57:35 +00006278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Chris Lattner48884cd2007-08-25 00:47:38 +00006279 if (C->getValue() <= 31) {
6280 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6281 break;
6282 }
Devang Patel84f7fd22007-03-17 00:13:28 +00006283 }
Chris Lattner48884cd2007-08-25 00:47:38 +00006284 return;
Chris Lattner188b9fe2007-03-25 01:57:35 +00006285 case 'N':
6286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Chris Lattner48884cd2007-08-25 00:47:38 +00006287 if (C->getValue() <= 255) {
6288 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6289 break;
6290 }
Chris Lattner188b9fe2007-03-25 01:57:35 +00006291 }
Chris Lattner48884cd2007-08-25 00:47:38 +00006292 return;
Chris Lattnerdc43a882007-05-03 16:52:29 +00006293 case 'i': {
Chris Lattner22aaf1d2006-10-31 20:13:11 +00006294 // Literal immediates are always ok.
Chris Lattner48884cd2007-08-25 00:47:38 +00006295 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
6296 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
6297 break;
6298 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006299
Chris Lattnerdc43a882007-05-03 16:52:29 +00006300 // If we are in non-pic codegen mode, we allow the address of a global (with
6301 // an optional displacement) to be used with 'i'.
6302 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
6303 int64_t Offset = 0;
6304
6305 // Match either (GA) or (GA+C)
6306 if (GA) {
6307 Offset = GA->getOffset();
6308 } else if (Op.getOpcode() == ISD::ADD) {
6309 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6310 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6311 if (C && GA) {
6312 Offset = GA->getOffset()+C->getValue();
6313 } else {
6314 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6315 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6316 if (C && GA)
6317 Offset = GA->getOffset()+C->getValue();
6318 else
6319 C = 0, GA = 0;
6320 }
6321 }
6322
6323 if (GA) {
6324 // If addressing this global requires a load (e.g. in PIC mode), we can't
6325 // match.
6326 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
6327 false))
Chris Lattner48884cd2007-08-25 00:47:38 +00006328 return;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006329
Chris Lattnerdc43a882007-05-03 16:52:29 +00006330 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
6331 Offset);
Chris Lattner48884cd2007-08-25 00:47:38 +00006332 Result = Op;
6333 break;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00006334 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006335
Chris Lattner22aaf1d2006-10-31 20:13:11 +00006336 // Otherwise, not valid for this mode.
Chris Lattner48884cd2007-08-25 00:47:38 +00006337 return;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00006338 }
Chris Lattnerdc43a882007-05-03 16:52:29 +00006339 }
Chris Lattner48884cd2007-08-25 00:47:38 +00006340
6341 if (Result.Val) {
6342 Ops.push_back(Result);
6343 return;
6344 }
6345 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
Chris Lattner22aaf1d2006-10-31 20:13:11 +00006346}
6347
Chris Lattner259e97c2006-01-31 19:43:35 +00006348std::vector<unsigned> X86TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +00006349getRegClassForInlineAsmConstraint(const std::string &Constraint,
6350 MVT::ValueType VT) const {
Chris Lattner259e97c2006-01-31 19:43:35 +00006351 if (Constraint.size() == 1) {
6352 // FIXME: not handling fp-stack yet!
Chris Lattner259e97c2006-01-31 19:43:35 +00006353 switch (Constraint[0]) { // GCC X86 Constraint Letters
Chris Lattnerf4dff842006-07-11 02:54:03 +00006354 default: break; // Unknown constraint letter
6355 case 'A': // EAX/EDX
6356 if (VT == MVT::i32 || VT == MVT::i64)
6357 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
6358 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00006359 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
6360 case 'Q': // Q_REGS
Chris Lattner80a7ecc2006-05-06 00:29:37 +00006361 if (VT == MVT::i32)
6362 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
6363 else if (VT == MVT::i16)
6364 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
6365 else if (VT == MVT::i8)
Evan Cheng12914382007-08-13 23:27:11 +00006366 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
Chris Lattner03e6c702007-11-04 06:51:12 +00006367 else if (VT == MVT::i64)
6368 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
6369 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00006370 }
6371 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006372
Chris Lattner1efa40f2006-02-22 00:56:39 +00006373 return std::vector<unsigned>();
Chris Lattner259e97c2006-01-31 19:43:35 +00006374}
Chris Lattnerf76d1802006-07-31 23:26:50 +00006375
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006376std::pair<unsigned, const TargetRegisterClass*>
Chris Lattnerf76d1802006-07-31 23:26:50 +00006377X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6378 MVT::ValueType VT) const {
Chris Lattnerad043e82007-04-09 05:11:28 +00006379 // First, see if this is a constraint that directly corresponds to an LLVM
6380 // register class.
6381 if (Constraint.size() == 1) {
6382 // GCC Constraint Letters
6383 switch (Constraint[0]) {
6384 default: break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00006385 case 'r': // GENERAL_REGS
6386 case 'R': // LEGACY_REGS
6387 case 'l': // INDEX_REGS
6388 if (VT == MVT::i64 && Subtarget->is64Bit())
6389 return std::make_pair(0U, X86::GR64RegisterClass);
6390 if (VT == MVT::i32)
6391 return std::make_pair(0U, X86::GR32RegisterClass);
6392 else if (VT == MVT::i16)
6393 return std::make_pair(0U, X86::GR16RegisterClass);
6394 else if (VT == MVT::i8)
6395 return std::make_pair(0U, X86::GR8RegisterClass);
6396 break;
Chris Lattner6c284d72007-04-12 04:14:49 +00006397 case 'y': // MMX_REGS if MMX allowed.
6398 if (!Subtarget->hasMMX()) break;
6399 return std::make_pair(0U, X86::VR64RegisterClass);
6400 break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00006401 case 'Y': // SSE_REGS if SSE2 allowed
6402 if (!Subtarget->hasSSE2()) break;
6403 // FALL THROUGH.
6404 case 'x': // SSE_REGS if SSE1 allowed
6405 if (!Subtarget->hasSSE1()) break;
6406
6407 switch (VT) {
6408 default: break;
6409 // Scalar SSE types.
6410 case MVT::f32:
6411 case MVT::i32:
Chris Lattnerad043e82007-04-09 05:11:28 +00006412 return std::make_pair(0U, X86::FR32RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00006413 case MVT::f64:
6414 case MVT::i64:
Chris Lattnerad043e82007-04-09 05:11:28 +00006415 return std::make_pair(0U, X86::FR64RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00006416 // Vector types.
Chris Lattner0f65cad2007-04-09 05:49:22 +00006417 case MVT::v16i8:
6418 case MVT::v8i16:
6419 case MVT::v4i32:
6420 case MVT::v2i64:
6421 case MVT::v4f32:
6422 case MVT::v2f64:
6423 return std::make_pair(0U, X86::VR128RegisterClass);
6424 }
Chris Lattnerad043e82007-04-09 05:11:28 +00006425 break;
6426 }
6427 }
6428
Chris Lattnerf76d1802006-07-31 23:26:50 +00006429 // Use the default implementation in TargetLowering to convert the register
6430 // constraint into a member of a register class.
6431 std::pair<unsigned, const TargetRegisterClass*> Res;
6432 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
Chris Lattner1a60aa72006-10-31 19:42:44 +00006433
6434 // Not found as a standard register?
6435 if (Res.second == 0) {
6436 // GCC calls "st(0)" just plain "st".
6437 if (StringsEqualNoCase("{st}", Constraint)) {
6438 Res.first = X86::ST0;
Chris Lattner9b4baf12007-09-24 05:27:37 +00006439 Res.second = X86::RFP80RegisterClass;
Chris Lattner1a60aa72006-10-31 19:42:44 +00006440 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006441
Chris Lattner1a60aa72006-10-31 19:42:44 +00006442 return Res;
6443 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006444
Chris Lattnerf76d1802006-07-31 23:26:50 +00006445 // Otherwise, check to see if this is a register class of the wrong value
6446 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
6447 // turn into {ax},{dx}.
6448 if (Res.second->hasType(VT))
6449 return Res; // Correct type already, nothing to do.
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006450
Chris Lattnerf76d1802006-07-31 23:26:50 +00006451 // All of the single-register GCC register classes map their values onto
6452 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
6453 // really want an 8-bit or 32-bit register, map to the appropriate register
6454 // class and return the appropriate register.
6455 if (Res.second != X86::GR16RegisterClass)
6456 return Res;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006457
Chris Lattnerf76d1802006-07-31 23:26:50 +00006458 if (VT == MVT::i8) {
6459 unsigned DestReg = 0;
6460 switch (Res.first) {
6461 default: break;
6462 case X86::AX: DestReg = X86::AL; break;
6463 case X86::DX: DestReg = X86::DL; break;
6464 case X86::CX: DestReg = X86::CL; break;
6465 case X86::BX: DestReg = X86::BL; break;
6466 }
6467 if (DestReg) {
6468 Res.first = DestReg;
6469 Res.second = Res.second = X86::GR8RegisterClass;
6470 }
6471 } else if (VT == MVT::i32) {
6472 unsigned DestReg = 0;
6473 switch (Res.first) {
6474 default: break;
6475 case X86::AX: DestReg = X86::EAX; break;
6476 case X86::DX: DestReg = X86::EDX; break;
6477 case X86::CX: DestReg = X86::ECX; break;
6478 case X86::BX: DestReg = X86::EBX; break;
6479 case X86::SI: DestReg = X86::ESI; break;
6480 case X86::DI: DestReg = X86::EDI; break;
6481 case X86::BP: DestReg = X86::EBP; break;
6482 case X86::SP: DestReg = X86::ESP; break;
6483 }
6484 if (DestReg) {
6485 Res.first = DestReg;
6486 Res.second = Res.second = X86::GR32RegisterClass;
6487 }
Evan Cheng25ab6902006-09-08 06:48:29 +00006488 } else if (VT == MVT::i64) {
6489 unsigned DestReg = 0;
6490 switch (Res.first) {
6491 default: break;
6492 case X86::AX: DestReg = X86::RAX; break;
6493 case X86::DX: DestReg = X86::RDX; break;
6494 case X86::CX: DestReg = X86::RCX; break;
6495 case X86::BX: DestReg = X86::RBX; break;
6496 case X86::SI: DestReg = X86::RSI; break;
6497 case X86::DI: DestReg = X86::RDI; break;
6498 case X86::BP: DestReg = X86::RBP; break;
6499 case X86::SP: DestReg = X86::RSP; break;
6500 }
6501 if (DestReg) {
6502 Res.first = DestReg;
6503 Res.second = Res.second = X86::GR64RegisterClass;
6504 }
Chris Lattnerf76d1802006-07-31 23:26:50 +00006505 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006506
Chris Lattnerf76d1802006-07-31 23:26:50 +00006507 return Res;
6508}