Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 3, |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 28 | SDTCisVT<3, i8>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 30 | def SDTX86BrCond : SDTypeProfile<0, 2, |
| 31 | [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 32 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 33 | def SDTX86SetCC : SDTypeProfile<1, 1, |
| 34 | [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 35 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 36 | def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 37 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 38 | def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; |
| 39 | def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>, |
| 40 | SDTCisVT<1, i32> ]>; |
| 41 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 42 | def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 43 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 44 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 45 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 46 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 47 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 48 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 49 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame^] | 50 | def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>; |
| 51 | |
| 52 | def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; |
| 53 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 54 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 55 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 56 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 57 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 58 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 59 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 60 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 61 | [SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 62 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 63 | [SDNPHasChain, SDNPInFlag]>; |
Evan Cheng | 5ee4ccc | 2006-01-12 08:27:59 +0000 | [diff] [blame] | 64 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 65 | [SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 66 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 67 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 68 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 69 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 70 | def X86callseq_start : |
| 71 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 72 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 73 | def X86callseq_end : |
| 74 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Chris Lattner | af63bb0 | 2006-01-24 05:17:12 +0000 | [diff] [blame] | 75 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 76 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 77 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 78 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 79 | |
Evan Cheng | fb914c4 | 2006-05-20 01:40:16 +0000 | [diff] [blame] | 80 | def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call, |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 81 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
| 82 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 83 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Evan Cheng | 9925642 | 2006-03-07 23:34:23 +0000 | [diff] [blame] | 84 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 85 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Evan Cheng | 9925642 | 2006-03-07 23:34:23 +0000 | [diff] [blame] | 86 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 87 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 88 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
| 89 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 90 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 91 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 92 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 93 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame^] | 94 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
| 95 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
| 96 | def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>; |
| 97 | |
| 98 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 99 | //===----------------------------------------------------------------------===// |
| 100 | // X86 Operand Definitions. |
| 101 | // |
| 102 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 103 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 104 | // |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 105 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 106 | let PrintMethod = printMethod; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 107 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 108 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 109 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 110 | def i8mem : X86MemOperand<"printi8mem">; |
| 111 | def i16mem : X86MemOperand<"printi16mem">; |
| 112 | def i32mem : X86MemOperand<"printi32mem">; |
| 113 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 114 | def i128mem : X86MemOperand<"printi128mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 115 | def f32mem : X86MemOperand<"printf32mem">; |
| 116 | def f64mem : X86MemOperand<"printf64mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 117 | def f128mem : X86MemOperand<"printf128mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 118 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 119 | def lea32mem : Operand<i32> { |
| 120 | let PrintMethod = "printi32mem"; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 121 | let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm); |
| 122 | } |
| 123 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 124 | def SSECC : Operand<i8> { |
| 125 | let PrintMethod = "printSSECC"; |
| 126 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 127 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 128 | def piclabel: Operand<i32> { |
| 129 | let PrintMethod = "printPICLabel"; |
| 130 | } |
| 131 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 132 | // A couple of more descriptive operand definitions. |
| 133 | // 16-bits but only 8 bits are significant. |
| 134 | def i16i8imm : Operand<i16>; |
| 135 | // 32-bits but only 8 bits are significant. |
| 136 | def i32i8imm : Operand<i32>; |
| 137 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 138 | // Branch targets have OtherVT type. |
| 139 | def brtarget : Operand<OtherVT>; |
| 140 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 141 | //===----------------------------------------------------------------------===// |
| 142 | // X86 Complex Pattern Definitions. |
| 143 | // |
| 144 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 145 | // Define X86 specific addressing mode. |
Evan Cheng | af9db75 | 2006-10-11 21:03:53 +0000 | [diff] [blame] | 146 | def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 147 | def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Evan Cheng | af9db75 | 2006-10-11 21:03:53 +0000 | [diff] [blame] | 148 | [add, mul, shl, or, frameindex], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 149 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 150 | //===----------------------------------------------------------------------===// |
| 151 | // X86 Instruction Format Definitions. |
| 152 | // |
| 153 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 154 | // Format specifies the encoding used by the instruction. This is part of the |
| 155 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 156 | // code emitter. |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 157 | class Format<bits<6> val> { |
| 158 | bits<6> Value = val; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 162 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 163 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 164 | def MRMSrcMem : Format<6>; |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 165 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 166 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 167 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 168 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 169 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 170 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 171 | def MRMInitReg : Format<32>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 172 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 173 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 174 | // X86 Instruction Predicate Definitions. |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 175 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
| 176 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
| 177 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 178 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 179 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 180 | def FPStack : Predicate<"!Subtarget->hasSSE2()">; |
| 181 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 182 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
| 183 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 184 | def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">; |
| 185 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 186 | |
| 187 | //===----------------------------------------------------------------------===// |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 188 | // X86 specific pattern fragments. |
| 189 | // |
| 190 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 191 | // ImmType - This specifies the immediate type used by an instruction. This is |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 192 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 193 | // machine code emitter. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 194 | class ImmType<bits<3> val> { |
| 195 | bits<3> Value = val; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 196 | } |
| 197 | def NoImm : ImmType<0>; |
| 198 | def Imm8 : ImmType<1>; |
| 199 | def Imm16 : ImmType<2>; |
| 200 | def Imm32 : ImmType<3>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 201 | def Imm64 : ImmType<4>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 202 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 203 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 204 | // the Floating-Point stackifier pass. |
| 205 | class FPFormat<bits<3> val> { |
| 206 | bits<3> Value = val; |
| 207 | } |
| 208 | def NotFP : FPFormat<0>; |
| 209 | def ZeroArgFP : FPFormat<1>; |
| 210 | def OneArgFP : FPFormat<2>; |
| 211 | def OneArgFPRW : FPFormat<3>; |
| 212 | def TwoArgFP : FPFormat<4>; |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 213 | def CompareFP : FPFormat<5>; |
| 214 | def CondMovFP : FPFormat<6>; |
| 215 | def SpecialFP : FPFormat<7>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 216 | |
| 217 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 218 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> |
| 219 | : Instruction { |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 220 | let Namespace = "X86"; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 221 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 222 | bits<8> Opcode = opcod; |
| 223 | Format Form = f; |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 224 | bits<6> FormBits = Form.Value; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 225 | ImmType ImmT = i; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 226 | bits<3> ImmTypeBits = ImmT.Value; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 227 | |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 228 | dag OperandList = ops; |
| 229 | string AsmString = AsmStr; |
| 230 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 231 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 232 | // Attributes specific to X86 instructions... |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 233 | // |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 234 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
| 235 | bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 236 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 237 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 238 | bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix? |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 239 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 240 | bits<3> FPFormBits = 0; |
| 241 | } |
| 242 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 243 | |
| 244 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 245 | // emitter that various prefix bytes are required. |
| 246 | class OpSize { bit hasOpSizePrefix = 1; } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 247 | class AdSize { bit hasAdSizePrefix = 1; } |
| 248 | class REX_W { bit hasREX_WPrefix = 1; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 249 | class TB { bits<4> Prefix = 1; } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 250 | class REP { bits<4> Prefix = 2; } |
| 251 | class D8 { bits<4> Prefix = 3; } |
| 252 | class D9 { bits<4> Prefix = 4; } |
| 253 | class DA { bits<4> Prefix = 5; } |
| 254 | class DB { bits<4> Prefix = 6; } |
| 255 | class DC { bits<4> Prefix = 7; } |
| 256 | class DD { bits<4> Prefix = 8; } |
| 257 | class DE { bits<4> Prefix = 9; } |
| 258 | class DF { bits<4> Prefix = 10; } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 259 | class XD { bits<4> Prefix = 11; } |
| 260 | class XS { bits<4> Prefix = 12; } |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 261 | class T8 { bits<4> Prefix = 13; } |
| 262 | class TA { bits<4> Prefix = 14; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 263 | |
| 264 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 265 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 266 | // Pattern fragments... |
| 267 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 268 | |
| 269 | // X86 specific condition code. These correspond to CondCode in |
| 270 | // X86ISelLowering.h. They must be kept in synch. |
| 271 | def X86_COND_A : PatLeaf<(i8 0)>; |
| 272 | def X86_COND_AE : PatLeaf<(i8 1)>; |
| 273 | def X86_COND_B : PatLeaf<(i8 2)>; |
| 274 | def X86_COND_BE : PatLeaf<(i8 3)>; |
| 275 | def X86_COND_E : PatLeaf<(i8 4)>; |
| 276 | def X86_COND_G : PatLeaf<(i8 5)>; |
| 277 | def X86_COND_GE : PatLeaf<(i8 6)>; |
| 278 | def X86_COND_L : PatLeaf<(i8 7)>; |
| 279 | def X86_COND_LE : PatLeaf<(i8 8)>; |
| 280 | def X86_COND_NE : PatLeaf<(i8 9)>; |
| 281 | def X86_COND_NO : PatLeaf<(i8 10)>; |
| 282 | def X86_COND_NP : PatLeaf<(i8 11)>; |
| 283 | def X86_COND_NS : PatLeaf<(i8 12)>; |
| 284 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 285 | def X86_COND_P : PatLeaf<(i8 14)>; |
| 286 | def X86_COND_S : PatLeaf<(i8 15)>; |
| 287 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 288 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 289 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 290 | // sign extended field. |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 291 | return (int16_t)N->getValue() == (int8_t)N->getValue(); |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 292 | }]>; |
| 293 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 294 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 295 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 296 | // sign extended field. |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 297 | return (int32_t)N->getValue() == (int8_t)N->getValue(); |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 298 | }]>; |
| 299 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 300 | // Helper fragments for loads. |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 301 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 302 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; |
| 303 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 304 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 305 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 306 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 307 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 308 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 309 | def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>; |
| 310 | def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>; |
| 311 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 312 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 313 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 314 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 315 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 316 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 317 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 318 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 319 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 320 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 321 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 322 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 323 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 324 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 325 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 326 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 327 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 328 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 329 | //===----------------------------------------------------------------------===// |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 330 | // Instruction templates... |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 331 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 332 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 333 | class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 334 | : X86Inst<o, f, NoImm, ops, asm> { |
| 335 | let Pattern = pattern; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 336 | let CodeSize = 3; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 337 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 338 | class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 339 | : X86Inst<o, f, Imm8 , ops, asm> { |
| 340 | let Pattern = pattern; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 341 | let CodeSize = 3; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 342 | } |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 343 | class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 344 | : X86Inst<o, f, Imm16, ops, asm> { |
| 345 | let Pattern = pattern; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 346 | let CodeSize = 3; |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 347 | } |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 348 | class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 349 | : X86Inst<o, f, Imm32, ops, asm> { |
| 350 | let Pattern = pattern; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 351 | let CodeSize = 3; |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 352 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 353 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 354 | //===----------------------------------------------------------------------===// |
| 355 | // Instruction list... |
| 356 | // |
| 357 | |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 358 | // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into |
| 359 | // a stack adjustment and the codegen must know that they may modify the stack |
| 360 | // pointer before prolog-epilog rewriting occurs. |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 361 | def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 362 | [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>; |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 363 | def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 364 | "#ADJCALLSTACKUP", |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 365 | [(X86callseq_end imm:$amt1, imm:$amt2)]>, |
| 366 | Imp<[ESP],[ESP]>; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 367 | def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; |
| 368 | def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 369 | def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 370 | "#IMPLICIT_DEF $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 371 | [(set GR8:$dst, (undef))]>; |
| 372 | def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 373 | "#IMPLICIT_DEF $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 374 | [(set GR16:$dst, (undef))]>; |
| 375 | def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 376 | "#IMPLICIT_DEF $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 377 | [(set GR32:$dst, (undef))]>; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 378 | |
| 379 | // Nop |
| 380 | def NOOP : I<0x90, RawFrm, (ops), "nop", []>; |
| 381 | |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 382 | // Truncate |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 383 | def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src), |
| 384 | "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>; |
| 385 | def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src), |
| 386 | "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>; |
| 387 | def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src), |
| 388 | "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}", |
| 389 | [(set GR16:$dst, (trunc GR32:$src))]>; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 390 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 391 | //===----------------------------------------------------------------------===// |
| 392 | // Control Flow Instructions... |
| 393 | // |
| 394 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 395 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 396 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
| 397 | hasCtrlDep = 1, noResults = 1 in { |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 398 | def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>; |
| 399 | def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", |
| 400 | [(X86retflag imm:$amt)]>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 401 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 402 | |
| 403 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 404 | let isBranch = 1, isTerminator = 1, noResults = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 405 | class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : |
| 406 | I<opcode, RawFrm, ops, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 407 | |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 408 | // Indirect branches |
Evan Cheng | ec3bc39 | 2006-09-07 19:03:48 +0000 | [diff] [blame] | 409 | let isBranch = 1, isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 410 | def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 411 | |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 412 | let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 413 | def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst", |
| 414 | [(brind GR32:$dst)]>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 415 | def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 416 | [(brind (loadi32 addr:$dst))]>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 417 | } |
| 418 | |
| 419 | // Conditional branches |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 420 | def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 421 | [(X86brcond bb:$dst, X86_COND_E)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 422 | def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 423 | [(X86brcond bb:$dst, X86_COND_NE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 424 | def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 425 | [(X86brcond bb:$dst, X86_COND_L)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 426 | def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 427 | [(X86brcond bb:$dst, X86_COND_LE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 428 | def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 429 | [(X86brcond bb:$dst, X86_COND_G)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 430 | def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 431 | [(X86brcond bb:$dst, X86_COND_GE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 432 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 433 | def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 434 | [(X86brcond bb:$dst, X86_COND_B)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 435 | def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 436 | [(X86brcond bb:$dst, X86_COND_BE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 437 | def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 438 | [(X86brcond bb:$dst, X86_COND_A)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 439 | def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 440 | [(X86brcond bb:$dst, X86_COND_AE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 441 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 442 | def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 443 | [(X86brcond bb:$dst, X86_COND_S)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 444 | def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 445 | [(X86brcond bb:$dst, X86_COND_NS)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 446 | def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 447 | [(X86brcond bb:$dst, X86_COND_P)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 448 | def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 449 | [(X86brcond bb:$dst, X86_COND_NP)]>, TB; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 450 | def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 451 | [(X86brcond bb:$dst, X86_COND_O)]>, TB; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 452 | def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 453 | [(X86brcond bb:$dst, X86_COND_NO)]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 454 | |
| 455 | //===----------------------------------------------------------------------===// |
| 456 | // Call Instructions... |
| 457 | // |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 458 | let isCall = 1, noResults = 1 in |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 459 | // All calls clobber the non-callee saved registers... |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 460 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 461 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { |
Evan Cheng | fae2994 | 2006-06-14 22:24:55 +0000 | [diff] [blame] | 462 | def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops), |
| 463 | "call ${dst:call}", []>; |
| 464 | def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), |
| 465 | "call {*}$dst", [(X86call GR32:$dst)]>; |
| 466 | def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops), |
| 467 | "call {*}$dst", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 468 | } |
| 469 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 470 | // Tail call stuff. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 471 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f10c17f | 2006-09-22 21:43:59 +0000 | [diff] [blame] | 472 | def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL", |
| 473 | []>; |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 474 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f10c17f | 2006-09-22 21:43:59 +0000 | [diff] [blame] | 475 | def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL", |
| 476 | []>; |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 477 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 478 | def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), |
| 479 | "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 480 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 481 | //===----------------------------------------------------------------------===// |
| 482 | // Miscellaneous Instructions... |
| 483 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 484 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 485 | (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 486 | def POP32r : I<0x58, AddRegFrm, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 487 | (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 488 | |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 489 | def PUSH32r : I<0x50, AddRegFrm, |
| 490 | (ops GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>; |
| 491 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 492 | def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label), |
| 493 | "call $label", []>; |
| 494 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 495 | let isTwoAddress = 1 in // GR32 = bswap GR32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 496 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 497 | (ops GR32:$dst, GR32:$src), |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 498 | "bswap{l} $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 499 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 500 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 501 | def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8 |
| 502 | (ops GR8:$src1, GR8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 503 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 504 | def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16 |
| 505 | (ops GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 506 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 507 | def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32 |
| 508 | (ops GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 509 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 510 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 511 | def XCHG8mr : I<0x86, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 512 | (ops i8mem:$src1, GR8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 513 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 514 | def XCHG16mr : I<0x87, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 515 | (ops i16mem:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 516 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 517 | def XCHG32mr : I<0x87, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 518 | (ops i32mem:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 519 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 520 | def XCHG8rm : I<0x86, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 521 | (ops GR8:$src1, i8mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 522 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 523 | def XCHG16rm : I<0x87, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 524 | (ops GR16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 525 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 526 | def XCHG32rm : I<0x87, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 527 | (ops GR32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 528 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 529 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 530 | def LEA16r : I<0x8D, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 531 | (ops GR16:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 532 | "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 533 | def LEA32r : I<0x8D, MRMSrcMem, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 534 | (ops GR32:$dst, lea32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 535 | "lea{l} {$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 536 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 537 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 538 | def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", |
| 539 | [(X86rep_movs i8)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 540 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 541 | def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", |
| 542 | [(X86rep_movs i16)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 543 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; |
Evan Cheng | 94b1453 | 2006-06-02 21:09:10 +0000 | [diff] [blame] | 544 | def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}", |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 545 | [(X86rep_movs i32)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 546 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 547 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 548 | def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", |
| 549 | [(X86rep_stos i8)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 550 | Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 551 | def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", |
| 552 | [(X86rep_stos i16)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 553 | Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 554 | def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", |
| 555 | [(X86rep_stos i32)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 556 | Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; |
| 557 | |
Evan Cheng | 3fa9dff | 2006-11-29 08:28:13 +0000 | [diff] [blame] | 558 | def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>, |
| 559 | TB, Imp<[],[RAX,RDX]>; |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 560 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 561 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 562 | // Input/Output Instructions... |
| 563 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 564 | def IN8rr : I<0xEC, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 565 | "in{b} {%dx, %al|%AL, %DX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 566 | []>, Imp<[DX], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 567 | def IN16rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 568 | "in{w} {%dx, %ax|%AX, %DX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 569 | []>, Imp<[DX], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 570 | def IN32rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 571 | "in{l} {%dx, %eax|%EAX, %DX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 572 | []>, Imp<[DX],[EAX]>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 573 | |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 574 | def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port), |
| 575 | "in{b} {$port, %al|%AL, $port}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 576 | []>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 577 | Imp<[], [AL]>; |
| 578 | def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 579 | "in{w} {$port, %ax|%AX, $port}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 580 | []>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 581 | Imp<[], [AX]>, OpSize; |
| 582 | def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 583 | "in{l} {$port, %eax|%EAX, $port}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 584 | []>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 585 | Imp<[],[EAX]>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 586 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 587 | def OUT8rr : I<0xEE, RawFrm, (ops), |
| 588 | "out{b} {%al, %dx|%DX, %AL}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 589 | []>, Imp<[DX, AL], []>; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 590 | def OUT16rr : I<0xEF, RawFrm, (ops), |
| 591 | "out{w} {%ax, %dx|%DX, %AX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 592 | []>, Imp<[DX, AX], []>, OpSize; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 593 | def OUT32rr : I<0xEF, RawFrm, (ops), |
| 594 | "out{l} {%eax, %dx|%DX, %EAX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 595 | []>, Imp<[DX, EAX], []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 596 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 597 | def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), |
| 598 | "out{b} {%al, $port|$port, %AL}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 599 | []>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 600 | Imp<[AL], []>; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 601 | def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 602 | "out{w} {%ax, $port|$port, %AX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 603 | []>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 604 | Imp<[AX], []>, OpSize; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 605 | def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 606 | "out{l} {%eax, $port|$port, %EAX}", |
Chris Lattner | 41edaa0 | 2006-03-03 00:19:58 +0000 | [diff] [blame] | 607 | []>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 608 | Imp<[EAX], []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 609 | |
| 610 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 611 | // Move Instructions... |
| 612 | // |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 613 | def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 614 | "mov{b} {$src, $dst|$dst, $src}", []>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 615 | def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 616 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 617 | def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 618 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Evan Cheng | 7681435 | 2007-03-21 00:16:56 +0000 | [diff] [blame] | 619 | let isReMaterializable = 1 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 620 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 621 | "mov{b} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 622 | [(set GR8:$dst, imm:$src)]>; |
| 623 | def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 624 | "mov{w} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 625 | [(set GR16:$dst, imm:$src)]>, OpSize; |
| 626 | def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 627 | "mov{l} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 628 | [(set GR32:$dst, imm:$src)]>; |
Evan Cheng | 7681435 | 2007-03-21 00:16:56 +0000 | [diff] [blame] | 629 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 630 | def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 631 | "mov{b} {$src, $dst|$dst, $src}", |
| 632 | [(store (i8 imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 633 | def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 634 | "mov{w} {$src, $dst|$dst, $src}", |
| 635 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 636 | def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 637 | "mov{l} {$src, $dst|$dst, $src}", |
| 638 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 639 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 640 | def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 641 | "mov{b} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 642 | [(set GR8:$dst, (load addr:$src))]>; |
| 643 | def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 644 | "mov{w} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 645 | [(set GR16:$dst, (load addr:$src))]>, OpSize; |
| 646 | def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 647 | "mov{l} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 648 | [(set GR32:$dst, (load addr:$src))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 649 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 650 | def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 651 | "mov{b} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 652 | [(store GR8:$src, addr:$dst)]>; |
| 653 | def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 654 | "mov{w} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 655 | [(store GR16:$src, addr:$dst)]>, OpSize; |
| 656 | def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 657 | "mov{l} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 658 | [(store GR32:$src, addr:$dst)]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 659 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 660 | //===----------------------------------------------------------------------===// |
| 661 | // Fixed-Register Multiplication and Division Instructions... |
| 662 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 663 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 664 | // Extra precision multiplication |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 665 | def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 666 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 667 | // This probably ought to be moved to a def : Pat<> if the |
| 668 | // syntax can be accepted. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 669 | [(set AL, (mul AL, GR8:$src))]>, |
| 670 | Imp<[AL],[AX]>; // AL,AH = AL*GR8 |
| 671 | def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>, |
| 672 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 |
| 673 | def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>, |
| 674 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 675 | def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 676 | "mul{b} $src", |
| 677 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 678 | // This probably ought to be moved to a def : Pat<> if the |
| 679 | // syntax can be accepted. |
| 680 | [(set AL, (mul AL, (loadi8 addr:$src)))]>, |
| 681 | Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 682 | def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 683 | "mul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 684 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 685 | def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 686 | "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 687 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 688 | def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>, |
| 689 | Imp<[AL],[AX]>; // AL,AH = AL*GR8 |
| 690 | def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>, |
| 691 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 |
| 692 | def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>, |
| 693 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 694 | def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 695 | "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 696 | def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 697 | "imul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 698 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 699 | def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 700 | "imul{l} $src", []>, |
| 701 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 702 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 703 | // unsigned division/remainder |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 704 | def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 705 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 706 | def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 707 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 708 | def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 709 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 710 | def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 711 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 712 | def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 713 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 714 | def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 715 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 716 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 717 | // Signed division/remainder. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 718 | def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 719 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 720 | def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 721 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 722 | def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 723 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 724 | def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 725 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 726 | def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 727 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 728 | def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 729 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 730 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 731 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 732 | //===----------------------------------------------------------------------===// |
| 733 | // Two address Instructions... |
| 734 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 735 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 736 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 737 | // Conditional moves |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 738 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 |
| 739 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 740 | "cmovb {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 741 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 742 | X86_COND_B))]>, |
| 743 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 744 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] |
| 745 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 746 | "cmovb {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 747 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 748 | X86_COND_B))]>, |
| 749 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 750 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32 |
| 751 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 752 | "cmovb {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 753 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 754 | X86_COND_B))]>, |
| 755 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 756 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32] |
| 757 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 758 | "cmovb {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 759 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 760 | X86_COND_B))]>, |
| 761 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 762 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 763 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 |
| 764 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 765 | "cmovae {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 766 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 767 | X86_COND_AE))]>, |
| 768 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 769 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] |
| 770 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 771 | "cmovae {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 772 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 773 | X86_COND_AE))]>, |
| 774 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 775 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 |
| 776 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 777 | "cmovae {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 778 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 779 | X86_COND_AE))]>, |
| 780 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 781 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] |
| 782 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 783 | "cmovae {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 784 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 785 | X86_COND_AE))]>, |
| 786 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 787 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 788 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 |
| 789 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 790 | "cmove {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 791 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 792 | X86_COND_E))]>, |
| 793 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 794 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] |
| 795 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 796 | "cmove {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 797 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 798 | X86_COND_E))]>, |
| 799 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 800 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 |
| 801 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 802 | "cmove {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 803 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 804 | X86_COND_E))]>, |
| 805 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 806 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] |
| 807 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 808 | "cmove {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 809 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 810 | X86_COND_E))]>, |
| 811 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 812 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 813 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 |
| 814 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 815 | "cmovne {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 816 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 817 | X86_COND_NE))]>, |
| 818 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 819 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] |
| 820 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 821 | "cmovne {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 822 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 823 | X86_COND_NE))]>, |
| 824 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 825 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 |
| 826 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 827 | "cmovne {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 828 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 829 | X86_COND_NE))]>, |
| 830 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 831 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] |
| 832 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 833 | "cmovne {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 834 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 835 | X86_COND_NE))]>, |
| 836 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 837 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 838 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 |
| 839 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 840 | "cmovbe {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 841 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 842 | X86_COND_BE))]>, |
| 843 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 844 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] |
| 845 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 846 | "cmovbe {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 847 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 848 | X86_COND_BE))]>, |
| 849 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 850 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 |
| 851 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 852 | "cmovbe {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 853 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 854 | X86_COND_BE))]>, |
| 855 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 856 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] |
| 857 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 858 | "cmovbe {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 859 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 860 | X86_COND_BE))]>, |
| 861 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 862 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 863 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 |
| 864 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 865 | "cmova {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 866 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 867 | X86_COND_A))]>, |
| 868 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 869 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] |
| 870 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 871 | "cmova {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 872 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 873 | X86_COND_A))]>, |
| 874 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 875 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 |
| 876 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 877 | "cmova {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 878 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 879 | X86_COND_A))]>, |
| 880 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 881 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] |
| 882 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 883 | "cmova {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 884 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 885 | X86_COND_A))]>, |
| 886 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 887 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 888 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16 |
| 889 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 890 | "cmovl {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 891 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 892 | X86_COND_L))]>, |
| 893 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 894 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16] |
| 895 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 896 | "cmovl {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 897 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 898 | X86_COND_L))]>, |
| 899 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 900 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 |
| 901 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 902 | "cmovl {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 903 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 904 | X86_COND_L))]>, |
| 905 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 906 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32] |
| 907 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 908 | "cmovl {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 909 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 910 | X86_COND_L))]>, |
| 911 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 912 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 913 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 |
| 914 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 915 | "cmovge {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 916 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 917 | X86_COND_GE))]>, |
| 918 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 919 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] |
| 920 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 921 | "cmovge {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 922 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 923 | X86_COND_GE))]>, |
| 924 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 925 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 |
| 926 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 927 | "cmovge {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 928 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 929 | X86_COND_GE))]>, |
| 930 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 931 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] |
| 932 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 933 | "cmovge {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 934 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 935 | X86_COND_GE))]>, |
| 936 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 937 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 938 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 |
| 939 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 940 | "cmovle {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 941 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 942 | X86_COND_LE))]>, |
| 943 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 944 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] |
| 945 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 946 | "cmovle {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 947 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 948 | X86_COND_LE))]>, |
| 949 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 950 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 |
| 951 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 952 | "cmovle {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 953 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 954 | X86_COND_LE))]>, |
| 955 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 956 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] |
| 957 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 958 | "cmovle {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 959 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 960 | X86_COND_LE))]>, |
| 961 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 962 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 963 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 |
| 964 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 965 | "cmovg {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 966 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 967 | X86_COND_G))]>, |
| 968 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 969 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] |
| 970 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 971 | "cmovg {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 972 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 973 | X86_COND_G))]>, |
| 974 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 975 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 |
| 976 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 977 | "cmovg {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 978 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 979 | X86_COND_G))]>, |
| 980 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 981 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] |
| 982 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 983 | "cmovg {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 984 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 985 | X86_COND_G))]>, |
| 986 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 987 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 988 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 |
| 989 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 990 | "cmovs {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 991 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 992 | X86_COND_S))]>, |
| 993 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 994 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] |
| 995 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 996 | "cmovs {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 997 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 998 | X86_COND_S))]>, |
| 999 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1000 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 |
| 1001 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1002 | "cmovs {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1003 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1004 | X86_COND_S))]>, |
| 1005 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1006 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] |
| 1007 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1008 | "cmovs {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1009 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1010 | X86_COND_S))]>, |
| 1011 | TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1012 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1013 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 |
| 1014 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1015 | "cmovns {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1016 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1017 | X86_COND_NS))]>, |
| 1018 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1019 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] |
| 1020 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1021 | "cmovns {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1022 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1023 | X86_COND_NS))]>, |
| 1024 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1025 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 |
| 1026 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1027 | "cmovns {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1028 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1029 | X86_COND_NS))]>, |
| 1030 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1031 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] |
| 1032 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1033 | "cmovns {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1034 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1035 | X86_COND_NS))]>, |
| 1036 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1037 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1038 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 |
| 1039 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1040 | "cmovp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1041 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1042 | X86_COND_P))]>, |
| 1043 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1044 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] |
| 1045 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1046 | "cmovp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1047 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1048 | X86_COND_P))]>, |
| 1049 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1050 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 |
| 1051 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1052 | "cmovp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1053 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1054 | X86_COND_P))]>, |
| 1055 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1056 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] |
| 1057 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1058 | "cmovp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1059 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1060 | X86_COND_P))]>, |
| 1061 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1062 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1063 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 |
| 1064 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1065 | "cmovnp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1066 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1067 | X86_COND_NP))]>, |
| 1068 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1069 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] |
| 1070 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1071 | "cmovnp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1072 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1073 | X86_COND_NP))]>, |
| 1074 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1075 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 |
| 1076 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1077 | "cmovnp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1078 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1079 | X86_COND_NP))]>, |
| 1080 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1081 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] |
| 1082 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1083 | "cmovnp {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1084 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1085 | X86_COND_NP))]>, |
| 1086 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1087 | |
| 1088 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1089 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1090 | let CodeSize = 2 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1091 | def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst", |
| 1092 | [(set GR8:$dst, (ineg GR8:$src))]>; |
| 1093 | def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst", |
| 1094 | [(set GR16:$dst, (ineg GR16:$src))]>, OpSize; |
| 1095 | def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst", |
| 1096 | [(set GR32:$dst, (ineg GR32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1097 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1098 | def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1099 | [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1100 | def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1101 | [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1102 | def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1103 | [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; |
| 1104 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1105 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1106 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1107 | def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst", |
| 1108 | [(set GR8:$dst, (not GR8:$src))]>; |
| 1109 | def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst", |
| 1110 | [(set GR16:$dst, (not GR16:$src))]>, OpSize; |
| 1111 | def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst", |
| 1112 | [(set GR32:$dst, (not GR32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1113 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1114 | def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1115 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1116 | def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1117 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1118 | def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1119 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1120 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1121 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1122 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1123 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1124 | let CodeSize = 2 in |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1125 | def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", |
| 1126 | [(set GR8:$dst, (add GR8:$src, 1))]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1127 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Evan Cheng | f7eb5d0 | 2006-07-11 19:49:49 +0000 | [diff] [blame] | 1128 | def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1129 | [(set GR16:$dst, (add GR16:$src, 1))]>, |
| 1130 | OpSize, Requires<[In32BitMode]>; |
Evan Cheng | f7eb5d0 | 2006-07-11 19:49:49 +0000 | [diff] [blame] | 1131 | def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1132 | [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1133 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1134 | let isTwoAddress = 0, CodeSize = 2 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1135 | def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1136 | [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1137 | def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1138 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1139 | def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1140 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1141 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1142 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1143 | let CodeSize = 2 in |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1144 | def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst", |
| 1145 | [(set GR8:$dst, (add GR8:$src, -1))]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1146 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Evan Cheng | f7eb5d0 | 2006-07-11 19:49:49 +0000 | [diff] [blame] | 1147 | def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1148 | [(set GR16:$dst, (add GR16:$src, -1))]>, |
| 1149 | OpSize, Requires<[In32BitMode]>; |
Evan Cheng | f7eb5d0 | 2006-07-11 19:49:49 +0000 | [diff] [blame] | 1150 | def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1151 | [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1152 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1153 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1154 | let isTwoAddress = 0, CodeSize = 2 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1155 | def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1156 | [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1157 | def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1158 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1159 | def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1160 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1161 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1162 | |
| 1163 | // Logical operators... |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1164 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1165 | def AND8rr : I<0x20, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1166 | (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1167 | "and{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1168 | [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1169 | def AND16rr : I<0x21, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1170 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1171 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1172 | [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1173 | def AND32rr : I<0x21, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1174 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1175 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1176 | [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1177 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1178 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1179 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1180 | (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1181 | "and{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1182 | [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1183 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1184 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1185 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1186 | [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1187 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1188 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1189 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1190 | [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1191 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1192 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1193 | (ops GR8 :$dst, GR8 :$src1, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1194 | "and{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1195 | [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1196 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1197 | (ops GR16:$dst, GR16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1198 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1199 | [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1200 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1201 | (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1202 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1203 | [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1204 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1205 | (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1206 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1207 | [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1208 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1209 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1210 | (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1211 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1212 | [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1213 | |
| 1214 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1215 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1216 | (ops i8mem :$dst, GR8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1217 | "and{b} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1218 | [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1219 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1220 | (ops i16mem:$dst, GR16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1221 | "and{w} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1222 | [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1223 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1224 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1225 | (ops i32mem:$dst, GR32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1226 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1227 | [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1228 | def AND8mi : Ii8<0x80, MRM4m, |
| 1229 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1230 | "and{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1231 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1232 | def AND16mi : Ii16<0x81, MRM4m, |
| 1233 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1234 | "and{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1235 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1236 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1237 | def AND32mi : Ii32<0x81, MRM4m, |
| 1238 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1239 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1240 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1241 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1242 | (ops i16mem:$dst, i16i8imm :$src), |
| 1243 | "and{w} {$src, $dst|$dst, $src}", |
| 1244 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1245 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1246 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1247 | (ops i32mem:$dst, i32i8imm :$src), |
| 1248 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | e3703d4 | 2006-01-14 01:18:49 +0000 | [diff] [blame] | 1249 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1250 | } |
| 1251 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1252 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1253 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1254 | def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1255 | "or{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1256 | [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>; |
| 1257 | def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1258 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1259 | [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize; |
| 1260 | def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1261 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1262 | [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1263 | } |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1264 | def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1265 | "or{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1266 | [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>; |
| 1267 | def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1268 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1269 | [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize; |
| 1270 | def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1271 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1272 | [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1273 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1274 | def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1275 | "or{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1276 | [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>; |
| 1277 | def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1278 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1279 | [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize; |
| 1280 | def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1281 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1282 | [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1283 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1284 | def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1285 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1286 | [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize; |
| 1287 | def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1288 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1289 | [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1290 | let isTwoAddress = 0 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1291 | def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1292 | "or{b} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1293 | [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; |
| 1294 | def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1295 | "or{w} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1296 | [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; |
| 1297 | def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1298 | "or{l} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1299 | [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1300 | def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1301 | "or{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1302 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1303 | def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1304 | "or{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1305 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1306 | OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1307 | def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1308 | "or{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1309 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1310 | def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src), |
| 1311 | "or{w} {$src, $dst|$dst, $src}", |
| 1312 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1313 | OpSize; |
| 1314 | def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src), |
| 1315 | "or{l} {$src, $dst|$dst, $src}", |
| 1316 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1317 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1318 | |
| 1319 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1320 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1321 | def XOR8rr : I<0x30, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1322 | (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1323 | "xor{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1324 | [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1325 | def XOR16rr : I<0x31, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1326 | (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1327 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1328 | [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1329 | def XOR32rr : I<0x31, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1330 | (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1331 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1332 | [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1333 | } |
| 1334 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1335 | def XOR8rm : I<0x32, MRMSrcMem , |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1336 | (ops GR8 :$dst, GR8:$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1337 | "xor{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1338 | [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1339 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1340 | (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1341 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1342 | [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1343 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1344 | (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1345 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1346 | [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1347 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1348 | def XOR8ri : Ii8<0x80, MRM6r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1349 | (ops GR8:$dst, GR8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1350 | "xor{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1351 | [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1352 | def XOR16ri : Ii16<0x81, MRM6r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1353 | (ops GR16:$dst, GR16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1354 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1355 | [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1356 | def XOR32ri : Ii32<0x81, MRM6r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1357 | (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1358 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1359 | [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1360 | def XOR16ri8 : Ii8<0x83, MRM6r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1361 | (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1362 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1363 | [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1364 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1365 | def XOR32ri8 : Ii8<0x83, MRM6r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1366 | (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1367 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1368 | [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1369 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1370 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1371 | (ops i8mem :$dst, GR8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1372 | "xor{b} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1373 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1374 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1375 | (ops i16mem:$dst, GR16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1376 | "xor{w} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1377 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1378 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1379 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1380 | (ops i32mem:$dst, GR32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1381 | "xor{l} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1382 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1383 | def XOR8mi : Ii8<0x80, MRM6m, |
| 1384 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1385 | "xor{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1386 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1387 | def XOR16mi : Ii16<0x81, MRM6m, |
| 1388 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1389 | "xor{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1390 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1391 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1392 | def XOR32mi : Ii32<0x81, MRM6m, |
| 1393 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1394 | "xor{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1395 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1396 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1397 | (ops i16mem:$dst, i16i8imm :$src), |
| 1398 | "xor{w} {$src, $dst|$dst, $src}", |
| 1399 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1400 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1401 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1402 | (ops i32mem:$dst, i32i8imm :$src), |
| 1403 | "xor{l} {$src, $dst|$dst, $src}", |
| 1404 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1405 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1406 | |
| 1407 | // Shift instructions |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1408 | def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1409 | "shl{b} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1410 | [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>; |
| 1411 | def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1412 | "shl{w} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1413 | [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
| 1414 | def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1415 | "shl{l} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1416 | [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1417 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1418 | def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1419 | "shl{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1420 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1421 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1422 | def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1423 | "shl{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1424 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1425 | def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1426 | "shl{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1427 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1428 | } |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1429 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1430 | // Shift left by one. Not used because (add x, x) is slightly cheaper. |
| 1431 | def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1), |
Evan Cheng | cbac2fa | 2006-07-20 21:37:39 +0000 | [diff] [blame] | 1432 | "shl{b} $dst", []>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1433 | def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1), |
Evan Cheng | cbac2fa | 2006-07-20 21:37:39 +0000 | [diff] [blame] | 1434 | "shl{w} $dst", []>, OpSize; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1435 | def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1), |
Evan Cheng | cbac2fa | 2006-07-20 21:37:39 +0000 | [diff] [blame] | 1436 | "shl{l} $dst", []>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1437 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1438 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1439 | def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1440 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1441 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1442 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1443 | def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1444 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1445 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1446 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1447 | def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1448 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1449 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1450 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1451 | def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1452 | "shl{b} {$src, $dst|$dst, $src}", |
| 1453 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1454 | def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1455 | "shl{w} {$src, $dst|$dst, $src}", |
| 1456 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1457 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1458 | def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1459 | "shl{l} {$src, $dst|$dst, $src}", |
| 1460 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1461 | |
| 1462 | // Shift by 1 |
| 1463 | def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst), |
| 1464 | "shl{b} $dst", |
| 1465 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 1466 | def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst), |
| 1467 | "shl{w} $dst", |
| 1468 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1469 | OpSize; |
| 1470 | def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst), |
| 1471 | "shl{l} $dst", |
| 1472 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1473 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1474 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1475 | def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1476 | "shr{b} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1477 | [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>; |
| 1478 | def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1479 | "shr{w} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1480 | [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
| 1481 | def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1482 | "shr{l} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1483 | [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1484 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1485 | def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1486 | "shr{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1487 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
| 1488 | def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1489 | "shr{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1490 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1491 | def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1492 | "shr{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1493 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1494 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1495 | // Shift by 1 |
| 1496 | def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1), |
| 1497 | "shr{b} $dst", |
| 1498 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
| 1499 | def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1), |
| 1500 | "shr{w} $dst", |
| 1501 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
| 1502 | def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1), |
| 1503 | "shr{l} $dst", |
| 1504 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
| 1505 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1506 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1507 | def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1508 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1509 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1510 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1511 | def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1512 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1513 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1514 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1515 | def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1516 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1517 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1518 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1519 | def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1520 | "shr{b} {$src, $dst|$dst, $src}", |
| 1521 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1522 | def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1523 | "shr{w} {$src, $dst|$dst, $src}", |
| 1524 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1525 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1526 | def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1527 | "shr{l} {$src, $dst|$dst, $src}", |
| 1528 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1529 | |
| 1530 | // Shift by 1 |
| 1531 | def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst), |
| 1532 | "shr{b} $dst", |
| 1533 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 1534 | def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst), |
| 1535 | "shr{w} $dst", |
| 1536 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
| 1537 | def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst), |
| 1538 | "shr{l} $dst", |
| 1539 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1540 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1541 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1542 | def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1543 | "sar{b} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1544 | [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>; |
| 1545 | def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1546 | "sar{w} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1547 | [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
| 1548 | def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1549 | "sar{l} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1550 | [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1551 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1552 | def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1553 | "sar{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1554 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
| 1555 | def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1556 | "sar{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1557 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1558 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1559 | def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1560 | "sar{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1561 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1562 | |
| 1563 | // Shift by 1 |
| 1564 | def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1), |
| 1565 | "sar{b} $dst", |
| 1566 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
| 1567 | def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1), |
| 1568 | "sar{w} $dst", |
| 1569 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
| 1570 | def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1), |
| 1571 | "sar{l} $dst", |
| 1572 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
| 1573 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1574 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1575 | def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1576 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1577 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1578 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1579 | def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1580 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1581 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1582 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1583 | def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1584 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1585 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1586 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1587 | def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1588 | "sar{b} {$src, $dst|$dst, $src}", |
| 1589 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1590 | def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1591 | "sar{w} {$src, $dst|$dst, $src}", |
| 1592 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1593 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1594 | def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1595 | "sar{l} {$src, $dst|$dst, $src}", |
| 1596 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1597 | |
| 1598 | // Shift by 1 |
| 1599 | def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst), |
| 1600 | "sar{b} $dst", |
| 1601 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 1602 | def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst), |
| 1603 | "sar{w} $dst", |
| 1604 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1605 | OpSize; |
| 1606 | def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst), |
| 1607 | "sar{l} $dst", |
| 1608 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1609 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1610 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1611 | // Rotate instructions |
| 1612 | // FIXME: provide shorter instructions when imm8 == 1 |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1613 | def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1614 | "rol{b} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1615 | [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>; |
| 1616 | def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1617 | "rol{w} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1618 | [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
| 1619 | def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1620 | "rol{l} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1621 | [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1622 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1623 | def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1624 | "rol{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1625 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
| 1626 | def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1627 | "rol{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1628 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1629 | def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1630 | "rol{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1631 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1632 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1633 | // Rotate by 1 |
| 1634 | def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1), |
| 1635 | "rol{b} $dst", |
| 1636 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
| 1637 | def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1), |
| 1638 | "rol{w} $dst", |
| 1639 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
| 1640 | def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1), |
| 1641 | "rol{l} $dst", |
| 1642 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
| 1643 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1644 | let isTwoAddress = 0 in { |
| 1645 | def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1646 | "rol{b} {%cl, $dst|$dst, %CL}", |
| 1647 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1648 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1649 | def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1650 | "rol{w} {%cl, $dst|$dst, %CL}", |
| 1651 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1652 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1653 | def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1654 | "rol{l} {%cl, $dst|$dst, %CL}", |
| 1655 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1656 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1657 | def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1658 | "rol{b} {$src, $dst|$dst, $src}", |
| 1659 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1660 | def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1661 | "rol{w} {$src, $dst|$dst, $src}", |
| 1662 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1663 | OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1664 | def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1665 | "rol{l} {$src, $dst|$dst, $src}", |
| 1666 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1667 | |
| 1668 | // Rotate by 1 |
| 1669 | def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst), |
| 1670 | "rol{b} $dst", |
| 1671 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 1672 | def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst), |
| 1673 | "rol{w} $dst", |
| 1674 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1675 | OpSize; |
| 1676 | def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst), |
| 1677 | "rol{l} $dst", |
| 1678 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1679 | } |
| 1680 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1681 | def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1682 | "ror{b} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1683 | [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>; |
| 1684 | def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1685 | "ror{w} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1686 | [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
| 1687 | def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1688 | "ror{l} {%cl, $dst|$dst, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1689 | [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1690 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1691 | def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1692 | "ror{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1693 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
| 1694 | def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1695 | "ror{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1696 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1697 | def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1698 | "ror{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1699 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1700 | |
| 1701 | // Rotate by 1 |
| 1702 | def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1), |
| 1703 | "ror{b} $dst", |
| 1704 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
| 1705 | def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1), |
| 1706 | "ror{w} $dst", |
| 1707 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
| 1708 | def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1), |
| 1709 | "ror{l} $dst", |
| 1710 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
| 1711 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1712 | let isTwoAddress = 0 in { |
| 1713 | def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1714 | "ror{b} {%cl, $dst|$dst, %CL}", |
| 1715 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1716 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1717 | def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1718 | "ror{w} {%cl, $dst|$dst, %CL}", |
| 1719 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1720 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1721 | def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1722 | "ror{l} {%cl, $dst|$dst, %CL}", |
| 1723 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1724 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1725 | def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1726 | "ror{b} {$src, $dst|$dst, $src}", |
| 1727 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1728 | def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1729 | "ror{w} {$src, $dst|$dst, $src}", |
| 1730 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1731 | OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1732 | def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1733 | "ror{l} {$src, $dst|$dst, $src}", |
| 1734 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1735 | |
| 1736 | // Rotate by 1 |
| 1737 | def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst), |
| 1738 | "ror{b} $dst", |
| 1739 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 1740 | def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst), |
| 1741 | "ror{w} $dst", |
| 1742 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1743 | OpSize; |
| 1744 | def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst), |
| 1745 | "ror{l} $dst", |
| 1746 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1747 | } |
| 1748 | |
| 1749 | |
| 1750 | |
| 1751 | // Double shift instructions (generalizations of rotate) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1752 | def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1753 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1754 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1755 | Imp<[CL],[]>, TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1756 | def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1757 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1758 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1759 | Imp<[CL],[]>, TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1760 | def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1761 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1762 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1763 | Imp<[CL],[]>, TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1764 | def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1765 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1766 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1767 | Imp<[CL],[]>, TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1768 | |
| 1769 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1770 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1771 | (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1772 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1773 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1774 | (i8 imm:$src3)))]>, |
| 1775 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1776 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1777 | (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1778 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1779 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1780 | (i8 imm:$src3)))]>, |
| 1781 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1782 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1783 | (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1784 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1785 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1786 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1787 | TB, OpSize; |
| 1788 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1789 | (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1790 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1791 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1792 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1793 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1794 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1795 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1796 | let isTwoAddress = 0 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1797 | def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1798 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1799 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1800 | addr:$dst)]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1801 | Imp<[CL],[]>, TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1802 | def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1803 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1804 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1805 | addr:$dst)]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1806 | Imp<[CL],[]>, TB; |
| 1807 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1808 | (ops i32mem:$dst, GR32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1809 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1810 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1811 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1812 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1813 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1814 | (ops i32mem:$dst, GR32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1815 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1816 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1817 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1818 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1819 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1820 | def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1821 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1822 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1823 | addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1824 | Imp<[CL],[]>, TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1825 | def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1826 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1827 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1828 | addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1829 | Imp<[CL],[]>, TB, OpSize; |
| 1830 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1831 | (ops i16mem:$dst, GR16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1832 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1833 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1834 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1835 | TB, OpSize; |
| 1836 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1837 | (ops i16mem:$dst, GR16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1838 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1839 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1840 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1841 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1842 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1843 | |
| 1844 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1845 | // Arithmetic. |
| 1846 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1847 | def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1848 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1849 | [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1850 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1851 | def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1852 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1853 | [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize; |
| 1854 | def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1855 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1856 | [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1857 | } // end isConvertibleToThreeAddress |
| 1858 | } // end isCommutable |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1859 | def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1860 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1861 | [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>; |
| 1862 | def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1863 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1864 | [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize; |
| 1865 | def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1866 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1867 | [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1868 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1869 | def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1870 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1871 | [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1872 | |
| 1873 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1874 | def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1875 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1876 | [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize; |
| 1877 | def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1878 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1879 | [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1880 | def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1881 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1882 | [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1883 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1884 | def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1885 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1886 | [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 1887 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1888 | |
| 1889 | let isTwoAddress = 0 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1890 | def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1891 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1892 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>; |
| 1893 | def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1894 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1895 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1896 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1897 | def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1898 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1899 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1900 | def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1901 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1902 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1903 | def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1904 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1905 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1906 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1907 | def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1908 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1909 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1910 | def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1911 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1912 | [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1913 | OpSize; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1914 | def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1915 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1916 | [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1917 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1918 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1919 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1920 | def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1921 | "adc{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1922 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1923 | } |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1924 | def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1925 | "adc{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1926 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
| 1927 | def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1928 | "adc{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1929 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
| 1930 | def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1931 | "adc{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1932 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1933 | |
| 1934 | let isTwoAddress = 0 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1935 | def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1936 | "adc{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1937 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1938 | def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1939 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1940 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1941 | def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1942 | "adc{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 1943 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1944 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1945 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1946 | def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1947 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1948 | [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>; |
| 1949 | def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1950 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1951 | [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize; |
| 1952 | def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1953 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1954 | [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; |
| 1955 | def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1956 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1957 | [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>; |
| 1958 | def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1959 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1960 | [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize; |
| 1961 | def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1962 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1963 | [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1964 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1965 | def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1966 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1967 | [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>; |
| 1968 | def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1969 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1970 | [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize; |
| 1971 | def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1972 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1973 | [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>; |
| 1974 | def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1975 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1976 | [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1977 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1978 | def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1979 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1980 | [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1981 | let isTwoAddress = 0 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1982 | def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1983 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1984 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>; |
| 1985 | def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1986 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1987 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1988 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1989 | def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1990 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1991 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1992 | def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1993 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1994 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1995 | def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1996 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1997 | [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1998 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1999 | def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 2000 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 2001 | [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 2002 | def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), |
| 2003 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2004 | [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 2005 | OpSize; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 2006 | def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), |
| 2007 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2008 | [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2009 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2010 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2011 | def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2012 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2013 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2014 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2015 | let isTwoAddress = 0 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2016 | def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2017 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2018 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2019 | def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2020 | "sbb{b} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2021 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2022 | def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2023 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2024 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2025 | def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2), |
| 2026 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2027 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2028 | } |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2029 | def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2030 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2031 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
| 2032 | def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2033 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2034 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
| 2035 | def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2036 | "sbb{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2037 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2038 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2039 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2040 | def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2041 | "imul{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2042 | [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize; |
| 2043 | def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2044 | "imul{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2045 | [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2046 | } |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2047 | def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2048 | "imul{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2049 | [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2050 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2051 | def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2052 | "imul{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2053 | [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2054 | |
| 2055 | } // end Two Address instructions |
| 2056 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2057 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2058 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
| 2059 | (ops GR16:$dst, GR16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 2060 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2061 | [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize; |
| 2062 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
| 2063 | (ops GR32:$dst, GR32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 2064 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2065 | [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>; |
| 2066 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
| 2067 | (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2068 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2069 | [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2070 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2071 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
| 2072 | (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2073 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2074 | [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2075 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2076 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
| 2077 | (ops GR16:$dst, i16mem:$src1, i16imm:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2078 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2079 | [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>, |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2080 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2081 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
| 2082 | (ops GR32:$dst, i32mem:$src1, i32imm:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2083 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2084 | [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>; |
| 2085 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
| 2086 | (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2087 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2088 | [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2089 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2090 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
| 2091 | (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2092 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2093 | [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2094 | |
| 2095 | //===----------------------------------------------------------------------===// |
| 2096 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2097 | // |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2098 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2099 | def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2100 | "test{b} {$src2, $src1|$src1, $src2}", |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2101 | [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2102 | def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2103 | "test{w} {$src2, $src1|$src1, $src2}", |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2104 | [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2105 | def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2106 | "test{l} {$src2, $src1|$src1, $src2}", |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2107 | [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2108 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2109 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2110 | def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2111 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2112 | [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2113 | def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2114 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2115 | [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2116 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2117 | def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2118 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2119 | [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2120 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2121 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
| 2122 | (ops GR8:$src1, i8imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2123 | "test{b} {$src2, $src1|$src1, $src2}", |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2124 | [(X86cmp (and GR8:$src1, imm:$src2), 0)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2125 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
| 2126 | (ops GR16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2127 | "test{w} {$src2, $src1|$src1, $src2}", |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2128 | [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2129 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
| 2130 | (ops GR32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2131 | "test{l} {$src2, $src1|$src1, $src2}", |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2132 | [(X86cmp (and GR32:$src1, imm:$src2), 0)]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2133 | |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2134 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2135 | (ops i8mem:$src1, i8imm:$src2), |
| 2136 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2137 | [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2138 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
| 2139 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2140 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2141 | [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2142 | OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2143 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
| 2144 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2145 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2146 | [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2147 | |
| 2148 | |
| 2149 | // Condition code ops, incl. set if equal/not equal/... |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2150 | def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH |
| 2151 | def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2152 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2153 | def SETEr : I<0x94, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2154 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2155 | "sete $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2156 | [(set GR8:$dst, (X86setcc X86_COND_E))]>, |
| 2157 | TB; // GR8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2158 | def SETEm : I<0x94, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2159 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2160 | "sete $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2161 | [(store (X86setcc X86_COND_E), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2162 | TB; // [mem8] = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2163 | def SETNEr : I<0x95, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2164 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2165 | "setne $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2166 | [(set GR8:$dst, (X86setcc X86_COND_NE))]>, |
| 2167 | TB; // GR8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2168 | def SETNEm : I<0x95, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2169 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2170 | "setne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2171 | [(store (X86setcc X86_COND_NE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2172 | TB; // [mem8] = != |
| 2173 | def SETLr : I<0x9C, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2174 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2175 | "setl $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2176 | [(set GR8:$dst, (X86setcc X86_COND_L))]>, |
| 2177 | TB; // GR8 = < signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2178 | def SETLm : I<0x9C, MRM0m, |
| 2179 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2180 | "setl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2181 | [(store (X86setcc X86_COND_L), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2182 | TB; // [mem8] = < signed |
| 2183 | def SETGEr : I<0x9D, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2184 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2185 | "setge $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2186 | [(set GR8:$dst, (X86setcc X86_COND_GE))]>, |
| 2187 | TB; // GR8 = >= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2188 | def SETGEm : I<0x9D, MRM0m, |
| 2189 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2190 | "setge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2191 | [(store (X86setcc X86_COND_GE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2192 | TB; // [mem8] = >= signed |
| 2193 | def SETLEr : I<0x9E, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2194 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2195 | "setle $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2196 | [(set GR8:$dst, (X86setcc X86_COND_LE))]>, |
| 2197 | TB; // GR8 = <= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2198 | def SETLEm : I<0x9E, MRM0m, |
| 2199 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2200 | "setle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2201 | [(store (X86setcc X86_COND_LE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2202 | TB; // [mem8] = <= signed |
| 2203 | def SETGr : I<0x9F, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2204 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2205 | "setg $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2206 | [(set GR8:$dst, (X86setcc X86_COND_G))]>, |
| 2207 | TB; // GR8 = > signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2208 | def SETGm : I<0x9F, MRM0m, |
| 2209 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2210 | "setg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2211 | [(store (X86setcc X86_COND_G), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2212 | TB; // [mem8] = > signed |
| 2213 | |
| 2214 | def SETBr : I<0x92, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2215 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2216 | "setb $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2217 | [(set GR8:$dst, (X86setcc X86_COND_B))]>, |
| 2218 | TB; // GR8 = < unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2219 | def SETBm : I<0x92, MRM0m, |
| 2220 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2221 | "setb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2222 | [(store (X86setcc X86_COND_B), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2223 | TB; // [mem8] = < unsign |
| 2224 | def SETAEr : I<0x93, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2225 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2226 | "setae $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2227 | [(set GR8:$dst, (X86setcc X86_COND_AE))]>, |
| 2228 | TB; // GR8 = >= unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2229 | def SETAEm : I<0x93, MRM0m, |
| 2230 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2231 | "setae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2232 | [(store (X86setcc X86_COND_AE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2233 | TB; // [mem8] = >= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2234 | def SETBEr : I<0x96, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2235 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2236 | "setbe $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2237 | [(set GR8:$dst, (X86setcc X86_COND_BE))]>, |
| 2238 | TB; // GR8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2239 | def SETBEm : I<0x96, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2240 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2241 | "setbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2242 | [(store (X86setcc X86_COND_BE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2243 | TB; // [mem8] = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2244 | def SETAr : I<0x97, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2245 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2246 | "seta $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2247 | [(set GR8:$dst, (X86setcc X86_COND_A))]>, |
| 2248 | TB; // GR8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2249 | def SETAm : I<0x97, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2250 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2251 | "seta $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2252 | [(store (X86setcc X86_COND_A), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2253 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2254 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2255 | def SETSr : I<0x98, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2256 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2257 | "sets $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2258 | [(set GR8:$dst, (X86setcc X86_COND_S))]>, |
| 2259 | TB; // GR8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2260 | def SETSm : I<0x98, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2261 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2262 | "sets $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2263 | [(store (X86setcc X86_COND_S), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2264 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2265 | def SETNSr : I<0x99, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2266 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2267 | "setns $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2268 | [(set GR8:$dst, (X86setcc X86_COND_NS))]>, |
| 2269 | TB; // GR8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2270 | def SETNSm : I<0x99, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2271 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2272 | "setns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2273 | [(store (X86setcc X86_COND_NS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2274 | TB; // [mem8] = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2275 | def SETPr : I<0x9A, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2276 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2277 | "setp $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2278 | [(set GR8:$dst, (X86setcc X86_COND_P))]>, |
| 2279 | TB; // GR8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2280 | def SETPm : I<0x9A, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2281 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2282 | "setp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2283 | [(store (X86setcc X86_COND_P), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2284 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2285 | def SETNPr : I<0x9B, MRM0r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2286 | (ops GR8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2287 | "setnp $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2288 | [(set GR8:$dst, (X86setcc X86_COND_NP))]>, |
| 2289 | TB; // GR8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2290 | def SETNPm : I<0x9B, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2291 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2292 | "setnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2293 | [(store (X86setcc X86_COND_NP), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2294 | TB; // [mem8] = not parity |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2295 | |
| 2296 | // Integer comparisons |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2297 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2298 | (ops GR8 :$src1, GR8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2299 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2300 | [(X86cmp GR8:$src1, GR8:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2301 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2302 | (ops GR16:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2303 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2304 | [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2305 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2306 | (ops GR32:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2307 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2308 | [(X86cmp GR32:$src1, GR32:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2309 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2310 | (ops i8mem :$src1, GR8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2311 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2312 | [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2313 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2314 | (ops i16mem:$src1, GR16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2315 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2316 | [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2317 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2318 | (ops i32mem:$src1, GR32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2319 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2320 | [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2321 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2322 | (ops GR8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2323 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2324 | [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2325 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2326 | (ops GR16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2327 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2328 | [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2329 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2330 | (ops GR32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2331 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2332 | [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2333 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2334 | (ops GR8:$src1, i8imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2335 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2336 | [(X86cmp GR8:$src1, imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2337 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2338 | (ops GR16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2339 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2340 | [(X86cmp GR16:$src1, imm:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2341 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2342 | (ops GR32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2343 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2344 | [(X86cmp GR32:$src1, imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2345 | def CMP8mi : Ii8 <0x80, MRM7m, |
| 2346 | (ops i8mem :$src1, i8imm :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2347 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2348 | [(X86cmp (loadi8 addr:$src1), imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2349 | def CMP16mi : Ii16<0x81, MRM7m, |
| 2350 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2351 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2352 | [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2353 | def CMP32mi : Ii32<0x81, MRM7m, |
| 2354 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2355 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2356 | [(X86cmp (loadi32 addr:$src1), imm:$src2)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2357 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2358 | (ops GR16:$src1, i16i8imm:$src2), |
Nate Begeman | ce94482 | 2006-03-23 01:29:48 +0000 | [diff] [blame] | 2359 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2360 | [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2361 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Nate Begeman | ce94482 | 2006-03-23 01:29:48 +0000 | [diff] [blame] | 2362 | (ops i16mem:$src1, i16i8imm:$src2), |
| 2363 | "cmp{w} {$src2, $src1|$src1, $src2}", |
| 2364 | [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2365 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Nate Begeman | ce94482 | 2006-03-23 01:29:48 +0000 | [diff] [blame] | 2366 | (ops i32mem:$src1, i32i8imm:$src2), |
| 2367 | "cmp{l} {$src2, $src1|$src1, $src2}", |
| 2368 | [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2369 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2370 | (ops GR32:$src1, i32i8imm:$src2), |
Nate Begeman | ce94482 | 2006-03-23 01:29:48 +0000 | [diff] [blame] | 2371 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2372 | [(X86cmp GR32:$src1, i32immSExt8:$src2)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2373 | |
| 2374 | // Sign/Zero extenders |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2375 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2376 | "movs{bw|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2377 | [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize; |
| 2378 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2379 | "movs{bw|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2380 | [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; |
| 2381 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2382 | "movs{bl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2383 | [(set GR32:$dst, (sext GR8:$src))]>, TB; |
| 2384 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2385 | "movs{bl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2386 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
| 2387 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2388 | "movs{wl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2389 | [(set GR32:$dst, (sext GR16:$src))]>, TB; |
| 2390 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2391 | "movs{wl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2392 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2393 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2394 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2395 | "movz{bw|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2396 | [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize; |
| 2397 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2398 | "movz{bw|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2399 | [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; |
| 2400 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2401 | "movz{bl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2402 | [(set GR32:$dst, (zext GR8:$src))]>, TB; |
| 2403 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2404 | "movz{bl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2405 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
| 2406 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2407 | "movz{wl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2408 | [(set GR32:$dst, (zext GR16:$src))]>, TB; |
| 2409 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2410 | "movz{wl|x} {$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2411 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2412 | |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 2413 | def CBW : I<0x98, RawFrm, (ops), |
Chris Lattner | d06b2ab | 2007-01-24 18:31:00 +0000 | [diff] [blame] | 2414 | "{cbtw|cbw}", []>, Imp<[AL],[AX]>, OpSize; // AX = signext(AL) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 2415 | def CWDE : I<0x98, RawFrm, (ops), |
| 2416 | "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX) |
| 2417 | |
| 2418 | def CWD : I<0x99, RawFrm, (ops), |
Chris Lattner | d06b2ab | 2007-01-24 18:31:00 +0000 | [diff] [blame] | 2419 | "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>, OpSize; // DX:AX = signext(AX) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 2420 | def CDQ : I<0x99, RawFrm, (ops), |
| 2421 | "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX) |
| 2422 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2423 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2424 | //===----------------------------------------------------------------------===// |
| 2425 | // Alias Instructions |
| 2426 | //===----------------------------------------------------------------------===// |
| 2427 | |
| 2428 | // Alias instructions that map movr0 to xor. |
| 2429 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2430 | def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst), |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2431 | "xor{b} $dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2432 | [(set GR8:$dst, 0)]>; |
| 2433 | def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst), |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2434 | "xor{w} $dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2435 | [(set GR16:$dst, 0)]>, OpSize; |
| 2436 | def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst), |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2437 | "xor{l} $dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2438 | [(set GR32:$dst, 0)]>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2439 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2440 | // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only |
| 2441 | // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX). |
| 2442 | def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2443 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2444 | def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2445 | "mov{l} {$src, $dst|$dst, $src}", []>; |
| 2446 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2447 | def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2448 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2449 | def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2450 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2451 | def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2452 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2453 | def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2454 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2455 | def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2456 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2457 | def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src), |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2458 | "mov{l} {$src, $dst|$dst, $src}", []>; |
| 2459 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2460 | //===----------------------------------------------------------------------===// |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame^] | 2461 | // Thread Local Storage Instructions |
| 2462 | // |
| 2463 | |
| 2464 | def TLS_addr : I<0, Pseudo, (ops GR32:$dst, i32imm:$sym), |
| 2465 | "leal $sym(,%ebx,1), $dst", |
| 2466 | [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>, |
| 2467 | Imp<[EBX],[]>; |
| 2468 | |
| 2469 | def TLS_tp : I<0, Pseudo, (ops GR32:$dst), |
| 2470 | "movl %gs:0, $dst", |
| 2471 | [(set GR32:$dst, X86TLStp)]>; |
| 2472 | |
| 2473 | //===----------------------------------------------------------------------===// |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2474 | // DWARF Pseudo Instructions |
| 2475 | // |
| 2476 | |
| 2477 | def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file), |
| 2478 | "; .loc $file, $line, $col", |
| 2479 | [(dwarf_loc (i32 imm:$line), (i32 imm:$col), |
| 2480 | (i32 imm:$file))]>; |
| 2481 | |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2482 | //===----------------------------------------------------------------------===// |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2483 | // Non-Instruction Patterns |
| 2484 | //===----------------------------------------------------------------------===// |
| 2485 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2486 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2487 | def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 2488 | def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2489 | def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; |
| 2490 | def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; |
| 2491 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2492 | def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), |
| 2493 | (ADD32ri GR32:$src1, tconstpool:$src2)>; |
| 2494 | def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), |
| 2495 | (ADD32ri GR32:$src1, tjumptable:$src2)>; |
| 2496 | def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), |
| 2497 | (ADD32ri GR32:$src1, tglobaladdr:$src2)>; |
| 2498 | def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), |
| 2499 | (ADD32ri GR32:$src1, texternalsym:$src2)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2500 | |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 2501 | def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2502 | (MOV32mi addr:$dst, tglobaladdr:$src)>; |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 2503 | def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2504 | (MOV32mi addr:$dst, texternalsym:$src)>; |
| 2505 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2506 | // Calls |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2507 | def : Pat<(X86tailcall GR32:$dst), |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2508 | (CALL32r GR32:$dst)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 2509 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2510 | def : Pat<(X86tailcall (i32 tglobaladdr:$dst)), |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 2511 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2512 | def : Pat<(X86tailcall (i32 texternalsym:$dst)), |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 2513 | (CALLpcrel32 texternalsym:$dst)>; |
| 2514 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2515 | def : Pat<(X86call (i32 tglobaladdr:$dst)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2516 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2517 | def : Pat<(X86call (i32 texternalsym:$dst)), |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 2518 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2519 | |
| 2520 | // X86 specific add which produces a flag. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2521 | def : Pat<(addc GR32:$src1, GR32:$src2), |
| 2522 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 2523 | def : Pat<(addc GR32:$src1, (load addr:$src2)), |
| 2524 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 2525 | def : Pat<(addc GR32:$src1, imm:$src2), |
| 2526 | (ADD32ri GR32:$src1, imm:$src2)>; |
| 2527 | def : Pat<(addc GR32:$src1, i32immSExt8:$src2), |
| 2528 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2529 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2530 | def : Pat<(subc GR32:$src1, GR32:$src2), |
| 2531 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 2532 | def : Pat<(subc GR32:$src1, (load addr:$src2)), |
| 2533 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 2534 | def : Pat<(subc GR32:$src1, imm:$src2), |
| 2535 | (SUB32ri GR32:$src1, imm:$src2)>; |
| 2536 | def : Pat<(subc GR32:$src1, i32immSExt8:$src2), |
| 2537 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2538 | |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 2539 | def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst), |
Evan Cheng | b841433 | 2006-01-13 21:45:19 +0000 | [diff] [blame] | 2540 | (MOV8mi addr:$dst, imm:$src)>; |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 2541 | def : Pat<(truncstorei1 GR8:$src, addr:$dst), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2542 | (MOV8mr addr:$dst, GR8:$src)>; |
Evan Cheng | b841433 | 2006-01-13 21:45:19 +0000 | [diff] [blame] | 2543 | |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2544 | // Comparisons. |
| 2545 | |
| 2546 | // TEST R,R is smaller than CMP R,0 |
| 2547 | def : Pat<(X86cmp GR8:$src1, 0), |
| 2548 | (TEST8rr GR8:$src1, GR8:$src1)>; |
| 2549 | def : Pat<(X86cmp GR16:$src1, 0), |
| 2550 | (TEST16rr GR16:$src1, GR16:$src1)>; |
| 2551 | def : Pat<(X86cmp GR32:$src1, 0), |
| 2552 | (TEST32rr GR32:$src1, GR32:$src1)>; |
| 2553 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2554 | // {s|z}extload bool -> {s|z}extload byte |
| 2555 | def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; |
| 2556 | def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 2557 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2558 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 2559 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 2560 | |
| 2561 | // extload bool -> extload byte |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 2562 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
| 2563 | def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 2564 | def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 2565 | def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 2566 | def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 2567 | def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2568 | |
| 2569 | // anyext -> zext |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2570 | def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; |
| 2571 | def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; |
| 2572 | def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>; |
Evan Cheng | 6e16ee5 | 2006-03-25 09:45:48 +0000 | [diff] [blame] | 2573 | def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>; |
| 2574 | def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>; |
| 2575 | def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2576 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 2577 | //===----------------------------------------------------------------------===// |
| 2578 | // Some peepholes |
| 2579 | //===----------------------------------------------------------------------===// |
| 2580 | |
| 2581 | // (shl x, 1) ==> (add x, x) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2582 | def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; |
| 2583 | def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; |
| 2584 | def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 2585 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2586 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2587 | def : Pat<(or (srl GR32:$src1, CL:$amt), |
| 2588 | (shl GR32:$src2, (sub 32, CL:$amt))), |
| 2589 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 2590 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2591 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2592 | (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 2593 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2594 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2595 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2596 | def : Pat<(or (shl GR32:$src1, CL:$amt), |
| 2597 | (srl GR32:$src2, (sub 32, CL:$amt))), |
| 2598 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2599 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2600 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2601 | (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 2602 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2603 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2604 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2605 | def : Pat<(or (srl GR16:$src1, CL:$amt), |
| 2606 | (shl GR16:$src2, (sub 16, CL:$amt))), |
| 2607 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2608 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2609 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2610 | (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 2611 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2612 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 2613 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2614 | def : Pat<(or (shl GR16:$src1, CL:$amt), |
| 2615 | (srl GR16:$src2, (sub 16, CL:$amt))), |
| 2616 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 2617 | |
| 2618 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2619 | (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 2620 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2621 | |
| 2622 | |
| 2623 | //===----------------------------------------------------------------------===// |
| 2624 | // Floating Point Stack Support |
| 2625 | //===----------------------------------------------------------------------===// |
| 2626 | |
| 2627 | include "X86InstrFPStack.td" |
| 2628 | |
| 2629 | //===----------------------------------------------------------------------===// |
| 2630 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) |
| 2631 | //===----------------------------------------------------------------------===// |
| 2632 | |
| 2633 | include "X86InstrMMX.td" |
| 2634 | |
| 2635 | //===----------------------------------------------------------------------===// |
| 2636 | // XMM Floating point support (requires SSE / SSE2) |
| 2637 | //===----------------------------------------------------------------------===// |
| 2638 | |
| 2639 | include "X86InstrSSE.td" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2640 | |
| 2641 | //===----------------------------------------------------------------------===// |
| 2642 | // X86-64 Support |
| 2643 | //===----------------------------------------------------------------------===// |
| 2644 | |
| 2645 | include "X86InstrX86-64.td" |