Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 9 | * the Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
Marek Olšák | 330b6c8 | 2012-03-05 15:17:00 +0100 | [diff] [blame] | 23 | #include "r600_formats.h" |
Marek Olšák | 555c8d5 | 2012-10-12 18:30:51 +0200 | [diff] [blame] | 24 | #include "r600_shader.h" |
Marek Olšák | 330b6c8 | 2012-03-05 15:17:00 +0100 | [diff] [blame] | 25 | #include "r600d.h" |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 26 | |
Marek Olšák | 330b6c8 | 2012-03-05 15:17:00 +0100 | [diff] [blame] | 27 | #include "pipe/p_shader_tokens.h" |
Kai Wasserbäch | 8fb7f1a | 2011-08-27 17:51:51 +0200 | [diff] [blame] | 28 | #include "util/u_pack_color.h" |
| 29 | #include "util/u_memory.h" |
Kai Wasserbäch | 8fb7f1a | 2011-08-27 17:51:51 +0200 | [diff] [blame] | 30 | #include "util/u_framebuffer.h" |
Dave Airlie | d1cc87c | 2012-03-24 13:37:16 +0000 | [diff] [blame] | 31 | #include "util/u_dual_blend.h" |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 32 | |
| 33 | static uint32_t r600_translate_blend_function(int blend_func) |
| 34 | { |
| 35 | switch (blend_func) { |
| 36 | case PIPE_BLEND_ADD: |
| 37 | return V_028804_COMB_DST_PLUS_SRC; |
| 38 | case PIPE_BLEND_SUBTRACT: |
| 39 | return V_028804_COMB_SRC_MINUS_DST; |
| 40 | case PIPE_BLEND_REVERSE_SUBTRACT: |
| 41 | return V_028804_COMB_DST_MINUS_SRC; |
| 42 | case PIPE_BLEND_MIN: |
| 43 | return V_028804_COMB_MIN_DST_SRC; |
| 44 | case PIPE_BLEND_MAX: |
| 45 | return V_028804_COMB_MAX_DST_SRC; |
| 46 | default: |
| 47 | R600_ERR("Unknown blend function %d\n", blend_func); |
| 48 | assert(0); |
| 49 | break; |
| 50 | } |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | static uint32_t r600_translate_blend_factor(int blend_fact) |
| 55 | { |
| 56 | switch (blend_fact) { |
| 57 | case PIPE_BLENDFACTOR_ONE: |
| 58 | return V_028804_BLEND_ONE; |
| 59 | case PIPE_BLENDFACTOR_SRC_COLOR: |
| 60 | return V_028804_BLEND_SRC_COLOR; |
| 61 | case PIPE_BLENDFACTOR_SRC_ALPHA: |
| 62 | return V_028804_BLEND_SRC_ALPHA; |
| 63 | case PIPE_BLENDFACTOR_DST_ALPHA: |
| 64 | return V_028804_BLEND_DST_ALPHA; |
| 65 | case PIPE_BLENDFACTOR_DST_COLOR: |
| 66 | return V_028804_BLEND_DST_COLOR; |
| 67 | case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: |
| 68 | return V_028804_BLEND_SRC_ALPHA_SATURATE; |
| 69 | case PIPE_BLENDFACTOR_CONST_COLOR: |
| 70 | return V_028804_BLEND_CONST_COLOR; |
| 71 | case PIPE_BLENDFACTOR_CONST_ALPHA: |
| 72 | return V_028804_BLEND_CONST_ALPHA; |
| 73 | case PIPE_BLENDFACTOR_ZERO: |
| 74 | return V_028804_BLEND_ZERO; |
| 75 | case PIPE_BLENDFACTOR_INV_SRC_COLOR: |
| 76 | return V_028804_BLEND_ONE_MINUS_SRC_COLOR; |
| 77 | case PIPE_BLENDFACTOR_INV_SRC_ALPHA: |
| 78 | return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; |
| 79 | case PIPE_BLENDFACTOR_INV_DST_ALPHA: |
| 80 | return V_028804_BLEND_ONE_MINUS_DST_ALPHA; |
| 81 | case PIPE_BLENDFACTOR_INV_DST_COLOR: |
| 82 | return V_028804_BLEND_ONE_MINUS_DST_COLOR; |
| 83 | case PIPE_BLENDFACTOR_INV_CONST_COLOR: |
| 84 | return V_028804_BLEND_ONE_MINUS_CONST_COLOR; |
| 85 | case PIPE_BLENDFACTOR_INV_CONST_ALPHA: |
| 86 | return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; |
| 87 | case PIPE_BLENDFACTOR_SRC1_COLOR: |
| 88 | return V_028804_BLEND_SRC1_COLOR; |
| 89 | case PIPE_BLENDFACTOR_SRC1_ALPHA: |
| 90 | return V_028804_BLEND_SRC1_ALPHA; |
| 91 | case PIPE_BLENDFACTOR_INV_SRC1_COLOR: |
| 92 | return V_028804_BLEND_INV_SRC1_COLOR; |
| 93 | case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: |
| 94 | return V_028804_BLEND_INV_SRC1_ALPHA; |
| 95 | default: |
| 96 | R600_ERR("Bad blend factor %d not supported!\n", blend_fact); |
| 97 | assert(0); |
| 98 | break; |
| 99 | } |
| 100 | return 0; |
| 101 | } |
| 102 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 103 | static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples) |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 104 | { |
| 105 | switch (dim) { |
| 106 | default: |
| 107 | case PIPE_TEXTURE_1D: |
| 108 | return V_038000_SQ_TEX_DIM_1D; |
| 109 | case PIPE_TEXTURE_1D_ARRAY: |
| 110 | return V_038000_SQ_TEX_DIM_1D_ARRAY; |
| 111 | case PIPE_TEXTURE_2D: |
| 112 | case PIPE_TEXTURE_RECT: |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 113 | return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA : |
| 114 | V_038000_SQ_TEX_DIM_2D; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 115 | case PIPE_TEXTURE_2D_ARRAY: |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 116 | return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA : |
| 117 | V_038000_SQ_TEX_DIM_2D_ARRAY; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 118 | case PIPE_TEXTURE_3D: |
| 119 | return V_038000_SQ_TEX_DIM_3D; |
| 120 | case PIPE_TEXTURE_CUBE: |
Dave Airlie | eb44c36d | 2012-11-03 20:53:33 +1000 | [diff] [blame] | 121 | case PIPE_TEXTURE_CUBE_ARRAY: |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 122 | return V_038000_SQ_TEX_DIM_CUBEMAP; |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | static uint32_t r600_translate_dbformat(enum pipe_format format) |
| 127 | { |
| 128 | switch (format) { |
| 129 | case PIPE_FORMAT_Z16_UNORM: |
| 130 | return V_028010_DEPTH_16; |
| 131 | case PIPE_FORMAT_Z24X8_UNORM: |
| 132 | return V_028010_DEPTH_X8_24; |
Dave Airlie | 866f9b1 | 2011-09-11 09:45:10 +0100 | [diff] [blame] | 133 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 134 | return V_028010_DEPTH_8_24; |
Marek Olšák | 8995472 | 2011-06-20 19:40:41 +0200 | [diff] [blame] | 135 | case PIPE_FORMAT_Z32_FLOAT: |
| 136 | return V_028010_DEPTH_32_FLOAT; |
Dave Airlie | 866f9b1 | 2011-09-11 09:45:10 +0100 | [diff] [blame] | 137 | case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: |
Marek Olšák | 8995472 | 2011-06-20 19:40:41 +0200 | [diff] [blame] | 138 | return V_028010_DEPTH_X24_8_32_FLOAT; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 139 | default: |
| 140 | return ~0U; |
| 141 | } |
| 142 | } |
| 143 | |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 144 | static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) |
| 145 | { |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 146 | return r600_translate_texformat(screen, format, NULL, NULL, NULL, |
| 147 | FALSE) != ~0U; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 148 | } |
| 149 | |
Marek Olšák | ac35ded | 2014-02-23 18:46:43 +0100 | [diff] [blame] | 150 | static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format) |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 151 | { |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 152 | return r600_translate_colorformat(chip, format, FALSE) != ~0U && |
| 153 | r600_translate_colorswap(format, FALSE) != ~0U; |
Henri Verbeet | 3fccc14 | 2011-07-05 01:58:47 +0200 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static bool r600_is_zs_format_supported(enum pipe_format format) |
| 157 | { |
| 158 | return r600_translate_dbformat(format) != ~0U; |
| 159 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 160 | |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 161 | boolean r600_is_format_supported(struct pipe_screen *screen, |
| 162 | enum pipe_format format, |
| 163 | enum pipe_texture_target target, |
| 164 | unsigned sample_count, |
| 165 | unsigned usage) |
| 166 | { |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 167 | struct r600_screen *rscreen = (struct r600_screen*)screen; |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 168 | unsigned retval = 0; |
| 169 | |
| 170 | if (target >= PIPE_MAX_TEXTURE_TYPES) { |
| 171 | R600_ERR("r600: unsupported texture type %d\n", target); |
| 172 | return FALSE; |
| 173 | } |
| 174 | |
| 175 | if (!util_format_is_supported(format, usage)) |
| 176 | return FALSE; |
| 177 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 178 | if (sample_count > 1) { |
Marek Olšák | 96ed6c9 | 2012-10-12 18:46:32 +0200 | [diff] [blame] | 179 | if (!rscreen->has_msaa) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 180 | return FALSE; |
Marek Olšák | c2e9dd0 | 2012-08-26 23:03:51 +0200 | [diff] [blame] | 181 | |
| 182 | /* R11G11B10 is broken on R6xx. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 183 | if (rscreen->b.chip_class == R600 && |
Marek Olšák | c2e9dd0 | 2012-08-26 23:03:51 +0200 | [diff] [blame] | 184 | format == PIPE_FORMAT_R11G11B10_FLOAT) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 185 | return FALSE; |
| 186 | |
Marek Olšák | df5e2c0 | 2012-09-08 15:50:30 +0200 | [diff] [blame] | 187 | /* MSAA integer colorbuffers hang. */ |
Marek Olšák | fc887d6 | 2012-09-13 00:45:05 +0200 | [diff] [blame] | 188 | if (util_format_is_pure_integer(format) && |
| 189 | !util_format_is_depth_or_stencil(format)) |
Marek Olšák | df5e2c0 | 2012-09-08 15:50:30 +0200 | [diff] [blame] | 190 | return FALSE; |
| 191 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 192 | switch (sample_count) { |
| 193 | case 2: |
| 194 | case 4: |
| 195 | case 8: |
| 196 | break; |
| 197 | default: |
| 198 | return FALSE; |
| 199 | } |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 200 | } |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 201 | |
Marek Olšák | 6a25087 | 2013-10-31 15:32:30 +0100 | [diff] [blame] | 202 | if (usage & PIPE_BIND_SAMPLER_VIEW) { |
| 203 | if (target == PIPE_BUFFER) { |
| 204 | if (r600_is_vertex_format_supported(format)) |
| 205 | retval |= PIPE_BIND_SAMPLER_VIEW; |
| 206 | } else { |
| 207 | if (r600_is_sampler_format_supported(screen, format)) |
| 208 | retval |= PIPE_BIND_SAMPLER_VIEW; |
| 209 | } |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | if ((usage & (PIPE_BIND_RENDER_TARGET | |
| 213 | PIPE_BIND_DISPLAY_TARGET | |
| 214 | PIPE_BIND_SCANOUT | |
Marek Olšák | 770719e | 2014-08-23 11:18:43 +0200 | [diff] [blame] | 215 | PIPE_BIND_SHARED | |
| 216 | PIPE_BIND_BLENDABLE)) && |
Marek Olšák | ac35ded | 2014-02-23 18:46:43 +0100 | [diff] [blame] | 217 | r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) { |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 218 | retval |= usage & |
| 219 | (PIPE_BIND_RENDER_TARGET | |
| 220 | PIPE_BIND_DISPLAY_TARGET | |
| 221 | PIPE_BIND_SCANOUT | |
| 222 | PIPE_BIND_SHARED); |
Marek Olšák | 770719e | 2014-08-23 11:18:43 +0200 | [diff] [blame] | 223 | if (!util_format_is_pure_integer(format) && |
| 224 | !util_format_is_depth_or_stencil(format)) |
| 225 | retval |= usage & PIPE_BIND_BLENDABLE; |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | if ((usage & PIPE_BIND_DEPTH_STENCIL) && |
| 229 | r600_is_zs_format_supported(format)) { |
| 230 | retval |= PIPE_BIND_DEPTH_STENCIL; |
| 231 | } |
| 232 | |
| 233 | if ((usage & PIPE_BIND_VERTEX_BUFFER) && |
| 234 | r600_is_vertex_format_supported(format)) { |
| 235 | retval |= PIPE_BIND_VERTEX_BUFFER; |
| 236 | } |
| 237 | |
| 238 | if (usage & PIPE_BIND_TRANSFER_READ) |
| 239 | retval |= PIPE_BIND_TRANSFER_READ; |
| 240 | if (usage & PIPE_BIND_TRANSFER_WRITE) |
| 241 | retval |= PIPE_BIND_TRANSFER_WRITE; |
| 242 | |
Christian König | 1faca43 | 2016-03-30 15:38:29 +0200 | [diff] [blame] | 243 | if ((usage & PIPE_BIND_LINEAR) && |
| 244 | !util_format_is_compressed(format) && |
| 245 | !(usage & PIPE_BIND_DEPTH_STENCIL)) |
| 246 | retval |= PIPE_BIND_LINEAR; |
| 247 | |
Henri Verbeet | 18cdb9c | 2011-07-05 01:58:46 +0200 | [diff] [blame] | 248 | return retval == usage; |
| 249 | } |
| 250 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 251 | static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a) |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 252 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 253 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 254 | struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; |
| 255 | float offset_units = state->offset_units; |
| 256 | float offset_scale = state->offset_scale; |
Axel Davy | 400e8d8 | 2016-06-14 22:22:50 +0200 | [diff] [blame^] | 257 | uint32_t pa_su_poly_offset_db_fmt_cntl = 0; |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 258 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 259 | switch (state->zs_format) { |
| 260 | case PIPE_FORMAT_Z24X8_UNORM: |
| 261 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: |
| 262 | offset_units *= 2.0f; |
Axel Davy | 400e8d8 | 2016-06-14 22:22:50 +0200 | [diff] [blame^] | 263 | pa_su_poly_offset_db_fmt_cntl = |
| 264 | S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24); |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 265 | break; |
| 266 | case PIPE_FORMAT_Z16_UNORM: |
| 267 | offset_units *= 4.0f; |
Axel Davy | 400e8d8 | 2016-06-14 22:22:50 +0200 | [diff] [blame^] | 268 | pa_su_poly_offset_db_fmt_cntl = |
| 269 | S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16); |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 270 | break; |
Axel Davy | 400e8d8 | 2016-06-14 22:22:50 +0200 | [diff] [blame^] | 271 | default: |
| 272 | pa_su_poly_offset_db_fmt_cntl = |
| 273 | S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) | |
| 274 | S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 275 | } |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 276 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 277 | radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 278 | radeon_emit(cs, fui(offset_scale)); |
| 279 | radeon_emit(cs, fui(offset_units)); |
| 280 | radeon_emit(cs, fui(offset_scale)); |
| 281 | radeon_emit(cs, fui(offset_units)); |
Axel Davy | 400e8d8 | 2016-06-14 22:22:50 +0200 | [diff] [blame^] | 282 | |
| 283 | radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, |
| 284 | pa_su_poly_offset_db_fmt_cntl); |
Jerome Glisse | 0b841b0 | 2010-12-03 12:20:40 -0500 | [diff] [blame] | 285 | } |
| 286 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 287 | static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i) |
| 288 | { |
| 289 | int j = state->independent_blend_enable ? i : 0; |
| 290 | |
| 291 | unsigned eqRGB = state->rt[j].rgb_func; |
| 292 | unsigned srcRGB = state->rt[j].rgb_src_factor; |
| 293 | unsigned dstRGB = state->rt[j].rgb_dst_factor; |
| 294 | |
| 295 | unsigned eqA = state->rt[j].alpha_func; |
| 296 | unsigned srcA = state->rt[j].alpha_src_factor; |
| 297 | unsigned dstA = state->rt[j].alpha_dst_factor; |
| 298 | uint32_t bc = 0; |
| 299 | |
| 300 | if (!state->rt[j].blend_enable) |
| 301 | return 0; |
| 302 | |
| 303 | bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); |
| 304 | bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); |
| 305 | bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); |
| 306 | |
| 307 | if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { |
| 308 | bc |= S_028804_SEPARATE_ALPHA_BLEND(1); |
| 309 | bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); |
| 310 | bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); |
| 311 | bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); |
| 312 | } |
| 313 | return bc; |
| 314 | } |
| 315 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 316 | static void *r600_create_blend_state_mode(struct pipe_context *ctx, |
| 317 | const struct pipe_blend_state *state, |
| 318 | int mode) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 319 | { |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 320 | struct r600_context *rctx = (struct r600_context *)ctx; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 321 | uint32_t color_control = 0, target_mask = 0; |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 322 | struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 323 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 324 | if (!blend) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 325 | return NULL; |
| 326 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 327 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 328 | r600_init_command_buffer(&blend->buffer, 20); |
| 329 | r600_init_command_buffer(&blend->buffer_no_blend, 20); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 330 | |
Alex Deucher | 3e30148 | 2011-03-14 17:53:00 -0400 | [diff] [blame] | 331 | /* R600 does not support per-MRT blends */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 332 | if (rctx->b.family > CHIP_R600) |
Alex Deucher | 3e30148 | 2011-03-14 17:53:00 -0400 | [diff] [blame] | 333 | color_control |= S_028808_PER_MRT_BLEND(1); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 334 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 335 | if (state->logicop_enable) { |
| 336 | color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); |
| 337 | } else { |
| 338 | color_control |= (0xcc << 16); |
| 339 | } |
| 340 | /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ |
| 341 | if (state->independent_blend_enable) { |
| 342 | for (int i = 0; i < 8; i++) { |
| 343 | if (state->rt[i].blend_enable) { |
| 344 | color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); |
| 345 | } |
| 346 | target_mask |= (state->rt[i].colormask << (4 * i)); |
| 347 | } |
| 348 | } else { |
| 349 | for (int i = 0; i < 8; i++) { |
| 350 | if (state->rt[0].blend_enable) { |
| 351 | color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); |
| 352 | } |
| 353 | target_mask |= (state->rt[0].colormask << (4 * i)); |
| 354 | } |
| 355 | } |
Marek Olšák | 43e3f19 | 2012-07-07 17:11:32 +0200 | [diff] [blame] | 356 | |
| 357 | if (target_mask) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 358 | color_control |= S_028808_SPECIAL_OP(mode); |
Marek Olšák | 43e3f19 | 2012-07-07 17:11:32 +0200 | [diff] [blame] | 359 | else |
| 360 | color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE); |
| 361 | |
Dave Airlie | d1cc87c | 2012-03-24 13:37:16 +0000 | [diff] [blame] | 362 | /* only MRT0 has dual src blend */ |
| 363 | blend->dual_src_blend = util_blend_state_is_dual(state, 0); |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 364 | blend->cb_target_mask = target_mask; |
| 365 | blend->cb_color_control = color_control; |
| 366 | blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE; |
| 367 | blend->alpha_to_one = state->alpha_to_one; |
Jerome Glisse | 7ffd4e9 | 2010-11-17 17:20:59 -0500 | [diff] [blame] | 368 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 369 | r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK, |
| 370 | S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | |
| 371 | S_028D44_ALPHA_TO_MASK_OFFSET0(2) | |
| 372 | S_028D44_ALPHA_TO_MASK_OFFSET1(2) | |
| 373 | S_028D44_ALPHA_TO_MASK_OFFSET2(2) | |
| 374 | S_028D44_ALPHA_TO_MASK_OFFSET3(2)); |
Julian Adams | 3f8455d | 2011-04-06 21:04:08 +0200 | [diff] [blame] | 375 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 376 | /* Copy over the registers set so far into buffer_no_blend. */ |
| 377 | memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4); |
| 378 | blend->buffer_no_blend.num_dw = blend->buffer.num_dw; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 379 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 380 | /* Only add blend registers if blending is enabled. */ |
| 381 | if (!G_028808_TARGET_BLEND_ENABLE(color_control)) { |
| 382 | return blend; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 383 | } |
Marek Olšák | 26cb887 | 2012-08-04 01:50:10 +0200 | [diff] [blame] | 384 | |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 385 | /* The first R600 does not support per-MRT blends */ |
| 386 | r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL, |
| 387 | r600_get_blend_control(state, 0)); |
Marek Olšák | 6517225 | 2012-07-22 06:36:58 +0200 | [diff] [blame] | 388 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 389 | if (rctx->b.family > CHIP_R600) { |
Marek Olšák | faaba52 | 2012-10-05 02:45:29 +0200 | [diff] [blame] | 390 | r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8); |
| 391 | for (int i = 0; i < 8; i++) { |
| 392 | r600_store_value(&blend->buffer, r600_get_blend_control(state, i)); |
| 393 | } |
| 394 | } |
| 395 | return blend; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 396 | } |
| 397 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 398 | static void *r600_create_blend_state(struct pipe_context *ctx, |
| 399 | const struct pipe_blend_state *state) |
| 400 | { |
| 401 | return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL); |
| 402 | } |
| 403 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 404 | static void *r600_create_dsa_state(struct pipe_context *ctx, |
| 405 | const struct pipe_depth_stencil_alpha_state *state) |
| 406 | { |
Marek Olšák | 3d061ca | 2012-01-28 06:03:53 +0100 | [diff] [blame] | 407 | unsigned db_depth_control, alpha_test_control, alpha_ref; |
Marek Olšák | ef72361 | 2012-10-05 20:11:15 +0200 | [diff] [blame] | 408 | struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 409 | |
Edward O'Callaghan | 13eb5f5 | 2015-12-04 22:08:22 +1100 | [diff] [blame] | 410 | if (!dsa) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 411 | return NULL; |
| 412 | } |
| 413 | |
Marek Olšák | ef72361 | 2012-10-05 20:11:15 +0200 | [diff] [blame] | 414 | r600_init_command_buffer(&dsa->buffer, 3); |
| 415 | |
Marek Olšák | a236194 | 2012-01-28 05:50:00 +0100 | [diff] [blame] | 416 | dsa->valuemask[0] = state->stencil[0].valuemask; |
| 417 | dsa->valuemask[1] = state->stencil[1].valuemask; |
| 418 | dsa->writemask[0] = state->stencil[0].writemask; |
| 419 | dsa->writemask[1] = state->stencil[1].writemask; |
Jerome Glisse | 6bc7605 | 2013-02-20 16:20:17 -0500 | [diff] [blame] | 420 | dsa->zwritemask = state->depth.writemask; |
Marek Olšák | a236194 | 2012-01-28 05:50:00 +0100 | [diff] [blame] | 421 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 422 | db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | |
| 423 | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | |
| 424 | S_028800_ZFUNC(state->depth.func); |
| 425 | |
| 426 | /* stencil */ |
| 427 | if (state->stencil[0].enabled) { |
| 428 | db_depth_control |= S_028800_STENCIL_ENABLE(1); |
Marek Olšák | d214275 | 2012-02-14 15:14:58 +0100 | [diff] [blame] | 429 | db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 430 | db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); |
| 431 | db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); |
| 432 | db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); |
| 433 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 434 | if (state->stencil[1].enabled) { |
| 435 | db_depth_control |= S_028800_BACKFACE_ENABLE(1); |
Marek Olšák | d214275 | 2012-02-14 15:14:58 +0100 | [diff] [blame] | 436 | db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 437 | db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); |
| 438 | db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); |
| 439 | db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 440 | } |
| 441 | } |
| 442 | |
| 443 | /* alpha */ |
| 444 | alpha_test_control = 0; |
| 445 | alpha_ref = 0; |
| 446 | if (state->alpha.enabled) { |
| 447 | alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); |
| 448 | alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); |
| 449 | alpha_ref = fui(state->alpha.ref_value); |
| 450 | } |
Dave Airlie | 4a26454 | 2012-04-22 20:51:43 +0100 | [diff] [blame] | 451 | dsa->sx_alpha_test_control = alpha_test_control & 0xff; |
Henri Verbeet | f60235e | 2011-05-05 20:54:36 +0200 | [diff] [blame] | 452 | dsa->alpha_ref = alpha_ref; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 453 | |
Marek Olšák | ef72361 | 2012-10-05 20:11:15 +0200 | [diff] [blame] | 454 | r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control); |
| 455 | return dsa; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 456 | } |
| 457 | |
| 458 | static void *r600_create_rs_state(struct pipe_context *ctx, |
Marek Olšák | 543b233 | 2011-11-08 21:58:27 +0100 | [diff] [blame] | 459 | const struct pipe_rasterizer_state *state) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 460 | { |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 461 | struct r600_context *rctx = (struct r600_context *)ctx; |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 462 | unsigned tmp, sc_mode_cntl, spi_interp; |
Marek Olšák | f183cc9 | 2012-01-27 21:20:27 +0100 | [diff] [blame] | 463 | float psize_min, psize_max; |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 464 | struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 465 | |
Edward O'Callaghan | 13eb5f5 | 2015-12-04 22:08:22 +1100 | [diff] [blame] | 466 | if (!rs) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 467 | return NULL; |
| 468 | } |
| 469 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 470 | r600_init_command_buffer(&rs->buffer, 30); |
Marek Olšák | a652cc4 | 2012-01-29 05:48:28 +0100 | [diff] [blame] | 471 | |
Marek Olšák | 686b018 | 2016-04-10 04:56:46 +0200 | [diff] [blame] | 472 | rs->scissor_enable = state->scissor; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 473 | rs->flatshade = state->flatshade; |
| 474 | rs->sprite_coord_enable = state->sprite_coord_enable; |
Vadim Girlin | 725a820 | 2012-01-06 08:13:18 +0400 | [diff] [blame] | 475 | rs->two_side = state->light_twoside; |
Vadim Girlin | 91d4729 | 2012-01-15 09:29:50 -0500 | [diff] [blame] | 476 | rs->clip_plane_enable = state->clip_plane_enable; |
Marek Olšák | 2000086 | 2012-01-29 05:22:00 +0100 | [diff] [blame] | 477 | rs->pa_sc_line_stipple = state->line_stipple_enable ? |
| 478 | S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | |
| 479 | S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; |
Marek Olšák | a494301 | 2012-01-29 07:16:10 +0100 | [diff] [blame] | 480 | rs->pa_cl_clip_cntl = |
Marek Olšák | a3591da | 2014-10-22 10:59:49 +0200 | [diff] [blame] | 481 | S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | |
Marek Olšák | a494301 | 2012-01-29 07:16:10 +0100 | [diff] [blame] | 482 | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | |
| 483 | S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | |
| 484 | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 485 | if (rctx->b.chip_class == R700) { |
| 486 | rs->pa_cl_clip_cntl |= |
| 487 | S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard); |
| 488 | } |
Marek Olšák | 26cb887 | 2012-08-04 01:50:10 +0200 | [diff] [blame] | 489 | rs->multisample_enable = state->multisample; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 490 | |
Jerome Glisse | 58c2439 | 2010-09-24 21:34:56 -0400 | [diff] [blame] | 491 | /* offset */ |
| 492 | rs->offset_units = state->offset_units; |
Marek Olšák | d335aad | 2015-08-11 22:36:51 +0200 | [diff] [blame] | 493 | rs->offset_scale = state->offset_scale * 16.0f; |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 494 | rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri; |
Jerome Glisse | 58c2439 | 2010-09-24 21:34:56 -0400 | [diff] [blame] | 495 | |
Marek Olšák | c7eaf274 | 2012-03-08 11:15:32 +0100 | [diff] [blame] | 496 | if (state->point_size_per_vertex) { |
Marek Olšák | e3032a0 | 2012-01-28 15:05:06 +0100 | [diff] [blame] | 497 | psize_min = util_get_min_point_size(state); |
| 498 | psize_max = 8192; |
| 499 | } else { |
| 500 | /* Force the point size to be as if the vertex output was disabled. */ |
| 501 | psize_min = state->point_size; |
| 502 | psize_max = state->point_size; |
| 503 | } |
Keith Whitwell | c28f764 | 2010-10-14 16:42:39 +0100 | [diff] [blame] | 504 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 505 | sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) | |
| 506 | S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 507 | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | |
| 508 | S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1); |
| 509 | if (rctx->b.family == CHIP_RV770) { |
| 510 | /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */ |
| 511 | sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1); |
| 512 | } |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 513 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 514 | sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) | |
| 515 | S_028A4C_R700_ZMM_LINE_OFFSET(1) | |
Marek Olšák | 686b018 | 2016-04-10 04:56:46 +0200 | [diff] [blame] | 516 | S_028A4C_R700_VPORT_SCISSOR_ENABLE(1); |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 517 | } else { |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 518 | sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1); |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 519 | } |
Jerome Glisse | 7ffd4e9 | 2010-11-17 17:20:59 -0500 | [diff] [blame] | 520 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 521 | spi_interp = S_0286D4_FLAT_SHADE_ENA(1); |
| 522 | if (state->sprite_coord_enable) { |
| 523 | spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) | |
| 524 | S_0286D4_PNT_SPRITE_OVRD_X(2) | |
| 525 | S_0286D4_PNT_SPRITE_OVRD_Y(3) | |
| 526 | S_0286D4_PNT_SPRITE_OVRD_Z(0) | |
| 527 | S_0286D4_PNT_SPRITE_OVRD_W(1); |
| 528 | if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { |
| 529 | spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1); |
| 530 | } |
| 531 | } |
Keith Whitwell | c3974dc | 2010-10-17 11:45:49 -0700 | [diff] [blame] | 532 | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 533 | r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3); |
| 534 | /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */ |
| 535 | tmp = r600_pack_float_12p4(state->point_size/2); |
| 536 | r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */ |
| 537 | S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); |
| 538 | r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */ |
| 539 | S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | |
| 540 | S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); |
| 541 | r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */ |
| 542 | S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2))); |
| 543 | |
| 544 | r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp); |
| 545 | r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); |
| 546 | r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL, |
José Fonseca | 2737abb | 2013-04-23 19:40:05 +0100 | [diff] [blame] | 547 | S_028C08_PIX_CENTER_HALF(state->half_pixel_center) | |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 548 | S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); |
| 549 | r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); |
Marek Olšák | ecc8a37 | 2014-04-20 15:19:43 +0200 | [diff] [blame] | 550 | |
| 551 | rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | |
| 552 | S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | |
| 553 | S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | |
| 554 | S_028814_FACE(!state->front_ccw) | |
Marek Olšák | dab177e | 2014-10-23 13:44:14 +0200 | [diff] [blame] | 555 | S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | |
| 556 | S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | |
| 557 | S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | |
Marek Olšák | ecc8a37 | 2014-04-20 15:19:43 +0200 | [diff] [blame] | 558 | S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || |
| 559 | state->fill_back != PIPE_POLYGON_MODE_FILL) | |
| 560 | S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | |
| 561 | S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)); |
| 562 | if (rctx->b.chip_class == R700) { |
| 563 | r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl); |
| 564 | } |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 565 | if (rctx->b.chip_class == R600) { |
| 566 | r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, |
| 567 | S_028350_MULTIPASS(state->rasterizer_discard)); |
| 568 | } |
Marek Olšák | 711f3ba | 2012-10-05 19:39:14 +0200 | [diff] [blame] | 569 | return rs; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 570 | } |
| 571 | |
Marek Olšák | 3bc2d96 | 2016-04-08 02:09:59 +0200 | [diff] [blame] | 572 | static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso) |
| 573 | { |
| 574 | if (filter == PIPE_TEX_FILTER_LINEAR) |
| 575 | return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR |
| 576 | : V_03C000_SQ_TEX_XY_FILTER_BILINEAR; |
| 577 | else |
| 578 | return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT |
| 579 | : V_03C000_SQ_TEX_XY_FILTER_POINT; |
| 580 | } |
| 581 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 582 | static void *r600_create_sampler_state(struct pipe_context *ctx, |
| 583 | const struct pipe_sampler_state *state) |
| 584 | { |
Marek Olšák | 04f15e4 | 2016-04-11 17:54:51 +0200 | [diff] [blame] | 585 | struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen; |
Marek Olšák | badf033 | 2011-06-19 23:41:02 +0200 | [diff] [blame] | 586 | struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); |
Marek Olšák | 04f15e4 | 2016-04-11 17:54:51 +0200 | [diff] [blame] | 587 | unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso |
| 588 | : state->max_anisotropy; |
| 589 | unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 590 | |
Edward O'Callaghan | 13eb5f5 | 2015-12-04 22:08:22 +1100 | [diff] [blame] | 591 | if (!ss) { |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 592 | return NULL; |
| 593 | } |
| 594 | |
Marek Olšák | badf033 | 2011-06-19 23:41:02 +0200 | [diff] [blame] | 595 | ss->seamless_cube_map = state->seamless_cube_map; |
Marek Olšák | 023dae7 | 2012-10-14 04:12:32 +0200 | [diff] [blame] | 596 | ss->border_color_use = sampler_state_needs_border_color(state); |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 597 | |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 598 | /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */ |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 599 | ss->tex_sampler_words[0] = |
| 600 | S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | |
| 601 | S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | |
| 602 | S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | |
Marek Olšák | 04f15e4 | 2016-04-11 17:54:51 +0200 | [diff] [blame] | 603 | S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) | |
| 604 | S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) | |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 605 | S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | |
Marek Olšák | 04f15e4 | 2016-04-11 17:54:51 +0200 | [diff] [blame] | 606 | S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) | |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 607 | S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | |
| 608 | S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 609 | /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 610 | ss->tex_sampler_words[1] = |
| 611 | S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | |
| 612 | S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | |
| 613 | S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 614 | /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */ |
| 615 | ss->tex_sampler_words[2] = S_03C008_TYPE(1); |
Marek Olšák | 33dda8f | 2012-10-14 03:53:09 +0200 | [diff] [blame] | 616 | |
| 617 | if (ss->border_color_use) { |
| 618 | memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color)); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 619 | } |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 620 | return ss; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 621 | } |
| 622 | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 623 | static struct pipe_sampler_view * |
| 624 | texture_buffer_sampler_view(struct r600_pipe_sampler_view *view, |
| 625 | unsigned width0, unsigned height0) |
| 626 | |
| 627 | { |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 628 | struct r600_texture *tmp = (struct r600_texture*)view->base.texture; |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 629 | int stride = util_format_get_blocksize(view->base.format); |
| 630 | unsigned format, num_format, format_comp, endian; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 631 | uint64_t offset = view->base.u.buf.first_element * stride; |
Fredrik Höglund | fb69dbb | 2013-03-22 17:14:43 +0100 | [diff] [blame] | 632 | unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride; |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 633 | |
| 634 | r600_vertex_data_type(view->base.format, |
| 635 | &format, &num_format, &format_comp, |
| 636 | &endian); |
| 637 | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 638 | view->tex_resource = &tmp->resource; |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 639 | view->skip_mip_address_reloc = true; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 640 | |
| 641 | view->tex_resource_words[0] = offset; |
Fredrik Höglund | fb69dbb | 2013-03-22 17:14:43 +0100 | [diff] [blame] | 642 | view->tex_resource_words[1] = size - 1; |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 643 | view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 644 | S_038008_STRIDE(stride) | |
| 645 | S_038008_DATA_FORMAT(format) | |
| 646 | S_038008_NUM_FORMAT_ALL(num_format) | |
| 647 | S_038008_FORMAT_COMP_ALL(format_comp) | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 648 | S_038008_ENDIAN_SWAP(endian); |
| 649 | view->tex_resource_words[3] = 0; |
| 650 | /* |
| 651 | * in theory dword 4 is for number of elements, for use with resinfo, |
| 652 | * but it seems to utterly fail to work, the amd gpu shader analyser |
| 653 | * uses a const buffer to store the element sizes for buffer txq |
| 654 | */ |
| 655 | view->tex_resource_words[4] = 0; |
| 656 | view->tex_resource_words[5] = 0; |
| 657 | view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER); |
| 658 | return &view->base; |
| 659 | } |
| 660 | |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 661 | struct pipe_sampler_view * |
| 662 | r600_create_sampler_view_custom(struct pipe_context *ctx, |
| 663 | struct pipe_resource *texture, |
| 664 | const struct pipe_sampler_view *state, |
| 665 | unsigned width_first_level, unsigned height_first_level) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 666 | { |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 667 | struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); |
Marek Olšák | 951ac46 | 2012-08-14 02:29:17 +0200 | [diff] [blame] | 668 | struct r600_texture *tmp = (struct r600_texture*)texture; |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 669 | unsigned format, endian; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 670 | uint32_t word4 = 0, yuv_format = 0, pitch = 0; |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 671 | unsigned char swizzle[4], array_mode = 0; |
Marek Olšák | 677a440 | 2011-06-15 02:24:03 +0200 | [diff] [blame] | 672 | unsigned width, height, depth, offset_level, last_level; |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 673 | bool do_endian_swap = FALSE; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 674 | |
Edward O'Callaghan | 13eb5f5 | 2015-12-04 22:08:22 +1100 | [diff] [blame] | 675 | if (!view) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 676 | return NULL; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 677 | |
| 678 | /* initialize base object */ |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 679 | view->base = *state; |
| 680 | view->base.texture = NULL; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 681 | pipe_reference(NULL, &texture->reference); |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 682 | view->base.texture = texture; |
| 683 | view->base.reference.count = 1; |
| 684 | view->base.context = ctx; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 685 | |
Dave Airlie | d23aa65 | 2012-12-16 10:31:32 +0000 | [diff] [blame] | 686 | if (texture->target == PIPE_BUFFER) |
| 687 | return texture_buffer_sampler_view(view, texture->width0, 1); |
| 688 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 689 | swizzle[0] = state->swizzle_r; |
| 690 | swizzle[1] = state->swizzle_g; |
| 691 | swizzle[2] = state->swizzle_b; |
| 692 | swizzle[3] = state->swizzle_a; |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 693 | |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 694 | if (R600_BIG_ENDIAN) |
| 695 | do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture); |
| 696 | |
Dave Airlie | 929be6e | 2011-03-01 14:55:35 +1000 | [diff] [blame] | 697 | format = r600_translate_texformat(ctx->screen, state->format, |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 698 | swizzle, |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 699 | &word4, &yuv_format, do_endian_swap); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 700 | assert(format != ~0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 701 | if (format == ~0) { |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 702 | FREE(view); |
| 703 | return NULL; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 704 | } |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 705 | |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 706 | if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) { |
Marek Olšák | 611dd52 | 2012-07-18 00:05:14 +0200 | [diff] [blame] | 707 | if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) { |
Marek Olšák | da98bb6 | 2012-06-25 12:45:32 +0200 | [diff] [blame] | 708 | FREE(view); |
| 709 | return NULL; |
| 710 | } |
Marek Olšák | 611dd52 | 2012-07-18 00:05:14 +0200 | [diff] [blame] | 711 | tmp = tmp->flushed_depth_texture; |
Henri Verbeet | d171ae0 | 2011-02-01 01:17:02 +0100 | [diff] [blame] | 712 | } |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 713 | |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 714 | endian = r600_colorformat_endian_swap(format, do_endian_swap); |
Dave Airlie | 231bf88 | 2011-02-17 10:25:57 +1000 | [diff] [blame] | 715 | |
Marek Olšák | 677a440 | 2011-06-15 02:24:03 +0200 | [diff] [blame] | 716 | offset_level = state->u.tex.first_level; |
| 717 | last_level = state->u.tex.last_level - offset_level; |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 718 | width = width_first_level; |
| 719 | height = height_first_level; |
Marek Olšák | 26c872c | 2013-01-25 18:27:05 +0100 | [diff] [blame] | 720 | depth = u_minify(texture->depth0, offset_level); |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 721 | pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); |
Marek Olšák | 677a440 | 2011-06-15 02:24:03 +0200 | [diff] [blame] | 722 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 723 | if (texture->target == PIPE_TEXTURE_1D_ARRAY) { |
| 724 | height = 1; |
| 725 | depth = texture->array_size; |
| 726 | } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { |
| 727 | depth = texture->array_size; |
Dave Airlie | eb44c36d | 2012-11-03 20:53:33 +1000 | [diff] [blame] | 728 | } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) |
| 729 | depth = texture->array_size / 6; |
Marek Olšák | 92f6af2 | 2016-04-22 23:39:23 +0200 | [diff] [blame] | 730 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 731 | switch (tmp->surface.level[offset_level].mode) { |
Marek Olšák | 92f6af2 | 2016-04-22 23:39:23 +0200 | [diff] [blame] | 732 | default: |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 733 | case RADEON_SURF_MODE_LINEAR_ALIGNED: |
| 734 | array_mode = V_038000_ARRAY_LINEAR_ALIGNED; |
| 735 | break; |
| 736 | case RADEON_SURF_MODE_1D: |
| 737 | array_mode = V_038000_ARRAY_1D_TILED_THIN1; |
| 738 | break; |
| 739 | case RADEON_SURF_MODE_2D: |
| 740 | array_mode = V_038000_ARRAY_2D_TILED_THIN1; |
| 741 | break; |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 742 | } |
| 743 | |
Marek Olšák | 27b102e | 2015-09-06 17:37:38 +0200 | [diff] [blame] | 744 | if (state->format == PIPE_FORMAT_X24S8_UINT || |
| 745 | state->format == PIPE_FORMAT_S8X24_UINT || |
| 746 | state->format == PIPE_FORMAT_X32_S8X24_UINT || |
| 747 | state->format == PIPE_FORMAT_S8_UINT) |
| 748 | view->is_stencil_sampler = true; |
| 749 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 750 | view->tex_resource = &tmp->resource; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 751 | view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 752 | S_038000_TILE_MODE(array_mode) | |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 753 | S_038000_TILE_TYPE(tmp->non_disp_tiling) | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 754 | S_038000_PITCH((pitch / 8) - 1) | |
| 755 | S_038000_TEX_WIDTH(width - 1)); |
| 756 | view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | |
| 757 | S_038004_TEX_DEPTH(depth - 1) | |
| 758 | S_038004_DATA_FORMAT(format)); |
| 759 | view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8; |
| 760 | if (offset_level >= tmp->surface.last_level) { |
| 761 | view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8; |
| 762 | } else { |
| 763 | view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8; |
| 764 | } |
| 765 | view->tex_resource_words[4] = (word4 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 766 | S_038010_REQUEST_SIZE(1) | |
| 767 | S_038010_ENDIAN_SWAP(endian) | |
| 768 | S_038010_BASE_LEVEL(0)); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 769 | view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 770 | S_038014_LAST_ARRAY(state->u.tex.last_layer)); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 771 | if (texture->nr_samples > 1) { |
| 772 | /* LAST_LEVEL holds log2(nr_samples) for multisample textures */ |
| 773 | view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples)); |
| 774 | } else { |
| 775 | view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level); |
| 776 | } |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 777 | view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | |
| 778 | S_038018_MAX_ANISO(4 /* max 16 samples */)); |
Marek Olšák | 565f39b | 2011-08-19 22:27:00 +0200 | [diff] [blame] | 779 | return &view->base; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 780 | } |
| 781 | |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 782 | static struct pipe_sampler_view * |
| 783 | r600_create_sampler_view(struct pipe_context *ctx, |
| 784 | struct pipe_resource *tex, |
| 785 | const struct pipe_sampler_view *state) |
| 786 | { |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 787 | return r600_create_sampler_view_custom(ctx, tex, state, |
Marek Olšák | 26c872c | 2013-01-25 18:27:05 +0100 | [diff] [blame] | 788 | u_minify(tex->width0, state->u.tex.first_level), |
| 789 | u_minify(tex->height0, state->u.tex.first_level)); |
Marek Olšák | 6db53ca | 2012-09-23 23:12:17 +0200 | [diff] [blame] | 790 | } |
| 791 | |
Marek Olšák | 2b8d39b | 2012-09-10 20:03:09 +0200 | [diff] [blame] | 792 | static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 793 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 794 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 2b8d39b | 2012-09-10 20:03:09 +0200 | [diff] [blame] | 795 | struct pipe_clip_state *state = &rctx->clip_state.state; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 796 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 797 | radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 798 | radeon_emit_array(cs, (unsigned*)state, 6*4); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 799 | } |
| 800 | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 801 | static void r600_set_polygon_stipple(struct pipe_context *ctx, |
| 802 | const struct pipe_poly_stipple *state) |
| 803 | { |
| 804 | } |
| 805 | |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 806 | static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen, |
| 807 | unsigned size, unsigned alignment) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 808 | { |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 809 | struct pipe_resource buffer; |
| 810 | |
| 811 | memset(&buffer, 0, sizeof buffer); |
| 812 | buffer.target = PIPE_BUFFER; |
| 813 | buffer.format = PIPE_FORMAT_R8_UNORM; |
| 814 | buffer.bind = PIPE_BIND_CUSTOM; |
Marek Olšák | c321144 | 2014-02-03 03:42:17 +0100 | [diff] [blame] | 815 | buffer.usage = PIPE_USAGE_DEFAULT; |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 816 | buffer.flags = 0; |
| 817 | buffer.width0 = size; |
| 818 | buffer.height0 = 1; |
| 819 | buffer.depth0 = 1; |
| 820 | buffer.array_size = 1; |
| 821 | |
| 822 | return (struct r600_resource*) |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 823 | r600_buffer_create(&rscreen->b.b, &buffer, alignment); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 824 | } |
| 825 | |
| 826 | static void r600_init_color_surface(struct r600_context *rctx, |
| 827 | struct r600_surface *surf, |
| 828 | bool force_cmask_fmask) |
| 829 | { |
| 830 | struct r600_screen *rscreen = rctx->screen; |
Marek Olšák | 951ac46 | 2012-08-14 02:29:17 +0200 | [diff] [blame] | 831 | struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 832 | unsigned level = surf->base.u.tex.level; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 833 | unsigned pitch, slice; |
| 834 | unsigned color_info; |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 835 | unsigned color_view; |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 836 | unsigned format, swap, ntype, endian; |
Roland Scheidegger | 4c70014 | 2010-12-02 04:33:43 +0100 | [diff] [blame] | 837 | unsigned offset; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 838 | const struct util_format_description *desc; |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 839 | int i; |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 840 | bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE; |
Dave Airlie | 3e9bc43 | 2011-02-04 09:07:08 +1000 | [diff] [blame] | 841 | |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 842 | if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 843 | r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL); |
Dave Airlie | 3e9bc43 | 2011-02-04 09:07:08 +1000 | [diff] [blame] | 844 | rtex = rtex->flushed_depth_texture; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 845 | assert(rtex); |
Dave Airlie | 3e9bc43 | 2011-02-04 09:07:08 +1000 | [diff] [blame] | 846 | } |
| 847 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 848 | offset = rtex->surface.level[level].offset; |
Marek Olšák | 92f6af2 | 2016-04-22 23:39:23 +0200 | [diff] [blame] | 849 | color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | |
| 850 | S_028080_SLICE_MAX(surf->base.u.tex.last_layer); |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 851 | |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 852 | pitch = rtex->surface.level[level].nblk_x / 8 - 1; |
| 853 | slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; |
| 854 | if (slice) { |
| 855 | slice = slice - 1; |
| 856 | } |
| 857 | color_info = 0; |
| 858 | switch (rtex->surface.level[level].mode) { |
Marek Olšák | 92f6af2 | 2016-04-22 23:39:23 +0200 | [diff] [blame] | 859 | default: |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 860 | case RADEON_SURF_MODE_LINEAR_ALIGNED: |
| 861 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); |
| 862 | break; |
| 863 | case RADEON_SURF_MODE_1D: |
| 864 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
| 865 | break; |
| 866 | case RADEON_SURF_MODE_2D: |
| 867 | color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); |
| 868 | break; |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 869 | } |
| 870 | |
Dave Airlie | 780c183 | 2011-02-06 18:57:11 +1000 | [diff] [blame] | 871 | desc = util_format_description(surf->base.format); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 872 | |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 873 | for (i = 0; i < 4; i++) { |
| 874 | if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { |
| 875 | break; |
| 876 | } |
| 877 | } |
Dave Airlie | 8d3e505 | 2011-10-10 20:27:51 +0100 | [diff] [blame] | 878 | |
Dave Airlie | 66866d6 | 2011-04-19 20:42:48 +1000 | [diff] [blame] | 879 | ntype = V_0280A0_NUMBER_UNORM; |
| 880 | if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) |
| 881 | ntype = V_0280A0_NUMBER_SRGB; |
Dave Airlie | 8d3e505 | 2011-10-10 20:27:51 +0100 | [diff] [blame] | 882 | else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { |
| 883 | if (desc->channel[i].normalized) |
| 884 | ntype = V_0280A0_NUMBER_SNORM; |
| 885 | else if (desc->channel[i].pure_integer) |
| 886 | ntype = V_0280A0_NUMBER_SINT; |
| 887 | } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { |
| 888 | if (desc->channel[i].normalized) |
| 889 | ntype = V_0280A0_NUMBER_UNORM; |
| 890 | else if (desc->channel[i].pure_integer) |
| 891 | ntype = V_0280A0_NUMBER_UINT; |
| 892 | } |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 893 | |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 894 | if (R600_BIG_ENDIAN) |
| 895 | do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture); |
| 896 | |
| 897 | format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format, |
| 898 | do_endian_swap); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 899 | assert(format != ~0); |
| 900 | |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 901 | swap = r600_translate_colorswap(surf->base.format, do_endian_swap); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 902 | assert(swap != ~0); |
| 903 | |
Oded Gabbay | 2242dbe | 2016-03-21 23:46:15 +0200 | [diff] [blame] | 904 | endian = r600_colorformat_endian_swap(format, do_endian_swap); |
Dave Airlie | 231bf88 | 2011-02-17 10:25:57 +1000 | [diff] [blame] | 905 | |
Dave Airlie | a33937d | 2012-01-29 19:38:28 +0000 | [diff] [blame] | 906 | /* set blend bypass according to docs if SINT/UINT or |
| 907 | 8/24 COLOR variants */ |
| 908 | if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || |
| 909 | format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || |
| 910 | format == V_0280A0_COLOR_X24_8_32_FLOAT) { |
| 911 | blend_clamp = 0; |
| 912 | blend_bypass = 1; |
| 913 | } |
| 914 | |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 915 | surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT; |
Dave Airlie | 4a26454 | 2012-04-22 20:51:43 +0100 | [diff] [blame] | 916 | |
Jerome Glisse | c0c979e | 2012-01-30 17:22:13 -0500 | [diff] [blame] | 917 | color_info |= S_0280A0_FORMAT(format) | |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 918 | S_0280A0_COMP_SWAP(swap) | |
Dave Airlie | a33937d | 2012-01-29 19:38:28 +0000 | [diff] [blame] | 919 | S_0280A0_BLEND_BYPASS(blend_bypass) | |
| 920 | S_0280A0_BLEND_CLAMP(blend_clamp) | |
Cédric Cano | 843dfe3 | 2011-04-19 13:02:14 -0400 | [diff] [blame] | 921 | S_0280A0_NUMBER_TYPE(ntype) | |
| 922 | S_0280A0_ENDIAN(endian); |
Dave Airlie | 0d851f6 | 2011-02-10 14:07:06 +1000 | [diff] [blame] | 923 | |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 924 | /* EXPORT_NORM is an optimzation that can be enabled for better |
| 925 | * performance in certain cases |
| 926 | */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 927 | if (rctx->b.chip_class == R600) { |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 928 | /* EXPORT_NORM can be enabled if: |
| 929 | * - 11-bit or smaller UNORM/SNORM/SRGB |
| 930 | * - BLEND_CLAMP is enabled |
| 931 | * - BLEND_FLOAT32 is disabled |
| 932 | */ |
| 933 | if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && |
| 934 | (desc->channel[i].size < 12 && |
| 935 | desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && |
| 936 | ntype != V_0280A0_NUMBER_UINT && |
| 937 | ntype != V_0280A0_NUMBER_SINT) && |
| 938 | G_0280A0_BLEND_CLAMP(color_info) && |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 939 | !G_0280A0_BLEND_FLOAT32(color_info)) { |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 940 | color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 941 | surf->export_16bpc = true; |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 942 | } |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 943 | } else { |
| 944 | /* EXPORT_NORM can be enabled if: |
| 945 | * - 11-bit or smaller UNORM/SNORM/SRGB |
| 946 | * - 16-bit or smaller FLOAT |
| 947 | */ |
| 948 | if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && |
| 949 | ((desc->channel[i].size < 12 && |
| 950 | desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && |
| 951 | ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || |
| 952 | (desc->channel[i].size < 17 && |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 953 | desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 954 | color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 955 | surf->export_16bpc = true; |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 956 | } |
Alex Deucher | 5939bc0 | 2011-05-05 18:54:03 -0400 | [diff] [blame] | 957 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 958 | |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 959 | /* These might not always be initialized to zero. */ |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 960 | surf->cb_color_base = offset >> 8; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 961 | surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) | |
| 962 | S_028060_SLICE_TILE_MAX(slice); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 963 | surf->cb_color_fmask = surf->cb_color_base; |
| 964 | surf->cb_color_cmask = surf->cb_color_base; |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 965 | surf->cb_color_mask = 0; |
| 966 | |
| 967 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, |
| 968 | &rtex->resource.b.b); |
| 969 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, |
| 970 | &rtex->resource.b.b); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 971 | |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 972 | if (rtex->cmask.size) { |
| 973 | surf->cb_color_cmask = rtex->cmask.offset >> 8; |
| 974 | surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 975 | |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 976 | if (rtex->fmask.size) { |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 977 | color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 978 | surf->cb_color_fmask = rtex->fmask.offset >> 8; |
| 979 | surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 980 | } else { /* cmask only */ |
| 981 | color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE); |
| 982 | } |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 983 | } else if (force_cmask_fmask) { |
| 984 | /* Allocate dummy FMASK and CMASK if they aren't allocated already. |
| 985 | * |
| 986 | * R6xx needs FMASK and CMASK for the destination buffer of color resolve, |
| 987 | * otherwise it hangs. We don't have FMASK and CMASK pre-allocated, |
| 988 | * because it's not an MSAA buffer. |
| 989 | */ |
| 990 | struct r600_cmask_info cmask; |
| 991 | struct r600_fmask_info fmask; |
| 992 | |
Marek Olšák | e64633e | 2013-09-22 13:06:27 +0200 | [diff] [blame] | 993 | r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask); |
| 994 | r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 995 | |
| 996 | /* CMASK. */ |
| 997 | if (!rctx->dummy_cmask || |
Marek Olšák | 5c6c5b5 | 2015-09-06 16:40:21 +0200 | [diff] [blame] | 998 | rctx->dummy_cmask->b.b.width0 < cmask.size || |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 999 | rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) { |
| 1000 | struct pipe_transfer *transfer; |
| 1001 | void *ptr; |
| 1002 | |
| 1003 | pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL); |
| 1004 | rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment); |
| 1005 | |
| 1006 | /* Set the contents to 0xCC. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1007 | ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1008 | memset(ptr, 0xCC, cmask.size); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1009 | pipe_buffer_unmap(&rctx->b.b, transfer); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1010 | } |
| 1011 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, |
| 1012 | &rctx->dummy_cmask->b.b); |
| 1013 | |
| 1014 | /* FMASK. */ |
| 1015 | if (!rctx->dummy_fmask || |
Marek Olšák | 5c6c5b5 | 2015-09-06 16:40:21 +0200 | [diff] [blame] | 1016 | rctx->dummy_fmask->b.b.width0 < fmask.size || |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1017 | rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) { |
| 1018 | pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL); |
| 1019 | rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment); |
| 1020 | |
| 1021 | } |
| 1022 | pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, |
| 1023 | &rctx->dummy_fmask->b.b); |
| 1024 | |
| 1025 | /* Init the registers. */ |
| 1026 | color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); |
| 1027 | surf->cb_color_cmask = 0; |
| 1028 | surf->cb_color_fmask = 0; |
| 1029 | surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) | |
Marek Olšák | 61c995b | 2013-04-11 14:54:40 +0200 | [diff] [blame] | 1030 | S_028100_FMASK_TILE_MAX(fmask.slice_tile_max); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1031 | } |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 1032 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1033 | surf->cb_color_info = color_info; |
Dave Airlie | 7863611 | 2014-01-28 23:15:29 +0000 | [diff] [blame] | 1034 | surf->cb_color_view = color_view; |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1035 | surf->color_initialized = true; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1036 | } |
| 1037 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1038 | static void r600_init_depth_surface(struct r600_context *rctx, |
| 1039 | struct r600_surface *surf) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1040 | { |
Marek Olšák | 951ac46 | 2012-08-14 02:29:17 +0200 | [diff] [blame] | 1041 | struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; |
Marek Olšák | faa16dc | 2011-10-25 01:28:39 +0200 | [diff] [blame] | 1042 | unsigned level, pitch, slice, format, offset, array_mode; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1043 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1044 | level = surf->base.u.tex.level; |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 1045 | offset = rtex->surface.level[level].offset; |
| 1046 | pitch = rtex->surface.level[level].nblk_x / 8 - 1; |
| 1047 | slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; |
| 1048 | if (slice) { |
| 1049 | slice = slice - 1; |
| 1050 | } |
| 1051 | switch (rtex->surface.level[level].mode) { |
| 1052 | case RADEON_SURF_MODE_2D: |
| 1053 | array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; |
| 1054 | break; |
| 1055 | case RADEON_SURF_MODE_1D: |
| 1056 | case RADEON_SURF_MODE_LINEAR_ALIGNED: |
Marek Olšák | 581f7e3 | 2012-07-29 18:53:19 +0200 | [diff] [blame] | 1057 | default: |
| 1058 | array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; |
| 1059 | break; |
Jerome Glisse | c0c979e | 2012-01-30 17:22:13 -0500 | [diff] [blame] | 1060 | } |
| 1061 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1062 | format = r600_translate_dbformat(surf->base.format); |
Marek Olšák | a460df9 | 2012-07-08 00:23:41 +0200 | [diff] [blame] | 1063 | assert(format != ~0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1064 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1065 | surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); |
| 1066 | surf->db_depth_base = offset >> 8; |
| 1067 | surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) | |
| 1068 | S_028004_SLICE_MAX(surf->base.u.tex.last_layer); |
| 1069 | surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); |
| 1070 | surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1; |
| 1071 | |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1072 | /* use htile only for first level */ |
Andreas Hartmetz | ca5812b | 2013-12-07 02:08:27 +0100 | [diff] [blame] | 1073 | if (rtex->htile_buffer && !level) { |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 1074 | surf->db_htile_data_base = 0; |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1075 | surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | |
Marek Olšák | 6d75106 | 2014-08-20 01:34:37 +0200 | [diff] [blame] | 1076 | S_028D24_HTILE_HEIGHT(1) | |
| 1077 | S_028D24_FULL_CACHE(1); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1078 | /* preload is not working properly on r6xx/r7xx */ |
| 1079 | surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1); |
| 1080 | } |
| 1081 | |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1082 | surf->depth_initialized = true; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1083 | } |
| 1084 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1085 | static void r600_set_framebuffer_state(struct pipe_context *ctx, |
| 1086 | const struct pipe_framebuffer_state *state) |
| 1087 | { |
| 1088 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 1089 | struct r600_surface *surf; |
| 1090 | struct r600_texture *rtex; |
| 1091 | unsigned i; |
| 1092 | |
Marek Olšák | 9c35ec2 | 2016-05-26 18:14:27 +0200 | [diff] [blame] | 1093 | /* Flush TC when changing the framebuffer state, because the only |
| 1094 | * client not using TC that can change textures is the framebuffer. |
| 1095 | * Other places don't typically have to flush TC. |
| 1096 | */ |
| 1097 | rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | |
| 1098 | R600_CONTEXT_FLUSH_AND_INV | |
| 1099 | R600_CONTEXT_FLUSH_AND_INV_CB | |
| 1100 | R600_CONTEXT_FLUSH_AND_INV_CB_META | |
| 1101 | R600_CONTEXT_FLUSH_AND_INV_DB | |
| 1102 | R600_CONTEXT_FLUSH_AND_INV_DB_META | |
| 1103 | R600_CONTEXT_INV_TEX_CACHE; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1104 | |
| 1105 | /* Set the new state. */ |
| 1106 | util_copy_framebuffer_state(&rctx->framebuffer.state, state); |
| 1107 | |
| 1108 | rctx->framebuffer.export_16bpc = state->nr_cbufs != 0; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1109 | rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1110 | util_format_is_pure_integer(state->cbufs[0]->format); |
| 1111 | rctx->framebuffer.compressed_cb_mask = 0; |
| 1112 | rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 && |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1113 | state->cbufs[0] && state->cbufs[1] && |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1114 | state->cbufs[0]->texture->nr_samples > 1 && |
| 1115 | state->cbufs[1]->texture->nr_samples <= 1; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1116 | rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1117 | |
| 1118 | /* Colorbuffers. */ |
| 1119 | for (i = 0; i < state->nr_cbufs; i++) { |
| 1120 | /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1121 | bool force_cmask_fmask = rctx->b.chip_class == R600 && |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1122 | rctx->framebuffer.is_msaa_resolve && |
| 1123 | i == 1; |
| 1124 | |
| 1125 | surf = (struct r600_surface*)state->cbufs[i]; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1126 | if (!surf) |
| 1127 | continue; |
| 1128 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1129 | rtex = (struct r600_texture*)surf->base.texture; |
Jerome Glisse | 5e0c956 | 2013-01-29 12:52:17 -0500 | [diff] [blame] | 1130 | r600_context_add_resource_size(ctx, state->cbufs[i]->texture); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1131 | |
| 1132 | if (!surf->color_initialized || force_cmask_fmask) { |
| 1133 | r600_init_color_surface(rctx, surf, force_cmask_fmask); |
| 1134 | if (force_cmask_fmask) { |
| 1135 | /* re-initialize later without compression */ |
| 1136 | surf->color_initialized = false; |
| 1137 | } |
| 1138 | } |
| 1139 | |
| 1140 | if (!surf->export_16bpc) { |
| 1141 | rctx->framebuffer.export_16bpc = false; |
| 1142 | } |
| 1143 | |
Marek Olšák | 39801d4 | 2013-09-21 19:56:24 +0200 | [diff] [blame] | 1144 | if (rtex->fmask.size && rtex->cmask.size) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1145 | rctx->framebuffer.compressed_cb_mask |= 1 << i; |
| 1146 | } |
| 1147 | } |
| 1148 | |
| 1149 | /* Update alpha-test state dependencies. |
| 1150 | * Alpha-test is done on the first colorbuffer only. */ |
| 1151 | if (state->nr_cbufs) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1152 | bool alphatest_bypass = false; |
| 1153 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1154 | surf = (struct r600_surface*)state->cbufs[0]; |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1155 | if (surf) { |
| 1156 | alphatest_bypass = surf->alphatest_bypass; |
| 1157 | } |
| 1158 | |
| 1159 | if (rctx->alphatest_state.bypass != alphatest_bypass) { |
| 1160 | rctx->alphatest_state.bypass = alphatest_bypass; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1161 | r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1162 | } |
| 1163 | } |
| 1164 | |
| 1165 | /* ZS buffer. */ |
| 1166 | if (state->zsbuf) { |
| 1167 | surf = (struct r600_surface*)state->zsbuf; |
| 1168 | |
Jerome Glisse | 5e0c956 | 2013-01-29 12:52:17 -0500 | [diff] [blame] | 1169 | r600_context_add_resource_size(ctx, state->zsbuf->texture); |
| 1170 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1171 | if (!surf->depth_initialized) { |
| 1172 | r600_init_depth_surface(rctx, surf); |
| 1173 | } |
| 1174 | |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 1175 | if (state->zsbuf->format != rctx->poly_offset_state.zs_format) { |
| 1176 | rctx->poly_offset_state.zs_format = state->zsbuf->format; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1177 | r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom); |
Marek Olšák | ab075de | 2012-10-05 04:59:50 +0200 | [diff] [blame] | 1178 | } |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1179 | |
| 1180 | if (rctx->db_state.rsurf != surf) { |
| 1181 | rctx->db_state.rsurf = surf; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1182 | r600_mark_atom_dirty(rctx, &rctx->db_state.atom); |
| 1183 | r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1184 | } |
| 1185 | } else if (rctx->db_state.rsurf) { |
| 1186 | rctx->db_state.rsurf = NULL; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1187 | r600_mark_atom_dirty(rctx, &rctx->db_state.atom); |
| 1188 | r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { |
| 1192 | rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1193 | r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1194 | } |
| 1195 | |
| 1196 | if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { |
| 1197 | rctx->alphatest_state.bypass = false; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1198 | r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | /* Calculate the CS size. */ |
| 1202 | rctx->framebuffer.atom.num_dw = |
| 1203 | 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/; |
| 1204 | |
| 1205 | if (rctx->framebuffer.state.nr_cbufs) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1206 | rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs; |
| 1207 | rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1208 | } |
| 1209 | if (rctx->framebuffer.state.zsbuf) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1210 | rctx->framebuffer.atom.num_dw += 16; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1211 | } else if (rctx->screen->b.info.drm_minor >= 18) { |
Marek Olšák | 9f5d632 | 2012-08-14 20:42:35 +0200 | [diff] [blame] | 1212 | rctx->framebuffer.atom.num_dw += 3; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1213 | } |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1214 | if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1215 | rctx->framebuffer.atom.num_dw += 2; |
| 1216 | } |
| 1217 | |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1218 | r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 1219 | |
| 1220 | r600_set_sample_locations_constant_buffer(rctx); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1221 | } |
| 1222 | |
Dave Airlie | f024c72 | 2013-03-04 06:19:07 +1000 | [diff] [blame] | 1223 | static uint32_t sample_locs_2x[] = { |
| 1224 | FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), |
| 1225 | FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), |
| 1226 | }; |
| 1227 | static unsigned max_dist_2x = 4; |
| 1228 | |
| 1229 | static uint32_t sample_locs_4x[] = { |
| 1230 | FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), |
| 1231 | FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), |
| 1232 | }; |
| 1233 | static unsigned max_dist_4x = 6; |
| 1234 | static uint32_t sample_locs_8x[] = { |
| 1235 | FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), |
| 1236 | FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), |
| 1237 | }; |
| 1238 | static unsigned max_dist_8x = 7; |
| 1239 | |
| 1240 | static void r600_get_sample_position(struct pipe_context *ctx, |
| 1241 | unsigned sample_count, |
| 1242 | unsigned sample_index, |
| 1243 | float *out_value) |
| 1244 | { |
| 1245 | int offset, index; |
| 1246 | struct { |
| 1247 | int idx:4; |
| 1248 | } val; |
| 1249 | switch (sample_count) { |
| 1250 | case 1: |
| 1251 | default: |
| 1252 | out_value[0] = out_value[1] = 0.5; |
| 1253 | break; |
| 1254 | case 2: |
| 1255 | offset = 4 * (sample_index * 2); |
| 1256 | val.idx = (sample_locs_2x[0] >> offset) & 0xf; |
| 1257 | out_value[0] = (float)(val.idx + 8) / 16.0f; |
| 1258 | val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; |
| 1259 | out_value[1] = (float)(val.idx + 8) / 16.0f; |
| 1260 | break; |
| 1261 | case 4: |
| 1262 | offset = 4 * (sample_index * 2); |
| 1263 | val.idx = (sample_locs_4x[0] >> offset) & 0xf; |
| 1264 | out_value[0] = (float)(val.idx + 8) / 16.0f; |
| 1265 | val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; |
| 1266 | out_value[1] = (float)(val.idx + 8) / 16.0f; |
| 1267 | break; |
| 1268 | case 8: |
| 1269 | offset = 4 * (sample_index % 4 * 2); |
| 1270 | index = (sample_index / 4); |
| 1271 | val.idx = (sample_locs_8x[index] >> offset) & 0xf; |
| 1272 | out_value[0] = (float)(val.idx + 8) / 16.0f; |
| 1273 | val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf; |
| 1274 | out_value[1] = (float)(val.idx + 8) / 16.0f; |
| 1275 | break; |
| 1276 | } |
| 1277 | } |
| 1278 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1279 | static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples) |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1280 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1281 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1282 | unsigned max_dist = 0; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1283 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1284 | if (rctx->b.family == CHIP_R600) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1285 | switch (nr_samples) { |
| 1286 | default: |
| 1287 | nr_samples = 0; |
| 1288 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1289 | case 2: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1290 | radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1291 | max_dist = max_dist_2x; |
| 1292 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1293 | case 4: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1294 | radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1295 | max_dist = max_dist_4x; |
| 1296 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1297 | case 8: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1298 | radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1299 | radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */ |
| 1300 | radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1301 | max_dist = max_dist_8x; |
| 1302 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1303 | } |
| 1304 | } else { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1305 | switch (nr_samples) { |
| 1306 | default: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1307 | radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1308 | radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1309 | radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1310 | nr_samples = 0; |
| 1311 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1312 | case 2: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1313 | radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1314 | radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1315 | radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1316 | max_dist = max_dist_2x; |
| 1317 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1318 | case 4: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1319 | radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1320 | radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1321 | radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1322 | max_dist = max_dist_4x; |
| 1323 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1324 | case 8: |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1325 | radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1326 | radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ |
| 1327 | radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1328 | max_dist = max_dist_8x; |
| 1329 | break; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1330 | } |
| 1331 | } |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1332 | |
| 1333 | if (nr_samples > 1) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1334 | radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1335 | radeon_emit(cs, S_028C00_LAST_PIXEL(1) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1336 | S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1337 | radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1338 | S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ |
| 1339 | } else { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1340 | radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1341 | radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ |
| 1342 | radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1343 | } |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1344 | } |
| 1345 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1346 | static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1347 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1348 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1349 | struct pipe_framebuffer_state *state = &rctx->framebuffer.state; |
| 1350 | unsigned nr_cbufs = state->nr_cbufs; |
| 1351 | struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0]; |
| 1352 | unsigned i, sbu = 0; |
Marek Olšák | fd2e34d | 2012-09-09 06:08:39 +0200 | [diff] [blame] | 1353 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1354 | /* Colorbuffers. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1355 | radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1356 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1357 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1358 | } |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1359 | /* set CB_COLOR1_INFO for possible dual-src blending */ |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1360 | if (i == 1 && cb[0]) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1361 | radeon_emit(cs, cb[0]->cb_color_info); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1362 | i++; |
| 1363 | } |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1364 | for (; i < 8; i++) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1365 | radeon_emit(cs, 0); |
Marek Olšák | 0d7e002 | 2012-08-14 22:10:35 +0200 | [diff] [blame] | 1366 | } |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1367 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1368 | if (nr_cbufs) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1369 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1370 | unsigned reloc; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1371 | |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1372 | if (!cb[i]) |
| 1373 | continue; |
| 1374 | |
| 1375 | /* COLOR_BASE */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1376 | radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1377 | |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 1378 | reloc = radeon_add_to_buffer_list(&rctx->b, |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1379 | &rctx->b.gfx, |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1380 | (struct r600_resource*)cb[i]->base.texture, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1381 | RADEON_USAGE_READWRITE, |
| 1382 | cb[i]->base.texture->nr_samples > 1 ? |
| 1383 | RADEON_PRIO_COLOR_BUFFER_MSAA : |
| 1384 | RADEON_PRIO_COLOR_BUFFER); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1385 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1386 | radeon_emit(cs, reloc); |
| 1387 | |
| 1388 | /* FMASK */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1389 | radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1390 | |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 1391 | reloc = radeon_add_to_buffer_list(&rctx->b, |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1392 | &rctx->b.gfx, |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1393 | cb[i]->cb_buffer_fmask, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1394 | RADEON_USAGE_READWRITE, |
| 1395 | cb[i]->base.texture->nr_samples > 1 ? |
| 1396 | RADEON_PRIO_COLOR_BUFFER_MSAA : |
| 1397 | RADEON_PRIO_COLOR_BUFFER); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1398 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1399 | radeon_emit(cs, reloc); |
| 1400 | |
| 1401 | /* CMASK */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1402 | radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask); |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1403 | |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 1404 | reloc = radeon_add_to_buffer_list(&rctx->b, |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1405 | &rctx->b.gfx, |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1406 | cb[i]->cb_buffer_cmask, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1407 | RADEON_USAGE_READWRITE, |
| 1408 | cb[i]->base.texture->nr_samples > 1 ? |
| 1409 | RADEON_PRIO_COLOR_BUFFER_MSAA : |
| 1410 | RADEON_PRIO_COLOR_BUFFER); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1411 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1412 | radeon_emit(cs, reloc); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1413 | } |
| 1414 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1415 | radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1416 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1417 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1418 | } |
| 1419 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1420 | radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1421 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1422 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1423 | } |
| 1424 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1425 | radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1426 | for (i = 0; i < nr_cbufs; i++) { |
Marek Olšák | 6e98a17 | 2014-01-08 18:13:24 +0100 | [diff] [blame] | 1427 | radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1428 | } |
| 1429 | |
| 1430 | sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs); |
Marek Olšák | cb922b6 | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1431 | } |
| 1432 | |
Jerome Glisse | 24b1206 | 2012-11-01 16:09:40 -0400 | [diff] [blame] | 1433 | /* SURFACE_BASE_UPDATE */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1434 | if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) { |
| 1435 | radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); |
| 1436 | radeon_emit(cs, sbu); |
Jerome Glisse | 24b1206 | 2012-11-01 16:09:40 -0400 | [diff] [blame] | 1437 | sbu = 0; |
| 1438 | } |
| 1439 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1440 | /* Zbuffer. */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1441 | if (state->zsbuf) { |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1442 | struct r600_surface *surf = (struct r600_surface*)state->zsbuf; |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 1443 | unsigned reloc = radeon_add_to_buffer_list(&rctx->b, |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1444 | &rctx->b.gfx, |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1445 | (struct r600_resource*)state->zsbuf->texture, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1446 | RADEON_USAGE_READWRITE, |
| 1447 | surf->base.texture->nr_samples > 1 ? |
| 1448 | RADEON_PRIO_DEPTH_BUFFER_MSAA : |
| 1449 | RADEON_PRIO_DEPTH_BUFFER); |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1450 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1451 | radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1452 | radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */ |
| 1453 | radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1454 | radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1455 | radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */ |
| 1456 | radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */ |
Marek Olšák | cdc681c | 2012-08-02 01:43:01 +0200 | [diff] [blame] | 1457 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1458 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1459 | radeon_emit(cs, reloc); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1460 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1461 | radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1462 | |
| 1463 | sbu |= SURFACE_BASE_UPDATE_DEPTH; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1464 | } else if (rctx->screen->b.info.drm_minor >= 18) { |
Marek Olšák | 9f5d632 | 2012-08-14 20:42:35 +0200 | [diff] [blame] | 1465 | /* DRM 2.6.18 allows the INVALID format to disable depth/stencil. |
| 1466 | * Older kernels are out of luck. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1467 | radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID)); |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1468 | } |
| 1469 | |
| 1470 | /* SURFACE_BASE_UPDATE */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1471 | if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) { |
| 1472 | radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); |
| 1473 | radeon_emit(cs, sbu); |
Jerome Glisse | 24b1206 | 2012-11-01 16:09:40 -0400 | [diff] [blame] | 1474 | sbu = 0; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1475 | } |
| 1476 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1477 | /* Framebuffer dimensions. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1478 | radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1479 | radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1480 | S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1481 | radeon_emit(cs, S_028244_BR_X(state->width) | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1482 | S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1483 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1484 | if (rctx->framebuffer.is_msaa_resolve) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1485 | radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1486 | } else { |
| 1487 | /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This |
| 1488 | * will assure that the alpha-test will work even if there is |
| 1489 | * no colorbuffer bound. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1490 | radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1491 | (1ull << MAX2(nr_cbufs, 1)) - 1); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1492 | } |
Marek Olšák | 82a1d24 | 2012-07-18 04:31:56 +0200 | [diff] [blame] | 1493 | |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 1494 | r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples); |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1495 | } |
| 1496 | |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 1497 | static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples) |
| 1498 | { |
| 1499 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 1500 | |
| 1501 | if (rctx->ps_iter_samples == min_samples) |
| 1502 | return; |
| 1503 | |
| 1504 | rctx->ps_iter_samples = min_samples; |
| 1505 | if (rctx->framebuffer.nr_samples > 1) { |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1506 | r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom); |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 1507 | if (rctx->b.chip_class == R600) |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 1508 | r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 1509 | } |
| 1510 | } |
| 1511 | |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1512 | static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1513 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1514 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1515 | struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; |
Marek Olšák | 0ea7691 | 2012-07-07 07:15:04 +0200 | [diff] [blame] | 1516 | |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1517 | if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1518 | radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1519 | if (rctx->b.chip_class == R600) { |
| 1520 | radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */ |
| 1521 | radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1522 | } else { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1523 | radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */ |
| 1524 | radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1525 | } |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1526 | radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control); |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1527 | } else { |
| 1528 | unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; |
| 1529 | unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1; |
| 1530 | unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1; |
| 1531 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1532 | radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1533 | radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1534 | /* Always enable the first color output to make sure alpha-test works even without one. */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1535 | radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1536 | radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, |
Marek Olšák | 863e2c8 | 2012-08-26 22:33:55 +0200 | [diff] [blame] | 1537 | a->cb_color_control | |
| 1538 | S_028808_MULTIWRITE_ENABLE(multiwrite)); |
| 1539 | } |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 1540 | } |
| 1541 | |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1542 | static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1543 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1544 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1545 | struct r600_db_state *a = (struct r600_db_state*)atom; |
| 1546 | |
Marek Olšák | ec266d0 | 2014-02-09 19:30:09 +0100 | [diff] [blame] | 1547 | if (a->rsurf && a->rsurf->db_htile_surface) { |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1548 | struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture; |
| 1549 | unsigned reloc_idx; |
| 1550 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1551 | radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); |
| 1552 | radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); |
| 1553 | radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1554 | reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1555 | RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE); |
Nicolai Hähnle | c232735 | 2016-05-06 16:42:03 -0500 | [diff] [blame] | 1556 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1557 | radeon_emit(cs, reloc_idx); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1558 | } else { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1559 | radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0); |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1560 | } |
| 1561 | } |
| 1562 | |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1563 | static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1564 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1565 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | e363dd5 | 2012-03-05 16:20:05 +0100 | [diff] [blame] | 1566 | struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1567 | unsigned db_render_control = 0; |
| 1568 | unsigned db_render_override = |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1569 | S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | |
| 1570 | S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); |
| 1571 | |
Glenn Kennard | 3f45d29 | 2015-10-17 16:53:28 +0200 | [diff] [blame] | 1572 | if (rctx->b.chip_class >= R700) { |
| 1573 | switch (a->ps_conservative_z) { |
| 1574 | default: /* fall through */ |
| 1575 | case TGSI_FS_DEPTH_LAYOUT_ANY: |
| 1576 | db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z); |
| 1577 | break; |
| 1578 | case TGSI_FS_DEPTH_LAYOUT_GREATER: |
| 1579 | db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z); |
| 1580 | break; |
| 1581 | case TGSI_FS_DEPTH_LAYOUT_LESS: |
| 1582 | db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z); |
| 1583 | break; |
| 1584 | } |
| 1585 | } |
| 1586 | |
Marek Olšák | e90fe60 | 2016-04-08 20:41:52 +0200 | [diff] [blame] | 1587 | if (rctx->b.num_occlusion_queries > 0 && |
| 1588 | !a->occlusion_queries_disabled) { |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1589 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1590 | db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); |
| 1591 | } |
| 1592 | db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); |
Marek Olšák | e90fe60 | 2016-04-08 20:41:52 +0200 | [diff] [blame] | 1593 | } else { |
| 1594 | db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1); |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1595 | } |
Marek Olšák | e90fe60 | 2016-04-08 20:41:52 +0200 | [diff] [blame] | 1596 | |
Marek Olšák | ec266d0 | 2014-02-09 19:30:09 +0100 | [diff] [blame] | 1597 | if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1598 | /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */ |
| 1599 | db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF); |
Jerome Glisse | 974b482 | 2013-02-08 16:02:32 -0500 | [diff] [blame] | 1600 | /* This is to fix a lockup when hyperz and alpha test are enabled at |
| 1601 | * the same time somehow GPU get confuse on which order to pick for |
| 1602 | * z test |
| 1603 | */ |
| 1604 | if (rctx->alphatest_state.sx_alpha_test_control) { |
| 1605 | db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1); |
| 1606 | } |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1607 | } else { |
| 1608 | db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); |
| 1609 | } |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 1610 | if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) { |
| 1611 | /* sample shading and hyperz causes lockups on R6xx chips */ |
| 1612 | db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); |
| 1613 | } |
Marek Olšák | df79eb5 | 2012-07-07 19:33:11 +0200 | [diff] [blame] | 1614 | if (a->flush_depthstencil_through_cb) { |
Marek Olšák | e2f623f | 2012-07-28 13:55:59 +0200 | [diff] [blame] | 1615 | assert(a->copy_depth || a->copy_stencil); |
| 1616 | |
| 1617 | db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) | |
| 1618 | S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 1619 | S_028D0C_COPY_CENTROID(1) | |
| 1620 | S_028D0C_COPY_SAMPLE(a->copy_sample); |
Marek Olšák | e6d191b | 2014-08-20 17:22:41 +0200 | [diff] [blame] | 1621 | |
| 1622 | if (rctx->b.chip_class == R600) |
| 1623 | db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); |
| 1624 | |
| 1625 | if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 || |
| 1626 | rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635) |
| 1627 | db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); |
Marek Olšák | 27b102e | 2015-09-06 17:37:38 +0200 | [diff] [blame] | 1628 | } else if (a->flush_depth_inplace || a->flush_stencil_inplace) { |
| 1629 | db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) | |
| 1630 | S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace); |
Marek Olšák | 428e37c | 2012-10-02 22:02:54 +0200 | [diff] [blame] | 1631 | db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1632 | } |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 1633 | if (a->htile_clear) { |
| 1634 | db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1); |
| 1635 | } |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1636 | |
Marek Olšák | 3d0c4f3 | 2014-04-20 18:11:56 +0200 | [diff] [blame] | 1637 | /* RV770 workaround for a hang with 8x MSAA. */ |
| 1638 | if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) { |
| 1639 | db_render_override |= S_028D10_MAX_TILES_IN_DTT(6); |
| 1640 | } |
| 1641 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1642 | radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1643 | radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ |
| 1644 | radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1645 | radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control); |
Marek Olšák | e280984 | 2012-02-02 14:01:12 +0100 | [diff] [blame] | 1646 | } |
| 1647 | |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 1648 | static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) |
| 1649 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1650 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 1651 | struct r600_config_state *a = (struct r600_config_state*)atom; |
| 1652 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1653 | radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); |
| 1654 | radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2); |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 1655 | } |
| 1656 | |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1657 | static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) |
| 1658 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1659 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1660 | uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1661 | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1662 | while (dirty_mask) { |
| 1663 | struct pipe_vertex_buffer *vb; |
| 1664 | struct r600_resource *rbuffer; |
| 1665 | unsigned offset; |
| 1666 | unsigned buffer_index = u_bit_scan(&dirty_mask); |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1667 | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1668 | vb = &rctx->vertex_buffer_state.vb[buffer_index]; |
| 1669 | rbuffer = (struct r600_resource*)vb->buffer; |
| 1670 | assert(rbuffer); |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1671 | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1672 | offset = vb->buffer_offset; |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1673 | |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1674 | /* fetch resources start at index 320 (OFFSET_FS) */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1675 | radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1676 | radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1677 | radeon_emit(cs, offset); /* RESOURCEi_WORD0 */ |
Marek Olšák | 5c6c5b5 | 2015-09-06 16:40:21 +0200 | [diff] [blame] | 1678 | radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1679 | radeon_emit(cs, /* RESOURCEi_WORD2 */ |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1680 | S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | |
Marek Olšák | 585baac | 2012-07-06 03:18:06 +0200 | [diff] [blame] | 1681 | S_038008_STRIDE(vb->stride)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1682 | radeon_emit(cs, 0); /* RESOURCEi_WORD3 */ |
| 1683 | radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ |
| 1684 | radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ |
| 1685 | radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1686 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1687 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1688 | radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1689 | RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER)); |
Marek Olšák | c76462b | 2012-03-30 23:52:45 +0200 | [diff] [blame] | 1690 | } |
| 1691 | } |
| 1692 | |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1693 | static void r600_emit_constant_buffers(struct r600_context *rctx, |
| 1694 | struct r600_constbuf_state *state, |
| 1695 | unsigned buffer_id_base, |
| 1696 | unsigned reg_alu_constbuf_size, |
| 1697 | unsigned reg_alu_const_cache) |
| 1698 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1699 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1700 | uint32_t dirty_mask = state->dirty_mask; |
| 1701 | |
| 1702 | while (dirty_mask) { |
Marek Olšák | 5073378 | 2012-04-24 19:52:26 +0200 | [diff] [blame] | 1703 | struct pipe_constant_buffer *cb; |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1704 | struct r600_resource *rbuffer; |
| 1705 | unsigned offset; |
| 1706 | unsigned buffer_index = ffs(dirty_mask) - 1; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1707 | unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER); |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1708 | cb = &state->cb[buffer_index]; |
| 1709 | rbuffer = (struct r600_resource*)cb->buffer; |
| 1710 | assert(rbuffer); |
| 1711 | |
| 1712 | offset = cb->buffer_offset; |
| 1713 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1714 | if (!gs_ring_buffer) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1715 | radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, |
Krzysztof Sobiecki | 0d7477a | 2015-12-29 20:27:44 +0100 | [diff] [blame] | 1716 | DIV_ROUND_UP(cb->buffer_size, 256)); |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1717 | radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1718 | } |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1719 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1720 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1721 | radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1722 | RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER)); |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1723 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1724 | radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); |
| 1725 | radeon_emit(cs, (buffer_id_base + buffer_index) * 7); |
| 1726 | radeon_emit(cs, offset); /* RESOURCEi_WORD0 */ |
Marek Olšák | 5c6c5b5 | 2015-09-06 16:40:21 +0200 | [diff] [blame] | 1727 | radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1728 | radeon_emit(cs, /* RESOURCEi_WORD2 */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1729 | S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) | |
| 1730 | S_038008_STRIDE(gs_ring_buffer ? 4 : 16)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1731 | radeon_emit(cs, 0); /* RESOURCEi_WORD3 */ |
| 1732 | radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ |
| 1733 | radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ |
| 1734 | radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1735 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1736 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1737 | radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1738 | RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER)); |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1739 | |
| 1740 | dirty_mask &= ~(1 << buffer_index); |
| 1741 | } |
| 1742 | state->dirty_mask = 0; |
| 1743 | } |
| 1744 | |
Marek Olšák | 0b4c5db | 2012-07-14 18:14:16 +0200 | [diff] [blame] | 1745 | static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1746 | { |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1747 | r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], |
| 1748 | R600_FETCH_CONSTANTS_OFFSET_VS, |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1749 | R_028180_ALU_CONST_BUFFER_SIZE_VS_0, |
| 1750 | R_028980_ALU_CONST_CACHE_VS_0); |
| 1751 | } |
| 1752 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1753 | static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) |
| 1754 | { |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1755 | r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], |
| 1756 | R600_FETCH_CONSTANTS_OFFSET_GS, |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1757 | R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, |
| 1758 | R_0289C0_ALU_CONST_CACHE_GS_0); |
| 1759 | } |
| 1760 | |
Marek Olšák | 0b4c5db | 2012-07-14 18:14:16 +0200 | [diff] [blame] | 1761 | static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1762 | { |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1763 | r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], |
| 1764 | R600_FETCH_CONSTANTS_OFFSET_PS, |
Marek Olšák | 68bbfc1 | 2012-04-01 22:03:15 +0200 | [diff] [blame] | 1765 | R_028140_ALU_CONST_BUFFER_SIZE_PS_0, |
| 1766 | R_028940_ALU_CONST_CACHE_PS_0); |
| 1767 | } |
| 1768 | |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1769 | static void r600_emit_sampler_views(struct r600_context *rctx, |
| 1770 | struct r600_samplerview_state *state, |
| 1771 | unsigned resource_id_base) |
| 1772 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1773 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1774 | uint32_t dirty_mask = state->dirty_mask; |
| 1775 | |
| 1776 | while (dirty_mask) { |
| 1777 | struct r600_pipe_sampler_view *rview; |
| 1778 | unsigned resource_index = u_bit_scan(&dirty_mask); |
| 1779 | unsigned reloc; |
| 1780 | |
| 1781 | rview = state->views[resource_index]; |
| 1782 | assert(rview); |
| 1783 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1784 | radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); |
| 1785 | radeon_emit(cs, (resource_id_base + resource_index) * 7); |
| 1786 | radeon_emit_array(cs, rview->tex_resource_words, 7); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1787 | |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1788 | reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1789 | RADEON_USAGE_READ, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1790 | r600_get_sampler_view_priority(rview->tex_resource)); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1791 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1792 | radeon_emit(cs, reloc); |
| 1793 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 1794 | radeon_emit(cs, reloc); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1795 | } |
| 1796 | state->dirty_mask = 0; |
| 1797 | } |
| 1798 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1799 | |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1800 | static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) |
| 1801 | { |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1802 | r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1803 | } |
| 1804 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1805 | static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) |
| 1806 | { |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1807 | r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS); |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1808 | } |
| 1809 | |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1810 | static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) |
| 1811 | { |
Dave Airlie | 0337a9b | 2015-09-11 03:11:43 +0100 | [diff] [blame] | 1812 | r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS); |
Marek Olšák | 5d8d425 | 2012-07-14 15:26:59 +0200 | [diff] [blame] | 1813 | } |
| 1814 | |
Marek Olšák | 3bffd8a | 2012-09-10 00:34:37 +0200 | [diff] [blame] | 1815 | static void r600_emit_sampler_states(struct r600_context *rctx, |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1816 | struct r600_textures_info *texinfo, |
| 1817 | unsigned resource_id_base, |
| 1818 | unsigned border_color_reg) |
| 1819 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1820 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1821 | uint32_t dirty_mask = texinfo->states.dirty_mask; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1822 | |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1823 | while (dirty_mask) { |
| 1824 | struct r600_pipe_sampler_state *rstate; |
| 1825 | struct r600_pipe_sampler_view *rview; |
| 1826 | unsigned i = u_bit_scan(&dirty_mask); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1827 | |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1828 | rstate = texinfo->states.states[i]; |
| 1829 | assert(rstate); |
| 1830 | rview = texinfo->views.views[i]; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1831 | |
| 1832 | /* TEX_ARRAY_OVERRIDE must be set for array textures to disable |
| 1833 | * filtering between layers. |
| 1834 | * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. |
| 1835 | */ |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1836 | if (rview) { |
| 1837 | enum pipe_texture_target target = rview->base.texture->target; |
| 1838 | if (target == PIPE_TEXTURE_1D_ARRAY || |
| 1839 | target == PIPE_TEXTURE_2D_ARRAY) { |
| 1840 | rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1841 | texinfo->is_array_sampler[i] = true; |
| 1842 | } else { |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1843 | rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1844 | texinfo->is_array_sampler[i] = false; |
| 1845 | } |
| 1846 | } |
| 1847 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1848 | radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0)); |
| 1849 | radeon_emit(cs, (resource_id_base + i) * 3); |
| 1850 | radeon_emit_array(cs, rstate->tex_sampler_words, 3); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1851 | |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1852 | if (rstate->border_color_use) { |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1853 | unsigned offset; |
| 1854 | |
| 1855 | offset = border_color_reg; |
| 1856 | offset += i * 16; |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1857 | radeon_set_config_reg_seq(cs, offset, 4); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1858 | radeon_emit_array(cs, rstate->border_color.ui, 4); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1859 | } |
| 1860 | } |
Marek Olšák | 3fe7859 | 2012-09-10 04:06:20 +0200 | [diff] [blame] | 1861 | texinfo->states.dirty_mask = 0; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1862 | } |
| 1863 | |
Marek Olšák | 3bffd8a | 2012-09-10 00:34:37 +0200 | [diff] [blame] | 1864 | static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1865 | { |
Marek Olšák | f2eac14 | 2012-09-10 04:53:33 +0200 | [diff] [blame] | 1866 | r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1867 | } |
| 1868 | |
Marek Olšák | 263045a | 2012-09-10 05:43:12 +0200 | [diff] [blame] | 1869 | static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) |
| 1870 | { |
| 1871 | r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED); |
| 1872 | } |
| 1873 | |
Marek Olšák | 3bffd8a | 2012-09-10 00:34:37 +0200 | [diff] [blame] | 1874 | static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom) |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1875 | { |
Marek Olšák | f2eac14 | 2012-09-10 04:53:33 +0200 | [diff] [blame] | 1876 | r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1877 | } |
| 1878 | |
| 1879 | static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom) |
| 1880 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1881 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1882 | unsigned tmp; |
| 1883 | |
| 1884 | tmp = S_009508_DISABLE_CUBE_ANISO(1) | |
| 1885 | S_009508_SYNC_GRADIENT(1) | |
| 1886 | S_009508_SYNC_WALKER(1) | |
| 1887 | S_009508_SYNC_ALIGNER(1); |
| 1888 | if (!rctx->seamless_cube_map.enabled) { |
| 1889 | tmp |= S_009508_DISABLE_CUBE_WRAP(1); |
| 1890 | } |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1891 | radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); |
Jerome Glisse | 2df399c | 2012-08-01 15:53:11 -0400 | [diff] [blame] | 1892 | } |
| 1893 | |
Marek Olšák | a01791a | 2012-07-22 07:48:52 +0200 | [diff] [blame] | 1894 | static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) |
| 1895 | { |
| 1896 | struct r600_sample_mask *s = (struct r600_sample_mask*)a; |
| 1897 | uint8_t mask = s->sample_mask; |
| 1898 | |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1899 | radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK, |
Marek Olšák | a01791a | 2012-07-22 07:48:52 +0200 | [diff] [blame] | 1900 | mask | (mask << 8) | (mask << 16) | (mask << 24)); |
| 1901 | } |
| 1902 | |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1903 | static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a) |
| 1904 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1905 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1906 | struct r600_cso_state *state = (struct r600_cso_state*)a; |
Marek Olšák | d225d07 | 2012-12-09 18:51:31 +0100 | [diff] [blame] | 1907 | struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso; |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1908 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1909 | radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 1910 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1911 | radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1912 | RADEON_USAGE_READ, |
| 1913 | RADEON_PRIO_INTERNAL_SHADER)); |
Marek Olšák | a50edc8 | 2012-10-05 04:02:22 +0200 | [diff] [blame] | 1914 | } |
| 1915 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1916 | static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) |
| 1917 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1918 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1919 | struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; |
| 1920 | |
| 1921 | uint32_t v2 = 0, primid = 0; |
| 1922 | |
Dave Airlie | 349df23 | 2015-01-27 13:39:51 +1000 | [diff] [blame] | 1923 | if (rctx->vs_shader->current->shader.vs_as_gs_a) { |
| 1924 | v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A); |
| 1925 | primid = 1; |
| 1926 | } |
| 1927 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1928 | if (state->geom_enable) { |
| 1929 | uint32_t cut_val; |
| 1930 | |
Edward O'Callaghan | b4dee1b | 2015-08-29 18:31:07 +1000 | [diff] [blame] | 1931 | if (rctx->gs_shader->gs_max_out_vertices <= 128) |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1932 | cut_val = V_028A40_GS_CUT_128; |
Edward O'Callaghan | b4dee1b | 2015-08-29 18:31:07 +1000 | [diff] [blame] | 1933 | else if (rctx->gs_shader->gs_max_out_vertices <= 256) |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1934 | cut_val = V_028A40_GS_CUT_256; |
Edward O'Callaghan | b4dee1b | 2015-08-29 18:31:07 +1000 | [diff] [blame] | 1935 | else if (rctx->gs_shader->gs_max_out_vertices <= 512) |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1936 | cut_val = V_028A40_GS_CUT_512; |
| 1937 | else |
| 1938 | cut_val = V_028A40_GS_CUT_1024; |
| 1939 | |
| 1940 | v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) | |
| 1941 | S_028A40_CUT_MODE(cut_val); |
| 1942 | |
| 1943 | if (rctx->gs_shader->current->shader.gs_prim_id_input) |
| 1944 | primid = 1; |
| 1945 | } |
| 1946 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1947 | radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2); |
| 1948 | radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1949 | } |
| 1950 | |
| 1951 | static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) |
| 1952 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1953 | struct radeon_winsys_cs *cs = rctx->b.gfx.cs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1954 | struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; |
| 1955 | struct r600_resource *rbuffer; |
| 1956 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1957 | radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1958 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 1959 | radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); |
| 1960 | |
| 1961 | if (state->enable) { |
| 1962 | rbuffer =(struct r600_resource*)state->esgs_ring.buffer; |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1963 | radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1964 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1965 | radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1966 | RADEON_USAGE_READWRITE, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1967 | RADEON_PRIO_RINGS_STREAMOUT)); |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1968 | radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1969 | state->esgs_ring.buffer_size >> 8); |
| 1970 | |
| 1971 | rbuffer =(struct r600_resource*)state->gsvs_ring.buffer; |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1972 | radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1973 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 1974 | radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, |
Marek Olšák | bee2b96 | 2014-02-20 15:39:35 +0100 | [diff] [blame] | 1975 | RADEON_USAGE_READWRITE, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 1976 | RADEON_PRIO_RINGS_STREAMOUT)); |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1977 | radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1978 | state->gsvs_ring.buffer_size >> 8); |
| 1979 | } else { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1980 | radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); |
| 1981 | radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1982 | } |
| 1983 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 1984 | radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1985 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 1986 | radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); |
| 1987 | } |
| 1988 | |
Vadim Girlin | 4acf71f | 2012-06-11 13:11:47 +0400 | [diff] [blame] | 1989 | /* Adjust GPR allocation on R6xx/R7xx */ |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1990 | bool r600_adjust_gprs(struct r600_context *rctx) |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 1991 | { |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 1992 | unsigned num_gprs[R600_NUM_HW_STAGES]; |
| 1993 | unsigned new_gprs[R600_NUM_HW_STAGES]; |
| 1994 | unsigned cur_gprs[R600_NUM_HW_STAGES]; |
| 1995 | unsigned def_gprs[R600_NUM_HW_STAGES]; |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 1996 | unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs; |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 1997 | unsigned max_gprs; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 1998 | unsigned tmp, tmp2; |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 1999 | unsigned i; |
| 2000 | bool need_recalc = false, use_default = true; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2001 | |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2002 | /* hardware will reserve twice num_clause_temp_gprs */ |
| 2003 | max_gprs = def_num_clause_temp_gprs * 2; |
| 2004 | for (i = 0; i < R600_NUM_HW_STAGES; i++) { |
| 2005 | def_gprs[i] = rctx->default_gprs[i]; |
| 2006 | max_gprs += def_gprs[i]; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2007 | } |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2008 | |
| 2009 | cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); |
| 2010 | cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); |
| 2011 | cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); |
| 2012 | cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); |
| 2013 | |
| 2014 | num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr; |
| 2015 | if (rctx->gs_shader) { |
| 2016 | num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr; |
| 2017 | num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr; |
| 2018 | num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr; |
| 2019 | } else { |
| 2020 | num_gprs[R600_HW_STAGE_ES] = 0; |
| 2021 | num_gprs[R600_HW_STAGE_GS] = 0; |
| 2022 | num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr; |
| 2023 | } |
| 2024 | |
| 2025 | for (i = 0; i < R600_NUM_HW_STAGES; i++) { |
| 2026 | new_gprs[i] = num_gprs[i]; |
| 2027 | if (new_gprs[i] > cur_gprs[i]) |
| 2028 | need_recalc = true; |
| 2029 | if (new_gprs[i] > def_gprs[i]) |
| 2030 | use_default = false; |
| 2031 | } |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2032 | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2033 | /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */ |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2034 | if (!need_recalc) |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2035 | return true; |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2036 | |
| 2037 | /* try to use switch back to default */ |
| 2038 | if (!use_default) { |
| 2039 | /* always privilege vs stage so that at worst we have the |
| 2040 | * pixel stage producing wrong output (not the vertex |
| 2041 | * stage) */ |
| 2042 | new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2; |
| 2043 | for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++) |
| 2044 | new_gprs[R600_HW_STAGE_PS] -= new_gprs[i]; |
| 2045 | } else { |
| 2046 | for (i = 0; i < R600_NUM_HW_STAGES; i++) |
| 2047 | new_gprs[i] = def_gprs[i]; |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2048 | } |
| 2049 | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2050 | /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <= |
| 2051 | * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup |
| 2052 | * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS |
| 2053 | * it will lockup. So in this case just discard the draw command |
| 2054 | * and don't change the current gprs repartitions. |
| 2055 | */ |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2056 | for (i = 0; i < R600_NUM_HW_STAGES; i++) { |
| 2057 | if (num_gprs[i] > new_gprs[i]) { |
| 2058 | R600_ERR("shaders require too many register (%d + %d + %d + %d) " |
| 2059 | "for a combined maximum of %d\n", |
| 2060 | num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs); |
| 2061 | return false; |
| 2062 | } |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2063 | } |
| 2064 | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2065 | /* in some case we endup recomputing the current value */ |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2066 | tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) | |
| 2067 | S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) | |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2068 | S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2069 | |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2070 | tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) | |
| 2071 | S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2072 | if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) { |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 2073 | rctx->config_state.sq_gpr_resource_mgmt_1 = tmp; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2074 | rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 2075 | r600_mark_atom_dirty(rctx, &rctx->config_state.atom); |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2076 | rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; |
Marek Olšák | 87a3413 | 2012-10-06 06:18:24 +0200 | [diff] [blame] | 2077 | } |
Jerome Glisse | 470952f | 2012-10-26 18:59:05 -0400 | [diff] [blame] | 2078 | return true; |
Dave Airlie | 04554c7 | 2011-06-08 14:35:00 +1000 | [diff] [blame] | 2079 | } |
| 2080 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2081 | void r600_init_atom_start_cs(struct r600_context *rctx) |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2082 | { |
| 2083 | int ps_prio; |
| 2084 | int vs_prio; |
| 2085 | int gs_prio; |
| 2086 | int es_prio; |
| 2087 | int num_ps_gprs; |
| 2088 | int num_vs_gprs; |
| 2089 | int num_gs_gprs; |
| 2090 | int num_es_gprs; |
| 2091 | int num_temp_gprs; |
| 2092 | int num_ps_threads; |
| 2093 | int num_vs_threads; |
| 2094 | int num_gs_threads; |
| 2095 | int num_es_threads; |
| 2096 | int num_ps_stack_entries; |
| 2097 | int num_vs_stack_entries; |
| 2098 | int num_gs_stack_entries; |
| 2099 | int num_es_stack_entries; |
| 2100 | enum radeon_family family; |
Marek Olšák | e363dd5 | 2012-03-05 16:20:05 +0100 | [diff] [blame] | 2101 | struct r600_command_buffer *cb = &rctx->start_cs_cmd; |
Marek Olšák | d522021 | 2014-07-31 02:33:12 +0200 | [diff] [blame] | 2102 | uint32_t tmp, i; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2103 | |
Marek Olšák | d8ea646 | 2012-10-05 00:20:27 +0200 | [diff] [blame] | 2104 | r600_init_command_buffer(cb, 256); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2105 | |
| 2106 | /* R6xx requires this packet at the start of each command buffer */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2107 | if (rctx->b.chip_class == R600) { |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2108 | r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); |
| 2109 | r600_store_value(cb, 0); |
| 2110 | } |
| 2111 | /* All asics require this one */ |
| 2112 | r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); |
| 2113 | r600_store_value(cb, 0x80000000); |
| 2114 | r600_store_value(cb, 0x80000000); |
| 2115 | |
Marek Olšák | ae25b93 | 2012-10-07 15:38:32 +0200 | [diff] [blame] | 2116 | /* We're setting config registers here. */ |
| 2117 | r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 2118 | r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); |
| 2119 | |
Marek Olšák | 12fee5b | 2016-04-08 21:10:58 +0200 | [diff] [blame] | 2120 | /* This enables pipeline stat & streamout queries. |
| 2121 | * They are only disabled by blits. |
| 2122 | */ |
| 2123 | r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); |
| 2124 | r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); |
| 2125 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2126 | family = rctx->b.family; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2127 | ps_prio = 0; |
| 2128 | vs_prio = 1; |
| 2129 | gs_prio = 2; |
| 2130 | es_prio = 3; |
| 2131 | switch (family) { |
| 2132 | case CHIP_R600: |
| 2133 | num_ps_gprs = 192; |
| 2134 | num_vs_gprs = 56; |
| 2135 | num_temp_gprs = 4; |
| 2136 | num_gs_gprs = 0; |
| 2137 | num_es_gprs = 0; |
| 2138 | num_ps_threads = 136; |
| 2139 | num_vs_threads = 48; |
| 2140 | num_gs_threads = 4; |
| 2141 | num_es_threads = 4; |
| 2142 | num_ps_stack_entries = 128; |
| 2143 | num_vs_stack_entries = 128; |
| 2144 | num_gs_stack_entries = 0; |
| 2145 | num_es_stack_entries = 0; |
| 2146 | break; |
| 2147 | case CHIP_RV630: |
| 2148 | case CHIP_RV635: |
| 2149 | num_ps_gprs = 84; |
| 2150 | num_vs_gprs = 36; |
| 2151 | num_temp_gprs = 4; |
| 2152 | num_gs_gprs = 0; |
| 2153 | num_es_gprs = 0; |
| 2154 | num_ps_threads = 144; |
| 2155 | num_vs_threads = 40; |
| 2156 | num_gs_threads = 4; |
| 2157 | num_es_threads = 4; |
| 2158 | num_ps_stack_entries = 40; |
| 2159 | num_vs_stack_entries = 40; |
| 2160 | num_gs_stack_entries = 32; |
| 2161 | num_es_stack_entries = 16; |
| 2162 | break; |
| 2163 | case CHIP_RV610: |
| 2164 | case CHIP_RV620: |
| 2165 | case CHIP_RS780: |
| 2166 | case CHIP_RS880: |
| 2167 | default: |
| 2168 | num_ps_gprs = 84; |
| 2169 | num_vs_gprs = 36; |
| 2170 | num_temp_gprs = 4; |
| 2171 | num_gs_gprs = 0; |
| 2172 | num_es_gprs = 0; |
Dave Airlie | 04efcc6 | 2015-02-24 16:30:05 +1000 | [diff] [blame] | 2173 | /* use limits 40 VS and at least 16 ES/GS */ |
| 2174 | num_ps_threads = 120; |
| 2175 | num_vs_threads = 40; |
| 2176 | num_gs_threads = 16; |
| 2177 | num_es_threads = 16; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2178 | num_ps_stack_entries = 40; |
| 2179 | num_vs_stack_entries = 40; |
| 2180 | num_gs_stack_entries = 32; |
| 2181 | num_es_stack_entries = 16; |
| 2182 | break; |
| 2183 | case CHIP_RV670: |
| 2184 | num_ps_gprs = 144; |
| 2185 | num_vs_gprs = 40; |
| 2186 | num_temp_gprs = 4; |
| 2187 | num_gs_gprs = 0; |
| 2188 | num_es_gprs = 0; |
| 2189 | num_ps_threads = 136; |
| 2190 | num_vs_threads = 48; |
| 2191 | num_gs_threads = 4; |
| 2192 | num_es_threads = 4; |
| 2193 | num_ps_stack_entries = 40; |
| 2194 | num_vs_stack_entries = 40; |
| 2195 | num_gs_stack_entries = 32; |
| 2196 | num_es_stack_entries = 16; |
| 2197 | break; |
| 2198 | case CHIP_RV770: |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2199 | num_ps_gprs = 130; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2200 | num_vs_gprs = 56; |
| 2201 | num_temp_gprs = 4; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2202 | num_gs_gprs = 31; |
| 2203 | num_es_gprs = 31; |
| 2204 | num_ps_threads = 180; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2205 | num_vs_threads = 60; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2206 | num_gs_threads = 4; |
| 2207 | num_es_threads = 4; |
| 2208 | num_ps_stack_entries = 128; |
| 2209 | num_vs_stack_entries = 128; |
| 2210 | num_gs_stack_entries = 128; |
| 2211 | num_es_stack_entries = 128; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2212 | break; |
| 2213 | case CHIP_RV730: |
| 2214 | case CHIP_RV740: |
| 2215 | num_ps_gprs = 84; |
| 2216 | num_vs_gprs = 36; |
| 2217 | num_temp_gprs = 4; |
| 2218 | num_gs_gprs = 0; |
| 2219 | num_es_gprs = 0; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2220 | num_ps_threads = 180; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2221 | num_vs_threads = 60; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2222 | num_gs_threads = 4; |
| 2223 | num_es_threads = 4; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2224 | num_ps_stack_entries = 128; |
| 2225 | num_vs_stack_entries = 128; |
| 2226 | num_gs_stack_entries = 0; |
| 2227 | num_es_stack_entries = 0; |
| 2228 | break; |
| 2229 | case CHIP_RV710: |
| 2230 | num_ps_gprs = 192; |
| 2231 | num_vs_gprs = 56; |
| 2232 | num_temp_gprs = 4; |
| 2233 | num_gs_gprs = 0; |
| 2234 | num_es_gprs = 0; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2235 | num_ps_threads = 136; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2236 | num_vs_threads = 48; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2237 | num_gs_threads = 4; |
| 2238 | num_es_threads = 4; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2239 | num_ps_stack_entries = 128; |
| 2240 | num_vs_stack_entries = 128; |
| 2241 | num_gs_stack_entries = 0; |
| 2242 | num_es_stack_entries = 0; |
| 2243 | break; |
| 2244 | } |
| 2245 | |
Dave Airlie | bb2b877 | 2015-11-30 13:15:57 +1000 | [diff] [blame] | 2246 | rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs; |
| 2247 | rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs; |
| 2248 | rctx->default_gprs[R600_HW_STAGE_GS] = 0; |
| 2249 | rctx->default_gprs[R600_HW_STAGE_ES] = 0; |
| 2250 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2251 | rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2252 | |
| 2253 | /* SQ_CONFIG */ |
| 2254 | tmp = 0; |
| 2255 | switch (family) { |
| 2256 | case CHIP_RV610: |
| 2257 | case CHIP_RV620: |
| 2258 | case CHIP_RS780: |
| 2259 | case CHIP_RS880: |
| 2260 | case CHIP_RV710: |
| 2261 | break; |
| 2262 | default: |
| 2263 | tmp |= S_008C00_VC_ENABLE(1); |
| 2264 | break; |
| 2265 | } |
Jerome Glisse | 153105c | 2010-09-30 10:43:26 -0400 | [diff] [blame] | 2266 | tmp |= S_008C00_DX9_CONSTS(0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2267 | tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); |
| 2268 | tmp |= S_008C00_PS_PRIO(ps_prio); |
| 2269 | tmp |= S_008C00_VS_PRIO(vs_prio); |
| 2270 | tmp |= S_008C00_GS_PRIO(gs_prio); |
| 2271 | tmp |= S_008C00_ES_PRIO(es_prio); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2272 | r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2273 | |
| 2274 | /* SQ_GPR_RESOURCE_MGMT_2 */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2275 | tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); |
Mathias Fröhlich | e252944 | 2011-06-08 17:33:57 +0200 | [diff] [blame] | 2276 | tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2277 | r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); |
| 2278 | r600_store_value(cb, tmp); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2279 | |
| 2280 | /* SQ_THREAD_RESOURCE_MGMT */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2281 | tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2282 | tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); |
| 2283 | tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); |
| 2284 | tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2285 | r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2286 | |
| 2287 | /* SQ_STACK_RESOURCE_MGMT_1 */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2288 | tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2289 | tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2290 | r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2291 | |
| 2292 | /* SQ_STACK_RESOURCE_MGMT_2 */ |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2293 | tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2294 | tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2295 | r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2296 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2297 | r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); |
| 2298 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2299 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | ba14d49 | 2014-08-20 23:58:24 +0200 | [diff] [blame] | 2300 | r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2301 | r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); |
| 2302 | r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); |
| 2303 | r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); |
| 2304 | r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2305 | } else { |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2306 | r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); |
| 2307 | r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); |
| 2308 | r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); |
| 2309 | r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2310 | } |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2311 | r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); |
| 2312 | r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ |
| 2313 | r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ |
| 2314 | r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ |
| 2315 | r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ |
| 2316 | r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ |
| 2317 | r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ |
| 2318 | r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ |
| 2319 | r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ |
| 2320 | r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2321 | |
Jerome Glisse | 841c1b5 | 2012-09-07 15:00:20 -0400 | [diff] [blame] | 2322 | /* to avoid GPU doing any preloading of constant from random address */ |
Marek Olšák | d522021 | 2014-07-31 02:33:12 +0200 | [diff] [blame] | 2323 | r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); |
| 2324 | for (i = 0; i < 16; i++) |
| 2325 | r600_store_value(cb, 0); |
| 2326 | |
| 2327 | r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); |
| 2328 | for (i = 0; i < 16; i++) |
| 2329 | r600_store_value(cb, 0); |
| 2330 | |
| 2331 | r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16); |
| 2332 | for (i = 0; i < 16; i++) |
| 2333 | r600_store_value(cb, 0); |
Jerome Glisse | 841c1b5 | 2012-09-07 15:00:20 -0400 | [diff] [blame] | 2334 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2335 | r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); |
| 2336 | r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ |
| 2337 | r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ |
| 2338 | r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ |
| 2339 | r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ |
| 2340 | r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ |
| 2341 | r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ |
| 2342 | r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ |
| 2343 | r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ |
| 2344 | r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ |
| 2345 | r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ |
| 2346 | r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ |
| 2347 | r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ |
| 2348 | r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ |
Marek Olšák | 0569f13 | 2012-01-29 07:21:03 +0100 | [diff] [blame] | 2349 | |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2350 | r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); |
| 2351 | r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); |
| 2352 | r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); |
| 2353 | |
Marek Olšák | f549129 | 2014-03-09 22:12:26 +0100 | [diff] [blame] | 2354 | r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2); |
Marek Olšák | f126253 | 2012-01-31 10:50:51 +0100 | [diff] [blame] | 2355 | r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ |
| 2356 | r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ |
| 2357 | |
| 2358 | r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); |
Marek Olšák | 182fd4c | 2012-02-02 08:27:01 +0100 | [diff] [blame] | 2359 | |
Marek Olšák | 182fd4c | 2012-02-02 08:27:01 +0100 | [diff] [blame] | 2360 | r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2361 | |
Jerome Glisse | 6532eb1 | 2012-10-11 10:40:30 -0400 | [diff] [blame] | 2362 | r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2363 | |
| 2364 | r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); |
| 2365 | r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ |
| 2366 | r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ |
| 2367 | r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ |
| 2368 | |
Alex Deucher | a991411 | 2013-03-19 14:25:32 -0400 | [diff] [blame] | 2369 | r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3); |
| 2370 | r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */ |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2371 | r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ |
| 2372 | r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ |
| 2373 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2374 | r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); |
| 2375 | r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); |
| 2376 | |
Alexandre Demers | 7a37d5c | 2015-02-25 01:50:49 -0500 | [diff] [blame] | 2377 | r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS); |
| 2378 | for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) { |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 2379 | r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ |
Marek Olšák | 93daf5a | 2015-02-20 12:22:00 +0100 | [diff] [blame] | 2380 | r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ |
Dave Airlie | 6d43425 | 2014-01-31 08:06:25 +0000 | [diff] [blame] | 2381 | } |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2382 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2383 | r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); |
Marek Olšák | aacd653 | 2012-02-26 13:17:53 +0100 | [diff] [blame] | 2384 | r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2385 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2386 | if (rctx->b.chip_class >= R700) { |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2387 | r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); |
| 2388 | } |
| 2389 | |
| 2390 | r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); |
| 2391 | r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ |
| 2392 | r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ |
| 2393 | r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ |
| 2394 | r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ |
| 2395 | |
Marek Olšák | c7eaf274 | 2012-03-08 11:15:32 +0100 | [diff] [blame] | 2396 | r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); |
| 2397 | r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ |
| 2398 | r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ |
Marek Olšák | ca78a47 | 2012-02-26 14:05:35 +0100 | [diff] [blame] | 2399 | |
| 2400 | r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); |
| 2401 | r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ |
| 2402 | r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ |
| 2403 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2404 | r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2405 | r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ |
| 2406 | r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2407 | r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */ |
| 2408 | r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */ |
| 2409 | r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */ |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2410 | |
Marek Olšák | 91107a3 | 2012-10-29 13:18:03 +0100 | [diff] [blame] | 2411 | r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0); |
| 2412 | |
| 2413 | r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); |
Marek Olšák | 30bcc55 | 2012-10-05 05:50:30 +0200 | [diff] [blame] | 2414 | r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ |
| 2415 | r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ |
| 2416 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2417 | r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2418 | |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 2419 | if (rctx->b.chip_class == R700) |
| 2420 | r600_store_context_reg(cb, R_028350_SX_MISC, 0); |
Marek Olšák | bba39d8 | 2013-11-28 15:09:35 +0100 | [diff] [blame] | 2421 | if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout) |
Marek Olšák | 6187503 | 2012-02-27 13:55:27 +0100 | [diff] [blame] | 2422 | r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); |
Marek Olšák | 3a3b1bf | 2014-04-20 18:17:51 +0200 | [diff] [blame] | 2423 | |
Marek Olšák | 96ef4dd | 2012-02-27 14:34:52 +0100 | [diff] [blame] | 2424 | r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); |
Marek Olšák | bba39d8 | 2013-11-28 15:09:35 +0100 | [diff] [blame] | 2425 | if (rctx->screen->b.has_streamout) { |
Jerome Glisse | b7b5a77 | 2012-07-23 11:26:24 -0400 | [diff] [blame] | 2426 | r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); |
| 2427 | } |
Marek Olšák | 6187503 | 2012-02-27 13:55:27 +0100 | [diff] [blame] | 2428 | |
Marek Olšák | fbebd43 | 2012-02-03 05:05:31 +0100 | [diff] [blame] | 2429 | r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); |
| 2430 | r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2431 | r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF); |
Jerome Glisse | fd266ec | 2010-09-17 10:41:50 -0400 | [diff] [blame] | 2432 | } |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2433 | |
Marek Olšák | 167263e | 2013-03-01 18:42:52 +0100 | [diff] [blame] | 2434 | void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2435 | { |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 2436 | struct r600_context *rctx = (struct r600_context *)ctx; |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2437 | struct r600_command_buffer *cb = &shader->command_buffer; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2438 | struct r600_shader *rshader = &shader->shader; |
| 2439 | unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2440 | int pos_index = -1, face_index = -1, fixed_pt_position_index = -1; |
Alex Deucher | 46ce257 | 2012-01-17 18:44:47 -0500 | [diff] [blame] | 2441 | unsigned tmp, sid, ufi = 0; |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2442 | int need_linear = 0; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2443 | unsigned z_export = 0, stencil_export = 0, mask_export = 0; |
Marek Olšák | 9a683d1 | 2012-10-05 16:51:41 +0200 | [diff] [blame] | 2444 | unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2445 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2446 | if (!cb->buf) { |
| 2447 | r600_init_command_buffer(cb, 64); |
| 2448 | } else { |
| 2449 | cb->num_dw = 0; |
| 2450 | } |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2451 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2452 | r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2453 | for (i = 0; i < rshader->ninput; i++) { |
| 2454 | if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) |
| 2455 | pos_index = i; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2456 | if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1) |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2457 | face_index = i; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2458 | if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) |
| 2459 | fixed_pt_position_index = i; |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2460 | |
| 2461 | sid = rshader->input[i].spi_sid; |
| 2462 | |
| 2463 | tmp = S_028644_SEMANTIC(sid); |
| 2464 | |
Axel Davy | 7e05e4c | 2016-03-19 19:55:24 +0100 | [diff] [blame] | 2465 | /* D3D 9 behaviour. GL is undefined */ |
| 2466 | if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0) |
| 2467 | tmp |= S_028644_DEFAULT_VAL(3); |
| 2468 | |
Vadim Girlin | 1a9d2b7 | 2012-01-24 23:32:50 +0400 | [diff] [blame] | 2469 | if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || |
| 2470 | rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || |
| 2471 | (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && |
| 2472 | rctx->rasterizer && rctx->rasterizer->flatshade)) |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2473 | tmp |= S_028644_FLAT_SHADE(1); |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2474 | |
| 2475 | if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && |
Marek Olšák | 9a683d1 | 2012-10-05 16:51:41 +0200 | [diff] [blame] | 2476 | sprite_coord_enable & (1 << rshader->input[i].sid)) { |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2477 | tmp |= S_028644_PT_SPRITE_TEX(1); |
| 2478 | } |
| 2479 | |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2480 | if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2481 | tmp |= S_028644_SEL_CENTROID(1); |
| 2482 | |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2483 | if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE) |
| 2484 | tmp |= S_028644_SEL_SAMPLE(1); |
| 2485 | |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2486 | if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { |
| 2487 | need_linear = 1; |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2488 | tmp |= S_028644_SEL_LINEAR(1); |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2489 | } |
Vadim Girlin | e532c71 | 2011-11-04 21:24:03 +0400 | [diff] [blame] | 2490 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2491 | r600_store_value(cb, tmp); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2492 | } |
| 2493 | |
Jerome Glisse | 974b482 | 2013-02-08 16:02:32 -0500 | [diff] [blame] | 2494 | db_shader_control = 0; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2495 | for (i = 0; i < rshader->noutput; i++) { |
| 2496 | if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2497 | z_export = 1; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2498 | if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2499 | stencil_export = 1; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2500 | if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK && |
| 2501 | rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) |
| 2502 | mask_export = 1; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2503 | } |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2504 | db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); |
| 2505 | db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export); |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2506 | db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2507 | if (rshader->uses_kill) |
| 2508 | db_shader_control |= S_02880C_KILL_ENABLE(1); |
| 2509 | |
| 2510 | exports_ps = 0; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2511 | for (i = 0; i < rshader->noutput; i++) { |
| 2512 | if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2513 | rshader->output[i].name == TGSI_SEMANTIC_STENCIL || |
| 2514 | rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) { |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2515 | exports_ps |= 1; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2516 | } |
| 2517 | } |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2518 | num_cout = rshader->nr_ps_color_exports; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2519 | exports_ps |= S_028854_EXPORT_COLORS(num_cout); |
| 2520 | if (!exports_ps) { |
| 2521 | /* always at least export 1 component per pixel */ |
| 2522 | exports_ps = 2; |
| 2523 | } |
| 2524 | |
Marek Olšák | 4fe7441 | 2012-07-07 09:01:38 +0200 | [diff] [blame] | 2525 | shader->nr_ps_color_outputs = num_cout; |
Dave Airlie | d1cc87c | 2012-03-24 13:37:16 +0000 | [diff] [blame] | 2526 | |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2527 | spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | |
Dave Airlie | 1fc001e | 2012-01-18 19:33:21 +1000 | [diff] [blame] | 2528 | S_0286CC_PERSP_GRADIENT_ENA(1)| |
| 2529 | S_0286CC_LINEAR_GRADIENT_ENA(need_linear); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2530 | spi_input_z = 0; |
| 2531 | if (pos_index != -1) { |
| 2532 | spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2533 | S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) | |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2534 | S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2535 | S_0286CC_BARYC_SAMPLE_CNTL(1)) | |
| 2536 | S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE); |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2537 | spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1); |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2538 | } |
| 2539 | |
| 2540 | spi_ps_in_control_1 = 0; |
| 2541 | if (face_index != -1) { |
| 2542 | spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | |
| 2543 | S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); |
| 2544 | } |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2545 | if (fixed_pt_position_index != -1) { |
| 2546 | spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) | |
| 2547 | S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr); |
| 2548 | } |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2549 | |
Alex Deucher | 46ce257 | 2012-01-17 18:44:47 -0500 | [diff] [blame] | 2550 | /* HW bug in original R600 */ |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2551 | if (rctx->b.family == CHIP_R600) |
Alex Deucher | 46ce257 | 2012-01-17 18:44:47 -0500 | [diff] [blame] | 2552 | ufi = 1; |
| 2553 | |
Marek Olšák | 65cbf89 | 2013-03-02 17:14:51 +0100 | [diff] [blame] | 2554 | r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2); |
| 2555 | r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */ |
| 2556 | r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */ |
| 2557 | |
| 2558 | r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z); |
| 2559 | |
| 2560 | r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2); |
| 2561 | r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/ |
| 2562 | S_028850_NUM_GPRS(rshader->bc.ngpr) | |
| 2563 | S_028850_STACK_SIZE(rshader->bc.nstack) | |
| 2564 | S_028850_UNCACHED_FIRST_INST(ufi)); |
| 2565 | r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */ |
| 2566 | |
| 2567 | r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0); |
| 2568 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
| 2569 | |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2570 | /* only set some bits here, the other bits are set in the dsa state */ |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2571 | shader->db_shader_control = db_shader_control; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 2572 | shader->ps_depth_export = z_export | stencil_export | mask_export; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2573 | |
Marek Olšák | 9a683d1 | 2012-10-05 16:51:41 +0200 | [diff] [blame] | 2574 | shader->sprite_coord_enable = sprite_coord_enable; |
Vadim Girlin | 1a9d2b7 | 2012-01-24 23:32:50 +0400 | [diff] [blame] | 2575 | if (rctx->rasterizer) |
| 2576 | shader->flatshade = rctx->rasterizer->flatshade; |
Henri Verbeet | f262ba2 | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2577 | } |
| 2578 | |
Marek Olšák | 167263e | 2013-03-01 18:42:52 +0100 | [diff] [blame] | 2579 | void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2580 | { |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2581 | struct r600_command_buffer *cb = &shader->command_buffer; |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2582 | struct r600_shader *rshader = &shader->shader; |
Vadim Girlin | 5b27b63 | 2011-11-05 08:48:02 +0400 | [diff] [blame] | 2583 | unsigned spi_vs_out_id[10] = {}; |
| 2584 | unsigned i, tmp, nparams = 0; |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2585 | |
Vadim Girlin | 5b27b63 | 2011-11-05 08:48:02 +0400 | [diff] [blame] | 2586 | for (i = 0; i < rshader->noutput; i++) { |
| 2587 | if (rshader->output[i].spi_sid) { |
| 2588 | tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); |
| 2589 | spi_vs_out_id[nparams / 4] |= tmp; |
| 2590 | nparams++; |
| 2591 | } |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2592 | } |
Vadim Girlin | 5b27b63 | 2011-11-05 08:48:02 +0400 | [diff] [blame] | 2593 | |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2594 | r600_init_command_buffer(cb, 32); |
| 2595 | |
| 2596 | r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10); |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2597 | for (i = 0; i < 10; i++) { |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2598 | r600_store_value(cb, spi_vs_out_id[i]); |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2599 | } |
| 2600 | |
Alex Deucher | dc1c0ca | 2011-07-29 11:29:53 -0400 | [diff] [blame] | 2601 | /* Certain attributes (position, psize, etc.) don't count as params. |
| 2602 | * VS is required to export at least one param and r600_shader_from_tgsi() |
| 2603 | * takes care of adding a dummy export. |
| 2604 | */ |
Alex Deucher | dc1c0ca | 2011-07-29 11:29:53 -0400 | [diff] [blame] | 2605 | if (nparams < 1) |
| 2606 | nparams = 1; |
| 2607 | |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2608 | r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG, |
| 2609 | S_0286C4_VS_EXPORT_COUNT(nparams - 1)); |
| 2610 | r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS, |
| 2611 | S_028868_NUM_GPRS(rshader->bc.ngpr) | |
| 2612 | S_028868_STACK_SIZE(rshader->bc.nstack)); |
Christoph Bumiller | b206f59 | 2014-05-17 01:20:20 +0200 | [diff] [blame] | 2613 | if (rshader->vs_position_window_space) { |
| 2614 | r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, |
| 2615 | S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1)); |
| 2616 | } else { |
| 2617 | r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, |
| 2618 | S_028818_VTX_W0_FMT(1) | |
| 2619 | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | |
| 2620 | S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | |
| 2621 | S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); |
| 2622 | |
| 2623 | } |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 2624 | r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0); |
| 2625 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2626 | |
Marek Olšák | 97acf2c | 2012-01-29 06:31:47 +0100 | [diff] [blame] | 2627 | shader->pa_cl_vs_out_cntl = |
| 2628 | S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | |
| 2629 | S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | |
| 2630 | S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | |
Marek Olšák | e5741f1 | 2014-04-19 17:21:57 +0200 | [diff] [blame] | 2631 | S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) | |
| 2632 | S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) | |
| 2633 | S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) | |
| 2634 | S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport); |
Henri Verbeet | c0ca43e | 2011-03-14 22:07:44 +0100 | [diff] [blame] | 2635 | } |
| 2636 | |
Dave Airlie | 8168dfd | 2015-02-18 23:51:19 +0000 | [diff] [blame] | 2637 | #define RV610_GSVS_ALIGN 32 |
| 2638 | #define R600_GSVS_ALIGN 16 |
| 2639 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2640 | void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
| 2641 | { |
| 2642 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 2643 | struct r600_command_buffer *cb = &shader->command_buffer; |
| 2644 | struct r600_shader *rshader = &shader->shader; |
| 2645 | struct r600_shader *cp_shader = &shader->gs_copy_shader->shader; |
| 2646 | unsigned gsvs_itemsize = |
Glenn Kennard | 3bfa345 | 2015-07-09 16:37:28 +1000 | [diff] [blame] | 2647 | (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2; |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2648 | |
Dave Airlie | 8168dfd | 2015-02-18 23:51:19 +0000 | [diff] [blame] | 2649 | /* some r600s needs gsvs itemsize aligned to cacheline size |
| 2650 | this was fixed in rs780 and above. */ |
| 2651 | switch (rctx->b.family) { |
| 2652 | case CHIP_RV610: |
| 2653 | gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN); |
| 2654 | break; |
| 2655 | case CHIP_R600: |
| 2656 | case CHIP_RV630: |
| 2657 | case CHIP_RV670: |
| 2658 | case CHIP_RV620: |
| 2659 | case CHIP_RV635: |
| 2660 | gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN); |
| 2661 | break; |
| 2662 | default: |
| 2663 | break; |
| 2664 | } |
| 2665 | |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2666 | r600_init_command_buffer(cb, 64); |
| 2667 | |
| 2668 | /* VGT_GS_MODE is written by r600_emit_shader_stages */ |
| 2669 | r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1); |
| 2670 | |
| 2671 | if (rctx->b.chip_class >= R700) { |
| 2672 | r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, |
Edward O'Callaghan | b4dee1b | 2015-08-29 18:31:07 +1000 | [diff] [blame] | 2673 | S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices)); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2674 | } |
| 2675 | r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE, |
Edward O'Callaghan | b4dee1b | 2015-08-29 18:31:07 +1000 | [diff] [blame] | 2676 | r600_conv_prim_to_gs_out(shader->selector->gs_output_prim)); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2677 | |
Dave Airlie | 7f21cf7 | 2014-12-10 13:48:29 +1000 | [diff] [blame] | 2678 | r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, |
Glenn Kennard | 3bfa345 | 2015-07-09 16:37:28 +1000 | [diff] [blame] | 2679 | cp_shader->ring_item_sizes[0] >> 2); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2680 | |
| 2681 | r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, |
Glenn Kennard | 3bfa345 | 2015-07-09 16:37:28 +1000 | [diff] [blame] | 2682 | (rshader->ring_item_sizes[0]) >> 2); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2683 | |
| 2684 | r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE, |
| 2685 | gsvs_itemsize); |
| 2686 | |
| 2687 | /* FIXME calculate these values somehow ??? */ |
| 2688 | r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2); |
| 2689 | r600_store_value(cb, 0x80); /* GS_PER_ES */ |
| 2690 | r600_store_value(cb, 0x100); /* ES_PER_GS */ |
| 2691 | r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1); |
| 2692 | r600_store_value(cb, 0x2); /* GS_PER_VS */ |
| 2693 | |
| 2694 | r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS, |
| 2695 | S_02887C_NUM_GPRS(rshader->bc.ngpr) | |
| 2696 | S_02887C_STACK_SIZE(rshader->bc.nstack)); |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 2697 | r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2698 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
| 2699 | } |
| 2700 | |
| 2701 | void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) |
| 2702 | { |
| 2703 | struct r600_command_buffer *cb = &shader->command_buffer; |
| 2704 | struct r600_shader *rshader = &shader->shader; |
| 2705 | |
| 2706 | r600_init_command_buffer(cb, 32); |
| 2707 | |
| 2708 | r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES, |
| 2709 | S_028890_NUM_GPRS(rshader->bc.ngpr) | |
| 2710 | S_028890_STACK_SIZE(rshader->bc.nstack)); |
Marek Olšák | 43b5c34 | 2014-08-06 21:45:41 +0200 | [diff] [blame] | 2711 | r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 2712 | /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ |
| 2713 | } |
| 2714 | |
| 2715 | |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2716 | void *r600_create_resolve_blend(struct r600_context *rctx) |
| 2717 | { |
| 2718 | struct pipe_blend_state blend; |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 2719 | unsigned i; |
| 2720 | |
| 2721 | memset(&blend, 0, sizeof(blend)); |
| 2722 | blend.independent_blend_enable = true; |
| 2723 | for (i = 0; i < 2; i++) { |
| 2724 | blend.rt[i].colormask = 0xf; |
| 2725 | blend.rt[i].blend_enable = 1; |
| 2726 | blend.rt[i].rgb_func = PIPE_BLEND_ADD; |
| 2727 | blend.rt[i].alpha_func = PIPE_BLEND_ADD; |
| 2728 | blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO; |
| 2729 | blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO; |
| 2730 | blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO; |
| 2731 | blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO; |
| 2732 | } |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2733 | return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX); |
Marek Olšák | 7835401 | 2012-08-26 22:38:35 +0200 | [diff] [blame] | 2734 | } |
| 2735 | |
| 2736 | void *r700_create_resolve_blend(struct r600_context *rctx) |
| 2737 | { |
| 2738 | struct pipe_blend_state blend; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2739 | |
| 2740 | memset(&blend, 0, sizeof(blend)); |
| 2741 | blend.independent_blend_enable = true; |
| 2742 | blend.rt[0].colormask = 0xf; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2743 | return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2744 | } |
| 2745 | |
| 2746 | void *r600_create_decompress_blend(struct r600_context *rctx) |
| 2747 | { |
| 2748 | struct pipe_blend_state blend; |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2749 | |
| 2750 | memset(&blend, 0, sizeof(blend)); |
| 2751 | blend.independent_blend_enable = true; |
| 2752 | blend.rt[0].colormask = 0xf; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2753 | return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES); |
Marek Olšák | 8698a3b | 2012-08-02 22:31:22 +0200 | [diff] [blame] | 2754 | } |
| 2755 | |
Marek Olšák | e4340c1 | 2012-01-29 23:25:42 +0100 | [diff] [blame] | 2756 | void *r600_create_db_flush_dsa(struct r600_context *rctx) |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2757 | { |
| 2758 | struct pipe_depth_stencil_alpha_state dsa; |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2759 | boolean quirk = false; |
| 2760 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2761 | if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 || |
| 2762 | rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635) |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2763 | quirk = true; |
| 2764 | |
| 2765 | memset(&dsa, 0, sizeof(dsa)); |
| 2766 | |
| 2767 | if (quirk) { |
| 2768 | dsa.depth.enabled = 1; |
| 2769 | dsa.depth.func = PIPE_FUNC_LEQUAL; |
| 2770 | dsa.stencil[0].enabled = 1; |
| 2771 | dsa.stencil[0].func = PIPE_FUNC_ALWAYS; |
| 2772 | dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; |
| 2773 | dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; |
| 2774 | dsa.stencil[0].writemask = 0xff; |
| 2775 | } |
| 2776 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 2777 | return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa); |
Dave Airlie | 084c29b | 2010-10-01 10:13:04 +1000 | [diff] [blame] | 2778 | } |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2779 | |
Marek Olšák | c5584e9 | 2012-10-06 06:05:32 +0200 | [diff] [blame] | 2780 | void r600_update_db_shader_control(struct r600_context * rctx) |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2781 | { |
Grigori Goronzy | 3de7e11 | 2013-10-11 01:23:20 +0200 | [diff] [blame] | 2782 | bool dual_export; |
| 2783 | unsigned db_shader_control; |
Glenn Kennard | 3f45d29 | 2015-10-17 16:53:28 +0200 | [diff] [blame] | 2784 | uint8_t ps_conservative_z; |
Marek Olšák | c8b06dc | 2012-09-18 19:42:29 +0200 | [diff] [blame] | 2785 | |
Grigori Goronzy | 3de7e11 | 2013-10-11 01:23:20 +0200 | [diff] [blame] | 2786 | if (!rctx->ps_shader) { |
| 2787 | return; |
| 2788 | } |
| 2789 | |
| 2790 | dual_export = rctx->framebuffer.export_16bpc && |
| 2791 | !rctx->ps_shader->current->ps_depth_export; |
| 2792 | |
| 2793 | db_shader_control = rctx->ps_shader->current->db_shader_control | |
| 2794 | S_02880C_DUAL_EXPORT_ENABLE(dual_export); |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2795 | |
Glenn Kennard | 3f45d29 | 2015-10-17 16:53:28 +0200 | [diff] [blame] | 2796 | ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z; |
| 2797 | |
Jerome Glisse | 974b482 | 2013-02-08 16:02:32 -0500 | [diff] [blame] | 2798 | /* When alpha test is enabled we can't trust the hw to make the proper |
| 2799 | * decision on the order in which ztest should be run related to fragment |
| 2800 | * shader execution. |
| 2801 | * |
| 2802 | * If alpha test is enabled perform z test after fragment. RE_Z (early |
| 2803 | * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx |
| 2804 | */ |
| 2805 | if (rctx->alphatest_state.sx_alpha_test_control) { |
| 2806 | db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); |
| 2807 | } else { |
| 2808 | db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); |
| 2809 | } |
| 2810 | |
Glenn Kennard | 3f45d29 | 2015-10-17 16:53:28 +0200 | [diff] [blame] | 2811 | if (db_shader_control != rctx->db_misc_state.db_shader_control || |
| 2812 | ps_conservative_z != rctx->db_misc_state.ps_conservative_z) { |
Marek Olšák | c5584e9 | 2012-10-06 06:05:32 +0200 | [diff] [blame] | 2813 | rctx->db_misc_state.db_shader_control = db_shader_control; |
Glenn Kennard | 3f45d29 | 2015-10-17 16:53:28 +0200 | [diff] [blame] | 2814 | rctx->db_misc_state.ps_conservative_z = ps_conservative_z; |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 2815 | r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); |
Jerome Glisse | b75f1d9 | 2012-06-26 12:24:08 -0400 | [diff] [blame] | 2816 | } |
| 2817 | } |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2818 | |
Ilia Mirkin | a2a1a58 | 2015-07-20 19:58:43 -0400 | [diff] [blame] | 2819 | static inline unsigned r600_array_mode(unsigned mode) |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2820 | { |
| 2821 | switch (mode) { |
Marek Olšák | 92f6af2 | 2016-04-22 23:39:23 +0200 | [diff] [blame] | 2822 | default: |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2823 | case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED; |
| 2824 | break; |
| 2825 | case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1; |
| 2826 | break; |
| 2827 | case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2828 | } |
| 2829 | } |
| 2830 | |
| 2831 | static boolean r600_dma_copy_tile(struct r600_context *rctx, |
| 2832 | struct pipe_resource *dst, |
| 2833 | unsigned dst_level, |
| 2834 | unsigned dst_x, |
| 2835 | unsigned dst_y, |
| 2836 | unsigned dst_z, |
| 2837 | struct pipe_resource *src, |
| 2838 | unsigned src_level, |
| 2839 | unsigned src_x, |
| 2840 | unsigned src_y, |
| 2841 | unsigned src_z, |
| 2842 | unsigned copy_height, |
| 2843 | unsigned pitch, |
| 2844 | unsigned bpp) |
| 2845 | { |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 2846 | struct radeon_winsys_cs *cs = rctx->b.dma.cs; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2847 | struct r600_texture *rsrc = (struct r600_texture*)src; |
| 2848 | struct r600_texture *rdst = (struct r600_texture*)dst; |
| 2849 | unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; |
| 2850 | unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode; |
Jerome Glisse | e1598cb | 2013-01-28 19:07:10 -0500 | [diff] [blame] | 2851 | uint64_t base, addr; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2852 | |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2853 | dst_mode = rdst->surface.level[dst_level].mode; |
| 2854 | src_mode = rsrc->surface.level[src_level].mode; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2855 | assert(dst_mode != src_mode); |
| 2856 | |
| 2857 | y = 0; |
| 2858 | lbpp = util_logbase2(bpp); |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2859 | pitch_tile_max = ((pitch / bpp) / 8) - 1; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2860 | |
Marek Olšák | 92f6af2 | 2016-04-22 23:39:23 +0200 | [diff] [blame] | 2861 | if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2862 | /* T2L */ |
| 2863 | array_mode = r600_array_mode(src_mode); |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2864 | slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); |
Jerome Glisse | 681707a | 2013-02-06 13:54:02 -0500 | [diff] [blame] | 2865 | slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2866 | /* linear height must be the same as the slice tile max height, it's ok even |
| 2867 | * if the linear destination/source have smaller heigh as the size of the |
| 2868 | * dma packet will be using the copy_height which is always smaller or equal |
| 2869 | * to the linear height |
| 2870 | */ |
| 2871 | height = rsrc->surface.level[src_level].npix_y; |
| 2872 | detile = 1; |
| 2873 | x = src_x; |
| 2874 | y = src_y; |
| 2875 | z = src_z; |
| 2876 | base = rsrc->surface.level[src_level].offset; |
| 2877 | addr = rdst->surface.level[dst_level].offset; |
| 2878 | addr += rdst->surface.level[dst_level].slice_size * dst_z; |
| 2879 | addr += dst_y * pitch + dst_x * bpp; |
| 2880 | } else { |
| 2881 | /* L2T */ |
| 2882 | array_mode = r600_array_mode(dst_mode); |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2883 | slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8); |
Jerome Glisse | 681707a | 2013-02-06 13:54:02 -0500 | [diff] [blame] | 2884 | slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2885 | /* linear height must be the same as the slice tile max height, it's ok even |
| 2886 | * if the linear destination/source have smaller heigh as the size of the |
| 2887 | * dma packet will be using the copy_height which is always smaller or equal |
| 2888 | * to the linear height |
| 2889 | */ |
| 2890 | height = rdst->surface.level[dst_level].npix_y; |
| 2891 | detile = 0; |
| 2892 | x = dst_x; |
| 2893 | y = dst_y; |
| 2894 | z = dst_z; |
| 2895 | base = rdst->surface.level[dst_level].offset; |
| 2896 | addr = rsrc->surface.level[src_level].offset; |
| 2897 | addr += rsrc->surface.level[src_level].slice_size * src_z; |
| 2898 | addr += src_y * pitch + src_x * bpp; |
| 2899 | } |
| 2900 | /* check that we are in dw/base alignment constraint */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2901 | if (addr % 4 || base % 256) { |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2902 | return FALSE; |
| 2903 | } |
| 2904 | |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2905 | /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number |
| 2906 | * line in the blit. Compute max 8 line we can copy in the size limit |
| 2907 | */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2908 | cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8; |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2909 | ncopy = (copy_height / cheight) + !!(copy_height % cheight); |
Marek Olšák | bb74152 | 2016-04-28 16:32:39 +0200 | [diff] [blame] | 2910 | r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource); |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2911 | |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2912 | for (i = 0; i < ncopy; i++) { |
Jerome Glisse | 323a448 | 2013-02-06 15:03:17 -0500 | [diff] [blame] | 2913 | cheight = cheight > copy_height ? copy_height : cheight; |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2914 | size = (cheight * pitch) / 4; |
Zoë Blade | 05e7f7f | 2015-04-22 11:33:17 +0100 | [diff] [blame] | 2915 | /* emit reloc before writing cs so that cs is always in consistent state */ |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 2916 | radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 2917 | RADEON_PRIO_SDMA_TEXTURE); |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 2918 | radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 2919 | RADEON_PRIO_SDMA_TEXTURE); |
Nicolai Hähnle | c232735 | 2016-05-06 16:42:03 -0500 | [diff] [blame] | 2920 | radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size)); |
| 2921 | radeon_emit(cs, base >> 8); |
| 2922 | radeon_emit(cs, (detile << 31) | (array_mode << 27) | |
| 2923 | (lbpp << 24) | ((height - 1) << 10) | |
| 2924 | pitch_tile_max); |
| 2925 | radeon_emit(cs, (slice_tile_max << 12) | (z << 0)); |
| 2926 | radeon_emit(cs, (x << 3) | (y << 17)); |
| 2927 | radeon_emit(cs, addr & 0xfffffffc); |
| 2928 | radeon_emit(cs, (addr >> 32UL) & 0xff); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2929 | copy_height -= cheight; |
| 2930 | addr += cheight * pitch; |
| 2931 | y += cheight; |
| 2932 | } |
Marek Olšák | a512da3 | 2016-04-26 19:29:55 +0200 | [diff] [blame] | 2933 | r600_dma_emit_wait_idle(&rctx->b); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2934 | return TRUE; |
| 2935 | } |
| 2936 | |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 2937 | static void r600_dma_copy(struct pipe_context *ctx, |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2938 | struct pipe_resource *dst, |
| 2939 | unsigned dst_level, |
| 2940 | unsigned dstx, unsigned dsty, unsigned dstz, |
| 2941 | struct pipe_resource *src, |
| 2942 | unsigned src_level, |
| 2943 | const struct pipe_box *src_box) |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2944 | { |
| 2945 | struct r600_context *rctx = (struct r600_context *)ctx; |
| 2946 | struct r600_texture *rsrc = (struct r600_texture*)src; |
| 2947 | struct r600_texture *rdst = (struct r600_texture*)dst; |
| 2948 | unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height; |
| 2949 | unsigned src_w, dst_w; |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 2950 | unsigned src_x, src_y; |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2951 | unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2952 | |
Marek Olšák | 6cc8f6c | 2015-11-07 14:00:30 +0100 | [diff] [blame] | 2953 | if (rctx->b.dma.cs == NULL) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2954 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2955 | } |
Marek Olšák | 171e484 | 2013-11-27 12:43:40 +0100 | [diff] [blame] | 2956 | |
| 2957 | if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2958 | if (dst_x % 4 || src_box->x % 4 || src_box->width % 4) |
| 2959 | goto fallback; |
| 2960 | |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 2961 | r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width); |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2962 | return; |
Marek Olšák | 171e484 | 2013-11-27 12:43:40 +0100 | [diff] [blame] | 2963 | } |
| 2964 | |
Marek Olšák | 2f173b8 | 2016-04-21 23:46:19 +0200 | [diff] [blame] | 2965 | if (src_box->depth > 1 || |
| 2966 | !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty, |
| 2967 | dstz, rsrc, src_level, src_box)) |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2968 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2969 | |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 2970 | src_x = util_format_get_nblocksx(src->format, src_box->x); |
| 2971 | dst_x = util_format_get_nblocksx(src->format, dst_x); |
| 2972 | src_y = util_format_get_nblocksy(src->format, src_box->y); |
| 2973 | dst_y = util_format_get_nblocksy(src->format, dst_y); |
| 2974 | |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2975 | bpp = rdst->surface.bpe; |
| 2976 | dst_pitch = rdst->surface.level[dst_level].pitch_bytes; |
| 2977 | src_pitch = rsrc->surface.level[src_level].pitch_bytes; |
| 2978 | src_w = rsrc->surface.level[src_level].npix_x; |
| 2979 | dst_w = rdst->surface.level[dst_level].npix_x; |
| 2980 | copy_height = src_box->height / rsrc->surface.blk_h; |
| 2981 | |
| 2982 | dst_mode = rdst->surface.level[dst_level].mode; |
| 2983 | src_mode = rsrc->surface.level[src_level].mode; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2984 | |
| 2985 | if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2986 | /* strict requirement on r6xx/r7xx */ |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2987 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2988 | } |
| 2989 | /* lot of constraint on alignment this should capture them all */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 2990 | if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 2991 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2992 | } |
| 2993 | |
| 2994 | if (src_mode == dst_mode) { |
Jerome Glisse | e1598cb | 2013-01-28 19:07:10 -0500 | [diff] [blame] | 2995 | uint64_t dst_offset, src_offset, size; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 2996 | |
| 2997 | /* simple dma blit would do NOTE code here assume : |
| 2998 | * src_box.x/y == 0 |
| 2999 | * dst_x/y == 0 |
| 3000 | * dst_pitch == src_pitch |
| 3001 | */ |
| 3002 | src_offset= rsrc->surface.level[src_level].offset; |
| 3003 | src_offset += rsrc->surface.level[src_level].slice_size * src_box->z; |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 3004 | src_offset += src_y * src_pitch + src_x * bpp; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 3005 | dst_offset = rdst->surface.level[dst_level].offset; |
| 3006 | dst_offset += rdst->surface.level[dst_level].slice_size * dst_z; |
| 3007 | dst_offset += dst_y * dst_pitch + dst_x * bpp; |
| 3008 | size = src_box->height * src_pitch; |
| 3009 | /* must be dw aligned */ |
Marek Olšák | 6c487ff | 2014-03-17 01:18:43 +0100 | [diff] [blame] | 3010 | if (dst_offset % 4 || src_offset % 4 || size % 4) { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 3011 | goto fallback; |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 3012 | } |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 3013 | r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 3014 | } else { |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 3015 | if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z, |
Christoph Bumiller | 9974593 | 2013-07-05 20:55:36 +0200 | [diff] [blame] | 3016 | src, src_level, src_x, src_y, src_box->z, |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 3017 | copy_height, dst_pitch, bpp)) { |
| 3018 | goto fallback; |
| 3019 | } |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 3020 | } |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 3021 | return; |
| 3022 | |
| 3023 | fallback: |
Marek Olšák | d13d2fd | 2014-09-06 17:07:50 +0200 | [diff] [blame] | 3024 | r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, |
Marek Olšák | 4ca3486 | 2014-03-08 15:15:41 +0100 | [diff] [blame] | 3025 | src, src_level, src_box); |
Jerome Glisse | 325422c | 2013-01-07 17:45:59 -0500 | [diff] [blame] | 3026 | } |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3027 | |
| 3028 | void r600_init_state_functions(struct r600_context *rctx) |
| 3029 | { |
Grazvydas Ignotas | 6ef4572 | 2015-09-03 01:54:30 +0300 | [diff] [blame] | 3030 | unsigned id = 1; |
Dave Airlie | 19799a5 | 2015-11-30 13:27:22 +1000 | [diff] [blame] | 3031 | unsigned i; |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3032 | /* !!! |
| 3033 | * To avoid GPU lockup registers must be emited in a specific order |
| 3034 | * (no kidding ...). The order below is important and have been |
| 3035 | * partialy infered from analyzing fglrx command stream. |
| 3036 | * |
| 3037 | * Don't reorder atom without carefully checking the effect (GPU lockup |
| 3038 | * or piglit regression). |
| 3039 | * !!! |
| 3040 | */ |
| 3041 | |
| 3042 | r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0); |
| 3043 | |
| 3044 | /* shader const */ |
| 3045 | r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0); |
| 3046 | r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0); |
| 3047 | r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0); |
| 3048 | |
| 3049 | /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change |
| 3050 | * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map) |
| 3051 | */ |
| 3052 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0); |
| 3053 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0); |
| 3054 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0); |
| 3055 | /* resource */ |
| 3056 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0); |
| 3057 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0); |
| 3058 | r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0); |
| 3059 | r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0); |
| 3060 | |
Glenn Kennard | d80701d | 2015-02-24 15:59:16 +0100 | [diff] [blame] | 3061 | r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3062 | |
| 3063 | r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3); |
| 3064 | r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3); |
| 3065 | rctx->sample_mask.sample_mask = ~0; |
| 3066 | |
| 3067 | r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6); |
| 3068 | r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6); |
| 3069 | r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0); |
| 3070 | r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7); |
| 3071 | r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6); |
| 3072 | r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26); |
| 3073 | r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7); |
| 3074 | r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11); |
| 3075 | r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); |
Axel Davy | 400e8d8 | 2016-06-14 22:22:50 +0200 | [diff] [blame^] | 3076 | r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3077 | r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); |
Marek Olšák | 686b018 | 2016-04-10 04:56:46 +0200 | [diff] [blame] | 3078 | r600_add_atom(rctx, &rctx->b.scissors.atom, id++); |
| 3079 | r600_add_atom(rctx, &rctx->b.viewports.atom, id++); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3080 | r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3); |
| 3081 | r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3082 | r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5); |
Marek Olšák | 12596cf | 2015-11-07 15:39:39 +0100 | [diff] [blame] | 3083 | r600_add_atom(rctx, &rctx->b.render_cond_atom, id++); |
Grazvydas Ignotas | 85adde3 | 2015-08-10 00:42:33 +0300 | [diff] [blame] | 3084 | r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++); |
| 3085 | r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++); |
Dave Airlie | 19799a5 | 2015-11-30 13:27:22 +1000 | [diff] [blame] | 3086 | for (i = 0; i < R600_NUM_HW_STAGES; i++) |
| 3087 | r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0); |
Dave Airlie | 79ea0f4 | 2014-01-30 04:19:57 +0000 | [diff] [blame] | 3088 | r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0); |
| 3089 | r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0); |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3090 | |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 3091 | rctx->b.b.create_blend_state = r600_create_blend_state; |
| 3092 | rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state; |
| 3093 | rctx->b.b.create_rasterizer_state = r600_create_rs_state; |
| 3094 | rctx->b.b.create_sampler_state = r600_create_sampler_state; |
| 3095 | rctx->b.b.create_sampler_view = r600_create_sampler_view; |
| 3096 | rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state; |
| 3097 | rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple; |
Glenn Kennard | a327fa3 | 2014-09-10 11:54:40 +0200 | [diff] [blame] | 3098 | rctx->b.b.set_min_samples = r600_set_min_samples; |
Marek Olšák | d5b23df | 2013-08-13 21:49:59 +0200 | [diff] [blame] | 3099 | rctx->b.b.get_sample_position = r600_get_sample_position; |
Marek Olšák | 54690a5 | 2014-03-17 01:19:51 +0100 | [diff] [blame] | 3100 | rctx->b.dma_copy = r600_dma_copy; |
Marek Olšák | 63042af | 2013-02-28 17:27:36 +0100 | [diff] [blame] | 3101 | } |
| 3102 | /* this function must be last */ |