Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 1 | /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 23 | * SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Rob Clark <robclark@freedesktop.org> |
| 27 | */ |
| 28 | |
| 29 | |
| 30 | #include "pipe/p_defines.h" |
| 31 | #include "pipe/p_screen.h" |
| 32 | #include "pipe/p_state.h" |
| 33 | |
| 34 | #include "util/u_memory.h" |
| 35 | #include "util/u_inlines.h" |
| 36 | #include "util/u_format.h" |
| 37 | #include "util/u_format_s3tc.h" |
| 38 | #include "util/u_string.h" |
Rob Clark | 634fb83 | 2013-03-25 14:57:24 -0400 | [diff] [blame] | 39 | #include "util/u_debug.h" |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 40 | |
| 41 | #include "os/os_time.h" |
| 42 | |
| 43 | #include <stdio.h> |
| 44 | #include <errno.h> |
| 45 | #include <stdlib.h> |
| 46 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 47 | #include "freedreno_screen.h" |
| 48 | #include "freedreno_resource.h" |
| 49 | #include "freedreno_fence.h" |
Rob Clark | 646c16a | 2014-01-07 21:39:13 -0500 | [diff] [blame] | 50 | #include "freedreno_query.h" |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 51 | #include "freedreno_util.h" |
| 52 | |
Emil Velikov | 458d03a | 2014-07-28 19:45:09 +0100 | [diff] [blame] | 53 | #include "a2xx/fd2_screen.h" |
| 54 | #include "a3xx/fd3_screen.h" |
Rob Clark | 61c68b6 | 2014-07-31 15:42:55 -0400 | [diff] [blame] | 55 | #include "a4xx/fd4_screen.h" |
Rob Clark | 18c317b | 2013-05-26 17:13:27 -0400 | [diff] [blame] | 56 | |
Rob Clark | 784086f | 2016-03-28 10:28:29 -0400 | [diff] [blame] | 57 | #include "ir3/ir3_nir.h" |
| 58 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 59 | /* XXX this should go away */ |
| 60 | #include "state_tracker/drm_driver.h" |
| 61 | |
Rob Clark | 634fb83 | 2013-03-25 14:57:24 -0400 | [diff] [blame] | 62 | static const struct debug_named_value debug_options[] = { |
| 63 | {"msgs", FD_DBG_MSGS, "Print debug messages"}, |
| 64 | {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"}, |
Rob Clark | 9495ee1 | 2013-04-24 10:50:51 -0400 | [diff] [blame] | 65 | {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"}, |
Rob Clark | ef7a563 | 2015-10-15 16:28:17 -0400 | [diff] [blame] | 66 | {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"}, |
Rob Clark | 3319354 | 2014-10-22 13:27:35 -0400 | [diff] [blame] | 67 | {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"}, |
Rob Clark | 1a42d4e | 2013-09-06 18:21:25 -0400 | [diff] [blame] | 68 | {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"}, |
Rob Clark | 3319354 | 2014-10-22 13:27:35 -0400 | [diff] [blame] | 69 | {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"}, |
Rob Clark | a53fe22 | 2013-10-31 09:59:49 -0400 | [diff] [blame] | 70 | {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"}, |
Rob Clark | 1b88607 | 2014-02-03 11:28:30 -0500 | [diff] [blame] | 71 | {"nobin", FD_DBG_NOBIN, "Disable hw binning"}, |
Rob Clark | 62cc003 | 2015-03-18 09:51:27 -0400 | [diff] [blame] | 72 | {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"}, |
Timothy Arceri | 1de93f9 | 2015-06-23 07:53:24 +1000 | [diff] [blame] | 73 | {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"}, |
Rob Clark | 65b2ae5 | 2015-07-05 18:23:25 -0400 | [diff] [blame] | 74 | {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"}, |
Rob Clark | ef7a563 | 2015-10-15 16:28:17 -0400 | [diff] [blame] | 75 | {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, |
Rob Clark | 6bf462a | 2016-04-11 17:55:37 -0400 | [diff] [blame] | 76 | {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"}, |
Rob Clark | 784086f | 2016-03-28 10:28:29 -0400 | [diff] [blame] | 77 | {"nir", FD_DBG_NIR, "Prefer NIR as native IR"}, |
Rob Clark | 9f219c7 | 2016-06-27 09:44:15 -0400 | [diff] [blame] | 78 | {"reorder", FD_DBG_REORDER,"Enable reordering for draws/blits"}, |
Rob Clark | dcde4cd | 2016-06-28 07:53:34 -0400 | [diff] [blame] | 79 | {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"}, |
Rob Clark | 634fb83 | 2013-03-25 14:57:24 -0400 | [diff] [blame] | 80 | DEBUG_NAMED_VALUE_END |
| 81 | }; |
| 82 | |
| 83 | DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0) |
| 84 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 85 | int fd_mesa_debug = 0; |
Rob Clark | 1b88607 | 2014-02-03 11:28:30 -0500 | [diff] [blame] | 86 | bool fd_binning_enabled = true; |
Rob Clark | fd17db6 | 2015-03-08 13:38:51 -0400 | [diff] [blame] | 87 | static bool glsl120 = false; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 88 | |
| 89 | static const char * |
| 90 | fd_screen_get_name(struct pipe_screen *pscreen) |
| 91 | { |
| 92 | static char buffer[128]; |
| 93 | util_snprintf(buffer, sizeof(buffer), "FD%03d", |
| 94 | fd_screen(pscreen)->device_id); |
| 95 | return buffer; |
| 96 | } |
| 97 | |
| 98 | static const char * |
| 99 | fd_screen_get_vendor(struct pipe_screen *pscreen) |
| 100 | { |
| 101 | return "freedreno"; |
| 102 | } |
| 103 | |
Giuseppe Bilotta | 76039b3 | 2015-03-22 07:21:01 +0100 | [diff] [blame] | 104 | static const char * |
| 105 | fd_screen_get_device_vendor(struct pipe_screen *pscreen) |
| 106 | { |
| 107 | return "Qualcomm"; |
| 108 | } |
| 109 | |
| 110 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 111 | static uint64_t |
| 112 | fd_screen_get_timestamp(struct pipe_screen *pscreen) |
| 113 | { |
Rob Clark | b888d8e | 2016-02-23 12:03:43 -0500 | [diff] [blame] | 114 | struct fd_screen *screen = fd_screen(pscreen); |
| 115 | |
| 116 | if (screen->has_timestamp) { |
| 117 | uint64_t n; |
| 118 | fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n); |
| 119 | debug_assert(screen->max_freq > 0); |
| 120 | return n * 1000000000 / screen->max_freq; |
| 121 | } else { |
| 122 | int64_t cpu_time = os_time_get() * 1000; |
| 123 | return cpu_time + screen->cpu_gpu_time_delta; |
| 124 | } |
| 125 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static void |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 129 | fd_screen_destroy(struct pipe_screen *pscreen) |
| 130 | { |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 131 | struct fd_screen *screen = fd_screen(pscreen); |
| 132 | |
| 133 | if (screen->pipe) |
| 134 | fd_pipe_del(screen->pipe); |
| 135 | |
| 136 | if (screen->dev) |
| 137 | fd_device_del(screen->dev); |
| 138 | |
Rob Clark | 9f219c7 | 2016-06-27 09:44:15 -0400 | [diff] [blame] | 139 | fd_bc_fini(&screen->batch_cache); |
| 140 | |
Nicolai Hähnle | 0334ba1 | 2016-09-27 19:06:13 +0200 | [diff] [blame] | 141 | slab_destroy_parent(&screen->transfer_pool); |
| 142 | |
Rob Clark | e684c32 | 2016-07-19 18:24:57 -0400 | [diff] [blame] | 143 | pipe_mutex_destroy(screen->lock); |
| 144 | |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 145 | free(screen); |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | /* |
Rob Clark | 18c317b | 2013-05-26 17:13:27 -0400 | [diff] [blame] | 149 | TODO either move caps to a2xx/a3xx specific code, or maybe have some |
| 150 | tables for things that differ if the delta is not too much.. |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 151 | */ |
| 152 | static int |
| 153 | fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) |
| 154 | { |
Rob Clark | f999c13 | 2014-05-11 14:15:32 -0400 | [diff] [blame] | 155 | struct fd_screen *screen = fd_screen(pscreen); |
| 156 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 157 | /* this is probably not totally correct.. but it's a start: */ |
| 158 | switch (param) { |
| 159 | /* Supported features (boolean caps). */ |
| 160 | case PIPE_CAP_NPOT_TEXTURES: |
Ilia Mirkin | 12d39b4 | 2013-10-04 04:32:15 -0400 | [diff] [blame] | 161 | case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 162 | case PIPE_CAP_TWO_SIDED_STENCIL: |
| 163 | case PIPE_CAP_ANISOTROPIC_FILTER: |
| 164 | case PIPE_CAP_POINT_SPRITE: |
| 165 | case PIPE_CAP_TEXTURE_SHADOW_MAP: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 166 | case PIPE_CAP_BLEND_EQUATION_SEPARATE: |
| 167 | case PIPE_CAP_TEXTURE_SWIZZLE: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 168 | case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: |
| 169 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: |
Ilia Mirkin | f0ca267 | 2014-10-03 16:23:19 -0400 | [diff] [blame] | 170 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 171 | case PIPE_CAP_SEAMLESS_CUBE_MAP: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 172 | case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: |
| 173 | case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 174 | case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: |
| 175 | case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: |
| 176 | case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: |
Rob Clark | 2868639 | 2014-05-24 10:07:13 -0400 | [diff] [blame] | 177 | case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: |
Ilia Mirkin | f6b2e8a | 2014-10-01 23:13:22 -0400 | [diff] [blame] | 178 | case PIPE_CAP_VERTEXID_NOBASE: |
Rob Clark | bc1a373 | 2015-08-10 12:11:13 -0400 | [diff] [blame] | 179 | case PIPE_CAP_STRING_MARKER: |
Ilia Mirkin | 9515d65 | 2016-08-20 22:40:33 -0400 | [diff] [blame] | 180 | case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 181 | return 1; |
Rob Clark | 980f1cf | 2013-03-25 11:55:18 -0400 | [diff] [blame] | 182 | |
Rob Clark | da39ac9 | 2016-06-22 14:45:25 -0400 | [diff] [blame] | 183 | case PIPE_CAP_USER_CONSTANT_BUFFERS: |
Rob Clark | 591eeb7 | 2016-07-29 14:58:39 -0400 | [diff] [blame] | 184 | return is_a4xx(screen) ? 0 : 1; |
Rob Clark | da39ac9 | 2016-06-22 14:45:25 -0400 | [diff] [blame] | 185 | |
Rob Clark | 8d27be2 | 2014-01-14 13:03:20 -0500 | [diff] [blame] | 186 | case PIPE_CAP_SHADER_STENCIL_EXPORT: |
Christoph Bumiller | 8acaf86 | 2013-03-15 22:11:31 +0100 | [diff] [blame] | 187 | case PIPE_CAP_TGSI_TEXCOORD: |
Rob Clark | 980f1cf | 2013-03-25 11:55:18 -0400 | [diff] [blame] | 188 | case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: |
Rob Clark | 2868639 | 2014-05-24 10:07:13 -0400 | [diff] [blame] | 189 | case PIPE_CAP_TEXTURE_MULTISAMPLE: |
| 190 | case PIPE_CAP_TEXTURE_BARRIER: |
Rob Clark | 5c72672 | 2014-09-26 10:35:52 -0400 | [diff] [blame] | 191 | case PIPE_CAP_TEXTURE_MIRROR_CLAMP: |
Ilia Mirkin | be00852 | 2014-10-02 03:39:05 -0400 | [diff] [blame] | 192 | case PIPE_CAP_COMPUTE: |
Marek Olšák | d2e4c9e | 2016-02-01 21:56:50 +0100 | [diff] [blame] | 193 | case PIPE_CAP_QUERY_MEMORY_INFO: |
Marek Olšák | dcb2b77 | 2016-02-29 20:22:37 +0100 | [diff] [blame] | 194 | case PIPE_CAP_PCI_GROUP: |
| 195 | case PIPE_CAP_PCI_BUS: |
| 196 | case PIPE_CAP_PCI_DEVICE: |
| 197 | case PIPE_CAP_PCI_FUNCTION: |
Christoph Bumiller | 8acaf86 | 2013-03-15 22:11:31 +0100 | [diff] [blame] | 198 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 199 | |
Ilia Mirkin | e6acf3a | 2014-09-27 10:50:40 -0400 | [diff] [blame] | 200 | case PIPE_CAP_SM3: |
Rob Clark | 720cfb6 | 2014-09-09 11:20:40 -0400 | [diff] [blame] | 201 | case PIPE_CAP_PRIMITIVE_RESTART: |
Rob Clark | 283bb48 | 2014-12-21 11:38:34 -0500 | [diff] [blame] | 202 | case PIPE_CAP_TGSI_INSTANCEID: |
Ilia Mirkin | 92fc8f0 | 2014-12-02 00:32:57 -0500 | [diff] [blame] | 203 | case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: |
Rob Clark | f72fead | 2015-08-10 20:41:45 -0400 | [diff] [blame] | 204 | case PIPE_CAP_INDEP_BLEND_ENABLE: |
| 205 | case PIPE_CAP_INDEP_BLEND_FUNC: |
Rob Clark | 500025a | 2015-08-11 16:47:16 -0400 | [diff] [blame] | 206 | case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: |
Ilia Mirkin | d19a98e | 2015-08-14 10:49:46 -0400 | [diff] [blame] | 207 | case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: |
Ilia Mirkin | d69e557 | 2015-11-07 23:20:31 -0500 | [diff] [blame] | 208 | case PIPE_CAP_CONDITIONAL_RENDER: |
| 209 | case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: |
Ilia Mirkin | 4607b2b | 2015-11-08 00:28:34 -0500 | [diff] [blame] | 210 | case PIPE_CAP_FAKE_SW_MSAA: |
Ilia Mirkin | b17a405 | 2015-11-19 00:06:46 -0500 | [diff] [blame] | 211 | case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: |
Ilia Mirkin | a05e549 | 2015-11-19 00:32:39 -0500 | [diff] [blame] | 212 | case PIPE_CAP_DEPTH_CLIP_DISABLE: |
| 213 | case PIPE_CAP_CLIP_HALFZ: |
Rob Clark | daccbd2 | 2014-12-21 11:52:44 -0500 | [diff] [blame] | 214 | return is_a3xx(screen) || is_a4xx(screen); |
Ilia Mirkin | f6b2e8a | 2014-10-01 23:13:22 -0400 | [diff] [blame] | 215 | |
Nicolai Hähnle | 3abb548 | 2016-01-26 10:26:30 -0500 | [diff] [blame] | 216 | case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: |
| 217 | return 0; |
Rob Clark | 500025a | 2015-08-11 16:47:16 -0400 | [diff] [blame] | 218 | case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: |
Ilia Mirkin | 99f12a3 | 2015-11-21 10:02:05 -0500 | [diff] [blame] | 219 | if (is_a3xx(screen)) return 16; |
| 220 | if (is_a4xx(screen)) return 32; |
| 221 | return 0; |
Rob Clark | 500025a | 2015-08-11 16:47:16 -0400 | [diff] [blame] | 222 | case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: |
Ilia Mirkin | c65bc2e | 2015-11-21 10:28:45 -0500 | [diff] [blame] | 223 | /* We could possibly emulate more by pretending 2d/rect textures and |
| 224 | * splitting high bits of index into 2nd dimension.. |
Rob Clark | 500025a | 2015-08-11 16:47:16 -0400 | [diff] [blame] | 225 | */ |
Ilia Mirkin | 9c409c8 | 2015-09-17 01:43:36 -0400 | [diff] [blame] | 226 | if (is_a3xx(screen)) return 8192; |
Ilia Mirkin | c65bc2e | 2015-11-21 10:28:45 -0500 | [diff] [blame] | 227 | if (is_a4xx(screen)) return 16384; |
Ilia Mirkin | 9c409c8 | 2015-09-17 01:43:36 -0400 | [diff] [blame] | 228 | return 0; |
Rob Clark | 500025a | 2015-08-11 16:47:16 -0400 | [diff] [blame] | 229 | |
Ilia Mirkin | d19a98e | 2015-08-14 10:49:46 -0400 | [diff] [blame] | 230 | case PIPE_CAP_TEXTURE_FLOAT_LINEAR: |
Ilia Mirkin | b4ace13 | 2015-08-03 02:13:33 -0400 | [diff] [blame] | 231 | case PIPE_CAP_CUBE_MAP_ARRAY: |
Ilia Mirkin | 801b55c | 2015-11-20 22:55:28 -0500 | [diff] [blame] | 232 | case PIPE_CAP_START_INSTANCE: |
Ilia Mirkin | f10bb0a | 2015-11-21 21:24:48 -0500 | [diff] [blame] | 233 | case PIPE_CAP_SAMPLER_VIEW_TARGET: |
Ilia Mirkin | 190acb3 | 2015-11-22 16:47:25 -0500 | [diff] [blame] | 234 | case PIPE_CAP_TEXTURE_QUERY_LOD: |
Ilia Mirkin | d19a98e | 2015-08-14 10:49:46 -0400 | [diff] [blame] | 235 | return is_a4xx(screen); |
| 236 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 237 | case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: |
Rob Clark | da39ac9 | 2016-06-22 14:45:25 -0400 | [diff] [blame] | 238 | return 64; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 239 | |
| 240 | case PIPE_CAP_GLSL_FEATURE_LEVEL: |
Rob Clark | fd17db6 | 2015-03-08 13:38:51 -0400 | [diff] [blame] | 241 | if (glsl120) |
| 242 | return 120; |
Ilia Mirkin | 4607b2b | 2015-11-08 00:28:34 -0500 | [diff] [blame] | 243 | return is_ir3(screen) ? 140 : 120; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 244 | |
| 245 | /* Unsupported features. */ |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 246 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: |
Ilia Mirkin | f0ca267 | 2014-10-03 16:23:19 -0400 | [diff] [blame] | 247 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 248 | case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 249 | case PIPE_CAP_USER_VERTEX_BUFFERS: |
| 250 | case PIPE_CAP_USER_INDEX_BUFFERS: |
Christoph Bumiller | f35e96d | 2013-03-29 13:02:49 +0100 | [diff] [blame] | 251 | case PIPE_CAP_QUERY_PIPELINE_STATISTICS: |
Christoph Bumiller | 729abfd | 2013-04-12 13:42:01 +0200 | [diff] [blame] | 252 | case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: |
Ilia Mirkin | 32b7124 | 2014-07-03 11:15:18 -0400 | [diff] [blame] | 253 | case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: |
Dave Airlie | 2fcbec4 | 2013-09-21 18:45:43 +1000 | [diff] [blame] | 254 | case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: |
| 255 | case PIPE_CAP_TEXTURE_GATHER_SM5: |
Ilia Mirkin | d95df4f | 2014-04-26 23:44:57 -0400 | [diff] [blame] | 256 | case PIPE_CAP_SAMPLE_SHADING: |
| 257 | case PIPE_CAP_TEXTURE_GATHER_OFFSETS: |
Christoph Bumiller | 4b586a2 | 2014-05-17 01:20:19 +0200 | [diff] [blame] | 258 | case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: |
Christoph Bumiller | bc198f8 | 2013-04-05 14:29:36 +0200 | [diff] [blame] | 259 | case PIPE_CAP_DRAW_INDIRECT: |
Ilia Mirkin | d67b9ba | 2015-12-31 13:30:13 -0500 | [diff] [blame] | 260 | case PIPE_CAP_MULTI_DRAW_INDIRECT: |
| 261 | case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: |
Ilia Mirkin | 8ee74ce | 2014-08-14 00:04:41 -0400 | [diff] [blame] | 262 | case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: |
Ilia Mirkin | 7c211a1 | 2015-02-01 09:01:50 -0500 | [diff] [blame] | 263 | case PIPE_CAP_POLYGON_OFFSET_CLAMP: |
Axel Davy | eb1c12d | 2015-01-17 14:30:17 +0100 | [diff] [blame] | 264 | case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: |
Ilia Mirkin | 069dab7 | 2015-02-18 22:36:13 -0500 | [diff] [blame] | 265 | case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: |
Marek Olšák | 79ffc08a | 2015-04-29 15:44:55 +0200 | [diff] [blame] | 266 | case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: |
Marek Olšák | 2622293 | 2015-06-12 14:24:17 +0200 | [diff] [blame] | 267 | case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: |
Marek Olšák | 3b7800e | 2015-08-10 02:11:48 +0200 | [diff] [blame] | 268 | case PIPE_CAP_DEPTH_BOUNDS_TEST: |
Ilia Mirkin | f46a53f | 2015-09-11 17:29:49 -0400 | [diff] [blame] | 269 | case PIPE_CAP_TGSI_TXQS: |
Rob Clark | e04db87 | 2016-04-25 09:07:04 -0400 | [diff] [blame] | 270 | /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */ |
Marek Olšák | f3b37e3 | 2015-09-27 19:32:07 +0200 | [diff] [blame] | 271 | case PIPE_CAP_FORCE_PERSAMPLE_INTERP: |
Marek Olšák | ce9db16 | 2015-08-24 01:19:35 +0200 | [diff] [blame] | 272 | case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: |
Ilia Mirkin | 3695b25 | 2015-11-09 13:27:07 -0500 | [diff] [blame] | 273 | case PIPE_CAP_CLEAR_TEXTURE: |
Ilia Mirkin | 87b4e4e | 2015-12-29 16:49:32 -0500 | [diff] [blame] | 274 | case PIPE_CAP_DRAW_PARAMETERS: |
Ilia Mirkin | e9f43d6 | 2016-01-02 18:55:48 -0500 | [diff] [blame] | 275 | case PIPE_CAP_TGSI_PACK_HALF_FLOAT: |
Marek Olšák | 34738a9 | 2016-01-02 20:45:00 +0100 | [diff] [blame] | 276 | case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: |
| 277 | case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: |
Ilia Mirkin | ebfb544 | 2016-01-02 21:56:45 -0500 | [diff] [blame] | 278 | case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: |
Nicolai Hähnle | 654670b | 2016-01-11 17:38:08 -0500 | [diff] [blame] | 279 | case PIPE_CAP_INVALIDATE_BUFFER: |
Charmaine Lee | 3038e89 | 2016-01-14 10:22:17 -0700 | [diff] [blame] | 280 | case PIPE_CAP_GENERATE_MIPMAP: |
Nicolai Hähnle | 6af6d7b | 2016-01-26 10:27:58 -0500 | [diff] [blame] | 281 | case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: |
Edward O'Callaghan | 4bc9130 | 2016-02-17 20:59:52 +1100 | [diff] [blame] | 282 | case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: |
Bas Nieuwenhuizen | 70dcd84 | 2016-04-12 15:00:31 +0200 | [diff] [blame] | 283 | case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: |
Tobias Klausmann | 2be258e | 2016-05-08 22:44:07 +0200 | [diff] [blame] | 284 | case PIPE_CAP_CULL_DISTANCE: |
Kenneth Graunke | 70048eb | 2016-05-20 21:05:34 -0700 | [diff] [blame] | 285 | case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: |
Ilia Mirkin | edfa7a4 | 2016-05-29 11:39:52 -0400 | [diff] [blame] | 286 | case PIPE_CAP_TGSI_VOTE: |
Ilia Mirkin | 07fcb06 | 2016-06-11 15:26:45 -0400 | [diff] [blame] | 287 | case PIPE_CAP_MAX_WINDOW_RECTANGLES: |
Axel Davy | 59a6929 | 2016-06-13 22:28:32 +0200 | [diff] [blame] | 288 | case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: |
JĂłzef Kucia | 3cd28fe | 2016-07-19 13:07:24 +0200 | [diff] [blame] | 289 | case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: |
Nicolai Hähnle | 700a571 | 2016-10-07 09:42:55 +0200 | [diff] [blame] | 290 | case PIPE_CAP_TGSI_ARRAY_COMPONENTS: |
Nicolai Hähnle | 611166b | 2016-11-18 20:49:54 +0100 | [diff] [blame] | 291 | case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 292 | return 0; |
| 293 | |
Rob Clark | 546d6c8 | 2014-09-26 15:40:35 -0400 | [diff] [blame] | 294 | case PIPE_CAP_MAX_VIEWPORTS: |
| 295 | return 1; |
| 296 | |
Rob Clark | c4ae047 | 2016-03-01 17:51:36 -0500 | [diff] [blame] | 297 | case PIPE_CAP_SHAREABLE_SHADERS: |
Rob Clark | e04db87 | 2016-04-25 09:07:04 -0400 | [diff] [blame] | 298 | /* manage the variants for these ourself, to avoid breaking precompile: */ |
| 299 | case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: |
| 300 | case PIPE_CAP_VERTEX_COLOR_CLAMPED: |
Rob Clark | c4ae047 | 2016-03-01 17:51:36 -0500 | [diff] [blame] | 301 | if (is_ir3(screen)) |
| 302 | return 1; |
| 303 | return 0; |
| 304 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 305 | /* Stream output. */ |
| 306 | case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: |
Rob Clark | f72fead | 2015-08-10 20:41:45 -0400 | [diff] [blame] | 307 | if (is_ir3(screen)) |
Rob Clark | 98a4b11 | 2015-07-25 12:53:23 -0400 | [diff] [blame] | 308 | return PIPE_MAX_SO_BUFFERS; |
| 309 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 310 | case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: |
Ilia Mirkin | 3fdeb7c | 2016-10-14 00:03:12 -0400 | [diff] [blame] | 311 | case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: |
Rob Clark | f72fead | 2015-08-10 20:41:45 -0400 | [diff] [blame] | 312 | if (is_ir3(screen)) |
Rob Clark | 98a4b11 | 2015-07-25 12:53:23 -0400 | [diff] [blame] | 313 | return 1; |
| 314 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 315 | case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: |
| 316 | case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: |
Rob Clark | f72fead | 2015-08-10 20:41:45 -0400 | [diff] [blame] | 317 | if (is_ir3(screen)) |
Rob Clark | c7deea5 | 2015-07-31 10:54:23 -0400 | [diff] [blame] | 318 | return 16 * 4; /* should only be shader out limit? */ |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 319 | return 0; |
| 320 | |
Grigori Goronzy | d34d5fd | 2014-02-09 22:56:20 +0100 | [diff] [blame] | 321 | /* Geometry shader output, unsupported. */ |
| 322 | case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: |
| 323 | case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: |
Ilia Mirkin | 746e526 | 2014-06-26 20:01:50 -0400 | [diff] [blame] | 324 | case PIPE_CAP_MAX_VERTEX_STREAMS: |
Grigori Goronzy | d34d5fd | 2014-02-09 22:56:20 +0100 | [diff] [blame] | 325 | return 0; |
| 326 | |
Timothy Arceri | 89e6806 | 2014-08-19 21:09:58 -1000 | [diff] [blame] | 327 | case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: |
| 328 | return 2048; |
| 329 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 330 | /* Texturing. */ |
| 331 | case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 332 | case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: |
Rob Clark | cb9e07a | 2013-08-31 09:14:27 -0400 | [diff] [blame] | 333 | return MAX_MIP_LEVELS; |
Rob Clark | 49b8fb9 | 2014-09-13 16:14:17 -0400 | [diff] [blame] | 334 | case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: |
| 335 | return 11; |
| 336 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 337 | case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: |
Rob Clark | f24e910 | 2014-12-12 18:51:36 -0500 | [diff] [blame] | 338 | return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 339 | |
| 340 | /* Render targets. */ |
| 341 | case PIPE_CAP_MAX_RENDER_TARGETS: |
Ilia Mirkin | 6f4c197 | 2015-04-01 01:14:39 -0400 | [diff] [blame] | 342 | return screen->max_rts; |
Ilia Mirkin | ee6b95c | 2015-09-13 19:50:45 -0400 | [diff] [blame] | 343 | case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: |
| 344 | return is_a3xx(screen) ? 1 : 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 345 | |
Rob Clark | f999c13 | 2014-05-11 14:15:32 -0400 | [diff] [blame] | 346 | /* Queries. */ |
Ilia Mirkin | f9e6f46 | 2016-01-09 23:30:16 -0500 | [diff] [blame] | 347 | case PIPE_CAP_QUERY_BUFFER_OBJECT: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 348 | return 0; |
Rob Clark | f999c13 | 2014-05-11 14:15:32 -0400 | [diff] [blame] | 349 | case PIPE_CAP_OCCLUSION_QUERY: |
Rob Clark | f24e910 | 2014-12-12 18:51:36 -0500 | [diff] [blame] | 350 | return is_a3xx(screen) || is_a4xx(screen); |
Rob Clark | 9253dcd | 2016-02-14 11:14:06 -0500 | [diff] [blame] | 351 | case PIPE_CAP_QUERY_TIMESTAMP: |
Rob Clark | 37d540b | 2016-02-10 14:40:24 -0500 | [diff] [blame] | 352 | case PIPE_CAP_QUERY_TIME_ELAPSED: |
| 353 | /* only a4xx, requires new enough kernel so we know max_freq: */ |
| 354 | return (screen->max_freq > 0) && is_a4xx(screen); |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 355 | |
Ilia Mirkin | c2f9ad5 | 2014-04-09 14:58:53 -0400 | [diff] [blame] | 356 | case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 357 | case PIPE_CAP_MIN_TEXEL_OFFSET: |
| 358 | return -8; |
| 359 | |
Ilia Mirkin | c2f9ad5 | 2014-04-09 14:58:53 -0400 | [diff] [blame] | 360 | case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 361 | case PIPE_CAP_MAX_TEXEL_OFFSET: |
| 362 | return 7; |
| 363 | |
Tom Stellard | 4e90bc9 | 2013-07-09 21:21:39 -0700 | [diff] [blame] | 364 | case PIPE_CAP_ENDIANNESS: |
| 365 | return PIPE_ENDIAN_LITTLE; |
| 366 | |
Rob Clark | f999c13 | 2014-05-11 14:15:32 -0400 | [diff] [blame] | 367 | case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: |
Ian Romanick | 25c14f4 | 2014-01-22 14:02:42 -0800 | [diff] [blame] | 368 | return 64; |
| 369 | |
Emil Velikov | e9c43b1 | 2014-08-14 19:42:39 +0100 | [diff] [blame] | 370 | case PIPE_CAP_VENDOR_ID: |
| 371 | return 0x5143; |
| 372 | case PIPE_CAP_DEVICE_ID: |
| 373 | return 0xFFFFFFFF; |
| 374 | case PIPE_CAP_ACCELERATED: |
| 375 | return 1; |
| 376 | case PIPE_CAP_VIDEO_MEMORY: |
| 377 | DBG("FINISHME: The value returned is incorrect\n"); |
| 378 | return 10; |
| 379 | case PIPE_CAP_UMA: |
| 380 | return 1; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 381 | } |
Rob Clark | f725994 | 2014-09-26 17:56:08 -0400 | [diff] [blame] | 382 | debug_printf("unknown param %d\n", param); |
| 383 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | static float |
| 387 | fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) |
| 388 | { |
| 389 | switch (param) { |
| 390 | case PIPE_CAPF_MAX_LINE_WIDTH: |
| 391 | case PIPE_CAPF_MAX_LINE_WIDTH_AA: |
Rob Clark | a7eb12d | 2016-04-11 17:46:08 -0400 | [diff] [blame] | 392 | /* NOTE: actual value is 127.0f, but this is working around a deqp |
| 393 | * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide |
| 394 | * uses too small of a render target size, and gets confused when |
| 395 | * the lines start going offscreen. |
| 396 | * |
| 397 | * See: https://code.google.com/p/android/issues/detail?id=206513 |
| 398 | */ |
| 399 | if (fd_mesa_debug & FD_DBG_DEQP) |
Rob Clark | edcc6ce | 2016-04-25 14:22:45 -0400 | [diff] [blame] | 400 | return 48.0f; |
Rob Clark | a7eb12d | 2016-04-11 17:46:08 -0400 | [diff] [blame] | 401 | return 127.0f; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 402 | case PIPE_CAPF_MAX_POINT_WIDTH: |
| 403 | case PIPE_CAPF_MAX_POINT_WIDTH_AA: |
Ilia Mirkin | 7fc5da8 | 2015-03-17 01:00:38 -0400 | [diff] [blame] | 404 | return 4092.0f; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 405 | case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: |
| 406 | return 16.0f; |
| 407 | case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: |
Rob Clark | 204dd73c | 2014-10-01 07:26:39 -0400 | [diff] [blame] | 408 | return 15.0f; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 409 | case PIPE_CAPF_GUARD_BAND_LEFT: |
| 410 | case PIPE_CAPF_GUARD_BAND_TOP: |
| 411 | case PIPE_CAPF_GUARD_BAND_RIGHT: |
| 412 | case PIPE_CAPF_GUARD_BAND_BOTTOM: |
| 413 | return 0.0f; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 414 | } |
Rob Clark | f725994 | 2014-09-26 17:56:08 -0400 | [diff] [blame] | 415 | debug_printf("unknown paramf %d\n", param); |
| 416 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 417 | } |
| 418 | |
| 419 | static int |
| 420 | fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, |
| 421 | enum pipe_shader_cap param) |
| 422 | { |
Rob Clark | 4317c4e | 2013-10-24 17:45:27 -0400 | [diff] [blame] | 423 | struct fd_screen *screen = fd_screen(pscreen); |
| 424 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 425 | switch(shader) |
| 426 | { |
| 427 | case PIPE_SHADER_FRAGMENT: |
| 428 | case PIPE_SHADER_VERTEX: |
| 429 | break; |
| 430 | case PIPE_SHADER_COMPUTE: |
| 431 | case PIPE_SHADER_GEOMETRY: |
| 432 | /* maye we could emulate.. */ |
| 433 | return 0; |
| 434 | default: |
| 435 | DBG("unknown shader type %d", shader); |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | /* this is probably not totally correct.. but it's a start: */ |
| 440 | switch (param) { |
| 441 | case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: |
| 442 | case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: |
| 443 | case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: |
| 444 | case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: |
| 445 | return 16384; |
| 446 | case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: |
| 447 | return 8; /* XXX */ |
| 448 | case PIPE_SHADER_CAP_MAX_INPUTS: |
Rob Clark | 3319354 | 2014-10-22 13:27:35 -0400 | [diff] [blame] | 449 | case PIPE_SHADER_CAP_MAX_OUTPUTS: |
Rob Clark | 5dcf59e | 2014-05-14 11:15:26 -0400 | [diff] [blame] | 450 | return 16; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 451 | case PIPE_SHADER_CAP_MAX_TEMPS: |
Rob Clark | 4317c4e | 2013-10-24 17:45:27 -0400 | [diff] [blame] | 452 | return 64; /* Max native temporaries. */ |
Marek Olšák | 04f2c88 | 2014-07-24 20:32:08 +0200 | [diff] [blame] | 453 | case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: |
Rob Clark | 652b8fb | 2014-10-15 13:08:00 -0400 | [diff] [blame] | 454 | /* NOTE: seems to be limit for a3xx is actually 512 but |
| 455 | * split between VS and FS. Use lower limit of 256 to |
| 456 | * avoid getting into impossible situations: |
| 457 | */ |
Ilia Mirkin | 1de72df | 2015-03-31 11:51:00 -0400 | [diff] [blame] | 458 | return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]); |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 459 | case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: |
Rob Clark | f72fead | 2015-08-10 20:41:45 -0400 | [diff] [blame] | 460 | return is_ir3(screen) ? 16 : 1; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 461 | case PIPE_SHADER_CAP_MAX_PREDS: |
| 462 | return 0; /* nothing uses this */ |
| 463 | case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: |
| 464 | return 1; |
| 465 | case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: |
| 466 | case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: |
Rob Clark | fad158a | 2016-01-10 14:10:08 -0500 | [diff] [blame] | 467 | /* Technically this should be the same as for TEMP/CONST, since |
| 468 | * everything is just normal registers. This is just temporary |
| 469 | * hack until load_input/store_output handle arrays in a similar |
| 470 | * way as load_var/store_var.. |
| 471 | */ |
| 472 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 473 | case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: |
| 474 | case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: |
Rob Clark | fad158a | 2016-01-10 14:10:08 -0500 | [diff] [blame] | 475 | /* a2xx compiler doesn't handle indirect: */ |
| 476 | return is_ir3(screen) ? 1 : 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 477 | case PIPE_SHADER_CAP_SUBROUTINES: |
Rob Clark | f725994 | 2014-09-26 17:56:08 -0400 | [diff] [blame] | 478 | case PIPE_SHADER_CAP_DOUBLES: |
Ilia Mirkin | c85a686 | 2015-02-19 23:30:36 -0500 | [diff] [blame] | 479 | case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: |
| 480 | case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: |
Marek Olšák | 216543e | 2015-02-28 00:26:31 +0100 | [diff] [blame] | 481 | case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: |
Rob Clark | 784086f | 2016-03-28 10:28:29 -0400 | [diff] [blame] | 482 | case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 483 | return 0; |
| 484 | case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: |
Rob Clark | 4ddd4e8 | 2013-10-25 11:48:24 -0400 | [diff] [blame] | 485 | return 1; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 486 | case PIPE_SHADER_CAP_INTEGERS: |
Rob Clark | fd17db6 | 2015-03-08 13:38:51 -0400 | [diff] [blame] | 487 | if (glsl120) |
| 488 | return 0; |
Rob Clark | f72fead | 2015-08-10 20:41:45 -0400 | [diff] [blame] | 489 | return is_ir3(screen) ? 1 : 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 490 | case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: |
Roland Scheidegger | 2983c03 | 2013-11-26 02:30:41 +0100 | [diff] [blame] | 491 | case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 492 | return 16; |
| 493 | case PIPE_SHADER_CAP_PREFERRED_IR: |
Rob Clark | 784086f | 2016-03-28 10:28:29 -0400 | [diff] [blame] | 494 | if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen)) |
| 495 | return PIPE_SHADER_IR_NIR; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 496 | return PIPE_SHADER_IR_TGSI; |
Samuel Pitoiset | 5e09ac7 | 2016-02-03 18:57:58 +0100 | [diff] [blame] | 497 | case PIPE_SHADER_CAP_SUPPORTED_IRS: |
| 498 | return 0; |
Marek Olšák | 814f314 | 2015-10-20 18:26:02 +0200 | [diff] [blame] | 499 | case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: |
| 500 | return 32; |
Ilia Mirkin | 266d001 | 2015-09-26 20:27:42 -0400 | [diff] [blame] | 501 | case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: |
Ilia Mirkin | 9fbfa1a | 2016-01-08 22:56:23 -0500 | [diff] [blame] | 502 | case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: |
Marek Olšák | 72217d4 | 2016-10-28 22:34:20 +0200 | [diff] [blame] | 503 | case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: |
Ilia Mirkin | 266d001 | 2015-09-26 20:27:42 -0400 | [diff] [blame] | 504 | return 0; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 505 | } |
Rob Clark | f725994 | 2014-09-26 17:56:08 -0400 | [diff] [blame] | 506 | debug_printf("unknown shader param %d\n", param); |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 507 | return 0; |
| 508 | } |
| 509 | |
Rob Clark | 784086f | 2016-03-28 10:28:29 -0400 | [diff] [blame] | 510 | static const void * |
| 511 | fd_get_compiler_options(struct pipe_screen *pscreen, |
| 512 | enum pipe_shader_ir ir, unsigned shader) |
| 513 | { |
| 514 | struct fd_screen *screen = fd_screen(pscreen); |
| 515 | |
| 516 | if (is_ir3(screen)) |
| 517 | return ir3_get_compiler_options(); |
| 518 | |
| 519 | return NULL; |
| 520 | } |
| 521 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 522 | boolean |
| 523 | fd_screen_bo_get_handle(struct pipe_screen *pscreen, |
| 524 | struct fd_bo *bo, |
| 525 | unsigned stride, |
| 526 | struct winsys_handle *whandle) |
| 527 | { |
| 528 | whandle->stride = stride; |
| 529 | |
| 530 | if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { |
| 531 | return fd_bo_get_name(bo, &whandle->handle) == 0; |
| 532 | } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { |
| 533 | whandle->handle = fd_bo_handle(bo); |
| 534 | return TRUE; |
Rob Clark | 18291ee | 2014-09-16 19:10:23 -0400 | [diff] [blame] | 535 | } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { |
| 536 | whandle->handle = fd_bo_dmabuf(bo); |
Rob Clark | e4c678c | 2014-09-26 10:35:33 -0400 | [diff] [blame] | 537 | return TRUE; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 538 | } else { |
| 539 | return FALSE; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | struct fd_bo * |
| 544 | fd_screen_bo_from_handle(struct pipe_screen *pscreen, |
Rob Clark | 32c061b | 2016-09-03 12:57:50 -0400 | [diff] [blame] | 545 | struct winsys_handle *whandle) |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 546 | { |
| 547 | struct fd_screen *screen = fd_screen(pscreen); |
| 548 | struct fd_bo *bo; |
| 549 | |
Rob Clark | 18291ee | 2014-09-16 19:10:23 -0400 | [diff] [blame] | 550 | if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { |
| 551 | bo = fd_bo_from_name(screen->dev, whandle->handle); |
| 552 | } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { |
| 553 | bo = fd_bo_from_handle(screen->dev, whandle->handle, 0); |
| 554 | } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { |
| 555 | bo = fd_bo_from_dmabuf(screen->dev, whandle->handle); |
| 556 | } else { |
Christopher James Halse Rogers | d5a3a2d | 2013-11-21 15:11:39 +1100 | [diff] [blame] | 557 | DBG("Attempt to import unsupported handle type %d", whandle->type); |
| 558 | return NULL; |
| 559 | } |
| 560 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 561 | if (!bo) { |
| 562 | DBG("ref name 0x%08x failed", whandle->handle); |
| 563 | return NULL; |
| 564 | } |
| 565 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 566 | return bo; |
| 567 | } |
| 568 | |
| 569 | struct pipe_screen * |
| 570 | fd_screen_create(struct fd_device *dev) |
| 571 | { |
| 572 | struct fd_screen *screen = CALLOC_STRUCT(fd_screen); |
| 573 | struct pipe_screen *pscreen; |
| 574 | uint64_t val; |
| 575 | |
Rob Clark | 634fb83 | 2013-03-25 14:57:24 -0400 | [diff] [blame] | 576 | fd_mesa_debug = debug_get_option_fd_mesa_debug(); |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 577 | |
Rob Clark | 1b88607 | 2014-02-03 11:28:30 -0500 | [diff] [blame] | 578 | if (fd_mesa_debug & FD_DBG_NOBIN) |
Rob Clark | c076652 | 2014-01-07 10:55:07 -0500 | [diff] [blame] | 579 | fd_binning_enabled = false; |
| 580 | |
Rob Clark | fd17db6 | 2015-03-08 13:38:51 -0400 | [diff] [blame] | 581 | glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120); |
Rob Clark | e189694 | 2014-05-14 11:06:21 -0400 | [diff] [blame] | 582 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 583 | if (!screen) |
| 584 | return NULL; |
| 585 | |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 586 | pscreen = &screen->base; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 587 | |
| 588 | screen->dev = dev; |
Rob Clark | 5bb41d9 | 2015-09-04 11:35:33 -0400 | [diff] [blame] | 589 | screen->refcnt = 1; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 590 | |
| 591 | // maybe this should be in context? |
| 592 | screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D); |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 593 | if (!screen->pipe) { |
| 594 | DBG("could not create 3d pipe"); |
| 595 | goto fail; |
| 596 | } |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 597 | |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 598 | if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) { |
| 599 | DBG("could not get GMEM size"); |
| 600 | goto fail; |
| 601 | } |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 602 | screen->gmemsize_bytes = val; |
| 603 | |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 604 | if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) { |
| 605 | DBG("could not get device-id"); |
| 606 | goto fail; |
| 607 | } |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 608 | screen->device_id = val; |
| 609 | |
Rob Clark | 45ab5b1 | 2016-02-10 13:25:32 -0500 | [diff] [blame] | 610 | if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) { |
| 611 | DBG("could not get gpu freq"); |
| 612 | /* this limits what performance related queries are |
| 613 | * supported but is not fatal |
| 614 | */ |
| 615 | screen->max_freq = 0; |
| 616 | } else { |
| 617 | screen->max_freq = val; |
Rob Clark | b888d8e | 2016-02-23 12:03:43 -0500 | [diff] [blame] | 618 | if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0) |
| 619 | screen->has_timestamp = true; |
Rob Clark | 45ab5b1 | 2016-02-10 13:25:32 -0500 | [diff] [blame] | 620 | } |
| 621 | |
Rob Clark | 18c317b | 2013-05-26 17:13:27 -0400 | [diff] [blame] | 622 | if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) { |
| 623 | DBG("could not get gpu-id"); |
| 624 | goto fail; |
| 625 | } |
| 626 | screen->gpu_id = val; |
| 627 | |
Rob Clark | d48faad | 2014-06-18 10:24:04 -0400 | [diff] [blame] | 628 | if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) { |
| 629 | DBG("could not get chip-id"); |
| 630 | /* older kernels may not have this property: */ |
| 631 | unsigned core = screen->gpu_id / 100; |
| 632 | unsigned major = (screen->gpu_id % 100) / 10; |
| 633 | unsigned minor = screen->gpu_id % 10; |
| 634 | unsigned patch = 0; /* assume the worst */ |
| 635 | val = (patch & 0xff) | ((minor & 0xff) << 8) | |
| 636 | ((major & 0xff) << 16) | ((core & 0xff) << 24); |
| 637 | } |
| 638 | screen->chip_id = val; |
| 639 | |
| 640 | DBG("Pipe Info:"); |
| 641 | DBG(" GPU-id: %d", screen->gpu_id); |
| 642 | DBG(" Chip-id: 0x%08x", screen->chip_id); |
| 643 | DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes); |
| 644 | |
Rob Clark | 18c317b | 2013-05-26 17:13:27 -0400 | [diff] [blame] | 645 | /* explicitly checking for GPU revisions that are known to work. This |
| 646 | * may be overly conservative for a3xx, where spoofing the gpu_id with |
| 647 | * the blob driver seems to generate identical cmdstream dumps. But |
| 648 | * on a2xx, there seem to be small differences between the GPU revs |
| 649 | * so it is probably better to actually test first on real hardware |
| 650 | * before enabling: |
| 651 | * |
| 652 | * If you have a different adreno version, feel free to add it to one |
Rob Clark | 61c68b6 | 2014-07-31 15:42:55 -0400 | [diff] [blame] | 653 | * of the cases below and see what happens. And if it works, please |
Rob Clark | 18c317b | 2013-05-26 17:13:27 -0400 | [diff] [blame] | 654 | * send a patch ;-) |
| 655 | */ |
| 656 | switch (screen->gpu_id) { |
| 657 | case 220: |
| 658 | fd2_screen_init(pscreen); |
| 659 | break; |
Guillaume Charifi | 6f5e0c0 | 2015-11-06 11:17:25 -0500 | [diff] [blame] | 660 | case 305: |
Rob Clark | fcc7d63 | 2015-05-12 14:46:50 -0400 | [diff] [blame] | 661 | case 307: |
Rob Clark | 2855f3f | 2013-05-26 17:13:44 -0400 | [diff] [blame] | 662 | case 320: |
Rob Clark | a1d8086 | 2013-12-07 08:47:10 -0500 | [diff] [blame] | 663 | case 330: |
Rob Clark | 2855f3f | 2013-05-26 17:13:44 -0400 | [diff] [blame] | 664 | fd3_screen_init(pscreen); |
| 665 | break; |
Rob Clark | 61c68b6 | 2014-07-31 15:42:55 -0400 | [diff] [blame] | 666 | case 420: |
cstout | 13b87e0 | 2015-12-11 16:58:45 -0800 | [diff] [blame] | 667 | case 430: |
Rob Clark | 61c68b6 | 2014-07-31 15:42:55 -0400 | [diff] [blame] | 668 | fd4_screen_init(pscreen); |
| 669 | break; |
Rob Clark | 18c317b | 2013-05-26 17:13:27 -0400 | [diff] [blame] | 670 | default: |
| 671 | debug_printf("unsupported GPU: a%03d\n", screen->gpu_id); |
| 672 | goto fail; |
| 673 | } |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 674 | |
Rob Clark | 8c56789 | 2016-11-23 09:53:44 -0500 | [diff] [blame^] | 675 | if (screen->gpu_id >= 500) { |
| 676 | screen->gmem_alignment = 64; |
| 677 | } else { |
| 678 | screen->gmem_alignment = 32; |
| 679 | } |
| 680 | |
Rob Clark | 9f219c7 | 2016-06-27 09:44:15 -0400 | [diff] [blame] | 681 | /* NOTE: don't enable reordering on a2xx, since completely untested. |
| 682 | * Also, don't enable if we have too old of a kernel to support |
| 683 | * growable cmdstream buffers, since memory requirement for cmdstream |
| 684 | * buffers would be too much otherwise. |
| 685 | */ |
| 686 | if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)) |
| 687 | screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER); |
| 688 | |
| 689 | fd_bc_init(&screen->batch_cache); |
| 690 | |
Rob Clark | e684c32 | 2016-07-19 18:24:57 -0400 | [diff] [blame] | 691 | pipe_mutex_init(screen->lock); |
| 692 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 693 | pscreen->destroy = fd_screen_destroy; |
| 694 | pscreen->get_param = fd_screen_get_param; |
| 695 | pscreen->get_paramf = fd_screen_get_paramf; |
| 696 | pscreen->get_shader_param = fd_screen_get_shader_param; |
Rob Clark | 784086f | 2016-03-28 10:28:29 -0400 | [diff] [blame] | 697 | pscreen->get_compiler_options = fd_get_compiler_options; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 698 | |
| 699 | fd_resource_screen_init(pscreen); |
Rob Clark | 646c16a | 2014-01-07 21:39:13 -0500 | [diff] [blame] | 700 | fd_query_screen_init(pscreen); |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 701 | |
| 702 | pscreen->get_name = fd_screen_get_name; |
| 703 | pscreen->get_vendor = fd_screen_get_vendor; |
Giuseppe Bilotta | 76039b3 | 2015-03-22 07:21:01 +0100 | [diff] [blame] | 704 | pscreen->get_device_vendor = fd_screen_get_device_vendor; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 705 | |
| 706 | pscreen->get_timestamp = fd_screen_get_timestamp; |
| 707 | |
| 708 | pscreen->fence_reference = fd_screen_fence_ref; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 709 | pscreen->fence_finish = fd_screen_fence_finish; |
| 710 | |
Nicolai Hähnle | 0334ba1 | 2016-09-27 19:06:13 +0200 | [diff] [blame] | 711 | slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16); |
| 712 | |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 713 | util_format_s3tc_init(); |
| 714 | |
| 715 | return pscreen; |
Rob Clark | 38d8b02 | 2013-04-22 13:42:55 -0400 | [diff] [blame] | 716 | |
| 717 | fail: |
| 718 | fd_screen_destroy(pscreen); |
| 719 | return NULL; |
Rob Clark | 6173cc1 | 2012-10-27 11:07:34 -0500 | [diff] [blame] | 720 | } |