Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2020 Collabora Ltd. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors (Collabora): |
| 24 | * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> |
| 25 | */ |
| 26 | |
| 27 | #ifndef __BIFROST_COMPILER_H |
| 28 | #define __BIFROST_COMPILER_H |
| 29 | |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 30 | #include "bifrost.h" |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 31 | #include "compiler/nir/nir.h" |
Alyssa Rosenzweig | 9b8cb9f | 2020-03-09 20:19:29 -0400 | [diff] [blame] | 32 | #include "panfrost/util/pan_ir.h" |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 33 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 34 | /* Bifrost opcodes are tricky -- the same op may exist on both FMA and |
| 35 | * ADD with two completely different opcodes, and opcodes can be varying |
| 36 | * length in some cases. Then we have different opcodes for int vs float |
| 37 | * and then sometimes even for different typesizes. Further, virtually |
| 38 | * every op has a number of flags which depend on the op. In constrast |
| 39 | * to Midgard where you have a strict ALU/LDST/TEX division and within |
| 40 | * ALU you have strict int/float and that's it... here it's a *lot* more |
| 41 | * involved. As such, we use something much higher level for our IR, |
| 42 | * encoding "classes" of operations, letting the opcode details get |
| 43 | * sorted out at emit time. |
| 44 | * |
| 45 | * Please keep this list alphabetized. Please use a dictionary if you |
| 46 | * don't know how to do that. |
| 47 | */ |
| 48 | |
| 49 | enum bi_class { |
| 50 | BI_ADD, |
| 51 | BI_ATEST, |
| 52 | BI_BRANCH, |
| 53 | BI_CMP, |
| 54 | BI_BLEND, |
| 55 | BI_BITWISE, |
Alyssa Rosenzweig | e0a51d5 | 2020-03-22 17:31:23 -0400 | [diff] [blame] | 56 | BI_COMBINE, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 57 | BI_CONVERT, |
| 58 | BI_CSEL, |
| 59 | BI_DISCARD, |
| 60 | BI_FMA, |
Alyssa Rosenzweig | 6b7077e | 2020-03-19 16:58:48 -0400 | [diff] [blame] | 61 | BI_FMOV, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 62 | BI_FREXP, |
Alyssa Rosenzweig | 55f0d81 | 2020-03-10 08:03:20 -0400 | [diff] [blame] | 63 | BI_ISUB, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 64 | BI_LOAD, |
Alyssa Rosenzweig | 1ead0d3 | 2020-03-06 09:52:09 -0500 | [diff] [blame] | 65 | BI_LOAD_UNIFORM, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 66 | BI_LOAD_ATTR, |
| 67 | BI_LOAD_VAR, |
| 68 | BI_LOAD_VAR_ADDRESS, |
| 69 | BI_MINMAX, |
| 70 | BI_MOV, |
Alyssa Rosenzweig | 62c8c34 | 2020-04-14 12:33:08 -0400 | [diff] [blame] | 71 | BI_REDUCE_FMA, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 72 | BI_SHIFT, |
| 73 | BI_STORE, |
| 74 | BI_STORE_VAR, |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 75 | BI_SPECIAL, /* _FAST on supported GPUs */ |
Alyssa Rosenzweig | 5896db9 | 2020-03-03 08:35:51 -0500 | [diff] [blame] | 76 | BI_SWIZZLE, |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 77 | BI_TABLE, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 78 | BI_TEX, |
| 79 | BI_ROUND, |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 80 | BI_NUM_CLASSES |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 81 | }; |
| 82 | |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 83 | /* Properties of a class... */ |
| 84 | extern unsigned bi_class_props[BI_NUM_CLASSES]; |
| 85 | |
| 86 | /* abs/neg/outmod valid for a float op */ |
| 87 | #define BI_MODS (1 << 0) |
| 88 | |
Alyssa Rosenzweig | 34165c7 | 2020-03-02 20:46:37 -0500 | [diff] [blame] | 89 | /* Generic enough that little class-specific information is required. In other |
| 90 | * words, it acts as a "normal" ALU op, even if the encoding ends up being |
| 91 | * irregular enough to warrant a separate class */ |
| 92 | #define BI_GENERIC (1 << 1) |
| 93 | |
Alyssa Rosenzweig | d69bf8d | 2020-03-02 20:52:36 -0500 | [diff] [blame] | 94 | /* Accepts a bifrost_roundmode */ |
| 95 | #define BI_ROUNDMODE (1 << 2) |
| 96 | |
Alyssa Rosenzweig | 99f3c1f | 2020-03-02 21:53:13 -0500 | [diff] [blame] | 97 | /* Can be scheduled to FMA */ |
| 98 | #define BI_SCHED_FMA (1 << 3) |
| 99 | |
| 100 | /* Can be scheduled to ADD */ |
| 101 | #define BI_SCHED_ADD (1 << 4) |
| 102 | |
| 103 | /* Most ALU ops can do either, actually */ |
| 104 | #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD) |
| 105 | |
Alyssa Rosenzweig | c70a198 | 2020-03-03 08:16:50 -0500 | [diff] [blame] | 106 | /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be |
| 107 | * nopped out. Used for _FAST operations. */ |
| 108 | #define BI_SCHED_SLOW (1 << 5) |
| 109 | |
Alyssa Rosenzweig | 5896db9 | 2020-03-03 08:35:51 -0500 | [diff] [blame] | 110 | /* Swizzling allowed for the 8/16-bit source */ |
| 111 | #define BI_SWIZZLABLE (1 << 6) |
| 112 | |
Alyssa Rosenzweig | 07228a6 | 2020-03-03 13:55:33 -0500 | [diff] [blame] | 113 | /* For scheduling purposes this is a high latency instruction and must be at |
| 114 | * the end of a clause. Implies ADD */ |
Alyssa Rosenzweig | e323df0 | 2020-03-18 13:42:12 -0400 | [diff] [blame] | 115 | #define BI_SCHED_HI_LATENCY (1 << 7) |
Alyssa Rosenzweig | 07228a6 | 2020-03-03 13:55:33 -0500 | [diff] [blame] | 116 | |
Alyssa Rosenzweig | 9458b01 | 2020-03-20 12:25:08 -0400 | [diff] [blame] | 117 | /* Intrinsic is vectorized and should read 4 components in the first source |
| 118 | * regardless of writemask */ |
Alyssa Rosenzweig | e1d9533 | 2020-03-11 21:41:57 -0400 | [diff] [blame] | 119 | #define BI_VECTOR (1 << 8) |
| 120 | |
Alyssa Rosenzweig | d4fbf75 | 2020-03-18 12:08:28 -0400 | [diff] [blame] | 121 | /* Use a data register for src0/dest respectively, bypassing the usual |
| 122 | * register accessor. Mutually exclusive. */ |
| 123 | #define BI_DATA_REG_SRC (1 << 9) |
| 124 | #define BI_DATA_REG_DEST (1 << 10) |
| 125 | |
Alyssa Rosenzweig | bd19e76 | 2020-03-30 12:25:20 -0400 | [diff] [blame] | 126 | /* Quirk: cannot encode multiple abs on FMA in fp16 mode */ |
| 127 | #define BI_NO_ABS_ABS_FP16_FMA (1 << 11) |
| 128 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 129 | /* It can't get any worse than csel4... can it? */ |
| 130 | #define BIR_SRC_COUNT 4 |
| 131 | |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 132 | /* BI_LD_VARY */ |
| 133 | struct bi_load_vary { |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 134 | enum bifrost_interp_mode interp_mode; |
| 135 | bool reuse; |
| 136 | bool flat; |
| 137 | }; |
| 138 | |
Alyssa Rosenzweig | 47451bb | 2020-03-03 13:48:13 -0500 | [diff] [blame] | 139 | /* BI_BRANCH encoding the details of the branch itself as well as a pointer to |
| 140 | * the target. We forward declare bi_block since this is mildly circular (not |
| 141 | * strictly, but this order of the file makes more sense I think) |
| 142 | * |
| 143 | * We define our own enum of conditions since the conditions in the hardware |
| 144 | * packed in crazy ways that would make manipulation unweildly (meaning changes |
| 145 | * based on port swapping, etc), so we defer dealing with that until emit time. |
| 146 | * Likewise, we expose NIR types instead of the crazy branch types, although |
| 147 | * the restrictions do eventually apply of course. */ |
| 148 | |
| 149 | struct bi_block; |
| 150 | |
| 151 | enum bi_cond { |
| 152 | BI_COND_ALWAYS, |
| 153 | BI_COND_LT, |
| 154 | BI_COND_LE, |
| 155 | BI_COND_GE, |
| 156 | BI_COND_GT, |
| 157 | BI_COND_EQ, |
| 158 | BI_COND_NE, |
| 159 | }; |
| 160 | |
| 161 | struct bi_branch { |
| 162 | /* Types are specified in src_types and must be compatible (either both |
| 163 | * int, or both float, 16/32, and same size or 32/16 if float. Types |
| 164 | * ignored if BI_COND_ALWAYS is set for an unconditional branch. */ |
| 165 | |
| 166 | enum bi_cond cond; |
| 167 | struct bi_block *target; |
| 168 | }; |
| 169 | |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame] | 170 | /* Opcodes within a class */ |
| 171 | enum bi_minmax_op { |
| 172 | BI_MINMAX_MIN, |
| 173 | BI_MINMAX_MAX |
| 174 | }; |
| 175 | |
| 176 | enum bi_bitwise_op { |
| 177 | BI_BITWISE_AND, |
| 178 | BI_BITWISE_OR, |
| 179 | BI_BITWISE_XOR |
| 180 | }; |
| 181 | |
| 182 | enum bi_round_op { |
| 183 | BI_ROUND_MODE, /* use round mode */ |
| 184 | BI_ROUND_ROUND /* i.e.: fround() */ |
| 185 | }; |
| 186 | |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 187 | enum bi_table_op { |
| 188 | /* fp32 log2() with low precision, suitable for GL or half_log2() in |
| 189 | * CL. In the first argument, takes x. Letting u be such that x = |
| 190 | * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns |
| 191 | * log2(u) / (u - 1). */ |
| 192 | |
| 193 | BI_TABLE_LOG2_U_OVER_U_1_LOW, |
| 194 | }; |
| 195 | |
Alyssa Rosenzweig | 62c8c34 | 2020-04-14 12:33:08 -0400 | [diff] [blame] | 196 | enum bi_reduce_op { |
| 197 | /* Takes two fp32 arguments and returns x + frexp(y). Used in |
| 198 | * low-precision log2 argument reduction on newer models. */ |
| 199 | |
| 200 | BI_REDUCE_ADD_FREXPM, |
| 201 | }; |
| 202 | |
Alyssa Rosenzweig | e067fd7 | 2020-04-14 12:37:29 -0400 | [diff] [blame] | 203 | enum bi_frexp_op { |
| 204 | BI_FREXPE_LOG, |
| 205 | }; |
| 206 | |
Alyssa Rosenzweig | b674e39 | 2020-03-09 21:20:03 -0400 | [diff] [blame] | 207 | enum bi_special_op { |
| 208 | BI_SPECIAL_FRCP, |
| 209 | BI_SPECIAL_FRSQ, |
Alyssa Rosenzweig | cc61156 | 2020-04-14 12:22:28 -0400 | [diff] [blame] | 210 | |
| 211 | /* fp32 exp2() with low precision, suitable for half_exp2() in CL or |
| 212 | * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In |
| 213 | * the second, it takes x itself. */ |
| 214 | BI_SPECIAL_EXP2_LOW, |
Alyssa Rosenzweig | b674e39 | 2020-03-09 21:20:03 -0400 | [diff] [blame] | 215 | }; |
| 216 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 217 | typedef struct { |
| 218 | struct list_head link; /* Must be first */ |
| 219 | enum bi_class type; |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 220 | |
| 221 | /* Indices, see bir_ssa_index etc. Note zero is special cased |
| 222 | * to "no argument" */ |
| 223 | unsigned dest; |
| 224 | unsigned src[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 225 | |
Alyssa Rosenzweig | 795646d | 2020-03-09 14:09:04 -0400 | [diff] [blame] | 226 | /* If one of the sources has BIR_INDEX_CONSTANT */ |
Alyssa Rosenzweig | b5bdd89 | 2020-03-03 07:47:29 -0500 | [diff] [blame] | 227 | union { |
| 228 | uint64_t u64; |
| 229 | uint32_t u32; |
| 230 | uint16_t u16[2]; |
| 231 | uint8_t u8[4]; |
| 232 | } constant; |
| 233 | |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 234 | /* Floating-point modifiers, type/class permitting. If not |
| 235 | * allowed for the type/class, these are ignored. */ |
| 236 | enum bifrost_outmod outmod; |
| 237 | bool src_abs[BIR_SRC_COUNT]; |
| 238 | bool src_neg[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | d69bf8d | 2020-03-02 20:52:36 -0500 | [diff] [blame] | 239 | |
| 240 | /* Round mode (requires BI_ROUNDMODE) */ |
| 241 | enum bifrost_roundmode roundmode; |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 242 | |
Alyssa Rosenzweig | e9d480c | 2020-03-09 14:25:00 -0400 | [diff] [blame] | 243 | /* Writemask (bit for each affected byte). This is quite restricted -- |
| 244 | * ALU ops can only write to a single channel (exception: <32 in which |
| 245 | * you can write to 32/N contiguous aligned channels). Load/store can |
| 246 | * only write to all channels at once, in a sense. But it's still |
| 247 | * better to use this generic form than have synthetic ops flying |
| 248 | * about, since we're not essentially vector for RA purposes. */ |
| 249 | uint16_t writemask; |
| 250 | |
Alyssa Rosenzweig | c42002d | 2020-03-02 22:03:05 -0500 | [diff] [blame] | 251 | /* Destination type. Usually the type of the instruction |
| 252 | * itself, but if sources and destination have different |
| 253 | * types, the type of the destination wins (so f2i would be |
| 254 | * int). Zero if there is no destination. Bitsize included */ |
| 255 | nir_alu_type dest_type; |
| 256 | |
Alyssa Rosenzweig | 8929fe0 | 2020-03-03 08:37:15 -0500 | [diff] [blame] | 257 | /* Source types if required by the class */ |
| 258 | nir_alu_type src_types[BIR_SRC_COUNT]; |
| 259 | |
Alyssa Rosenzweig | 795646d | 2020-03-09 14:09:04 -0400 | [diff] [blame] | 260 | /* If the source type is 8-bit or 16-bit such that SIMD is possible, |
| 261 | * and the class has BI_SWIZZLABLE, this is a swizzle in the usual |
| 262 | * sense. On non-SIMD instructions, it can be used for component |
| 263 | * selection, so we don't have to special case extraction. */ |
| 264 | uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS]; |
Alyssa Rosenzweig | 5896db9 | 2020-03-03 08:35:51 -0500 | [diff] [blame] | 265 | |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame] | 266 | /* A class-specific op from which the actual opcode can be derived |
| 267 | * (along with the above information) */ |
| 268 | |
| 269 | union { |
| 270 | enum bi_minmax_op minmax; |
| 271 | enum bi_bitwise_op bitwise; |
| 272 | enum bi_round_op round; |
Alyssa Rosenzweig | b674e39 | 2020-03-09 21:20:03 -0400 | [diff] [blame] | 273 | enum bi_special_op special; |
Alyssa Rosenzweig | 62c8c34 | 2020-04-14 12:33:08 -0400 | [diff] [blame] | 274 | enum bi_reduce_op reduce; |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 275 | enum bi_table_op table; |
Alyssa Rosenzweig | e067fd7 | 2020-04-14 12:37:29 -0400 | [diff] [blame] | 276 | enum bi_frexp_op frexp; |
Alyssa Rosenzweig | 20c7d57 | 2020-03-10 08:47:20 -0400 | [diff] [blame] | 277 | enum bi_cond compare; |
Alyssa Rosenzweig | 4570c34 | 2020-04-14 16:13:53 -0400 | [diff] [blame] | 278 | |
| 279 | /* For FMA/ADD, should we add a biased exponent? */ |
| 280 | bool mscale; |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame] | 281 | } op; |
| 282 | |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 283 | /* Union for class-specific information */ |
| 284 | union { |
| 285 | enum bifrost_minmax_mode minmax; |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 286 | struct bi_load_vary load_vary; |
Alyssa Rosenzweig | 47451bb | 2020-03-03 13:48:13 -0500 | [diff] [blame] | 287 | struct bi_branch branch; |
Alyssa Rosenzweig | 546c301 | 2020-03-05 07:46:00 -0500 | [diff] [blame] | 288 | |
| 289 | /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make |
| 290 | * sense here but you can always just use a move for that */ |
| 291 | enum bi_cond csel_cond; |
Alyssa Rosenzweig | 92a4f26 | 2020-03-06 09:25:58 -0500 | [diff] [blame] | 292 | |
| 293 | /* For BLEND -- the location 0-7 */ |
| 294 | unsigned blend_location; |
Alyssa Rosenzweig | 9213b25 | 2020-03-20 12:38:53 -0400 | [diff] [blame] | 295 | |
| 296 | /* For STORE, STORE_VAR -- channel count */ |
| 297 | unsigned store_channels; |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 298 | }; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 299 | } bi_instruction; |
| 300 | |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 301 | /* Scheduling takes place in two steps. Step 1 groups instructions within a |
| 302 | * block into distinct clauses (bi_clause). Step 2 schedules instructions |
| 303 | * within a clause into FMA/ADD pairs (bi_bundle). |
| 304 | * |
| 305 | * A bi_bundle contains two paired instruction pointers. If a slot is unfilled, |
| 306 | * leave it NULL; the emitter will fill in a nop. |
| 307 | */ |
| 308 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 309 | typedef struct { |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 310 | bi_instruction *fma; |
| 311 | bi_instruction *add; |
| 312 | } bi_bundle; |
| 313 | |
| 314 | typedef struct { |
| 315 | struct list_head link; |
| 316 | |
| 317 | /* A clause can have 8 instructions in bundled FMA/ADD sense, so there |
| 318 | * can be 8 bundles. But each bundle can have both an FMA and an ADD, |
| 319 | * so a clause can have up to 16 bi_instructions. Whether bundles or |
| 320 | * instructions are used depends on where in scheduling we are. */ |
| 321 | |
| 322 | unsigned instruction_count; |
| 323 | unsigned bundle_count; |
| 324 | |
| 325 | union { |
| 326 | bi_instruction *instructions[16]; |
| 327 | bi_bundle bundles[8]; |
| 328 | }; |
Alyssa Rosenzweig | fba1d12 | 2020-03-03 08:09:18 -0500 | [diff] [blame] | 329 | |
| 330 | /* For scoreboarding -- the clause ID (this is not globally unique!) |
| 331 | * and its dependencies in terms of other clauses, computed during |
| 332 | * scheduling and used when emitting code. Dependencies expressed as a |
| 333 | * bitfield matching the hardware, except shifted by a clause (the |
| 334 | * shift back to the ISA's off-by-one encoding is worked out when |
| 335 | * emitting clauses) */ |
| 336 | unsigned scoreboard_id; |
| 337 | uint8_t dependencies; |
| 338 | |
| 339 | /* Back-to-back corresponds directly to the back-to-back bit. Branch |
| 340 | * conditional corresponds to the branch conditional bit except that in |
| 341 | * the emitted code it's always set if back-to-bit is, whereas we use |
| 342 | * the actual value (without back-to-back so to speak) internally */ |
| 343 | bool back_to_back; |
| 344 | bool branch_conditional; |
| 345 | |
Alyssa Rosenzweig | 42af9f4 | 2020-03-18 12:18:30 -0400 | [diff] [blame] | 346 | /* Assigned data register */ |
| 347 | unsigned data_register; |
| 348 | |
Alyssa Rosenzweig | fba1d12 | 2020-03-03 08:09:18 -0500 | [diff] [blame] | 349 | /* Corresponds to the usual bit but shifted by a clause */ |
| 350 | bool data_register_write_barrier; |
Alyssa Rosenzweig | d3370bd | 2020-03-03 13:01:41 -0500 | [diff] [blame] | 351 | |
| 352 | /* Constants read by this clause. ISA limit. */ |
| 353 | uint64_t constants[8]; |
| 354 | unsigned constant_count; |
Alyssa Rosenzweig | 42af9f4 | 2020-03-18 12:18:30 -0400 | [diff] [blame] | 355 | |
| 356 | /* What type of high latency instruction is here, basically */ |
| 357 | unsigned clause_type; |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 358 | } bi_clause; |
| 359 | |
| 360 | typedef struct bi_block { |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 361 | pan_block base; /* must be first */ |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 362 | |
| 363 | /* If true, uses clauses; if false, uses instructions */ |
| 364 | bool scheduled; |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 365 | struct list_head clauses; /* list of bi_clause */ |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 366 | } bi_block; |
| 367 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 368 | typedef struct { |
| 369 | nir_shader *nir; |
Alyssa Rosenzweig | 0d29184 | 2020-03-05 10:11:39 -0500 | [diff] [blame] | 370 | gl_shader_stage stage; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 371 | struct list_head blocks; /* list of bi_block */ |
Alyssa Rosenzweig | 218785c | 2020-03-10 16:20:18 -0400 | [diff] [blame] | 372 | struct panfrost_sysvals sysvals; |
Alyssa Rosenzweig | 0b26cb1 | 2020-03-03 14:27:05 -0500 | [diff] [blame] | 373 | uint32_t quirks; |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 374 | |
| 375 | /* During NIR->BIR */ |
Alyssa Rosenzweig | d86659c | 2020-03-06 09:43:43 -0500 | [diff] [blame] | 376 | nir_function_impl *impl; |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 377 | bi_block *current_block; |
| 378 | unsigned block_name_count; |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 379 | bi_block *after_block; |
Alyssa Rosenzweig | 987aea1 | 2020-03-05 17:03:53 -0500 | [diff] [blame] | 380 | bi_block *break_block; |
| 381 | bi_block *continue_block; |
Alyssa Rosenzweig | dabb6c6 | 2020-03-06 09:26:44 -0500 | [diff] [blame] | 382 | bool emitted_atest; |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 383 | |
Alyssa Rosenzweig | d86659c | 2020-03-06 09:43:43 -0500 | [diff] [blame] | 384 | /* For creating temporaries */ |
| 385 | unsigned temp_alloc; |
| 386 | |
Alyssa Rosenzweig | 56e1c60 | 2020-03-11 14:54:49 -0400 | [diff] [blame] | 387 | /* Analysis results */ |
| 388 | bool has_liveness; |
| 389 | |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 390 | /* Stats for shader-db */ |
| 391 | unsigned instruction_count; |
Alyssa Rosenzweig | 987aea1 | 2020-03-05 17:03:53 -0500 | [diff] [blame] | 392 | unsigned loop_count; |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 393 | } bi_context; |
| 394 | |
| 395 | static inline bi_instruction * |
| 396 | bi_emit(bi_context *ctx, bi_instruction ins) |
| 397 | { |
| 398 | bi_instruction *u = rzalloc(ctx, bi_instruction); |
| 399 | memcpy(u, &ins, sizeof(ins)); |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 400 | list_addtail(&u->link, &ctx->current_block->base.instructions); |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 401 | return u; |
| 402 | } |
| 403 | |
Alyssa Rosenzweig | 58a51c4 | 2020-03-19 17:21:34 -0400 | [diff] [blame] | 404 | static inline bi_instruction * |
| 405 | bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins) |
| 406 | { |
| 407 | bi_instruction *u = rzalloc(ctx, bi_instruction); |
| 408 | memcpy(u, &ins, sizeof(ins)); |
| 409 | list_addtail(&u->link, &tag->link); |
| 410 | return u; |
| 411 | } |
| 412 | |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 413 | static inline void |
| 414 | bi_remove_instruction(bi_instruction *ins) |
| 415 | { |
| 416 | list_del(&ins->link); |
| 417 | } |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 418 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 419 | /* So we can distinguish between SSA/reg/sentinel quickly */ |
| 420 | #define BIR_NO_ARG (0) |
| 421 | #define BIR_IS_REG (1) |
| 422 | |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 423 | /* If high bits are set, instead of SSA/registers, we have specials indexed by |
| 424 | * the low bits if necessary. |
| 425 | * |
| 426 | * Fixed register: do not allocate register, do not collect $200. |
| 427 | * Uniform: access a uniform register given by low bits. |
Alyssa Rosenzweig | 11bccb0 | 2020-03-21 18:42:58 -0400 | [diff] [blame] | 428 | * Constant: access the specified constant (specifies a bit offset / shift) |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 429 | * Zero: special cased to avoid wasting a constant |
Alyssa Rosenzweig | cd40e18 | 2020-03-18 09:57:32 -0400 | [diff] [blame] | 430 | * Passthrough: a bifrost_packed_src to passthrough T/T0/T1 |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 431 | */ |
| 432 | |
| 433 | #define BIR_INDEX_REGISTER (1 << 31) |
| 434 | #define BIR_INDEX_UNIFORM (1 << 30) |
| 435 | #define BIR_INDEX_CONSTANT (1 << 29) |
| 436 | #define BIR_INDEX_ZERO (1 << 28) |
Alyssa Rosenzweig | cd40e18 | 2020-03-18 09:57:32 -0400 | [diff] [blame] | 437 | #define BIR_INDEX_PASS (1 << 27) |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 438 | |
| 439 | /* Keep me synced please so we can check src & BIR_SPECIAL */ |
| 440 | |
| 441 | #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \ |
Alyssa Rosenzweig | cd40e18 | 2020-03-18 09:57:32 -0400 | [diff] [blame] | 442 | (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS)) |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 443 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 444 | static inline unsigned |
Alyssa Rosenzweig | 0bff6e5 | 2020-03-11 14:51:57 -0400 | [diff] [blame] | 445 | bi_max_temp(bi_context *ctx) |
| 446 | { |
| 447 | unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc); |
Alyssa Rosenzweig | e8139ef | 2020-03-11 20:39:36 -0400 | [diff] [blame] | 448 | return ((alloc + 2 + ctx->temp_alloc) << 1); |
Alyssa Rosenzweig | 0bff6e5 | 2020-03-11 14:51:57 -0400 | [diff] [blame] | 449 | } |
| 450 | |
| 451 | static inline unsigned |
Alyssa Rosenzweig | d86659c | 2020-03-06 09:43:43 -0500 | [diff] [blame] | 452 | bi_make_temp(bi_context *ctx) |
| 453 | { |
| 454 | return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1; |
| 455 | } |
| 456 | |
| 457 | static inline unsigned |
| 458 | bi_make_temp_reg(bi_context *ctx) |
| 459 | { |
| 460 | return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG; |
| 461 | } |
| 462 | |
| 463 | static inline unsigned |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 464 | bir_ssa_index(nir_ssa_def *ssa) |
| 465 | { |
| 466 | /* Off-by-one ensures BIR_NO_ARG is skipped */ |
| 467 | return ((ssa->index + 1) << 1) | 0; |
| 468 | } |
| 469 | |
| 470 | static inline unsigned |
| 471 | bir_src_index(nir_src *src) |
| 472 | { |
| 473 | if (src->is_ssa) |
| 474 | return bir_ssa_index(src->ssa); |
| 475 | else { |
| 476 | assert(!src->reg.indirect); |
| 477 | return (src->reg.reg->index << 1) | BIR_IS_REG; |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | static inline unsigned |
| 482 | bir_dest_index(nir_dest *dst) |
| 483 | { |
| 484 | if (dst->is_ssa) |
| 485 | return bir_ssa_index(&dst->ssa); |
| 486 | else { |
| 487 | assert(!dst->reg.indirect); |
| 488 | return (dst->reg.reg->index << 1) | BIR_IS_REG; |
| 489 | } |
| 490 | } |
| 491 | |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 492 | /* Iterators for Bifrost IR */ |
| 493 | |
| 494 | #define bi_foreach_block(ctx, v) \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 495 | list_for_each_entry(pan_block, v, &ctx->blocks, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 496 | |
| 497 | #define bi_foreach_block_from(ctx, from, v) \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 498 | list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 499 | |
| 500 | #define bi_foreach_instr_in_block(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 501 | list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 502 | |
| 503 | #define bi_foreach_instr_in_block_rev(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 504 | list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 505 | |
| 506 | #define bi_foreach_instr_in_block_safe(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 507 | list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 508 | |
| 509 | #define bi_foreach_instr_in_block_safe_rev(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 510 | list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 511 | |
| 512 | #define bi_foreach_instr_in_block_from(block, v, from) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 513 | list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 514 | |
| 515 | #define bi_foreach_instr_in_block_from_rev(block, v, from) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 516 | list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 517 | |
| 518 | #define bi_foreach_clause_in_block(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 519 | list_for_each_entry(bi_clause, v, &(block)->clauses, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 520 | |
| 521 | #define bi_foreach_instr_global(ctx, v) \ |
| 522 | bi_foreach_block(ctx, v_block) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 523 | bi_foreach_instr_in_block((bi_block *) v_block, v) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 524 | |
| 525 | #define bi_foreach_instr_global_safe(ctx, v) \ |
| 526 | bi_foreach_block(ctx, v_block) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 527 | bi_foreach_instr_in_block_safe((bi_block *) v_block, v) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 528 | |
| 529 | /* Based on set_foreach, expanded with automatic type casts */ |
| 530 | |
| 531 | #define bi_foreach_predecessor(blk, v) \ |
| 532 | struct set_entry *_entry_##v; \ |
| 533 | bi_block *v; \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 534 | for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \ |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 535 | v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \ |
| 536 | _entry_##v != NULL; \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 537 | _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \ |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 538 | v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL)) |
| 539 | |
| 540 | #define bi_foreach_src(ins, v) \ |
| 541 | for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v) |
| 542 | |
Alyssa Rosenzweig | 6e0479a | 2020-03-11 14:48:55 -0400 | [diff] [blame] | 543 | static inline bi_instruction * |
| 544 | bi_prev_op(bi_instruction *ins) |
| 545 | { |
| 546 | return list_last_entry(&(ins->link), bi_instruction, link); |
| 547 | } |
| 548 | |
| 549 | static inline bi_instruction * |
| 550 | bi_next_op(bi_instruction *ins) |
| 551 | { |
| 552 | return list_first_entry(&(ins->link), bi_instruction, link); |
| 553 | } |
| 554 | |
Alyssa Rosenzweig | 9269c85 | 2020-03-12 14:16:22 -0400 | [diff] [blame] | 555 | static inline pan_block * |
| 556 | pan_next_block(pan_block *block) |
| 557 | { |
| 558 | return list_first_entry(&(block->link), pan_block, link); |
| 559 | } |
| 560 | |
Alyssa Rosenzweig | 8e52206 | 2020-04-14 18:52:21 -0400 | [diff] [blame^] | 561 | /* Special functions */ |
| 562 | |
| 563 | void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr); |
| 564 | |
Alyssa Rosenzweig | 5d16a81 | 2020-03-04 09:19:06 -0500 | [diff] [blame] | 565 | /* BIR manipulation */ |
| 566 | |
| 567 | bool bi_has_outmod(bi_instruction *ins); |
| 568 | bool bi_has_source_mods(bi_instruction *ins); |
| 569 | bool bi_is_src_swizzled(bi_instruction *ins, unsigned s); |
Alyssa Rosenzweig | e94754a | 2020-03-11 14:40:01 -0400 | [diff] [blame] | 570 | bool bi_has_arg(bi_instruction *ins, unsigned arg); |
Alyssa Rosenzweig | e1d9533 | 2020-03-11 21:41:57 -0400 | [diff] [blame] | 571 | uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes); |
Alyssa Rosenzweig | 9458b01 | 2020-03-20 12:25:08 -0400 | [diff] [blame] | 572 | unsigned bi_get_component_count(bi_instruction *ins, unsigned s); |
Alyssa Rosenzweig | 908341e | 2020-03-20 11:52:33 -0400 | [diff] [blame] | 573 | unsigned bi_load32_components(bi_instruction *ins); |
Alyssa Rosenzweig | e623007 | 2020-03-11 14:46:01 -0400 | [diff] [blame] | 574 | uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node); |
Alyssa Rosenzweig | 11bccb0 | 2020-03-21 18:42:58 -0400 | [diff] [blame] | 575 | uint64_t bi_get_immediate(bi_instruction *ins, unsigned index); |
Alyssa Rosenzweig | 375a7d0 | 2020-03-27 14:40:30 -0400 | [diff] [blame] | 576 | bool bi_writes_component(bi_instruction *ins, unsigned comp); |
Alyssa Rosenzweig | 5d16a81 | 2020-03-04 09:19:06 -0500 | [diff] [blame] | 577 | |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 578 | /* BIR passes */ |
| 579 | |
Alyssa Rosenzweig | e0a51d5 | 2020-03-22 17:31:23 -0400 | [diff] [blame] | 580 | void bi_lower_combine(bi_context *ctx, bi_block *block); |
Alyssa Rosenzweig | 58f9171 | 2020-03-11 15:10:32 -0400 | [diff] [blame] | 581 | bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block); |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 582 | void bi_schedule(bi_context *ctx); |
Alyssa Rosenzweig | e8139ef | 2020-03-11 20:39:36 -0400 | [diff] [blame] | 583 | void bi_register_allocate(bi_context *ctx); |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 584 | |
Alyssa Rosenzweig | 56e1c60 | 2020-03-11 14:54:49 -0400 | [diff] [blame] | 585 | /* Liveness */ |
| 586 | |
| 587 | void bi_compute_liveness(bi_context *ctx); |
| 588 | void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max); |
| 589 | void bi_invalidate_liveness(bi_context *ctx); |
| 590 | bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src); |
| 591 | |
Alyssa Rosenzweig | 9269c85 | 2020-03-12 14:16:22 -0400 | [diff] [blame] | 592 | /* Code emit */ |
| 593 | |
| 594 | void bi_pack(bi_context *ctx, struct util_dynarray *emission); |
| 595 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 596 | #endif |