Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 1 | /* |
Daniele Castagna | 7a755de | 2016-12-16 17:32:30 -0500 | [diff] [blame] | 2 | * Copyright 2014 The Chromium OS Authors. All rights reserved. |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | */ |
| 6 | |
Gurchetan Singh | 46faf6b | 2016-08-05 14:40:07 -0700 | [diff] [blame] | 7 | #ifdef DRV_I915 |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 8 | |
| 9 | #include <errno.h> |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 10 | #include <i915_drm.h> |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 11 | #include <stdio.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 12 | #include <string.h> |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 13 | #include <sys/mman.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 14 | #include <xf86drm.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 15 | |
Gurchetan Singh | 46faf6b | 2016-08-05 14:40:07 -0700 | [diff] [blame] | 16 | #include "drv_priv.h" |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 17 | #include "helpers.h" |
| 18 | #include "util.h" |
| 19 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 20 | #define I915_CACHELINE_SIZE 64 |
| 21 | #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1) |
| 22 | |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 23 | static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888, |
| 24 | DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, |
| 25 | DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555, |
| 26 | DRM_FORMAT_XRGB8888 }; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 27 | |
Dongseong Hwang | 750e0b9 | 2017-06-07 15:17:25 -0700 | [diff] [blame] | 28 | static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12, |
| 29 | DRM_FORMAT_R8, DRM_FORMAT_UYVY, |
| 30 | DRM_FORMAT_YUYV }; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 31 | |
| 32 | static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID }; |
Gurchetan Singh | 179687e | 2016-10-28 10:07:35 -0700 | [diff] [blame] | 33 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 34 | struct i915_device { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 35 | uint32_t gen; |
| 36 | int32_t has_llc; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 37 | }; |
| 38 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 39 | static uint32_t i915_get_gen(int device_id) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 40 | { |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 41 | const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE, |
| 42 | 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 }; |
Stéphane Marchesin | a39dfde | 2014-09-15 15:38:25 -0700 | [diff] [blame] | 43 | unsigned i; |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 44 | for (i = 0; i < ARRAY_SIZE(gen3_ids); i++) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 45 | if (gen3_ids[i] == device_id) |
| 46 | return 3; |
| 47 | |
| 48 | return 4; |
| 49 | } |
| 50 | |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 51 | static int i915_add_kms_item(struct driver *drv, const struct kms_item *item) |
| 52 | { |
| 53 | uint32_t i; |
| 54 | struct combination *combo; |
| 55 | |
| 56 | /* |
| 57 | * Older hardware can't scanout Y-tiled formats. Newer devices can, and |
| 58 | * report this functionality via format modifiers. |
| 59 | */ |
Ege Mihmanli | 96b7d46 | 2017-09-19 20:13:26 -0700 | [diff] [blame] | 60 | for (i = 0; i < drv->combos.size; i++) { |
| 61 | combo = &drv->combos.data[i]; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 62 | if (combo->format != item->format) |
| 63 | continue; |
| 64 | |
| 65 | if (item->modifier == DRM_FORMAT_MOD_NONE && |
| 66 | combo->metadata.tiling == I915_TILING_X) { |
| 67 | /* |
| 68 | * FIXME: drv_query_kms() does not report the available modifiers |
| 69 | * yet, but we know that all hardware can scanout from X-tiled |
| 70 | * buffers, so let's add this to our combinations, except for |
| 71 | * cursor, which must not be tiled. |
| 72 | */ |
| 73 | combo->usage |= item->usage & ~BO_USE_CURSOR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 74 | } |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 75 | |
| 76 | if (combo->metadata.modifier == item->modifier) |
| 77 | combo->usage |= item->usage; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static int i915_add_combinations(struct driver *drv) |
| 84 | { |
| 85 | int ret; |
| 86 | uint32_t i, num_items; |
| 87 | struct kms_item *items; |
| 88 | struct format_metadata metadata; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 89 | uint64_t render_flags, texture_flags; |
| 90 | |
| 91 | render_flags = BO_USE_RENDER_MASK; |
| 92 | texture_flags = BO_USE_TEXTURE_MASK; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 93 | |
| 94 | metadata.tiling = I915_TILING_NONE; |
| 95 | metadata.priority = 1; |
| 96 | metadata.modifier = DRM_FORMAT_MOD_NONE; |
| 97 | |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 98 | ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 99 | &metadata, render_flags); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 100 | if (ret) |
| 101 | return ret; |
| 102 | |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 103 | ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), |
| 104 | &metadata, texture_flags); |
| 105 | if (ret) |
| 106 | return ret; |
| 107 | |
| 108 | ret = drv_add_combinations(drv, tileable_texture_source_formats, |
Dongseong Hwang | 3c5be5a | 2017-06-14 10:47:11 -0700 | [diff] [blame] | 109 | ARRAY_SIZE(tileable_texture_source_formats), &metadata, |
| 110 | texture_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 111 | if (ret) |
| 112 | return ret; |
| 113 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 114 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 115 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 116 | |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 117 | /* IPU3 camera ISP supports only NV12 output. */ |
| 118 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 119 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 120 | /* |
| 121 | * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots |
| 122 | * from camera. |
| 123 | */ |
| 124 | drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 125 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 126 | |
Gurchetan Singh | 43ba07f | 2017-08-03 18:34:05 -0700 | [diff] [blame] | 127 | render_flags &= ~BO_USE_RENDERSCRIPT; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 128 | render_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 129 | render_flags &= ~BO_USE_SW_READ_OFTEN; |
| 130 | render_flags &= ~BO_USE_LINEAR; |
| 131 | |
Gurchetan Singh | 43ba07f | 2017-08-03 18:34:05 -0700 | [diff] [blame] | 132 | texture_flags &= ~BO_USE_RENDERSCRIPT; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 133 | texture_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 134 | texture_flags &= ~BO_USE_SW_READ_OFTEN; |
| 135 | texture_flags &= ~BO_USE_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 136 | |
| 137 | metadata.tiling = I915_TILING_X; |
| 138 | metadata.priority = 2; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 139 | metadata.modifier = I915_FORMAT_MOD_X_TILED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 140 | |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 141 | ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 142 | &metadata, render_flags); |
| 143 | if (ret) |
| 144 | return ret; |
| 145 | |
| 146 | ret = drv_add_combinations(drv, tileable_texture_source_formats, |
| 147 | ARRAY_SIZE(tileable_texture_source_formats), &metadata, |
| 148 | texture_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 149 | if (ret) |
| 150 | return ret; |
| 151 | |
| 152 | metadata.tiling = I915_TILING_Y; |
| 153 | metadata.priority = 3; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 154 | metadata.modifier = I915_FORMAT_MOD_Y_TILED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 155 | |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 156 | ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 157 | &metadata, render_flags); |
| 158 | if (ret) |
| 159 | return ret; |
| 160 | |
| 161 | ret = drv_add_combinations(drv, tileable_texture_source_formats, |
| 162 | ARRAY_SIZE(tileable_texture_source_formats), &metadata, |
| 163 | texture_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 164 | if (ret) |
| 165 | return ret; |
| 166 | |
| 167 | items = drv_query_kms(drv, &num_items); |
| 168 | if (!items || !num_items) |
| 169 | return 0; |
| 170 | |
| 171 | for (i = 0; i < num_items; i++) { |
| 172 | ret = i915_add_kms_item(drv, &items[i]); |
| 173 | if (ret) { |
| 174 | free(items); |
| 175 | return ret; |
| 176 | } |
| 177 | } |
| 178 | |
| 179 | free(items); |
| 180 | return 0; |
| 181 | } |
| 182 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 183 | static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride, |
| 184 | uint32_t *aligned_height) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 185 | { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 186 | struct i915_device *i915 = bo->drv->priv; |
| 187 | uint32_t horizontal_alignment = 4; |
| 188 | uint32_t vertical_alignment = 4; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 189 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 190 | switch (tiling) { |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 191 | default: |
| 192 | case I915_TILING_NONE: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 193 | horizontal_alignment = 64; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 194 | break; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 195 | |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 196 | case I915_TILING_X: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 197 | horizontal_alignment = 512; |
| 198 | vertical_alignment = 8; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 199 | break; |
| 200 | |
| 201 | case I915_TILING_Y: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 202 | if (i915->gen == 3) { |
| 203 | horizontal_alignment = 512; |
| 204 | vertical_alignment = 8; |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 205 | } else { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 206 | horizontal_alignment = 128; |
| 207 | vertical_alignment = 32; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 208 | } |
| 209 | break; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 210 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 211 | |
Tomasz Figa | 33615a5 | 2017-07-29 15:37:58 +0900 | [diff] [blame] | 212 | /* |
| 213 | * The alignment calculated above is based on the full size luma plane and to have chroma |
| 214 | * planes properly aligned with subsampled formats, we need to multiply luma alignment by |
| 215 | * subsampling factor. |
| 216 | */ |
| 217 | switch (bo->format) { |
| 218 | case DRM_FORMAT_YVU420_ANDROID: |
| 219 | case DRM_FORMAT_YVU420: |
| 220 | horizontal_alignment *= 2; |
Gurchetan Singh | 7dcdff1 | 2017-09-14 13:04:11 -0700 | [diff] [blame] | 221 | /* Fall through */ |
Tomasz Figa | 33615a5 | 2017-07-29 15:37:58 +0900 | [diff] [blame] | 222 | case DRM_FORMAT_NV12: |
| 223 | vertical_alignment *= 2; |
| 224 | break; |
| 225 | } |
| 226 | |
Alexandre Courbot | 6a88284 | 2017-08-30 14:37:36 +0900 | [diff] [blame] | 227 | /* |
| 228 | * For multi-planar formats we must be aligned to 16 |
| 229 | */ |
| 230 | if (bo->num_planes > 1) |
| 231 | vertical_alignment = MAX(vertical_alignment, 16); |
| 232 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 233 | *aligned_height = ALIGN(bo->height, vertical_alignment); |
| 234 | if (i915->gen > 3) { |
| 235 | *stride = ALIGN(*stride, horizontal_alignment); |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 236 | } else { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 237 | while (*stride > horizontal_alignment) |
| 238 | horizontal_alignment <<= 1; |
| 239 | |
| 240 | *stride = horizontal_alignment; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 241 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 242 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 243 | if (i915->gen <= 3 && *stride > 8192) |
| 244 | return -EINVAL; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 245 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 246 | return 0; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 247 | } |
| 248 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 249 | static void i915_clflush(void *start, size_t size) |
| 250 | { |
| 251 | void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK); |
| 252 | void *end = (void *)((uintptr_t)start + size); |
| 253 | |
| 254 | __builtin_ia32_mfence(); |
| 255 | while (p < end) { |
| 256 | __builtin_ia32_clflush(p); |
| 257 | p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE); |
| 258 | } |
| 259 | } |
| 260 | |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 261 | static int i915_init(struct driver *drv) |
| 262 | { |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 263 | int ret; |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 264 | int device_id; |
| 265 | struct i915_device *i915; |
| 266 | drm_i915_getparam_t get_param; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 267 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 268 | i915 = calloc(1, sizeof(*i915)); |
| 269 | if (!i915) |
| 270 | return -ENOMEM; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 271 | |
| 272 | memset(&get_param, 0, sizeof(get_param)); |
| 273 | get_param.param = I915_PARAM_CHIPSET_ID; |
| 274 | get_param.value = &device_id; |
| 275 | ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); |
| 276 | if (ret) { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 277 | fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n"); |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 278 | free(i915); |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 279 | return -EINVAL; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 280 | } |
| 281 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 282 | i915->gen = i915_get_gen(device_id); |
| 283 | |
| 284 | memset(&get_param, 0, sizeof(get_param)); |
| 285 | get_param.param = I915_PARAM_HAS_LLC; |
| 286 | get_param.value = &i915->has_llc; |
| 287 | ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); |
| 288 | if (ret) { |
| 289 | fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n"); |
| 290 | free(i915); |
| 291 | return -EINVAL; |
| 292 | } |
| 293 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 294 | drv->priv = i915; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 295 | |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 296 | return i915_add_combinations(drv); |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 297 | } |
| 298 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 299 | static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
Gurchetan Singh | 60ee583 | 2017-09-28 16:25:12 -0700 | [diff] [blame^] | 300 | uint64_t flags) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 301 | { |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 302 | int ret; |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 303 | size_t plane; |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 304 | uint32_t stride; |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 305 | struct drm_i915_gem_create gem_create; |
| 306 | struct drm_i915_gem_set_tiling gem_set_tiling; |
Tomasz Figa | 7ec0788 | 2017-06-23 18:04:02 +0900 | [diff] [blame] | 307 | struct combination *combo; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 308 | |
Tomasz Figa | 7ec0788 | 2017-06-23 18:04:02 +0900 | [diff] [blame] | 309 | combo = drv_get_combination(bo->drv, format, flags); |
| 310 | if (!combo) |
| 311 | return -EINVAL; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 312 | |
Tomasz Figa | 7ec0788 | 2017-06-23 18:04:02 +0900 | [diff] [blame] | 313 | bo->tiling = combo->metadata.tiling; |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 314 | |
| 315 | stride = drv_stride_from_format(format, width, 0); |
Gurchetan Singh | 507f5dd | 2017-03-16 13:14:30 -0700 | [diff] [blame] | 316 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 317 | ret = i915_align_dimensions(bo, bo->tiling, &stride, &height); |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 318 | if (ret) |
| 319 | return ret; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 320 | |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 321 | /* |
Tomasz Figa | d846de6 | 2017-07-29 15:47:54 +0900 | [diff] [blame] | 322 | * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep |
| 323 | * total size as with aligned height to ensure enough padding space after each plane to |
| 324 | * satisfy GPU alignment requirements. |
| 325 | * |
| 326 | * We do it by first calling drv_bo_from_format() with aligned height and |
| 327 | * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates |
| 328 | * and then calling it again with requested parameters. |
| 329 | * |
| 330 | * This relies on the fact that i965 driver uses separate surfaces for each plane and |
| 331 | * contents of padding bytes is not affected, as it is only used to satisfy GPU cache |
| 332 | * requests. |
| 333 | * |
| 334 | * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside |
| 335 | * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8. |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 336 | */ |
Tomasz Figa | d846de6 | 2017-07-29 15:47:54 +0900 | [diff] [blame] | 337 | if (format == DRM_FORMAT_YVU420_ANDROID) { |
| 338 | uint32_t unaligned_height = bo->height; |
| 339 | size_t total_size; |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 340 | |
Tomasz Figa | d846de6 | 2017-07-29 15:47:54 +0900 | [diff] [blame] | 341 | drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420); |
| 342 | total_size = bo->total_size; |
| 343 | drv_bo_from_format(bo, stride, unaligned_height, format); |
| 344 | bo->total_size = total_size; |
| 345 | } else { |
| 346 | drv_bo_from_format(bo, stride, height, format); |
| 347 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 348 | |
Tomasz Figa | 581f3a5 | 2017-07-23 15:02:19 +0900 | [diff] [blame] | 349 | /* |
| 350 | * Quoting Mesa ISL library: |
| 351 | * |
| 352 | * - For linear surfaces, additional padding of 64 bytes is required at |
| 353 | * the bottom of the surface. This is in addition to the padding |
| 354 | * required above. |
| 355 | */ |
| 356 | if (bo->tiling == I915_TILING_NONE) |
| 357 | bo->total_size += 64; |
| 358 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 359 | memset(&gem_create, 0, sizeof(gem_create)); |
| 360 | gem_create.size = bo->total_size; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 361 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 362 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create); |
| 363 | if (ret) { |
| 364 | fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", |
| 365 | gem_create.size); |
| 366 | return ret; |
Ilja H. Friedel | f9d2ab7 | 2015-04-09 14:08:36 -0700 | [diff] [blame] | 367 | } |
Gurchetan Singh | 83dc4fb | 2016-07-19 15:52:33 -0700 | [diff] [blame] | 368 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 369 | for (plane = 0; plane < bo->num_planes; plane++) |
| 370 | bo->handles[plane].u32 = gem_create.handle; |
Daniel Nicoara | 1de26dc | 2014-09-25 18:53:19 -0400 | [diff] [blame] | 371 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 372 | memset(&gem_set_tiling, 0, sizeof(gem_set_tiling)); |
| 373 | gem_set_tiling.handle = bo->handles[0].u32; |
| 374 | gem_set_tiling.tiling_mode = bo->tiling; |
| 375 | gem_set_tiling.stride = bo->strides[0]; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 376 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 377 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling); |
| 378 | if (ret) { |
| 379 | struct drm_gem_close gem_close; |
| 380 | memset(&gem_close, 0, sizeof(gem_close)); |
| 381 | gem_close.handle = bo->handles[0].u32; |
| 382 | drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 383 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 384 | fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno); |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 385 | return -errno; |
| 386 | } |
| 387 | |
| 388 | return 0; |
| 389 | } |
| 390 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 391 | static void i915_close(struct driver *drv) |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 392 | { |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 393 | free(drv->priv); |
| 394 | drv->priv = NULL; |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 395 | } |
| 396 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 397 | static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data) |
| 398 | { |
| 399 | int ret; |
| 400 | struct drm_i915_gem_get_tiling gem_get_tiling; |
| 401 | |
| 402 | ret = drv_prime_bo_import(bo, data); |
| 403 | if (ret) |
| 404 | return ret; |
| 405 | |
| 406 | /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */ |
| 407 | memset(&gem_get_tiling, 0, sizeof(gem_get_tiling)); |
| 408 | gem_get_tiling.handle = bo->handles[0].u32; |
| 409 | |
| 410 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling); |
| 411 | if (ret) { |
Joe Kniss | 9e5d12a | 2017-06-29 11:54:22 -0700 | [diff] [blame] | 412 | drv_gem_bo_destroy(bo); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 413 | fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed."); |
| 414 | return ret; |
| 415 | } |
| 416 | |
| 417 | bo->tiling = gem_get_tiling.tiling_mode; |
| 418 | return 0; |
| 419 | } |
| 420 | |
Joe Kniss | 6570585 | 2017-06-29 15:02:46 -0700 | [diff] [blame] | 421 | static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot) |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 422 | { |
| 423 | int ret; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 424 | void *addr; |
| 425 | struct drm_i915_gem_set_domain set_domain; |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 426 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 427 | memset(&set_domain, 0, sizeof(set_domain)); |
| 428 | set_domain.handle = bo->handles[0].u32; |
| 429 | if (bo->tiling == I915_TILING_NONE) { |
| 430 | struct drm_i915_gem_mmap gem_map; |
| 431 | memset(&gem_map, 0, sizeof(gem_map)); |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 432 | |
Gurchetan Singh | 5af2023 | 2017-09-19 15:10:58 -0700 | [diff] [blame] | 433 | if ((bo->flags & BO_USE_SCANOUT) && !(bo->flags & BO_USE_RENDERSCRIPT)) |
| 434 | gem_map.flags = I915_MMAP_WC; |
| 435 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 436 | gem_map.handle = bo->handles[0].u32; |
| 437 | gem_map.offset = 0; |
| 438 | gem_map.size = bo->total_size; |
| 439 | |
| 440 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map); |
| 441 | if (ret) { |
| 442 | fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n"); |
| 443 | return MAP_FAILED; |
| 444 | } |
| 445 | |
| 446 | addr = (void *)(uintptr_t)gem_map.addr_ptr; |
| 447 | set_domain.read_domains = I915_GEM_DOMAIN_CPU; |
| 448 | set_domain.write_domain = I915_GEM_DOMAIN_CPU; |
| 449 | |
| 450 | } else { |
| 451 | struct drm_i915_gem_mmap_gtt gem_map; |
| 452 | memset(&gem_map, 0, sizeof(gem_map)); |
| 453 | |
| 454 | gem_map.handle = bo->handles[0].u32; |
| 455 | |
| 456 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map); |
| 457 | if (ret) { |
| 458 | fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n"); |
| 459 | return MAP_FAILED; |
| 460 | } |
| 461 | |
Joe Kniss | 6570585 | 2017-06-29 15:02:46 -0700 | [diff] [blame] | 462 | addr = mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.offset); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 463 | set_domain.read_domains = I915_GEM_DOMAIN_GTT; |
| 464 | set_domain.write_domain = I915_GEM_DOMAIN_GTT; |
| 465 | } |
| 466 | |
| 467 | if (addr == MAP_FAILED) { |
| 468 | fprintf(stderr, "drv: i915 GEM mmap failed\n"); |
| 469 | return addr; |
| 470 | } |
| 471 | |
| 472 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain); |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 473 | if (ret) { |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 474 | fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n"); |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 475 | return MAP_FAILED; |
| 476 | } |
| 477 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 478 | data->length = bo->total_size; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 479 | return addr; |
| 480 | } |
Gurchetan Singh | 1a31e60 | 2016-10-06 10:58:00 -0700 | [diff] [blame] | 481 | |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 482 | static int i915_bo_flush(struct bo *bo, struct map_info *data) |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 483 | { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 484 | struct i915_device *i915 = bo->drv->priv; |
| 485 | if (!i915->has_llc && bo->tiling == I915_TILING_NONE) |
| 486 | i915_clflush(data->addr, data->length); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 487 | |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 488 | return 0; |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 489 | } |
| 490 | |
Tomasz Figa | ce1ae02 | 2017-07-05 18:15:06 +0900 | [diff] [blame] | 491 | static uint32_t i915_resolve_format(uint32_t format, uint64_t usage) |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 492 | { |
| 493 | switch (format) { |
Gurchetan Singh | f3b22da | 2016-11-21 10:46:38 -0800 | [diff] [blame] | 494 | case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 495 | /* KBL camera subsystem requires NV12. */ |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 496 | if (usage & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 497 | return DRM_FORMAT_NV12; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 498 | /*HACK: See b/28671744 */ |
Gurchetan Singh | f3b22da | 2016-11-21 10:46:38 -0800 | [diff] [blame] | 499 | return DRM_FORMAT_XBGR8888; |
| 500 | case DRM_FORMAT_FLEX_YCbCr_420_888: |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 501 | /* KBL camera subsystem requires NV12. */ |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 502 | if (usage & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 503 | return DRM_FORMAT_NV12; |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 504 | return DRM_FORMAT_YVU420; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 505 | default: |
| 506 | return format; |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 507 | } |
| 508 | } |
| 509 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 510 | struct backend backend_i915 = { |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 511 | .name = "i915", |
Gurchetan Singh | d7c84fd | 2016-08-16 18:18:24 -0700 | [diff] [blame] | 512 | .init = i915_init, |
| 513 | .close = i915_close, |
| 514 | .bo_create = i915_bo_create, |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 515 | .bo_destroy = drv_gem_bo_destroy, |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 516 | .bo_import = i915_bo_import, |
Gurchetan Singh | d7c84fd | 2016-08-16 18:18:24 -0700 | [diff] [blame] | 517 | .bo_map = i915_bo_map, |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 518 | .bo_unmap = drv_bo_munmap, |
| 519 | .bo_flush = i915_bo_flush, |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 520 | .resolve_format = i915_resolve_format, |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 521 | }; |
| 522 | |
| 523 | #endif |