sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin guest_x86_toIR.c ---*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 4 | /*--------------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2010 OpenWorks LLP |
| 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 36 | /* Translates x86 code to IR. */ |
| 37 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 38 | /* TODO: |
sewardj | 45f1ff8 | 2005-05-05 12:04:14 +0000 | [diff] [blame] | 39 | |
sewardj | 3b3eacd | 2005-08-24 10:01:36 +0000 | [diff] [blame] | 40 | All Puts to CC_OP/CC_DEP1/CC_DEP2/CC_NDEP should really be checked |
| 41 | to ensure a 32-bit value is being written. |
| 42 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 43 | FUCOMI(P): what happens to A and S flags? Currently are forced |
| 44 | to zero. |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 45 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 46 | x87 FP Limitations: |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 47 | |
| 48 | * all arithmetic done at 64 bits |
| 49 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 50 | * no FP exceptions, except for handling stack over/underflow |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 51 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 52 | * FP rounding mode observed only for float->int conversions |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 53 | and int->float conversions which could lose accuracy, and |
| 54 | for float-to-float rounding. For all other operations, |
| 55 | round-to-nearest is used, regardless. |
| 56 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 57 | * FP sin/cos/tan/sincos: C2 flag is always cleared. IOW the |
| 58 | simulation claims the argument is in-range (-2^63 <= arg <= 2^63) |
| 59 | even when it isn't. |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 60 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 61 | * some of the FCOM cases could do with testing -- not convinced |
| 62 | that the args are the right way round. |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 63 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 64 | * FSAVE does not re-initialise the FPU; it should do |
| 65 | |
| 66 | * FINIT not only initialises the FPU environment, it also |
| 67 | zeroes all the FP registers. It should leave the registers |
| 68 | unchanged. |
| 69 | |
sewardj | cb2c99d | 2004-12-17 19:14:24 +0000 | [diff] [blame] | 70 | SAHF should cause eflags[1] == 1, and in fact it produces 0. As |
| 71 | per Intel docs this bit has no meaning anyway. Since PUSHF is the |
| 72 | only way to observe eflags[1], a proper fix would be to make that |
| 73 | bit be set by PUSHF. |
| 74 | |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 75 | The state of %eflags.AC (alignment check, bit 18) is recorded by |
| 76 | the simulation (viz, if you set it with popf then a pushf produces |
| 77 | the value you set it to), but it is otherwise ignored. In |
| 78 | particular, setting it to 1 does NOT cause alignment checking to |
| 79 | happen. Programs that set it to 1 and then rely on the resulting |
| 80 | SIGBUSs to inform them of misaligned accesses will not work. |
| 81 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 82 | Implementation of sysenter is necessarily partial. sysenter is a |
| 83 | kind of system call entry. When doing a sysenter, the return |
| 84 | address is not known -- that is something that is beyond Vex's |
| 85 | knowledge. So the generated IR forces a return to the scheduler, |
| 86 | which can do what it likes to simulate the systenter, but it MUST |
| 87 | set this thread's guest_EIP field with the continuation address |
| 88 | before resuming execution. If that doesn't happen, the thread will |
| 89 | jump to address zero, which is probably fatal. |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 90 | |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 91 | This module uses global variables and so is not MT-safe (if that |
sewardj | e395ae8 | 2005-02-26 02:00:50 +0000 | [diff] [blame] | 92 | should ever become relevant). |
| 93 | |
| 94 | The delta values are 32-bit ints, not 64-bit ints. That means |
| 95 | this module may not work right if run on a 64-bit host. That should |
| 96 | be fixed properly, really -- if anyone ever wants to use Vex to |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 97 | translate x86 code for execution on a 64-bit host. |
| 98 | |
| 99 | casLE (implementation of lock-prefixed insns) and rep-prefixed |
| 100 | insns: the side-exit back to the start of the insn is done with |
| 101 | Ijk_Boring. This is quite wrong, it should be done with |
| 102 | Ijk_NoRedir, since otherwise the side exit, which is intended to |
| 103 | restart the instruction for whatever reason, could go somewhere |
| 104 | entirely else. Doing it right (with Ijk_NoRedir jumps) would make |
| 105 | no-redir jumps performance critical, at least for rep-prefixed |
| 106 | instructions, since all iterations thereof would involve such a |
| 107 | jump. It's not such a big deal with casLE since the side exit is |
| 108 | only taken if the CAS fails, that is, the location is contended, |
| 109 | which is relatively unlikely. |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 110 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 111 | XXXX: Nov 2009: handling of SWP on ARM suffers from the same |
| 112 | problem. |
| 113 | |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 114 | Note also, the test for CAS success vs failure is done using |
| 115 | Iop_CasCmp{EQ,NE}{8,16,32,64} rather than the ordinary |
| 116 | Iop_Cmp{EQ,NE} equivalents. This is so as to tell Memcheck that it |
| 117 | shouldn't definedness-check these comparisons. See |
| 118 | COMMENT_ON_CasCmpEQ in memcheck/mc_translate.c for |
| 119 | background/rationale. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 120 | */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 121 | |
sewardj | 9f8a395 | 2005-04-06 10:27:11 +0000 | [diff] [blame] | 122 | /* Performance holes: |
| 123 | |
| 124 | - fcom ; fstsw %ax ; sahf |
| 125 | sahf does not update the O flag (sigh) and so O needs to |
| 126 | be computed. This is done expensively; it would be better |
| 127 | to have a calculate_eflags_o helper. |
| 128 | |
| 129 | - emwarns; some FP codes can generate huge numbers of these |
| 130 | if the fpucw is changed in an inner loop. It would be |
| 131 | better for the guest state to have an emwarn-enable reg |
| 132 | which can be set zero or nonzero. If it is zero, emwarns |
| 133 | are not flagged, and instead control just flows all the |
| 134 | way through bbs as usual. |
| 135 | */ |
| 136 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 137 | /* "Special" instructions. |
| 138 | |
| 139 | This instruction decoder can decode three special instructions |
| 140 | which mean nothing natively (are no-ops as far as regs/mem are |
| 141 | concerned) but have meaning for supporting Valgrind. A special |
| 142 | instruction is flagged by the 12-byte preamble C1C703 C1C70D C1C71D |
| 143 | C1C713 (in the standard interpretation, that means: roll $3, %edi; |
| 144 | roll $13, %edi; roll $29, %edi; roll $19, %edi). Following that, |
| 145 | one of the following 3 are allowed (standard interpretation in |
| 146 | parentheses): |
| 147 | |
| 148 | 87DB (xchgl %ebx,%ebx) %EDX = client_request ( %EAX ) |
| 149 | 87C9 (xchgl %ecx,%ecx) %EAX = guest_NRADDR |
| 150 | 87D2 (xchgl %edx,%edx) call-noredir *%EAX |
| 151 | |
| 152 | Any other bytes following the 12-byte preamble are illegal and |
| 153 | constitute a failure in instruction decoding. This all assumes |
| 154 | that the preamble will never occur except in specific code |
| 155 | fragments designed for Valgrind to catch. |
| 156 | |
| 157 | No prefixes may precede a "Special" instruction. |
| 158 | */ |
| 159 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 160 | /* LOCK prefixed instructions. These are translated using IR-level |
| 161 | CAS statements (IRCAS) and are believed to preserve atomicity, even |
| 162 | from the point of view of some other process racing against a |
| 163 | simulated one (presumably they communicate via a shared memory |
| 164 | segment). |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 165 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 166 | Handlers which are aware of LOCK prefixes are: |
| 167 | dis_op2_G_E (add, or, adc, sbb, and, sub, xor) |
| 168 | dis_cmpxchg_G_E (cmpxchg) |
| 169 | dis_Grp1 (add, or, adc, sbb, and, sub, xor) |
| 170 | dis_Grp3 (not, neg) |
| 171 | dis_Grp4 (inc, dec) |
| 172 | dis_Grp5 (inc, dec) |
| 173 | dis_Grp8_Imm (bts, btc, btr) |
| 174 | dis_bt_G_E (bts, btc, btr) |
| 175 | dis_xadd_G_E (xadd) |
| 176 | */ |
| 177 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 178 | |
| 179 | #include "libvex_basictypes.h" |
| 180 | #include "libvex_ir.h" |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 181 | #include "libvex.h" |
sewardj | f6dc3ce | 2004-10-19 01:03:46 +0000 | [diff] [blame] | 182 | #include "libvex_guest_x86.h" |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 183 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 184 | #include "main_util.h" |
| 185 | #include "main_globals.h" |
| 186 | #include "guest_generic_bb_to_IR.h" |
| 187 | #include "guest_generic_x87.h" |
| 188 | #include "guest_x86_defs.h" |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 189 | |
| 190 | |
| 191 | /*------------------------------------------------------------*/ |
| 192 | /*--- Globals ---*/ |
| 193 | /*------------------------------------------------------------*/ |
| 194 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 195 | /* These are set at the start of the translation of an insn, right |
| 196 | down in disInstr_X86, so that we don't have to pass them around |
| 197 | endlessly. They are all constant during the translation of any |
| 198 | given insn. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 199 | |
| 200 | /* We need to know this to do sub-register accesses correctly. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 201 | static Bool host_is_bigendian; |
| 202 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 203 | /* Pointer to the guest code area (points to start of BB, not to the |
| 204 | insn being processed). */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 205 | static UChar* guest_code; |
| 206 | |
| 207 | /* The guest address corresponding to guest_code[0]. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 208 | static Addr32 guest_EIP_bbstart; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 209 | |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 210 | /* The guest address for the instruction currently being |
| 211 | translated. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 212 | static Addr32 guest_EIP_curr_instr; |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 213 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 214 | /* The IRSB* into which we're generating code. */ |
| 215 | static IRSB* irsb; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 216 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 217 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 218 | /*------------------------------------------------------------*/ |
| 219 | /*--- Debugging output ---*/ |
| 220 | /*------------------------------------------------------------*/ |
| 221 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 222 | #define DIP(format, args...) \ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 223 | if (vex_traceflags & VEX_TRACE_FE) \ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 224 | vex_printf(format, ## args) |
| 225 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 226 | #define DIS(buf, format, args...) \ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 227 | if (vex_traceflags & VEX_TRACE_FE) \ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 228 | vex_sprintf(buf, format, ## args) |
| 229 | |
| 230 | |
| 231 | /*------------------------------------------------------------*/ |
sewardj | dcc85fc | 2004-10-26 13:26:20 +0000 | [diff] [blame] | 232 | /*--- Offsets of various parts of the x86 guest state. ---*/ |
| 233 | /*------------------------------------------------------------*/ |
| 234 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 235 | #define OFFB_EAX offsetof(VexGuestX86State,guest_EAX) |
| 236 | #define OFFB_EBX offsetof(VexGuestX86State,guest_EBX) |
| 237 | #define OFFB_ECX offsetof(VexGuestX86State,guest_ECX) |
| 238 | #define OFFB_EDX offsetof(VexGuestX86State,guest_EDX) |
| 239 | #define OFFB_ESP offsetof(VexGuestX86State,guest_ESP) |
| 240 | #define OFFB_EBP offsetof(VexGuestX86State,guest_EBP) |
| 241 | #define OFFB_ESI offsetof(VexGuestX86State,guest_ESI) |
| 242 | #define OFFB_EDI offsetof(VexGuestX86State,guest_EDI) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 243 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 244 | #define OFFB_EIP offsetof(VexGuestX86State,guest_EIP) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 245 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 246 | #define OFFB_CC_OP offsetof(VexGuestX86State,guest_CC_OP) |
| 247 | #define OFFB_CC_DEP1 offsetof(VexGuestX86State,guest_CC_DEP1) |
| 248 | #define OFFB_CC_DEP2 offsetof(VexGuestX86State,guest_CC_DEP2) |
| 249 | #define OFFB_CC_NDEP offsetof(VexGuestX86State,guest_CC_NDEP) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 250 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 251 | #define OFFB_FPREGS offsetof(VexGuestX86State,guest_FPREG[0]) |
| 252 | #define OFFB_FPTAGS offsetof(VexGuestX86State,guest_FPTAG[0]) |
| 253 | #define OFFB_DFLAG offsetof(VexGuestX86State,guest_DFLAG) |
| 254 | #define OFFB_IDFLAG offsetof(VexGuestX86State,guest_IDFLAG) |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 255 | #define OFFB_ACFLAG offsetof(VexGuestX86State,guest_ACFLAG) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 256 | #define OFFB_FTOP offsetof(VexGuestX86State,guest_FTOP) |
| 257 | #define OFFB_FC3210 offsetof(VexGuestX86State,guest_FC3210) |
| 258 | #define OFFB_FPROUND offsetof(VexGuestX86State,guest_FPROUND) |
| 259 | |
| 260 | #define OFFB_CS offsetof(VexGuestX86State,guest_CS) |
| 261 | #define OFFB_DS offsetof(VexGuestX86State,guest_DS) |
| 262 | #define OFFB_ES offsetof(VexGuestX86State,guest_ES) |
| 263 | #define OFFB_FS offsetof(VexGuestX86State,guest_FS) |
| 264 | #define OFFB_GS offsetof(VexGuestX86State,guest_GS) |
| 265 | #define OFFB_SS offsetof(VexGuestX86State,guest_SS) |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 266 | #define OFFB_LDT offsetof(VexGuestX86State,guest_LDT) |
| 267 | #define OFFB_GDT offsetof(VexGuestX86State,guest_GDT) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 268 | |
| 269 | #define OFFB_SSEROUND offsetof(VexGuestX86State,guest_SSEROUND) |
| 270 | #define OFFB_XMM0 offsetof(VexGuestX86State,guest_XMM0) |
| 271 | #define OFFB_XMM1 offsetof(VexGuestX86State,guest_XMM1) |
| 272 | #define OFFB_XMM2 offsetof(VexGuestX86State,guest_XMM2) |
| 273 | #define OFFB_XMM3 offsetof(VexGuestX86State,guest_XMM3) |
| 274 | #define OFFB_XMM4 offsetof(VexGuestX86State,guest_XMM4) |
| 275 | #define OFFB_XMM5 offsetof(VexGuestX86State,guest_XMM5) |
| 276 | #define OFFB_XMM6 offsetof(VexGuestX86State,guest_XMM6) |
| 277 | #define OFFB_XMM7 offsetof(VexGuestX86State,guest_XMM7) |
| 278 | |
| 279 | #define OFFB_EMWARN offsetof(VexGuestX86State,guest_EMWARN) |
sewardj | dcc85fc | 2004-10-26 13:26:20 +0000 | [diff] [blame] | 280 | |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 281 | #define OFFB_TISTART offsetof(VexGuestX86State,guest_TISTART) |
| 282 | #define OFFB_TILEN offsetof(VexGuestX86State,guest_TILEN) |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 283 | #define OFFB_NRADDR offsetof(VexGuestX86State,guest_NRADDR) |
| 284 | |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 285 | #define OFFB_IP_AT_SYSCALL offsetof(VexGuestX86State,guest_IP_AT_SYSCALL) |
| 286 | |
sewardj | dcc85fc | 2004-10-26 13:26:20 +0000 | [diff] [blame] | 287 | |
| 288 | /*------------------------------------------------------------*/ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 289 | /*--- Helper bits and pieces for deconstructing the ---*/ |
| 290 | /*--- x86 insn stream. ---*/ |
| 291 | /*------------------------------------------------------------*/ |
| 292 | |
| 293 | /* This is the Intel register encoding -- integer regs. */ |
| 294 | #define R_EAX 0 |
| 295 | #define R_ECX 1 |
| 296 | #define R_EDX 2 |
| 297 | #define R_EBX 3 |
| 298 | #define R_ESP 4 |
| 299 | #define R_EBP 5 |
| 300 | #define R_ESI 6 |
| 301 | #define R_EDI 7 |
| 302 | |
| 303 | #define R_AL (0+R_EAX) |
| 304 | #define R_AH (4+R_EAX) |
| 305 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 306 | /* This is the Intel register encoding -- segment regs. */ |
| 307 | #define R_ES 0 |
| 308 | #define R_CS 1 |
| 309 | #define R_SS 2 |
| 310 | #define R_DS 3 |
| 311 | #define R_FS 4 |
| 312 | #define R_GS 5 |
| 313 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 314 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 315 | /* Add a statement to the list held by "irbb". */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 316 | static void stmt ( IRStmt* st ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 317 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 318 | addStmtToIRSB( irsb, st ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | /* Generate a new temporary of the given type. */ |
| 322 | static IRTemp newTemp ( IRType ty ) |
| 323 | { |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 324 | vassert(isPlausibleIRType(ty)); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 325 | return newIRTemp( irsb->tyenv, ty ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 326 | } |
| 327 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 328 | /* Various simple conversions */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 329 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 330 | static UInt extend_s_8to32( UInt x ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 331 | { |
| 332 | return (UInt)((((Int)x) << 24) >> 24); |
| 333 | } |
| 334 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 335 | static UInt extend_s_16to32 ( UInt x ) |
| 336 | { |
| 337 | return (UInt)((((Int)x) << 16) >> 16); |
| 338 | } |
| 339 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 340 | /* Fetch a byte from the guest insn stream. */ |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 341 | static UChar getIByte ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 342 | { |
| 343 | return guest_code[delta]; |
| 344 | } |
| 345 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 346 | /* Extract the reg field from a modRM byte. */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 347 | static Int gregOfRM ( UChar mod_reg_rm ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 348 | { |
| 349 | return (Int)( (mod_reg_rm >> 3) & 7 ); |
| 350 | } |
| 351 | |
| 352 | /* Figure out whether the mod and rm parts of a modRM byte refer to a |
| 353 | register or memory. If so, the byte will have the form 11XXXYYY, |
| 354 | where YYY is the register number. */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 355 | static Bool epartIsReg ( UChar mod_reg_rm ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 356 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 357 | return toBool(0xC0 == (mod_reg_rm & 0xC0)); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | /* ... and extract the register number ... */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 361 | static Int eregOfRM ( UChar mod_reg_rm ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 362 | { |
| 363 | return (Int)(mod_reg_rm & 0x7); |
| 364 | } |
| 365 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 366 | /* Get a 8/16/32-bit unsigned value out of the insn stream. */ |
| 367 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 368 | static UChar getUChar ( Int delta ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 369 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 370 | UChar v = guest_code[delta+0]; |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 371 | return toUChar(v); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 372 | } |
| 373 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 374 | static UInt getUDisp16 ( Int delta ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 375 | { |
| 376 | UInt v = guest_code[delta+1]; v <<= 8; |
| 377 | v |= guest_code[delta+0]; |
| 378 | return v & 0xFFFF; |
| 379 | } |
| 380 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 381 | static UInt getUDisp32 ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 382 | { |
| 383 | UInt v = guest_code[delta+3]; v <<= 8; |
| 384 | v |= guest_code[delta+2]; v <<= 8; |
| 385 | v |= guest_code[delta+1]; v <<= 8; |
| 386 | v |= guest_code[delta+0]; |
| 387 | return v; |
| 388 | } |
| 389 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 390 | static UInt getUDisp ( Int size, Int delta ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 391 | { |
| 392 | switch (size) { |
| 393 | case 4: return getUDisp32(delta); |
| 394 | case 2: return getUDisp16(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 395 | case 1: return (UInt)getUChar(delta); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 396 | default: vpanic("getUDisp(x86)"); |
| 397 | } |
| 398 | return 0; /*notreached*/ |
| 399 | } |
| 400 | |
| 401 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 402 | /* Get a byte value out of the insn stream and sign-extend to 32 |
| 403 | bits. */ |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 404 | static UInt getSDisp8 ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 405 | { |
| 406 | return extend_s_8to32( (UInt) (guest_code[delta]) ); |
| 407 | } |
| 408 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 409 | static UInt getSDisp16 ( Int delta0 ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 410 | { |
| 411 | UChar* eip = (UChar*)(&guest_code[delta0]); |
| 412 | UInt d = *eip++; |
| 413 | d |= ((*eip++) << 8); |
| 414 | return extend_s_16to32(d); |
| 415 | } |
| 416 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 417 | static UInt getSDisp ( Int size, Int delta ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 418 | { |
| 419 | switch (size) { |
| 420 | case 4: return getUDisp32(delta); |
| 421 | case 2: return getSDisp16(delta); |
| 422 | case 1: return getSDisp8(delta); |
| 423 | default: vpanic("getSDisp(x86)"); |
| 424 | } |
| 425 | return 0; /*notreached*/ |
| 426 | } |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 427 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 428 | |
| 429 | /*------------------------------------------------------------*/ |
| 430 | /*--- Helpers for constructing IR. ---*/ |
| 431 | /*------------------------------------------------------------*/ |
| 432 | |
| 433 | /* Create a 1/2/4 byte read of an x86 integer registers. For 16/8 bit |
| 434 | register references, we need to take the host endianness into |
| 435 | account. Supplied value is 0 .. 7 and in the Intel instruction |
| 436 | encoding. */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 437 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 438 | static IRType szToITy ( Int n ) |
| 439 | { |
| 440 | switch (n) { |
| 441 | case 1: return Ity_I8; |
| 442 | case 2: return Ity_I16; |
| 443 | case 4: return Ity_I32; |
| 444 | default: vpanic("szToITy(x86)"); |
| 445 | } |
| 446 | } |
| 447 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 448 | /* On a little-endian host, less significant bits of the guest |
| 449 | registers are at lower addresses. Therefore, if a reference to a |
| 450 | register low half has the safe guest state offset as a reference to |
| 451 | the full register. |
| 452 | */ |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 453 | static Int integerGuestRegOffset ( Int sz, UInt archreg ) |
| 454 | { |
| 455 | vassert(archreg < 8); |
| 456 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 457 | /* Correct for little-endian host only. */ |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 458 | vassert(!host_is_bigendian); |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 459 | |
| 460 | if (sz == 4 || sz == 2 || (sz == 1 && archreg < 4)) { |
| 461 | switch (archreg) { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 462 | case R_EAX: return OFFB_EAX; |
| 463 | case R_EBX: return OFFB_EBX; |
| 464 | case R_ECX: return OFFB_ECX; |
| 465 | case R_EDX: return OFFB_EDX; |
| 466 | case R_ESI: return OFFB_ESI; |
| 467 | case R_EDI: return OFFB_EDI; |
| 468 | case R_ESP: return OFFB_ESP; |
| 469 | case R_EBP: return OFFB_EBP; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 470 | default: vpanic("integerGuestRegOffset(x86,le)(4,2)"); |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | vassert(archreg >= 4 && archreg < 8 && sz == 1); |
| 475 | switch (archreg-4) { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 476 | case R_EAX: return 1+ OFFB_EAX; |
| 477 | case R_EBX: return 1+ OFFB_EBX; |
| 478 | case R_ECX: return 1+ OFFB_ECX; |
| 479 | case R_EDX: return 1+ OFFB_EDX; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 480 | default: vpanic("integerGuestRegOffset(x86,le)(1h)"); |
| 481 | } |
| 482 | |
| 483 | /* NOTREACHED */ |
| 484 | vpanic("integerGuestRegOffset(x86,le)"); |
| 485 | } |
| 486 | |
| 487 | static Int segmentGuestRegOffset ( UInt sreg ) |
| 488 | { |
| 489 | switch (sreg) { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 490 | case R_ES: return OFFB_ES; |
| 491 | case R_CS: return OFFB_CS; |
| 492 | case R_SS: return OFFB_SS; |
| 493 | case R_DS: return OFFB_DS; |
| 494 | case R_FS: return OFFB_FS; |
| 495 | case R_GS: return OFFB_GS; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 496 | default: vpanic("segmentGuestRegOffset(x86)"); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 497 | } |
| 498 | } |
| 499 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 500 | static Int xmmGuestRegOffset ( UInt xmmreg ) |
| 501 | { |
| 502 | switch (xmmreg) { |
| 503 | case 0: return OFFB_XMM0; |
| 504 | case 1: return OFFB_XMM1; |
| 505 | case 2: return OFFB_XMM2; |
| 506 | case 3: return OFFB_XMM3; |
| 507 | case 4: return OFFB_XMM4; |
| 508 | case 5: return OFFB_XMM5; |
| 509 | case 6: return OFFB_XMM6; |
| 510 | case 7: return OFFB_XMM7; |
| 511 | default: vpanic("xmmGuestRegOffset"); |
| 512 | } |
| 513 | } |
| 514 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 515 | /* Lanes of vector registers are always numbered from zero being the |
| 516 | least significant lane (rightmost in the register). */ |
| 517 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 518 | static Int xmmGuestRegLane16offset ( UInt xmmreg, Int laneno ) |
| 519 | { |
| 520 | /* Correct for little-endian host only. */ |
| 521 | vassert(!host_is_bigendian); |
| 522 | vassert(laneno >= 0 && laneno < 8); |
| 523 | return xmmGuestRegOffset( xmmreg ) + 2 * laneno; |
| 524 | } |
| 525 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 526 | static Int xmmGuestRegLane32offset ( UInt xmmreg, Int laneno ) |
| 527 | { |
| 528 | /* Correct for little-endian host only. */ |
| 529 | vassert(!host_is_bigendian); |
| 530 | vassert(laneno >= 0 && laneno < 4); |
| 531 | return xmmGuestRegOffset( xmmreg ) + 4 * laneno; |
| 532 | } |
| 533 | |
| 534 | static Int xmmGuestRegLane64offset ( UInt xmmreg, Int laneno ) |
| 535 | { |
| 536 | /* Correct for little-endian host only. */ |
| 537 | vassert(!host_is_bigendian); |
| 538 | vassert(laneno >= 0 && laneno < 2); |
| 539 | return xmmGuestRegOffset( xmmreg ) + 8 * laneno; |
| 540 | } |
| 541 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 542 | static IRExpr* getIReg ( Int sz, UInt archreg ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 543 | { |
| 544 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 545 | vassert(archreg < 8); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 546 | return IRExpr_Get( integerGuestRegOffset(sz,archreg), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 547 | szToITy(sz) ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | /* Ditto, but write to a reg instead. */ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 551 | static void putIReg ( Int sz, UInt archreg, IRExpr* e ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 552 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 553 | IRType ty = typeOfIRExpr(irsb->tyenv, e); |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 554 | switch (sz) { |
| 555 | case 1: vassert(ty == Ity_I8); break; |
| 556 | case 2: vassert(ty == Ity_I16); break; |
| 557 | case 4: vassert(ty == Ity_I32); break; |
| 558 | default: vpanic("putIReg(x86)"); |
| 559 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 560 | vassert(archreg < 8); |
sewardj | eeb9ef8 | 2004-07-15 12:39:03 +0000 | [diff] [blame] | 561 | stmt( IRStmt_Put(integerGuestRegOffset(sz,archreg), e) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 562 | } |
| 563 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 564 | static IRExpr* getSReg ( UInt sreg ) |
| 565 | { |
| 566 | return IRExpr_Get( segmentGuestRegOffset(sreg), Ity_I16 ); |
| 567 | } |
| 568 | |
| 569 | static void putSReg ( UInt sreg, IRExpr* e ) |
| 570 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 571 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16); |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 572 | stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) ); |
| 573 | } |
| 574 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 575 | static IRExpr* getXMMReg ( UInt xmmreg ) |
| 576 | { |
| 577 | return IRExpr_Get( xmmGuestRegOffset(xmmreg), Ity_V128 ); |
| 578 | } |
| 579 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 580 | static IRExpr* getXMMRegLane64 ( UInt xmmreg, Int laneno ) |
| 581 | { |
| 582 | return IRExpr_Get( xmmGuestRegLane64offset(xmmreg,laneno), Ity_I64 ); |
| 583 | } |
| 584 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 585 | static IRExpr* getXMMRegLane64F ( UInt xmmreg, Int laneno ) |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 586 | { |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 587 | return IRExpr_Get( xmmGuestRegLane64offset(xmmreg,laneno), Ity_F64 ); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 588 | } |
| 589 | |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 590 | static IRExpr* getXMMRegLane32 ( UInt xmmreg, Int laneno ) |
| 591 | { |
| 592 | return IRExpr_Get( xmmGuestRegLane32offset(xmmreg,laneno), Ity_I32 ); |
| 593 | } |
| 594 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 595 | static IRExpr* getXMMRegLane32F ( UInt xmmreg, Int laneno ) |
| 596 | { |
| 597 | return IRExpr_Get( xmmGuestRegLane32offset(xmmreg,laneno), Ity_F32 ); |
| 598 | } |
| 599 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 600 | static void putXMMReg ( UInt xmmreg, IRExpr* e ) |
| 601 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 602 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V128); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 603 | stmt( IRStmt_Put( xmmGuestRegOffset(xmmreg), e ) ); |
| 604 | } |
| 605 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 606 | static void putXMMRegLane64 ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 607 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 608 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 609 | stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) ); |
| 610 | } |
| 611 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 612 | static void putXMMRegLane64F ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 613 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 614 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F64); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 615 | stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) ); |
| 616 | } |
| 617 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 618 | static void putXMMRegLane32F ( UInt xmmreg, Int laneno, IRExpr* e ) |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 619 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 620 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F32); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 621 | stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) ); |
| 622 | } |
| 623 | |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 624 | static void putXMMRegLane32 ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 625 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 626 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I32); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 627 | stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) ); |
| 628 | } |
| 629 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 630 | static void putXMMRegLane16 ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 631 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 632 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 633 | stmt( IRStmt_Put( xmmGuestRegLane16offset(xmmreg,laneno), e ) ); |
| 634 | } |
| 635 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 636 | static void assign ( IRTemp dst, IRExpr* e ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 637 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 638 | stmt( IRStmt_WrTmp(dst, e) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 639 | } |
| 640 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 641 | static void storeLE ( IRExpr* addr, IRExpr* data ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 642 | { |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 643 | stmt( IRStmt_Store(Iend_LE, addr, data) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 644 | } |
| 645 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 646 | static IRExpr* unop ( IROp op, IRExpr* a ) |
| 647 | { |
| 648 | return IRExpr_Unop(op, a); |
| 649 | } |
| 650 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 651 | static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) |
| 652 | { |
| 653 | return IRExpr_Binop(op, a1, a2); |
| 654 | } |
| 655 | |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 656 | static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) |
| 657 | { |
| 658 | return IRExpr_Triop(op, a1, a2, a3); |
| 659 | } |
| 660 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 661 | static IRExpr* mkexpr ( IRTemp tmp ) |
| 662 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 663 | return IRExpr_RdTmp(tmp); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 664 | } |
| 665 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 666 | static IRExpr* mkU8 ( UInt i ) |
| 667 | { |
| 668 | vassert(i < 256); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 669 | return IRExpr_Const(IRConst_U8( (UChar)i )); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 670 | } |
| 671 | |
| 672 | static IRExpr* mkU16 ( UInt i ) |
| 673 | { |
| 674 | vassert(i < 65536); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 675 | return IRExpr_Const(IRConst_U16( (UShort)i )); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 676 | } |
| 677 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 678 | static IRExpr* mkU32 ( UInt i ) |
| 679 | { |
| 680 | return IRExpr_Const(IRConst_U32(i)); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 681 | } |
| 682 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 683 | static IRExpr* mkU64 ( ULong i ) |
| 684 | { |
| 685 | return IRExpr_Const(IRConst_U64(i)); |
| 686 | } |
| 687 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 688 | static IRExpr* mkU ( IRType ty, UInt i ) |
| 689 | { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 690 | if (ty == Ity_I8) return mkU8(i); |
| 691 | if (ty == Ity_I16) return mkU16(i); |
| 692 | if (ty == Ity_I32) return mkU32(i); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 693 | /* If this panics, it usually means you passed a size (1,2,4) |
| 694 | value as the IRType, rather than a real IRType. */ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 695 | vpanic("mkU(x86)"); |
| 696 | } |
| 697 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 698 | static IRExpr* mkV128 ( UShort mask ) |
| 699 | { |
| 700 | return IRExpr_Const(IRConst_V128(mask)); |
| 701 | } |
| 702 | |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 703 | static IRExpr* loadLE ( IRType ty, IRExpr* addr ) |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 704 | { |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 705 | return IRExpr_Load(Iend_LE, ty, addr); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 706 | } |
| 707 | |
| 708 | static IROp mkSizedOp ( IRType ty, IROp op8 ) |
| 709 | { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 710 | Int adj; |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 711 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 712 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 713 | || op8 == Iop_Mul8 |
| 714 | || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 715 | || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 716 | || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 717 | || op8 == Iop_CasCmpNE8 |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 718 | || op8 == Iop_Not8); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 719 | adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
| 720 | return adj + op8; |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 721 | } |
| 722 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 723 | static IROp mkWidenOp ( Int szSmall, Int szBig, Bool signd ) |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 724 | { |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 725 | if (szSmall == 1 && szBig == 4) { |
| 726 | return signd ? Iop_8Sto32 : Iop_8Uto32; |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 727 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 728 | if (szSmall == 1 && szBig == 2) { |
| 729 | return signd ? Iop_8Sto16 : Iop_8Uto16; |
| 730 | } |
| 731 | if (szSmall == 2 && szBig == 4) { |
| 732 | return signd ? Iop_16Sto32 : Iop_16Uto32; |
| 733 | } |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 734 | vpanic("mkWidenOp(x86,guest)"); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 735 | } |
| 736 | |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 737 | static IRExpr* mkAnd1 ( IRExpr* x, IRExpr* y ) |
| 738 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 739 | vassert(typeOfIRExpr(irsb->tyenv,x) == Ity_I1); |
| 740 | vassert(typeOfIRExpr(irsb->tyenv,y) == Ity_I1); |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 741 | return unop(Iop_32to1, |
| 742 | binop(Iop_And32, |
| 743 | unop(Iop_1Uto32,x), |
| 744 | unop(Iop_1Uto32,y))); |
| 745 | } |
| 746 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 747 | /* Generate a compare-and-swap operation, operating on memory at |
| 748 | 'addr'. The expected value is 'expVal' and the new value is |
| 749 | 'newVal'. If the operation fails, then transfer control (with a |
| 750 | no-redir jump (XXX no -- see comment at top of this file)) to |
| 751 | 'restart_point', which is presumably the address of the guest |
| 752 | instruction again -- retrying, essentially. */ |
| 753 | static void casLE ( IRExpr* addr, IRExpr* expVal, IRExpr* newVal, |
| 754 | Addr32 restart_point ) |
| 755 | { |
| 756 | IRCAS* cas; |
| 757 | IRType tyE = typeOfIRExpr(irsb->tyenv, expVal); |
| 758 | IRType tyN = typeOfIRExpr(irsb->tyenv, newVal); |
| 759 | IRTemp oldTmp = newTemp(tyE); |
| 760 | IRTemp expTmp = newTemp(tyE); |
| 761 | vassert(tyE == tyN); |
| 762 | vassert(tyE == Ity_I32 || tyE == Ity_I16 || tyE == Ity_I8); |
| 763 | assign(expTmp, expVal); |
| 764 | cas = mkIRCAS( IRTemp_INVALID, oldTmp, Iend_LE, addr, |
| 765 | NULL, mkexpr(expTmp), NULL, newVal ); |
| 766 | stmt( IRStmt_CAS(cas) ); |
| 767 | stmt( IRStmt_Exit( |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 768 | binop( mkSizedOp(tyE,Iop_CasCmpNE8), |
| 769 | mkexpr(oldTmp), mkexpr(expTmp) ), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 770 | Ijk_Boring, /*Ijk_NoRedir*/ |
| 771 | IRConst_U32( restart_point ) |
| 772 | )); |
| 773 | } |
| 774 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 775 | |
| 776 | /*------------------------------------------------------------*/ |
| 777 | /*--- Helpers for %eflags. ---*/ |
| 778 | /*------------------------------------------------------------*/ |
| 779 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 780 | /* -------------- Evaluating the flags-thunk. -------------- */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 781 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 782 | /* Build IR to calculate all the eflags from stored |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 783 | CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: |
| 784 | Ity_I32. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 785 | static IRExpr* mk_x86g_calculate_eflags_all ( void ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 786 | { |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 787 | IRExpr** args |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 788 | = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), |
| 789 | IRExpr_Get(OFFB_CC_DEP1, Ity_I32), |
| 790 | IRExpr_Get(OFFB_CC_DEP2, Ity_I32), |
| 791 | IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 792 | IRExpr* call |
| 793 | = mkIRExprCCall( |
| 794 | Ity_I32, |
| 795 | 0/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 796 | "x86g_calculate_eflags_all", &x86g_calculate_eflags_all, |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 797 | args |
| 798 | ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 799 | /* Exclude OP and NDEP from definedness checking. We're only |
| 800 | interested in DEP1 and DEP2. */ |
| 801 | call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 802 | return call; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 803 | } |
| 804 | |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 805 | /* Build IR to calculate some particular condition from stored |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 806 | CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: |
| 807 | Ity_Bit. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 808 | static IRExpr* mk_x86g_calculate_condition ( X86Condcode cond ) |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 809 | { |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 810 | IRExpr** args |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 811 | = mkIRExprVec_5( mkU32(cond), |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 812 | IRExpr_Get(OFFB_CC_OP, Ity_I32), |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 813 | IRExpr_Get(OFFB_CC_DEP1, Ity_I32), |
| 814 | IRExpr_Get(OFFB_CC_DEP2, Ity_I32), |
| 815 | IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 816 | IRExpr* call |
| 817 | = mkIRExprCCall( |
| 818 | Ity_I32, |
| 819 | 0/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 820 | "x86g_calculate_condition", &x86g_calculate_condition, |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 821 | args |
| 822 | ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 823 | /* Exclude the requested condition, OP and NDEP from definedness |
| 824 | checking. We're only interested in DEP1 and DEP2. */ |
| 825 | call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<1) | (1<<4); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 826 | return unop(Iop_32to1, call); |
| 827 | } |
| 828 | |
| 829 | /* Build IR to calculate just the carry flag from stored |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 830 | CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: Ity_I32. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 831 | static IRExpr* mk_x86g_calculate_eflags_c ( void ) |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 832 | { |
| 833 | IRExpr** args |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 834 | = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), |
| 835 | IRExpr_Get(OFFB_CC_DEP1, Ity_I32), |
| 836 | IRExpr_Get(OFFB_CC_DEP2, Ity_I32), |
| 837 | IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 838 | IRExpr* call |
| 839 | = mkIRExprCCall( |
| 840 | Ity_I32, |
sewardj | 893a330 | 2005-01-24 10:49:02 +0000 | [diff] [blame] | 841 | 3/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 842 | "x86g_calculate_eflags_c", &x86g_calculate_eflags_c, |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 843 | args |
| 844 | ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 845 | /* Exclude OP and NDEP from definedness checking. We're only |
| 846 | interested in DEP1 and DEP2. */ |
| 847 | call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 848 | return call; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 849 | } |
| 850 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 851 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 852 | /* -------------- Building the flags-thunk. -------------- */ |
| 853 | |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 854 | /* The machinery in this section builds the flag-thunk following a |
| 855 | flag-setting operation. Hence the various setFlags_* functions. |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 856 | */ |
| 857 | |
| 858 | static Bool isAddSub ( IROp op8 ) |
| 859 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 860 | return toBool(op8 == Iop_Add8 || op8 == Iop_Sub8); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 861 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 862 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 863 | static Bool isLogic ( IROp op8 ) |
| 864 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 865 | return toBool(op8 == Iop_And8 || op8 == Iop_Or8 || op8 == Iop_Xor8); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 866 | } |
| 867 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 868 | /* U-widen 8/16/32 bit int expr to 32. */ |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 869 | static IRExpr* widenUto32 ( IRExpr* e ) |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 870 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 871 | switch (typeOfIRExpr(irsb->tyenv,e)) { |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 872 | case Ity_I32: return e; |
| 873 | case Ity_I16: return unop(Iop_16Uto32,e); |
| 874 | case Ity_I8: return unop(Iop_8Uto32,e); |
| 875 | default: vpanic("widenUto32"); |
| 876 | } |
| 877 | } |
| 878 | |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 879 | /* S-widen 8/16/32 bit int expr to 32. */ |
| 880 | static IRExpr* widenSto32 ( IRExpr* e ) |
| 881 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 882 | switch (typeOfIRExpr(irsb->tyenv,e)) { |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 883 | case Ity_I32: return e; |
| 884 | case Ity_I16: return unop(Iop_16Sto32,e); |
| 885 | case Ity_I8: return unop(Iop_8Sto32,e); |
| 886 | default: vpanic("widenSto32"); |
| 887 | } |
| 888 | } |
| 889 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 890 | /* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some |
| 891 | of these combinations make sense. */ |
| 892 | static IRExpr* narrowTo ( IRType dst_ty, IRExpr* e ) |
| 893 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 894 | IRType src_ty = typeOfIRExpr(irsb->tyenv,e); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 895 | if (src_ty == dst_ty) |
| 896 | return e; |
| 897 | if (src_ty == Ity_I32 && dst_ty == Ity_I16) |
| 898 | return unop(Iop_32to16, e); |
| 899 | if (src_ty == Ity_I32 && dst_ty == Ity_I8) |
| 900 | return unop(Iop_32to8, e); |
| 901 | |
| 902 | vex_printf("\nsrc, dst tys are: "); |
| 903 | ppIRType(src_ty); |
| 904 | vex_printf(", "); |
| 905 | ppIRType(dst_ty); |
| 906 | vex_printf("\n"); |
| 907 | vpanic("narrowTo(x86)"); |
| 908 | } |
| 909 | |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 910 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 911 | /* Set the flags thunk OP, DEP1 and DEP2 fields. The supplied op is |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 912 | auto-sized up to the real op. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 913 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 914 | static |
| 915 | void setFlags_DEP1_DEP2 ( IROp op8, IRTemp dep1, IRTemp dep2, IRType ty ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 916 | { |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 917 | Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
| 918 | |
| 919 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 920 | |
| 921 | switch (op8) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 922 | case Iop_Add8: ccOp += X86G_CC_OP_ADDB; break; |
| 923 | case Iop_Sub8: ccOp += X86G_CC_OP_SUBB; break; |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 924 | default: ppIROp(op8); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 925 | vpanic("setFlags_DEP1_DEP2(x86)"); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 926 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 927 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(ccOp)) ); |
| 928 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(dep1))) ); |
| 929 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(mkexpr(dep2))) ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 930 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 931 | elimination of previous stores to this field work better. */ |
| 932 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 933 | } |
| 934 | |
| 935 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 936 | /* Set the OP and DEP1 fields only, and write zero to DEP2. */ |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 937 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 938 | static |
| 939 | void setFlags_DEP1 ( IROp op8, IRTemp dep1, IRType ty ) |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 940 | { |
| 941 | Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 942 | |
| 943 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 944 | |
| 945 | switch (op8) { |
| 946 | case Iop_Or8: |
| 947 | case Iop_And8: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 948 | case Iop_Xor8: ccOp += X86G_CC_OP_LOGICB; break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 949 | default: ppIROp(op8); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 950 | vpanic("setFlags_DEP1(x86)"); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 951 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 952 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(ccOp)) ); |
| 953 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(dep1))) ); |
| 954 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0)) ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 955 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 956 | elimination of previous stores to this field work better. */ |
| 957 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 958 | } |
| 959 | |
| 960 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 961 | /* For shift operations, we put in the result and the undershifted |
| 962 | result. Except if the shift amount is zero, the thunk is left |
| 963 | unchanged. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 964 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 965 | static void setFlags_DEP1_DEP2_shift ( IROp op32, |
| 966 | IRTemp res, |
| 967 | IRTemp resUS, |
| 968 | IRType ty, |
| 969 | IRTemp guard ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 970 | { |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 971 | Int ccOp = ty==Ity_I8 ? 2 : (ty==Ity_I16 ? 1 : 0); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 972 | |
| 973 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 974 | vassert(guard); |
| 975 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 976 | /* Both kinds of right shifts are handled by the same thunk |
| 977 | operation. */ |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 978 | switch (op32) { |
| 979 | case Iop_Shr32: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 980 | case Iop_Sar32: ccOp = X86G_CC_OP_SHRL - ccOp; break; |
| 981 | case Iop_Shl32: ccOp = X86G_CC_OP_SHLL - ccOp; break; |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 982 | default: ppIROp(op32); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 983 | vpanic("setFlags_DEP1_DEP2_shift(x86)"); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 984 | } |
| 985 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 986 | /* DEP1 contains the result, DEP2 contains the undershifted value. */ |
sewardj | eeb9ef8 | 2004-07-15 12:39:03 +0000 | [diff] [blame] | 987 | stmt( IRStmt_Put( OFFB_CC_OP, |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 988 | IRExpr_Mux0X( mkexpr(guard), |
| 989 | IRExpr_Get(OFFB_CC_OP,Ity_I32), |
| 990 | mkU32(ccOp))) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 991 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 992 | IRExpr_Mux0X( mkexpr(guard), |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 993 | IRExpr_Get(OFFB_CC_DEP1,Ity_I32), |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 994 | widenUto32(mkexpr(res)))) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 995 | stmt( IRStmt_Put( OFFB_CC_DEP2, |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 996 | IRExpr_Mux0X( mkexpr(guard), |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 997 | IRExpr_Get(OFFB_CC_DEP2,Ity_I32), |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 998 | widenUto32(mkexpr(resUS)))) ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 999 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 1000 | elimination of previous stores to this field work better. */ |
sewardj | 17b0e21 | 2011-03-26 07:28:51 +0000 | [diff] [blame] | 1001 | stmt( IRStmt_Put( OFFB_CC_NDEP, |
| 1002 | IRExpr_Mux0X( mkexpr(guard), |
| 1003 | IRExpr_Get(OFFB_CC_NDEP,Ity_I32), |
| 1004 | mkU32(0) ))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1005 | } |
| 1006 | |
| 1007 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1008 | /* For the inc/dec case, we store in DEP1 the result value and in NDEP |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1009 | the former value of the carry flag, which unfortunately we have to |
| 1010 | compute. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1011 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1012 | static void setFlags_INC_DEC ( Bool inc, IRTemp res, IRType ty ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1013 | { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1014 | Int ccOp = inc ? X86G_CC_OP_INCB : X86G_CC_OP_DECB; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1015 | |
| 1016 | ccOp += ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
| 1017 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 1018 | |
| 1019 | /* This has to come first, because calculating the C flag |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1020 | may require reading all four thunk fields. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1021 | stmt( IRStmt_Put( OFFB_CC_NDEP, mk_x86g_calculate_eflags_c()) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1022 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(ccOp)) ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1023 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(res))) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1024 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0)) ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1028 | /* Multiplies are pretty much like add and sub: DEP1 and DEP2 hold the |
| 1029 | two arguments. */ |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1030 | |
| 1031 | static |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1032 | void setFlags_MUL ( IRType ty, IRTemp arg1, IRTemp arg2, UInt base_op ) |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1033 | { |
| 1034 | switch (ty) { |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1035 | case Ity_I8: |
| 1036 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(base_op+0) ) ); |
| 1037 | break; |
| 1038 | case Ity_I16: |
| 1039 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(base_op+1) ) ); |
| 1040 | break; |
| 1041 | case Ity_I32: |
| 1042 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(base_op+2) ) ); |
| 1043 | break; |
| 1044 | default: |
| 1045 | vpanic("setFlags_MUL(x86)"); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1046 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1047 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(arg1)) )); |
| 1048 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(mkexpr(arg2)) )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 1049 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 1050 | elimination of previous stores to this field work better. */ |
| 1051 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1052 | } |
| 1053 | |
| 1054 | |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1055 | /* -------------- Condition codes. -------------- */ |
| 1056 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1057 | /* Condition codes, using the Intel encoding. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1058 | |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1059 | static HChar* name_X86Condcode ( X86Condcode cond ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1060 | { |
| 1061 | switch (cond) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1062 | case X86CondO: return "o"; |
| 1063 | case X86CondNO: return "no"; |
| 1064 | case X86CondB: return "b"; |
| 1065 | case X86CondNB: return "nb"; |
| 1066 | case X86CondZ: return "z"; |
| 1067 | case X86CondNZ: return "nz"; |
| 1068 | case X86CondBE: return "be"; |
| 1069 | case X86CondNBE: return "nbe"; |
| 1070 | case X86CondS: return "s"; |
| 1071 | case X86CondNS: return "ns"; |
| 1072 | case X86CondP: return "p"; |
| 1073 | case X86CondNP: return "np"; |
| 1074 | case X86CondL: return "l"; |
| 1075 | case X86CondNL: return "nl"; |
| 1076 | case X86CondLE: return "le"; |
| 1077 | case X86CondNLE: return "nle"; |
| 1078 | case X86CondAlways: return "ALWAYS"; |
| 1079 | default: vpanic("name_X86Condcode"); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1080 | } |
| 1081 | } |
| 1082 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1083 | static |
| 1084 | X86Condcode positiveIse_X86Condcode ( X86Condcode cond, |
sewardj | dbf550c | 2005-01-24 11:54:11 +0000 | [diff] [blame] | 1085 | Bool* needInvert ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1086 | { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1087 | vassert(cond >= X86CondO && cond <= X86CondNLE); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1088 | if (cond & 1) { |
| 1089 | *needInvert = True; |
| 1090 | return cond-1; |
| 1091 | } else { |
| 1092 | *needInvert = False; |
| 1093 | return cond; |
| 1094 | } |
| 1095 | } |
| 1096 | |
| 1097 | |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1098 | /* -------------- Helpers for ADD/SUB with carry. -------------- */ |
| 1099 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1100 | /* Given ta1, ta2 and tres, compute tres = ADC(ta1,ta2) and set flags |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1101 | appropriately. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1102 | |
| 1103 | Optionally, generate a store for the 'tres' value. This can either |
| 1104 | be a normal store, or it can be a cas-with-possible-failure style |
| 1105 | store: |
| 1106 | |
| 1107 | if taddr is IRTemp_INVALID, then no store is generated. |
| 1108 | |
| 1109 | if taddr is not IRTemp_INVALID, then a store (using taddr as |
| 1110 | the address) is generated: |
| 1111 | |
| 1112 | if texpVal is IRTemp_INVALID then a normal store is |
| 1113 | generated, and restart_point must be zero (it is irrelevant). |
| 1114 | |
| 1115 | if texpVal is not IRTemp_INVALID then a cas-style store is |
| 1116 | generated. texpVal is the expected value, restart_point |
| 1117 | is the restart point if the store fails, and texpVal must |
| 1118 | have the same type as tres. |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1119 | */ |
| 1120 | static void helper_ADC ( Int sz, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1121 | IRTemp tres, IRTemp ta1, IRTemp ta2, |
| 1122 | /* info about optional store: */ |
| 1123 | IRTemp taddr, IRTemp texpVal, Addr32 restart_point ) |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1124 | { |
| 1125 | UInt thunkOp; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1126 | IRType ty = szToITy(sz); |
| 1127 | IRTemp oldc = newTemp(Ity_I32); |
| 1128 | IRTemp oldcn = newTemp(ty); |
| 1129 | IROp plus = mkSizedOp(ty, Iop_Add8); |
| 1130 | IROp xor = mkSizedOp(ty, Iop_Xor8); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1131 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1132 | vassert(typeOfIRTemp(irsb->tyenv, tres) == ty); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1133 | vassert(sz == 1 || sz == 2 || sz == 4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1134 | thunkOp = sz==4 ? X86G_CC_OP_ADCL |
| 1135 | : (sz==2 ? X86G_CC_OP_ADCW : X86G_CC_OP_ADCB); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1136 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1137 | /* oldc = old carry flag, 0 or 1 */ |
| 1138 | assign( oldc, binop(Iop_And32, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1139 | mk_x86g_calculate_eflags_c(), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1140 | mkU32(1)) ); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1141 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1142 | assign( oldcn, narrowTo(ty, mkexpr(oldc)) ); |
| 1143 | |
| 1144 | assign( tres, binop(plus, |
| 1145 | binop(plus,mkexpr(ta1),mkexpr(ta2)), |
| 1146 | mkexpr(oldcn)) ); |
| 1147 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1148 | /* Possibly generate a store of 'tres' to 'taddr'. See comment at |
| 1149 | start of this function. */ |
| 1150 | if (taddr != IRTemp_INVALID) { |
| 1151 | if (texpVal == IRTemp_INVALID) { |
| 1152 | vassert(restart_point == 0); |
| 1153 | storeLE( mkexpr(taddr), mkexpr(tres) ); |
| 1154 | } else { |
| 1155 | vassert(typeOfIRTemp(irsb->tyenv, texpVal) == ty); |
| 1156 | /* .. and hence 'texpVal' has the same type as 'tres'. */ |
| 1157 | casLE( mkexpr(taddr), |
| 1158 | mkexpr(texpVal), mkexpr(tres), restart_point ); |
| 1159 | } |
| 1160 | } |
| 1161 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1162 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(thunkOp) ) ); |
sewardj | 3b3eacd | 2005-08-24 10:01:36 +0000 | [diff] [blame] | 1163 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(ta1)) )); |
| 1164 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(binop(xor, mkexpr(ta2), |
| 1165 | mkexpr(oldcn)) )) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1166 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) ); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1167 | } |
| 1168 | |
| 1169 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1170 | /* Given ta1, ta2 and tres, compute tres = SBB(ta1,ta2) and set flags |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1171 | appropriately. As with helper_ADC, possibly generate a store of |
| 1172 | the result -- see comments on helper_ADC for details. |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1173 | */ |
| 1174 | static void helper_SBB ( Int sz, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1175 | IRTemp tres, IRTemp ta1, IRTemp ta2, |
| 1176 | /* info about optional store: */ |
| 1177 | IRTemp taddr, IRTemp texpVal, Addr32 restart_point ) |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1178 | { |
| 1179 | UInt thunkOp; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1180 | IRType ty = szToITy(sz); |
| 1181 | IRTemp oldc = newTemp(Ity_I32); |
| 1182 | IRTemp oldcn = newTemp(ty); |
| 1183 | IROp minus = mkSizedOp(ty, Iop_Sub8); |
| 1184 | IROp xor = mkSizedOp(ty, Iop_Xor8); |
| 1185 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1186 | vassert(typeOfIRTemp(irsb->tyenv, tres) == ty); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1187 | vassert(sz == 1 || sz == 2 || sz == 4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1188 | thunkOp = sz==4 ? X86G_CC_OP_SBBL |
| 1189 | : (sz==2 ? X86G_CC_OP_SBBW : X86G_CC_OP_SBBB); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1190 | |
| 1191 | /* oldc = old carry flag, 0 or 1 */ |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1192 | assign( oldc, binop(Iop_And32, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1193 | mk_x86g_calculate_eflags_c(), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1194 | mkU32(1)) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1195 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1196 | assign( oldcn, narrowTo(ty, mkexpr(oldc)) ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1197 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1198 | assign( tres, binop(minus, |
| 1199 | binop(minus,mkexpr(ta1),mkexpr(ta2)), |
| 1200 | mkexpr(oldcn)) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1201 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1202 | /* Possibly generate a store of 'tres' to 'taddr'. See comment at |
| 1203 | start of this function. */ |
| 1204 | if (taddr != IRTemp_INVALID) { |
| 1205 | if (texpVal == IRTemp_INVALID) { |
| 1206 | vassert(restart_point == 0); |
| 1207 | storeLE( mkexpr(taddr), mkexpr(tres) ); |
| 1208 | } else { |
| 1209 | vassert(typeOfIRTemp(irsb->tyenv, texpVal) == ty); |
| 1210 | /* .. and hence 'texpVal' has the same type as 'tres'. */ |
| 1211 | casLE( mkexpr(taddr), |
| 1212 | mkexpr(texpVal), mkexpr(tres), restart_point ); |
| 1213 | } |
| 1214 | } |
| 1215 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1216 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(thunkOp) ) ); |
sewardj | 3b3eacd | 2005-08-24 10:01:36 +0000 | [diff] [blame] | 1217 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(ta1) )) ); |
| 1218 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(binop(xor, mkexpr(ta2), |
| 1219 | mkexpr(oldcn)) )) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1220 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1221 | } |
| 1222 | |
| 1223 | |
sewardj | 7dd2eb2 | 2005-01-05 10:38:54 +0000 | [diff] [blame] | 1224 | /* -------------- Helpers for disassembly printing. -------------- */ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 1225 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1226 | static HChar* nameGrp1 ( Int opc_aux ) |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 1227 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1228 | static HChar* grp1_names[8] |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 1229 | = { "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp" }; |
| 1230 | if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp1(x86)"); |
| 1231 | return grp1_names[opc_aux]; |
| 1232 | } |
| 1233 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1234 | static HChar* nameGrp2 ( Int opc_aux ) |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 1235 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1236 | static HChar* grp2_names[8] |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 1237 | = { "rol", "ror", "rcl", "rcr", "shl", "shr", "shl", "sar" }; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 1238 | if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp2(x86)"); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 1239 | return grp2_names[opc_aux]; |
| 1240 | } |
| 1241 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1242 | static HChar* nameGrp4 ( Int opc_aux ) |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 1243 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1244 | static HChar* grp4_names[8] |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 1245 | = { "inc", "dec", "???", "???", "???", "???", "???", "???" }; |
| 1246 | if (opc_aux < 0 || opc_aux > 1) vpanic("nameGrp4(x86)"); |
| 1247 | return grp4_names[opc_aux]; |
| 1248 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1249 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1250 | static HChar* nameGrp5 ( Int opc_aux ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1251 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1252 | static HChar* grp5_names[8] |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1253 | = { "inc", "dec", "call*", "call*", "jmp*", "jmp*", "push", "???" }; |
| 1254 | if (opc_aux < 0 || opc_aux > 6) vpanic("nameGrp5(x86)"); |
| 1255 | return grp5_names[opc_aux]; |
| 1256 | } |
| 1257 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 1258 | static HChar* nameGrp8 ( Int opc_aux ) |
| 1259 | { |
| 1260 | static HChar* grp8_names[8] |
| 1261 | = { "???", "???", "???", "???", "bt", "bts", "btr", "btc" }; |
| 1262 | if (opc_aux < 4 || opc_aux > 7) vpanic("nameGrp8(x86)"); |
| 1263 | return grp8_names[opc_aux]; |
| 1264 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1265 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1266 | static HChar* nameIReg ( Int size, Int reg ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1267 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1268 | static HChar* ireg32_names[8] |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1269 | = { "%eax", "%ecx", "%edx", "%ebx", |
| 1270 | "%esp", "%ebp", "%esi", "%edi" }; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1271 | static HChar* ireg16_names[8] |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1272 | = { "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di" }; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1273 | static HChar* ireg8_names[8] |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1274 | = { "%al", "%cl", "%dl", "%bl", |
| 1275 | "%ah{sp}", "%ch{bp}", "%dh{si}", "%bh{di}" }; |
| 1276 | if (reg < 0 || reg > 7) goto bad; |
| 1277 | switch (size) { |
| 1278 | case 4: return ireg32_names[reg]; |
| 1279 | case 2: return ireg16_names[reg]; |
| 1280 | case 1: return ireg8_names[reg]; |
| 1281 | } |
| 1282 | bad: |
| 1283 | vpanic("nameIReg(X86)"); |
| 1284 | return NULL; /*notreached*/ |
| 1285 | } |
| 1286 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1287 | static HChar* nameSReg ( UInt sreg ) |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 1288 | { |
| 1289 | switch (sreg) { |
| 1290 | case R_ES: return "%es"; |
| 1291 | case R_CS: return "%cs"; |
| 1292 | case R_SS: return "%ss"; |
| 1293 | case R_DS: return "%ds"; |
| 1294 | case R_FS: return "%fs"; |
| 1295 | case R_GS: return "%gs"; |
| 1296 | default: vpanic("nameSReg(x86)"); |
| 1297 | } |
| 1298 | } |
| 1299 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1300 | static HChar* nameMMXReg ( Int mmxreg ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1301 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1302 | static HChar* mmx_names[8] |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1303 | = { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" }; |
| 1304 | if (mmxreg < 0 || mmxreg > 7) vpanic("nameMMXReg(x86,guest)"); |
| 1305 | return mmx_names[mmxreg]; |
| 1306 | } |
| 1307 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1308 | static HChar* nameXMMReg ( Int xmmreg ) |
| 1309 | { |
| 1310 | static HChar* xmm_names[8] |
| 1311 | = { "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
| 1312 | "%xmm4", "%xmm5", "%xmm6", "%xmm7" }; |
| 1313 | if (xmmreg < 0 || xmmreg > 7) vpanic("name_of_xmm_reg"); |
| 1314 | return xmm_names[xmmreg]; |
| 1315 | } |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1316 | |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1317 | static HChar* nameMMXGran ( Int gran ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1318 | { |
| 1319 | switch (gran) { |
| 1320 | case 0: return "b"; |
| 1321 | case 1: return "w"; |
| 1322 | case 2: return "d"; |
| 1323 | case 3: return "q"; |
| 1324 | default: vpanic("nameMMXGran(x86,guest)"); |
| 1325 | } |
| 1326 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1327 | |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1328 | static HChar nameISize ( Int size ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1329 | { |
| 1330 | switch (size) { |
| 1331 | case 4: return 'l'; |
| 1332 | case 2: return 'w'; |
| 1333 | case 1: return 'b'; |
| 1334 | default: vpanic("nameISize(x86)"); |
| 1335 | } |
| 1336 | } |
| 1337 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1338 | |
| 1339 | /*------------------------------------------------------------*/ |
| 1340 | /*--- JMP helpers ---*/ |
| 1341 | /*------------------------------------------------------------*/ |
| 1342 | |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 1343 | static void jmp_lit( IRJumpKind kind, Addr32 d32 ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1344 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1345 | irsb->next = mkU32(d32); |
| 1346 | irsb->jumpkind = kind; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1347 | } |
| 1348 | |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 1349 | static void jmp_treg( IRJumpKind kind, IRTemp t ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1350 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1351 | irsb->next = mkexpr(t); |
| 1352 | irsb->jumpkind = kind; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1353 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1354 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1355 | static |
| 1356 | void jcc_01( X86Condcode cond, Addr32 d32_false, Addr32 d32_true ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1357 | { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1358 | Bool invert; |
| 1359 | X86Condcode condPos; |
| 1360 | condPos = positiveIse_X86Condcode ( cond, &invert ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1361 | if (invert) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1362 | stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1363 | Ijk_Boring, |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 1364 | IRConst_U32(d32_false) ) ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1365 | irsb->next = mkU32(d32_true); |
| 1366 | irsb->jumpkind = Ijk_Boring; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1367 | } else { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1368 | stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1369 | Ijk_Boring, |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 1370 | IRConst_U32(d32_true) ) ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1371 | irsb->next = mkU32(d32_false); |
| 1372 | irsb->jumpkind = Ijk_Boring; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1373 | } |
| 1374 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1375 | |
| 1376 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1377 | /*------------------------------------------------------------*/ |
| 1378 | /*--- Disassembling addressing modes ---*/ |
| 1379 | /*------------------------------------------------------------*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1380 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1381 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1382 | HChar* sorbTxt ( UChar sorb ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1383 | { |
| 1384 | switch (sorb) { |
| 1385 | case 0: return ""; /* no override */ |
| 1386 | case 0x3E: return "%ds"; |
| 1387 | case 0x26: return "%es:"; |
| 1388 | case 0x64: return "%fs:"; |
| 1389 | case 0x65: return "%gs:"; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1390 | default: vpanic("sorbTxt(x86,guest)"); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1391 | } |
| 1392 | } |
| 1393 | |
| 1394 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1395 | /* 'virtual' is an IRExpr* holding a virtual address. Convert it to a |
| 1396 | linear address by adding any required segment override as indicated |
| 1397 | by sorb. */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1398 | static |
| 1399 | IRExpr* handleSegOverride ( UChar sorb, IRExpr* virtual ) |
| 1400 | { |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1401 | Int sreg; |
| 1402 | IRType hWordTy; |
| 1403 | IRTemp ldt_ptr, gdt_ptr, seg_selector, r64; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1404 | |
| 1405 | if (sorb == 0) |
| 1406 | /* the common case - no override */ |
| 1407 | return virtual; |
| 1408 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1409 | switch (sorb) { |
| 1410 | case 0x3E: sreg = R_DS; break; |
| 1411 | case 0x26: sreg = R_ES; break; |
| 1412 | case 0x64: sreg = R_FS; break; |
| 1413 | case 0x65: sreg = R_GS; break; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1414 | default: vpanic("handleSegOverride(x86,guest)"); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1415 | } |
| 1416 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1417 | hWordTy = sizeof(HWord)==4 ? Ity_I32 : Ity_I64; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1418 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1419 | seg_selector = newTemp(Ity_I32); |
| 1420 | ldt_ptr = newTemp(hWordTy); |
| 1421 | gdt_ptr = newTemp(hWordTy); |
| 1422 | r64 = newTemp(Ity_I64); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1423 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1424 | assign( seg_selector, unop(Iop_16Uto32, getSReg(sreg)) ); |
| 1425 | assign( ldt_ptr, IRExpr_Get( OFFB_LDT, hWordTy )); |
| 1426 | assign( gdt_ptr, IRExpr_Get( OFFB_GDT, hWordTy )); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1427 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1428 | /* |
| 1429 | Call this to do the translation and limit checks: |
| 1430 | ULong x86g_use_seg_selector ( HWord ldt, HWord gdt, |
| 1431 | UInt seg_selector, UInt virtual_addr ) |
| 1432 | */ |
| 1433 | assign( |
| 1434 | r64, |
| 1435 | mkIRExprCCall( |
| 1436 | Ity_I64, |
| 1437 | 0/*regparms*/, |
| 1438 | "x86g_use_seg_selector", |
| 1439 | &x86g_use_seg_selector, |
| 1440 | mkIRExprVec_4( mkexpr(ldt_ptr), mkexpr(gdt_ptr), |
| 1441 | mkexpr(seg_selector), virtual) |
| 1442 | ) |
| 1443 | ); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1444 | |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 1445 | /* If the high 32 of the result are non-zero, there was a |
| 1446 | failure in address translation. In which case, make a |
| 1447 | quick exit. |
| 1448 | */ |
| 1449 | stmt( |
| 1450 | IRStmt_Exit( |
| 1451 | binop(Iop_CmpNE32, unop(Iop_64HIto32, mkexpr(r64)), mkU32(0)), |
| 1452 | Ijk_MapFail, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 1453 | IRConst_U32( guest_EIP_curr_instr ) |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 1454 | ) |
| 1455 | ); |
| 1456 | |
| 1457 | /* otherwise, here's the translated result. */ |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1458 | return unop(Iop_64to32, mkexpr(r64)); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1459 | } |
| 1460 | |
| 1461 | |
| 1462 | /* Generate IR to calculate an address indicated by a ModRM and |
| 1463 | following SIB bytes. The expression, and the number of bytes in |
| 1464 | the address mode, are returned. Note that this fn should not be |
| 1465 | called if the R/M part of the address denotes a register instead of |
| 1466 | memory. If print_codegen is true, text of the addressing mode is |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1467 | placed in buf. |
| 1468 | |
| 1469 | The computed address is stored in a new tempreg, and the |
| 1470 | identity of the tempreg is returned. */ |
| 1471 | |
| 1472 | static IRTemp disAMode_copy2tmp ( IRExpr* addr32 ) |
| 1473 | { |
| 1474 | IRTemp tmp = newTemp(Ity_I32); |
| 1475 | assign( tmp, addr32 ); |
| 1476 | return tmp; |
| 1477 | } |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1478 | |
| 1479 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1480 | IRTemp disAMode ( Int* len, UChar sorb, Int delta, HChar* buf ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1481 | { |
| 1482 | UChar mod_reg_rm = getIByte(delta); |
| 1483 | delta++; |
| 1484 | |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 1485 | buf[0] = (UChar)0; |
| 1486 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1487 | /* squeeze out the reg field from mod_reg_rm, since a 256-entry |
| 1488 | jump table seems a bit excessive. |
| 1489 | */ |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1490 | mod_reg_rm &= 0xC7; /* is now XX000YYY */ |
| 1491 | mod_reg_rm = toUChar(mod_reg_rm | (mod_reg_rm >> 3)); |
| 1492 | /* is now XX0XXYYY */ |
| 1493 | mod_reg_rm &= 0x1F; /* is now 000XXYYY */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1494 | switch (mod_reg_rm) { |
| 1495 | |
| 1496 | /* (%eax) .. (%edi), not including (%esp) or (%ebp). |
| 1497 | --> GET %reg, t |
| 1498 | */ |
| 1499 | case 0x00: case 0x01: case 0x02: case 0x03: |
| 1500 | /* ! 04 */ /* ! 05 */ case 0x06: case 0x07: |
| 1501 | { UChar rm = mod_reg_rm; |
| 1502 | DIS(buf, "%s(%s)", sorbTxt(sorb), nameIReg(4,rm)); |
| 1503 | *len = 1; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1504 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1505 | handleSegOverride(sorb, getIReg(4,rm))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1506 | } |
| 1507 | |
| 1508 | /* d8(%eax) ... d8(%edi), not including d8(%esp) |
| 1509 | --> GET %reg, t ; ADDL d8, t |
| 1510 | */ |
| 1511 | case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 1512 | /* ! 0C */ case 0x0D: case 0x0E: case 0x0F: |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1513 | { UChar rm = toUChar(mod_reg_rm & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1514 | UInt d = getSDisp8(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1515 | DIS(buf, "%s%d(%s)", sorbTxt(sorb), (Int)d, nameIReg(4,rm)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1516 | *len = 2; |
| 1517 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1518 | handleSegOverride(sorb, |
| 1519 | binop(Iop_Add32,getIReg(4,rm),mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1520 | } |
| 1521 | |
| 1522 | /* d32(%eax) ... d32(%edi), not including d32(%esp) |
| 1523 | --> GET %reg, t ; ADDL d8, t |
| 1524 | */ |
| 1525 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 1526 | /* ! 14 */ case 0x15: case 0x16: case 0x17: |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1527 | { UChar rm = toUChar(mod_reg_rm & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1528 | UInt d = getUDisp32(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1529 | DIS(buf, "%s0x%x(%s)", sorbTxt(sorb), (Int)d, nameIReg(4,rm)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1530 | *len = 5; |
| 1531 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1532 | handleSegOverride(sorb, |
| 1533 | binop(Iop_Add32,getIReg(4,rm),mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1534 | } |
| 1535 | |
| 1536 | /* a register, %eax .. %edi. This shouldn't happen. */ |
| 1537 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 1538 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: |
| 1539 | vpanic("disAMode(x86): not an addr!"); |
| 1540 | |
| 1541 | /* a 32-bit literal address |
| 1542 | --> MOV d32, tmp |
| 1543 | */ |
| 1544 | case 0x05: |
| 1545 | { UInt d = getUDisp32(delta); |
| 1546 | *len = 5; |
| 1547 | DIS(buf, "%s(0x%x)", sorbTxt(sorb), d); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1548 | return disAMode_copy2tmp( |
| 1549 | handleSegOverride(sorb, mkU32(d))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1550 | } |
| 1551 | |
| 1552 | case 0x04: { |
| 1553 | /* SIB, with no displacement. Special cases: |
| 1554 | -- %esp cannot act as an index value. |
| 1555 | If index_r indicates %esp, zero is used for the index. |
| 1556 | -- when mod is zero and base indicates EBP, base is instead |
| 1557 | a 32-bit literal. |
| 1558 | It's all madness, I tell you. Extract %index, %base and |
| 1559 | scale from the SIB byte. The value denoted is then: |
| 1560 | | %index == %ESP && %base == %EBP |
| 1561 | = d32 following SIB byte |
| 1562 | | %index == %ESP && %base != %EBP |
| 1563 | = %base |
| 1564 | | %index != %ESP && %base == %EBP |
| 1565 | = d32 following SIB byte + (%index << scale) |
| 1566 | | %index != %ESP && %base != %ESP |
| 1567 | = %base + (%index << scale) |
| 1568 | |
| 1569 | What happens to the souls of CPU architects who dream up such |
| 1570 | horrendous schemes, do you suppose? |
| 1571 | */ |
| 1572 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1573 | UChar scale = toUChar((sib >> 6) & 3); |
| 1574 | UChar index_r = toUChar((sib >> 3) & 7); |
| 1575 | UChar base_r = toUChar(sib & 7); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1576 | delta++; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1577 | |
| 1578 | if (index_r != R_ESP && base_r != R_EBP) { |
| 1579 | DIS(buf, "%s(%s,%s,%d)", sorbTxt(sorb), |
| 1580 | nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1581 | *len = 2; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1582 | return |
| 1583 | disAMode_copy2tmp( |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1584 | handleSegOverride(sorb, |
| 1585 | binop(Iop_Add32, |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1586 | getIReg(4,base_r), |
| 1587 | binop(Iop_Shl32, getIReg(4,index_r), |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 1588 | mkU8(scale))))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1589 | } |
| 1590 | |
| 1591 | if (index_r != R_ESP && base_r == R_EBP) { |
| 1592 | UInt d = getUDisp32(delta); |
| 1593 | DIS(buf, "%s0x%x(,%s,%d)", sorbTxt(sorb), d, |
| 1594 | nameIReg(4,index_r), 1<<scale); |
| 1595 | *len = 6; |
| 1596 | return |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1597 | disAMode_copy2tmp( |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1598 | handleSegOverride(sorb, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1599 | binop(Iop_Add32, |
| 1600 | binop(Iop_Shl32, getIReg(4,index_r), mkU8(scale)), |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1601 | mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1602 | } |
| 1603 | |
| 1604 | if (index_r == R_ESP && base_r != R_EBP) { |
| 1605 | DIS(buf, "%s(%s,,)", sorbTxt(sorb), nameIReg(4,base_r)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1606 | *len = 2; |
| 1607 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1608 | handleSegOverride(sorb, getIReg(4,base_r))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1609 | } |
| 1610 | |
| 1611 | if (index_r == R_ESP && base_r == R_EBP) { |
| 1612 | UInt d = getUDisp32(delta); |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 1613 | DIS(buf, "%s0x%x(,,)", sorbTxt(sorb), d); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1614 | *len = 6; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1615 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1616 | handleSegOverride(sorb, mkU32(d))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1617 | } |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 1618 | /*NOTREACHED*/ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1619 | vassert(0); |
| 1620 | } |
| 1621 | |
| 1622 | /* SIB, with 8-bit displacement. Special cases: |
| 1623 | -- %esp cannot act as an index value. |
| 1624 | If index_r indicates %esp, zero is used for the index. |
| 1625 | Denoted value is: |
| 1626 | | %index == %ESP |
| 1627 | = d8 + %base |
| 1628 | | %index != %ESP |
| 1629 | = d8 + %base + (%index << scale) |
| 1630 | */ |
| 1631 | case 0x0C: { |
| 1632 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1633 | UChar scale = toUChar((sib >> 6) & 3); |
| 1634 | UChar index_r = toUChar((sib >> 3) & 7); |
| 1635 | UChar base_r = toUChar(sib & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1636 | UInt d = getSDisp8(delta+1); |
| 1637 | |
| 1638 | if (index_r == R_ESP) { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1639 | DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), |
| 1640 | (Int)d, nameIReg(4,base_r)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1641 | *len = 3; |
| 1642 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1643 | handleSegOverride(sorb, |
| 1644 | binop(Iop_Add32, getIReg(4,base_r), mkU32(d)) )); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1645 | } else { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1646 | DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), (Int)d, |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1647 | nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1648 | *len = 3; |
| 1649 | return |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1650 | disAMode_copy2tmp( |
| 1651 | handleSegOverride(sorb, |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 1652 | binop(Iop_Add32, |
| 1653 | binop(Iop_Add32, |
| 1654 | getIReg(4,base_r), |
| 1655 | binop(Iop_Shl32, |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 1656 | getIReg(4,index_r), mkU8(scale))), |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1657 | mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1658 | } |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 1659 | /*NOTREACHED*/ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1660 | vassert(0); |
| 1661 | } |
| 1662 | |
| 1663 | /* SIB, with 32-bit displacement. Special cases: |
| 1664 | -- %esp cannot act as an index value. |
| 1665 | If index_r indicates %esp, zero is used for the index. |
| 1666 | Denoted value is: |
| 1667 | | %index == %ESP |
| 1668 | = d32 + %base |
| 1669 | | %index != %ESP |
| 1670 | = d32 + %base + (%index << scale) |
| 1671 | */ |
| 1672 | case 0x14: { |
| 1673 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1674 | UChar scale = toUChar((sib >> 6) & 3); |
| 1675 | UChar index_r = toUChar((sib >> 3) & 7); |
| 1676 | UChar base_r = toUChar(sib & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1677 | UInt d = getUDisp32(delta+1); |
| 1678 | |
| 1679 | if (index_r == R_ESP) { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1680 | DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), |
| 1681 | (Int)d, nameIReg(4,base_r)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1682 | *len = 6; |
| 1683 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1684 | handleSegOverride(sorb, |
| 1685 | binop(Iop_Add32, getIReg(4,base_r), mkU32(d)) )); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1686 | } else { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1687 | DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), (Int)d, |
| 1688 | nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1689 | *len = 6; |
| 1690 | return |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1691 | disAMode_copy2tmp( |
| 1692 | handleSegOverride(sorb, |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1693 | binop(Iop_Add32, |
| 1694 | binop(Iop_Add32, |
| 1695 | getIReg(4,base_r), |
| 1696 | binop(Iop_Shl32, |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 1697 | getIReg(4,index_r), mkU8(scale))), |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1698 | mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1699 | } |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 1700 | /*NOTREACHED*/ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1701 | vassert(0); |
| 1702 | } |
| 1703 | |
| 1704 | default: |
| 1705 | vpanic("disAMode(x86)"); |
| 1706 | return 0; /*notreached*/ |
| 1707 | } |
| 1708 | } |
| 1709 | |
| 1710 | |
| 1711 | /* Figure out the number of (insn-stream) bytes constituting the amode |
| 1712 | beginning at delta. Is useful for getting hold of literals beyond |
| 1713 | the end of the amode before it has been disassembled. */ |
| 1714 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1715 | static UInt lengthAMode ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1716 | { |
| 1717 | UChar mod_reg_rm = getIByte(delta); delta++; |
| 1718 | |
| 1719 | /* squeeze out the reg field from mod_reg_rm, since a 256-entry |
| 1720 | jump table seems a bit excessive. |
| 1721 | */ |
| 1722 | mod_reg_rm &= 0xC7; /* is now XX000YYY */ |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1723 | mod_reg_rm = toUChar(mod_reg_rm | (mod_reg_rm >> 3)); |
| 1724 | /* is now XX0XXYYY */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1725 | mod_reg_rm &= 0x1F; /* is now 000XXYYY */ |
| 1726 | switch (mod_reg_rm) { |
| 1727 | |
| 1728 | /* (%eax) .. (%edi), not including (%esp) or (%ebp). */ |
| 1729 | case 0x00: case 0x01: case 0x02: case 0x03: |
| 1730 | /* ! 04 */ /* ! 05 */ case 0x06: case 0x07: |
| 1731 | return 1; |
| 1732 | |
| 1733 | /* d8(%eax) ... d8(%edi), not including d8(%esp). */ |
| 1734 | case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 1735 | /* ! 0C */ case 0x0D: case 0x0E: case 0x0F: |
| 1736 | return 2; |
| 1737 | |
| 1738 | /* d32(%eax) ... d32(%edi), not including d32(%esp). */ |
| 1739 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 1740 | /* ! 14 */ case 0x15: case 0x16: case 0x17: |
| 1741 | return 5; |
| 1742 | |
| 1743 | /* a register, %eax .. %edi. (Not an addr, but still handled.) */ |
| 1744 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 1745 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: |
| 1746 | return 1; |
| 1747 | |
| 1748 | /* a 32-bit literal address. */ |
| 1749 | case 0x05: return 5; |
| 1750 | |
| 1751 | /* SIB, no displacement. */ |
| 1752 | case 0x04: { |
| 1753 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1754 | UChar base_r = toUChar(sib & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1755 | if (base_r == R_EBP) return 6; else return 2; |
| 1756 | } |
| 1757 | /* SIB, with 8-bit displacement. */ |
| 1758 | case 0x0C: return 3; |
| 1759 | |
| 1760 | /* SIB, with 32-bit displacement. */ |
| 1761 | case 0x14: return 6; |
| 1762 | |
| 1763 | default: |
| 1764 | vpanic("lengthAMode"); |
| 1765 | return 0; /*notreached*/ |
| 1766 | } |
| 1767 | } |
| 1768 | |
| 1769 | /*------------------------------------------------------------*/ |
| 1770 | /*--- Disassembling common idioms ---*/ |
| 1771 | /*------------------------------------------------------------*/ |
| 1772 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1773 | /* Handle binary integer instructions of the form |
| 1774 | op E, G meaning |
| 1775 | op reg-or-mem, reg |
| 1776 | Is passed the a ptr to the modRM byte, the actual operation, and the |
| 1777 | data size. Returns the address advanced completely over this |
| 1778 | instruction. |
| 1779 | |
| 1780 | E(src) is reg-or-mem |
| 1781 | G(dst) is reg. |
| 1782 | |
| 1783 | If E is reg, --> GET %G, tmp |
| 1784 | OP %E, tmp |
| 1785 | PUT tmp, %G |
| 1786 | |
| 1787 | If E is mem and OP is not reversible, |
| 1788 | --> (getAddr E) -> tmpa |
| 1789 | LD (tmpa), tmpa |
| 1790 | GET %G, tmp2 |
| 1791 | OP tmpa, tmp2 |
| 1792 | PUT tmp2, %G |
| 1793 | |
| 1794 | If E is mem and OP is reversible |
| 1795 | --> (getAddr E) -> tmpa |
| 1796 | LD (tmpa), tmpa |
| 1797 | OP %G, tmpa |
| 1798 | PUT tmpa, %G |
| 1799 | */ |
| 1800 | static |
| 1801 | UInt dis_op2_E_G ( UChar sorb, |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1802 | Bool addSubCarry, |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1803 | IROp op8, |
| 1804 | Bool keep, |
| 1805 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1806 | Int delta0, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1807 | HChar* t_x86opc ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1808 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1809 | HChar dis_buf[50]; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1810 | Int len; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1811 | IRType ty = szToITy(size); |
| 1812 | IRTemp dst1 = newTemp(ty); |
| 1813 | IRTemp src = newTemp(ty); |
| 1814 | IRTemp dst0 = newTemp(ty); |
| 1815 | UChar rm = getUChar(delta0); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 1816 | IRTemp addr = IRTemp_INVALID; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1817 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1818 | /* addSubCarry == True indicates the intended operation is |
| 1819 | add-with-carry or subtract-with-borrow. */ |
| 1820 | if (addSubCarry) { |
| 1821 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8); |
| 1822 | vassert(keep); |
| 1823 | } |
| 1824 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1825 | if (epartIsReg(rm)) { |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1826 | /* Specially handle XOR reg,reg, because that doesn't really |
| 1827 | depend on reg, and doing the obvious thing potentially |
| 1828 | generates a spurious value check failure due to the bogus |
sewardj | 55efbdf | 2005-05-02 17:07:02 +0000 | [diff] [blame] | 1829 | dependency. Ditto SBB reg,reg. */ |
| 1830 | if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry)) |
| 1831 | && gregOfRM(rm) == eregOfRM(rm)) { |
| 1832 | putIReg(size, gregOfRM(rm), mkU(ty,0)); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1833 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1834 | assign( dst0, getIReg(size,gregOfRM(rm)) ); |
| 1835 | assign( src, getIReg(size,eregOfRM(rm)) ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1836 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1837 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1838 | helper_ADC( size, dst1, dst0, src, |
| 1839 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1840 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1841 | } else |
| 1842 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1843 | helper_SBB( size, dst1, dst0, src, |
| 1844 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1845 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1846 | } else { |
| 1847 | assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1848 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1849 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 1850 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1851 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1852 | if (keep) |
| 1853 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1854 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1855 | |
| 1856 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 1857 | nameIReg(size,eregOfRM(rm)), |
| 1858 | nameIReg(size,gregOfRM(rm))); |
| 1859 | return 1+delta0; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1860 | } else { |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1861 | /* E refers to memory */ |
| 1862 | addr = disAMode ( &len, sorb, delta0, dis_buf); |
| 1863 | assign( dst0, getIReg(size,gregOfRM(rm)) ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1864 | assign( src, loadLE(szToITy(size), mkexpr(addr)) ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1865 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1866 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1867 | helper_ADC( size, dst1, dst0, src, |
| 1868 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1869 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1870 | } else |
| 1871 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1872 | helper_SBB( size, dst1, dst0, src, |
| 1873 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1874 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1875 | } else { |
| 1876 | assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1877 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1878 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 1879 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1880 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1881 | if (keep) |
| 1882 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1883 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1884 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1885 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 1886 | dis_buf,nameIReg(size,gregOfRM(rm))); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1887 | return len+delta0; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1888 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1889 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1890 | |
| 1891 | |
| 1892 | |
| 1893 | /* Handle binary integer instructions of the form |
| 1894 | op G, E meaning |
| 1895 | op reg, reg-or-mem |
| 1896 | Is passed the a ptr to the modRM byte, the actual operation, and the |
| 1897 | data size. Returns the address advanced completely over this |
| 1898 | instruction. |
| 1899 | |
| 1900 | G(src) is reg. |
| 1901 | E(dst) is reg-or-mem |
| 1902 | |
| 1903 | If E is reg, --> GET %E, tmp |
| 1904 | OP %G, tmp |
| 1905 | PUT tmp, %E |
| 1906 | |
| 1907 | If E is mem, --> (getAddr E) -> tmpa |
| 1908 | LD (tmpa), tmpv |
| 1909 | OP %G, tmpv |
| 1910 | ST tmpv, (tmpa) |
| 1911 | */ |
| 1912 | static |
| 1913 | UInt dis_op2_G_E ( UChar sorb, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1914 | Bool locked, |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1915 | Bool addSubCarry, |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1916 | IROp op8, |
| 1917 | Bool keep, |
| 1918 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1919 | Int delta0, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1920 | HChar* t_x86opc ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1921 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1922 | HChar dis_buf[50]; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1923 | Int len; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1924 | IRType ty = szToITy(size); |
| 1925 | IRTemp dst1 = newTemp(ty); |
| 1926 | IRTemp src = newTemp(ty); |
| 1927 | IRTemp dst0 = newTemp(ty); |
| 1928 | UChar rm = getIByte(delta0); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 1929 | IRTemp addr = IRTemp_INVALID; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1930 | |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1931 | /* addSubCarry == True indicates the intended operation is |
| 1932 | add-with-carry or subtract-with-borrow. */ |
| 1933 | if (addSubCarry) { |
| 1934 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8); |
| 1935 | vassert(keep); |
| 1936 | } |
| 1937 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1938 | if (epartIsReg(rm)) { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1939 | /* Specially handle XOR reg,reg, because that doesn't really |
| 1940 | depend on reg, and doing the obvious thing potentially |
| 1941 | generates a spurious value check failure due to the bogus |
sewardj | 55efbdf | 2005-05-02 17:07:02 +0000 | [diff] [blame] | 1942 | dependency. Ditto SBB reg,reg.*/ |
| 1943 | if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry)) |
| 1944 | && gregOfRM(rm) == eregOfRM(rm)) { |
| 1945 | putIReg(size, eregOfRM(rm), mkU(ty,0)); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1946 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1947 | assign(dst0, getIReg(size,eregOfRM(rm))); |
| 1948 | assign(src, getIReg(size,gregOfRM(rm))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1949 | |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1950 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1951 | helper_ADC( size, dst1, dst0, src, |
| 1952 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 1953 | putIReg(size, eregOfRM(rm), mkexpr(dst1)); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1954 | } else |
| 1955 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1956 | helper_SBB( size, dst1, dst0, src, |
| 1957 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1958 | putIReg(size, eregOfRM(rm), mkexpr(dst1)); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1959 | } else { |
| 1960 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1961 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1962 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 1963 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1964 | setFlags_DEP1(op8, dst1, ty); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1965 | if (keep) |
| 1966 | putIReg(size, eregOfRM(rm), mkexpr(dst1)); |
| 1967 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1968 | |
| 1969 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 1970 | nameIReg(size,gregOfRM(rm)), |
| 1971 | nameIReg(size,eregOfRM(rm))); |
| 1972 | return 1+delta0; |
| 1973 | } |
| 1974 | |
| 1975 | /* E refers to memory */ |
| 1976 | { |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1977 | addr = disAMode ( &len, sorb, delta0, dis_buf); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1978 | assign(dst0, loadLE(ty,mkexpr(addr))); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1979 | assign(src, getIReg(size,gregOfRM(rm))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1980 | |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1981 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1982 | if (locked) { |
| 1983 | /* cas-style store */ |
| 1984 | helper_ADC( size, dst1, dst0, src, |
| 1985 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 1986 | } else { |
| 1987 | /* normal store */ |
| 1988 | helper_ADC( size, dst1, dst0, src, |
| 1989 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 1990 | } |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1991 | } else |
| 1992 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1993 | if (locked) { |
| 1994 | /* cas-style store */ |
| 1995 | helper_SBB( size, dst1, dst0, src, |
| 1996 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 1997 | } else { |
| 1998 | /* normal store */ |
| 1999 | helper_SBB( size, dst1, dst0, src, |
| 2000 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2001 | } |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2002 | } else { |
| 2003 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2004 | if (keep) { |
| 2005 | if (locked) { |
| 2006 | if (0) vex_printf("locked case\n" ); |
| 2007 | casLE( mkexpr(addr), |
| 2008 | mkexpr(dst0)/*expval*/, |
| 2009 | mkexpr(dst1)/*newval*/, guest_EIP_curr_instr ); |
| 2010 | } else { |
| 2011 | if (0) vex_printf("nonlocked case\n"); |
| 2012 | storeLE(mkexpr(addr), mkexpr(dst1)); |
| 2013 | } |
| 2014 | } |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2015 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2016 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2017 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2018 | setFlags_DEP1(op8, dst1, ty); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2019 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2020 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2021 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 2022 | nameIReg(size,gregOfRM(rm)), dis_buf); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2023 | return len+delta0; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2024 | } |
| 2025 | } |
| 2026 | |
| 2027 | |
| 2028 | /* Handle move instructions of the form |
| 2029 | mov E, G meaning |
| 2030 | mov reg-or-mem, reg |
| 2031 | Is passed the a ptr to the modRM byte, and the data size. Returns |
| 2032 | the address advanced completely over this instruction. |
| 2033 | |
| 2034 | E(src) is reg-or-mem |
| 2035 | G(dst) is reg. |
| 2036 | |
| 2037 | If E is reg, --> GET %E, tmpv |
| 2038 | PUT tmpv, %G |
| 2039 | |
| 2040 | If E is mem --> (getAddr E) -> tmpa |
| 2041 | LD (tmpa), tmpb |
| 2042 | PUT tmpb, %G |
| 2043 | */ |
| 2044 | static |
| 2045 | UInt dis_mov_E_G ( UChar sorb, |
| 2046 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2047 | Int delta0 ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2048 | { |
| 2049 | Int len; |
| 2050 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2051 | HChar dis_buf[50]; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2052 | |
| 2053 | if (epartIsReg(rm)) { |
sewardj | 7ca37d9 | 2004-10-25 02:58:30 +0000 | [diff] [blame] | 2054 | putIReg(size, gregOfRM(rm), getIReg(size, eregOfRM(rm))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2055 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2056 | nameIReg(size,eregOfRM(rm)), |
| 2057 | nameIReg(size,gregOfRM(rm))); |
sewardj | 7ca37d9 | 2004-10-25 02:58:30 +0000 | [diff] [blame] | 2058 | return 1+delta0; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2059 | } |
| 2060 | |
| 2061 | /* E refers to memory */ |
| 2062 | { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2063 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 2064 | putIReg(size, gregOfRM(rm), loadLE(szToITy(size), mkexpr(addr))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2065 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2066 | dis_buf,nameIReg(size,gregOfRM(rm))); |
| 2067 | return delta0+len; |
| 2068 | } |
| 2069 | } |
| 2070 | |
| 2071 | |
| 2072 | /* Handle move instructions of the form |
| 2073 | mov G, E meaning |
| 2074 | mov reg, reg-or-mem |
| 2075 | Is passed the a ptr to the modRM byte, and the data size. Returns |
| 2076 | the address advanced completely over this instruction. |
| 2077 | |
| 2078 | G(src) is reg. |
| 2079 | E(dst) is reg-or-mem |
| 2080 | |
| 2081 | If E is reg, --> GET %G, tmp |
| 2082 | PUT tmp, %E |
| 2083 | |
| 2084 | If E is mem, --> (getAddr E) -> tmpa |
| 2085 | GET %G, tmpv |
| 2086 | ST tmpv, (tmpa) |
| 2087 | */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2088 | static |
| 2089 | UInt dis_mov_G_E ( UChar sorb, |
| 2090 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2091 | Int delta0 ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2092 | { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2093 | Int len; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2094 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2095 | HChar dis_buf[50]; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2096 | |
| 2097 | if (epartIsReg(rm)) { |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2098 | putIReg(size, eregOfRM(rm), getIReg(size, gregOfRM(rm))); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2099 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2100 | nameIReg(size,gregOfRM(rm)), |
| 2101 | nameIReg(size,eregOfRM(rm))); |
| 2102 | return 1+delta0; |
| 2103 | } |
| 2104 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2105 | /* E refers to memory */ |
| 2106 | { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2107 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf); |
| 2108 | storeLE( mkexpr(addr), getIReg(size, gregOfRM(rm)) ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2109 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2110 | nameIReg(size,gregOfRM(rm)), dis_buf); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2111 | return len+delta0; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2112 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2113 | } |
| 2114 | |
| 2115 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2116 | /* op $immediate, AL/AX/EAX. */ |
| 2117 | static |
| 2118 | UInt dis_op_imm_A ( Int size, |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2119 | Bool carrying, |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2120 | IROp op8, |
| 2121 | Bool keep, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2122 | Int delta, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 2123 | HChar* t_x86opc ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2124 | { |
| 2125 | IRType ty = szToITy(size); |
| 2126 | IRTemp dst0 = newTemp(ty); |
| 2127 | IRTemp src = newTemp(ty); |
| 2128 | IRTemp dst1 = newTemp(ty); |
| 2129 | UInt lit = getUDisp(size,delta); |
| 2130 | assign(dst0, getIReg(size,R_EAX)); |
| 2131 | assign(src, mkU(ty,lit)); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2132 | |
| 2133 | if (isAddSub(op8) && !carrying) { |
| 2134 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2135 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2136 | } |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2137 | else |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2138 | if (isLogic(op8)) { |
| 2139 | vassert(!carrying); |
| 2140 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2141 | setFlags_DEP1(op8, dst1, ty); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2142 | } |
| 2143 | else |
| 2144 | if (op8 == Iop_Add8 && carrying) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2145 | helper_ADC( size, dst1, dst0, src, |
| 2146 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2147 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2148 | else |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 2149 | if (op8 == Iop_Sub8 && carrying) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2150 | helper_SBB( size, dst1, dst0, src, |
| 2151 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 2152 | } |
| 2153 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2154 | vpanic("dis_op_imm_A(x86,guest)"); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2155 | |
| 2156 | if (keep) |
| 2157 | putIReg(size, R_EAX, mkexpr(dst1)); |
| 2158 | |
| 2159 | DIP("%s%c $0x%x, %s\n", t_x86opc, nameISize(size), |
| 2160 | lit, nameIReg(size,R_EAX)); |
| 2161 | return delta+size; |
| 2162 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2163 | |
| 2164 | |
| 2165 | /* Sign- and Zero-extending moves. */ |
| 2166 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2167 | UInt dis_movx_E_G ( UChar sorb, |
| 2168 | Int delta, Int szs, Int szd, Bool sign_extend ) |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2169 | { |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2170 | UChar rm = getIByte(delta); |
| 2171 | if (epartIsReg(rm)) { |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 2172 | if (szd == szs) { |
| 2173 | // mutant case. See #250799 |
| 2174 | putIReg(szd, gregOfRM(rm), |
| 2175 | getIReg(szs,eregOfRM(rm))); |
| 2176 | } else { |
| 2177 | // normal case |
| 2178 | putIReg(szd, gregOfRM(rm), |
| 2179 | unop(mkWidenOp(szs,szd,sign_extend), |
| 2180 | getIReg(szs,eregOfRM(rm)))); |
| 2181 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2182 | DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z', |
| 2183 | nameISize(szs), nameISize(szd), |
| 2184 | nameIReg(szs,eregOfRM(rm)), |
| 2185 | nameIReg(szd,gregOfRM(rm))); |
| 2186 | return 1+delta; |
| 2187 | } |
| 2188 | |
| 2189 | /* E refers to memory */ |
| 2190 | { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2191 | Int len; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2192 | HChar dis_buf[50]; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2193 | IRTemp addr = disAMode ( &len, sorb, delta, dis_buf ); |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 2194 | if (szd == szs) { |
| 2195 | // mutant case. See #250799 |
| 2196 | putIReg(szd, gregOfRM(rm), |
| 2197 | loadLE(szToITy(szs),mkexpr(addr))); |
| 2198 | } else { |
| 2199 | // normal case |
| 2200 | putIReg(szd, gregOfRM(rm), |
| 2201 | unop(mkWidenOp(szs,szd,sign_extend), |
| 2202 | loadLE(szToITy(szs),mkexpr(addr)))); |
| 2203 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2204 | DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z', |
| 2205 | nameISize(szs), nameISize(szd), |
| 2206 | dis_buf, nameIReg(szd,gregOfRM(rm))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2207 | return len+delta; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2208 | } |
| 2209 | } |
| 2210 | |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2211 | |
| 2212 | /* Generate code to divide ArchRegs EDX:EAX / DX:AX / AX by the 32 / |
| 2213 | 16 / 8 bit quantity in the given IRTemp. */ |
| 2214 | static |
| 2215 | void codegen_div ( Int sz, IRTemp t, Bool signed_divide ) |
| 2216 | { |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2217 | IROp op = signed_divide ? Iop_DivModS64to32 : Iop_DivModU64to32; |
| 2218 | IRTemp src64 = newTemp(Ity_I64); |
| 2219 | IRTemp dst64 = newTemp(Ity_I64); |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2220 | switch (sz) { |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2221 | case 4: |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2222 | assign( src64, binop(Iop_32HLto64, |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2223 | getIReg(4,R_EDX), getIReg(4,R_EAX)) ); |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2224 | assign( dst64, binop(op, mkexpr(src64), mkexpr(t)) ); |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 2225 | putIReg( 4, R_EAX, unop(Iop_64to32,mkexpr(dst64)) ); |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2226 | putIReg( 4, R_EDX, unop(Iop_64HIto32,mkexpr(dst64)) ); |
| 2227 | break; |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2228 | case 2: { |
| 2229 | IROp widen3264 = signed_divide ? Iop_32Sto64 : Iop_32Uto64; |
| 2230 | IROp widen1632 = signed_divide ? Iop_16Sto32 : Iop_16Uto32; |
| 2231 | assign( src64, unop(widen3264, |
| 2232 | binop(Iop_16HLto32, |
| 2233 | getIReg(2,R_EDX), getIReg(2,R_EAX))) ); |
| 2234 | assign( dst64, binop(op, mkexpr(src64), unop(widen1632,mkexpr(t))) ); |
| 2235 | putIReg( 2, R_EAX, unop(Iop_32to16,unop(Iop_64to32,mkexpr(dst64))) ); |
| 2236 | putIReg( 2, R_EDX, unop(Iop_32to16,unop(Iop_64HIto32,mkexpr(dst64))) ); |
| 2237 | break; |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2238 | } |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 2239 | case 1: { |
| 2240 | IROp widen3264 = signed_divide ? Iop_32Sto64 : Iop_32Uto64; |
| 2241 | IROp widen1632 = signed_divide ? Iop_16Sto32 : Iop_16Uto32; |
| 2242 | IROp widen816 = signed_divide ? Iop_8Sto16 : Iop_8Uto16; |
| 2243 | assign( src64, unop(widen3264, unop(widen1632, getIReg(2,R_EAX))) ); |
| 2244 | assign( dst64, |
| 2245 | binop(op, mkexpr(src64), |
| 2246 | unop(widen1632, unop(widen816, mkexpr(t)))) ); |
| 2247 | putIReg( 1, R_AL, unop(Iop_16to8, unop(Iop_32to16, |
| 2248 | unop(Iop_64to32,mkexpr(dst64)))) ); |
| 2249 | putIReg( 1, R_AH, unop(Iop_16to8, unop(Iop_32to16, |
| 2250 | unop(Iop_64HIto32,mkexpr(dst64)))) ); |
| 2251 | break; |
| 2252 | } |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2253 | default: vpanic("codegen_div(x86)"); |
| 2254 | } |
| 2255 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2256 | |
| 2257 | |
| 2258 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2259 | UInt dis_Grp1 ( UChar sorb, Bool locked, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2260 | Int delta, UChar modrm, |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2261 | Int am_sz, Int d_sz, Int sz, UInt d32 ) |
| 2262 | { |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2263 | Int len; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2264 | HChar dis_buf[50]; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2265 | IRType ty = szToITy(sz); |
| 2266 | IRTemp dst1 = newTemp(ty); |
| 2267 | IRTemp src = newTemp(ty); |
| 2268 | IRTemp dst0 = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 2269 | IRTemp addr = IRTemp_INVALID; |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2270 | IROp op8 = Iop_INVALID; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2271 | UInt mask = sz==1 ? 0xFF : (sz==2 ? 0xFFFF : 0xFFFFFFFF); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2272 | |
| 2273 | switch (gregOfRM(modrm)) { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2274 | case 0: op8 = Iop_Add8; break; case 1: op8 = Iop_Or8; break; |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2275 | case 2: break; // ADC |
| 2276 | case 3: break; // SBB |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2277 | case 4: op8 = Iop_And8; break; case 5: op8 = Iop_Sub8; break; |
| 2278 | case 6: op8 = Iop_Xor8; break; case 7: op8 = Iop_Sub8; break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2279 | /*NOTREACHED*/ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2280 | default: vpanic("dis_Grp1: unhandled case"); |
| 2281 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2282 | |
| 2283 | if (epartIsReg(modrm)) { |
| 2284 | vassert(am_sz == 1); |
| 2285 | |
| 2286 | assign(dst0, getIReg(sz,eregOfRM(modrm))); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2287 | assign(src, mkU(ty,d32 & mask)); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2288 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2289 | if (gregOfRM(modrm) == 2 /* ADC */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2290 | helper_ADC( sz, dst1, dst0, src, |
| 2291 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2292 | } else |
| 2293 | if (gregOfRM(modrm) == 3 /* SBB */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2294 | helper_SBB( sz, dst1, dst0, src, |
| 2295 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2296 | } else { |
| 2297 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2298 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2299 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2300 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2301 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2302 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2303 | |
| 2304 | if (gregOfRM(modrm) < 7) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2305 | putIReg(sz, eregOfRM(modrm), mkexpr(dst1)); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2306 | |
| 2307 | delta += (am_sz + d_sz); |
| 2308 | DIP("%s%c $0x%x, %s\n", nameGrp1(gregOfRM(modrm)), nameISize(sz), d32, |
| 2309 | nameIReg(sz,eregOfRM(modrm))); |
| 2310 | } else { |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2311 | addr = disAMode ( &len, sorb, delta, dis_buf); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2312 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2313 | assign(dst0, loadLE(ty,mkexpr(addr))); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2314 | assign(src, mkU(ty,d32 & mask)); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2315 | |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2316 | if (gregOfRM(modrm) == 2 /* ADC */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2317 | if (locked) { |
| 2318 | /* cas-style store */ |
| 2319 | helper_ADC( sz, dst1, dst0, src, |
| 2320 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 2321 | } else { |
| 2322 | /* normal store */ |
| 2323 | helper_ADC( sz, dst1, dst0, src, |
| 2324 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2325 | } |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 2326 | } else |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2327 | if (gregOfRM(modrm) == 3 /* SBB */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2328 | if (locked) { |
| 2329 | /* cas-style store */ |
| 2330 | helper_SBB( sz, dst1, dst0, src, |
| 2331 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 2332 | } else { |
| 2333 | /* normal store */ |
| 2334 | helper_SBB( sz, dst1, dst0, src, |
| 2335 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2336 | } |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 2337 | } else { |
| 2338 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2339 | if (gregOfRM(modrm) < 7) { |
| 2340 | if (locked) { |
| 2341 | casLE( mkexpr(addr), mkexpr(dst0)/*expVal*/, |
| 2342 | mkexpr(dst1)/*newVal*/, |
| 2343 | guest_EIP_curr_instr ); |
| 2344 | } else { |
| 2345 | storeLE(mkexpr(addr), mkexpr(dst1)); |
| 2346 | } |
| 2347 | } |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2348 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2349 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2350 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2351 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 2352 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2353 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2354 | delta += (len+d_sz); |
| 2355 | DIP("%s%c $0x%x, %s\n", nameGrp1(gregOfRM(modrm)), nameISize(sz), |
| 2356 | d32, dis_buf); |
| 2357 | } |
| 2358 | return delta; |
| 2359 | } |
| 2360 | |
| 2361 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2362 | /* Group 2 extended opcodes. shift_expr must be an 8-bit typed |
| 2363 | expression. */ |
| 2364 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2365 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2366 | UInt dis_Grp2 ( UChar sorb, |
| 2367 | Int delta, UChar modrm, |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2368 | Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2369 | HChar* shift_expr_txt, Bool* decode_OK ) |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2370 | { |
| 2371 | /* delta on entry points at the modrm byte. */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2372 | HChar dis_buf[50]; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2373 | Int len; |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2374 | Bool isShift, isRotate, isRotateC; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2375 | IRType ty = szToITy(sz); |
| 2376 | IRTemp dst0 = newTemp(ty); |
| 2377 | IRTemp dst1 = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 2378 | IRTemp addr = IRTemp_INVALID; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2379 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2380 | *decode_OK = True; |
| 2381 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2382 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 2383 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2384 | /* Put value to shift/rotate in dst0. */ |
| 2385 | if (epartIsReg(modrm)) { |
| 2386 | assign(dst0, getIReg(sz, eregOfRM(modrm))); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2387 | delta += (am_sz + d_sz); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2388 | } else { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2389 | addr = disAMode ( &len, sorb, delta, dis_buf); |
| 2390 | assign(dst0, loadLE(ty,mkexpr(addr))); |
| 2391 | delta += len + d_sz; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2392 | } |
| 2393 | |
| 2394 | isShift = False; |
tom | d6b43fd | 2011-08-19 16:06:52 +0000 | [diff] [blame^] | 2395 | switch (gregOfRM(modrm)) { case 4: case 5: case 6: case 7: isShift = True; } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2396 | |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2397 | isRotate = False; |
| 2398 | switch (gregOfRM(modrm)) { case 0: case 1: isRotate = True; } |
| 2399 | |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2400 | isRotateC = False; |
| 2401 | switch (gregOfRM(modrm)) { case 2: case 3: isRotateC = True; } |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2402 | |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2403 | if (!isShift && !isRotate && !isRotateC) { |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2404 | /*NOTREACHED*/ |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 2405 | vpanic("dis_Grp2(Reg): unhandled case(x86)"); |
| 2406 | } |
| 2407 | |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2408 | if (isRotateC) { |
| 2409 | /* call a helper; these insns are so ridiculous they do not |
| 2410 | deserve better */ |
| 2411 | Bool left = toBool(gregOfRM(modrm) == 2); |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2412 | IRTemp r64 = newTemp(Ity_I64); |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2413 | IRExpr** args |
| 2414 | = mkIRExprVec_4( widenUto32(mkexpr(dst0)), /* thing to rotate */ |
| 2415 | widenUto32(shift_expr), /* rotate amount */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2416 | widenUto32(mk_x86g_calculate_eflags_all()), |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2417 | mkU32(sz) ); |
| 2418 | assign( r64, mkIRExprCCall( |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2419 | Ity_I64, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2420 | 0/*regparm*/, |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2421 | left ? "x86g_calculate_RCL" : "x86g_calculate_RCR", |
| 2422 | left ? &x86g_calculate_RCL : &x86g_calculate_RCR, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2423 | args |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2424 | ) |
| 2425 | ); |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2426 | /* new eflags in hi half r64; new value in lo half r64 */ |
| 2427 | assign( dst1, narrowTo(ty, unop(Iop_64to32, mkexpr(r64))) ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2428 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2429 | stmt( IRStmt_Put( OFFB_CC_DEP1, unop(Iop_64HIto32, mkexpr(r64)) )); |
| 2430 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 2431 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 2432 | elimination of previous stores to this field work better. */ |
| 2433 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2434 | } |
| 2435 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2436 | if (isShift) { |
| 2437 | |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2438 | IRTemp pre32 = newTemp(Ity_I32); |
| 2439 | IRTemp res32 = newTemp(Ity_I32); |
| 2440 | IRTemp res32ss = newTemp(Ity_I32); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2441 | IRTemp shift_amt = newTemp(Ity_I8); |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2442 | IROp op32; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2443 | |
| 2444 | switch (gregOfRM(modrm)) { |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2445 | case 4: op32 = Iop_Shl32; break; |
| 2446 | case 5: op32 = Iop_Shr32; break; |
tom | d6b43fd | 2011-08-19 16:06:52 +0000 | [diff] [blame^] | 2447 | case 6: op32 = Iop_Shl32; break; |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2448 | case 7: op32 = Iop_Sar32; break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2449 | /*NOTREACHED*/ |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2450 | default: vpanic("dis_Grp2:shift"); break; |
| 2451 | } |
| 2452 | |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2453 | /* Widen the value to be shifted to 32 bits, do the shift, and |
| 2454 | narrow back down. This seems surprisingly long-winded, but |
| 2455 | unfortunately the Intel semantics requires that 8/16-bit |
| 2456 | shifts give defined results for shift values all the way up |
| 2457 | to 31, and this seems the simplest way to do it. It has the |
| 2458 | advantage that the only IR level shifts generated are of 32 |
| 2459 | bit values, and the shift amount is guaranteed to be in the |
| 2460 | range 0 .. 31, thereby observing the IR semantics requiring |
| 2461 | all shift values to be in the range 0 .. 2^word_size-1. */ |
| 2462 | |
| 2463 | /* shift_amt = shift_expr & 31, regardless of operation size */ |
| 2464 | assign( shift_amt, binop(Iop_And8, shift_expr, mkU8(31)) ); |
| 2465 | |
| 2466 | /* suitably widen the value to be shifted to 32 bits. */ |
| 2467 | assign( pre32, op32==Iop_Sar32 ? widenSto32(mkexpr(dst0)) |
| 2468 | : widenUto32(mkexpr(dst0)) ); |
| 2469 | |
| 2470 | /* res32 = pre32 `shift` shift_amt */ |
| 2471 | assign( res32, binop(op32, mkexpr(pre32), mkexpr(shift_amt)) ); |
| 2472 | |
| 2473 | /* res32ss = pre32 `shift` ((shift_amt - 1) & 31) */ |
| 2474 | assign( res32ss, |
| 2475 | binop(op32, |
| 2476 | mkexpr(pre32), |
| 2477 | binop(Iop_And8, |
| 2478 | binop(Iop_Sub8, |
| 2479 | mkexpr(shift_amt), mkU8(1)), |
| 2480 | mkU8(31))) ); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2481 | |
| 2482 | /* Build the flags thunk. */ |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2483 | setFlags_DEP1_DEP2_shift(op32, res32, res32ss, ty, shift_amt); |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2484 | |
| 2485 | /* Narrow the result back down. */ |
| 2486 | assign( dst1, narrowTo(ty, mkexpr(res32)) ); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2487 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2488 | } /* if (isShift) */ |
| 2489 | |
| 2490 | else |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2491 | if (isRotate) { |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2492 | Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 2493 | Bool left = toBool(gregOfRM(modrm) == 0); |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2494 | IRTemp rot_amt = newTemp(Ity_I8); |
| 2495 | IRTemp rot_amt32 = newTemp(Ity_I8); |
| 2496 | IRTemp oldFlags = newTemp(Ity_I32); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2497 | |
| 2498 | /* rot_amt = shift_expr & mask */ |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2499 | /* By masking the rotate amount thusly, the IR-level Shl/Shr |
| 2500 | expressions never shift beyond the word size and thus remain |
| 2501 | well defined. */ |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2502 | assign(rot_amt32, binop(Iop_And8, shift_expr, mkU8(31))); |
| 2503 | |
| 2504 | if (ty == Ity_I32) |
| 2505 | assign(rot_amt, mkexpr(rot_amt32)); |
| 2506 | else |
| 2507 | assign(rot_amt, binop(Iop_And8, mkexpr(rot_amt32), mkU8(8*sz-1))); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2508 | |
| 2509 | if (left) { |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2510 | |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2511 | /* dst1 = (dst0 << rot_amt) | (dst0 >>u (wordsize-rot_amt)) */ |
| 2512 | assign(dst1, |
| 2513 | binop( mkSizedOp(ty,Iop_Or8), |
| 2514 | binop( mkSizedOp(ty,Iop_Shl8), |
| 2515 | mkexpr(dst0), |
| 2516 | mkexpr(rot_amt) |
| 2517 | ), |
| 2518 | binop( mkSizedOp(ty,Iop_Shr8), |
| 2519 | mkexpr(dst0), |
| 2520 | binop(Iop_Sub8,mkU8(8*sz), mkexpr(rot_amt)) |
| 2521 | ) |
| 2522 | ) |
| 2523 | ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2524 | ccOp += X86G_CC_OP_ROLB; |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2525 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2526 | } else { /* right */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2527 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2528 | /* dst1 = (dst0 >>u rot_amt) | (dst0 << (wordsize-rot_amt)) */ |
| 2529 | assign(dst1, |
| 2530 | binop( mkSizedOp(ty,Iop_Or8), |
| 2531 | binop( mkSizedOp(ty,Iop_Shr8), |
| 2532 | mkexpr(dst0), |
| 2533 | mkexpr(rot_amt) |
| 2534 | ), |
| 2535 | binop( mkSizedOp(ty,Iop_Shl8), |
| 2536 | mkexpr(dst0), |
| 2537 | binop(Iop_Sub8,mkU8(8*sz), mkexpr(rot_amt)) |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2538 | ) |
| 2539 | ) |
| 2540 | ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2541 | ccOp += X86G_CC_OP_RORB; |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2542 | |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2543 | } |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2544 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2545 | /* dst1 now holds the rotated value. Build flag thunk. We |
| 2546 | need the resulting value for this, and the previous flags. |
| 2547 | Except don't set it if the rotate count is zero. */ |
| 2548 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2549 | assign(oldFlags, mk_x86g_calculate_eflags_all()); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2550 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2551 | /* CC_DEP1 is the rotated value. CC_NDEP is flags before. */ |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2552 | stmt( IRStmt_Put( OFFB_CC_OP, |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2553 | IRExpr_Mux0X( mkexpr(rot_amt32), |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2554 | IRExpr_Get(OFFB_CC_OP,Ity_I32), |
| 2555 | mkU32(ccOp))) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2556 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2557 | IRExpr_Mux0X( mkexpr(rot_amt32), |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2558 | IRExpr_Get(OFFB_CC_DEP1,Ity_I32), |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2559 | widenUto32(mkexpr(dst1)))) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2560 | stmt( IRStmt_Put( OFFB_CC_DEP2, |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2561 | IRExpr_Mux0X( mkexpr(rot_amt32), |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2562 | IRExpr_Get(OFFB_CC_DEP2,Ity_I32), |
| 2563 | mkU32(0))) ); |
| 2564 | stmt( IRStmt_Put( OFFB_CC_NDEP, |
| 2565 | IRExpr_Mux0X( mkexpr(rot_amt32), |
| 2566 | IRExpr_Get(OFFB_CC_NDEP,Ity_I32), |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2567 | mkexpr(oldFlags))) ); |
| 2568 | } /* if (isRotate) */ |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2569 | |
| 2570 | /* Save result, and finish up. */ |
| 2571 | if (epartIsReg(modrm)) { |
| 2572 | putIReg(sz, eregOfRM(modrm), mkexpr(dst1)); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 2573 | if (vex_traceflags & VEX_TRACE_FE) { |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2574 | vex_printf("%s%c ", |
| 2575 | nameGrp2(gregOfRM(modrm)), nameISize(sz) ); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2576 | if (shift_expr_txt) |
| 2577 | vex_printf("%s", shift_expr_txt); |
| 2578 | else |
| 2579 | ppIRExpr(shift_expr); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2580 | vex_printf(", %s\n", nameIReg(sz,eregOfRM(modrm))); |
| 2581 | } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2582 | } else { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2583 | storeLE(mkexpr(addr), mkexpr(dst1)); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 2584 | if (vex_traceflags & VEX_TRACE_FE) { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2585 | vex_printf("%s%c ", |
| 2586 | nameGrp2(gregOfRM(modrm)), nameISize(sz) ); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2587 | if (shift_expr_txt) |
| 2588 | vex_printf("%s", shift_expr_txt); |
| 2589 | else |
| 2590 | ppIRExpr(shift_expr); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2591 | vex_printf(", %s\n", dis_buf); |
| 2592 | } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2593 | } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2594 | return delta; |
| 2595 | } |
| 2596 | |
| 2597 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2598 | /* Group 8 extended opcodes (but BT/BTS/BTC/BTR only). */ |
| 2599 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2600 | UInt dis_Grp8_Imm ( UChar sorb, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2601 | Bool locked, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2602 | Int delta, UChar modrm, |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2603 | Int am_sz, Int sz, UInt src_val, |
| 2604 | Bool* decode_OK ) |
| 2605 | { |
| 2606 | /* src_val denotes a d8. |
| 2607 | And delta on entry points at the modrm byte. */ |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2608 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2609 | IRType ty = szToITy(sz); |
| 2610 | IRTemp t2 = newTemp(Ity_I32); |
| 2611 | IRTemp t2m = newTemp(Ity_I32); |
| 2612 | IRTemp t_addr = IRTemp_INVALID; |
| 2613 | HChar dis_buf[50]; |
| 2614 | UInt mask; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 2615 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2616 | /* we're optimists :-) */ |
| 2617 | *decode_OK = True; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 2618 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2619 | /* Limit src_val -- the bit offset -- to something within a word. |
| 2620 | The Intel docs say that literal offsets larger than a word are |
| 2621 | masked in this way. */ |
| 2622 | switch (sz) { |
| 2623 | case 2: src_val &= 15; break; |
| 2624 | case 4: src_val &= 31; break; |
| 2625 | default: *decode_OK = False; return delta; |
| 2626 | } |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2627 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2628 | /* Invent a mask suitable for the operation. */ |
| 2629 | switch (gregOfRM(modrm)) { |
| 2630 | case 4: /* BT */ mask = 0; break; |
| 2631 | case 5: /* BTS */ mask = 1 << src_val; break; |
| 2632 | case 6: /* BTR */ mask = ~(1 << src_val); break; |
| 2633 | case 7: /* BTC */ mask = 1 << src_val; break; |
| 2634 | /* If this needs to be extended, probably simplest to make a |
| 2635 | new function to handle the other cases (0 .. 3). The |
| 2636 | Intel docs do however not indicate any use for 0 .. 3, so |
| 2637 | we don't expect this to happen. */ |
| 2638 | default: *decode_OK = False; return delta; |
| 2639 | } |
| 2640 | |
| 2641 | /* Fetch the value to be tested and modified into t2, which is |
| 2642 | 32-bits wide regardless of sz. */ |
| 2643 | if (epartIsReg(modrm)) { |
| 2644 | vassert(am_sz == 1); |
sewardj | 5a8334e | 2005-03-13 19:52:45 +0000 | [diff] [blame] | 2645 | assign( t2, widenUto32(getIReg(sz, eregOfRM(modrm))) ); |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2646 | delta += (am_sz + 1); |
| 2647 | DIP("%s%c $0x%x, %s\n", nameGrp8(gregOfRM(modrm)), nameISize(sz), |
| 2648 | src_val, nameIReg(sz,eregOfRM(modrm))); |
| 2649 | } else { |
| 2650 | Int len; |
| 2651 | t_addr = disAMode ( &len, sorb, delta, dis_buf); |
| 2652 | delta += (len+1); |
| 2653 | assign( t2, widenUto32(loadLE(ty, mkexpr(t_addr))) ); |
| 2654 | DIP("%s%c $0x%x, %s\n", nameGrp8(gregOfRM(modrm)), nameISize(sz), |
| 2655 | src_val, dis_buf); |
| 2656 | } |
| 2657 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2658 | /* Compute the new value into t2m, if non-BT. */ |
| 2659 | switch (gregOfRM(modrm)) { |
| 2660 | case 4: /* BT */ |
| 2661 | break; |
| 2662 | case 5: /* BTS */ |
| 2663 | assign( t2m, binop(Iop_Or32, mkU32(mask), mkexpr(t2)) ); |
| 2664 | break; |
| 2665 | case 6: /* BTR */ |
| 2666 | assign( t2m, binop(Iop_And32, mkU32(mask), mkexpr(t2)) ); |
| 2667 | break; |
| 2668 | case 7: /* BTC */ |
| 2669 | assign( t2m, binop(Iop_Xor32, mkU32(mask), mkexpr(t2)) ); |
| 2670 | break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 2671 | default: |
| 2672 | /*NOTREACHED*/ /*the previous switch guards this*/ |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2673 | vassert(0); |
| 2674 | } |
| 2675 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2676 | /* Write the result back, if non-BT. If the CAS fails then we |
| 2677 | side-exit from the trace at this point, and so the flag state is |
| 2678 | not affected. This is of course as required. */ |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2679 | if (gregOfRM(modrm) != 4 /* BT */) { |
| 2680 | if (epartIsReg(modrm)) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2681 | putIReg(sz, eregOfRM(modrm), narrowTo(ty, mkexpr(t2m))); |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2682 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2683 | if (locked) { |
| 2684 | casLE( mkexpr(t_addr), |
| 2685 | narrowTo(ty, mkexpr(t2))/*expd*/, |
| 2686 | narrowTo(ty, mkexpr(t2m))/*new*/, |
| 2687 | guest_EIP_curr_instr ); |
| 2688 | } else { |
| 2689 | storeLE(mkexpr(t_addr), narrowTo(ty, mkexpr(t2m))); |
| 2690 | } |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2691 | } |
| 2692 | } |
| 2693 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2694 | /* Copy relevant bit from t2 into the carry flag. */ |
| 2695 | /* Flags: C=selected bit, O,S,Z,A,P undefined, so are set to zero. */ |
| 2696 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 2697 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 2698 | stmt( IRStmt_Put( |
| 2699 | OFFB_CC_DEP1, |
| 2700 | binop(Iop_And32, |
| 2701 | binop(Iop_Shr32, mkexpr(t2), mkU8(src_val)), |
| 2702 | mkU32(1)) |
| 2703 | )); |
| 2704 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 2705 | elimination of previous stores to this field work better. */ |
| 2706 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 2707 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2708 | return delta; |
| 2709 | } |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2710 | |
| 2711 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2712 | /* Signed/unsigned widening multiply. Generate IR to multiply the |
| 2713 | value in EAX/AX/AL by the given IRTemp, and park the result in |
| 2714 | EDX:EAX/DX:AX/AX. |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2715 | */ |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2716 | static void codegen_mulL_A_D ( Int sz, Bool syned, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 2717 | IRTemp tmp, HChar* tmp_txt ) |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2718 | { |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2719 | IRType ty = szToITy(sz); |
| 2720 | IRTemp t1 = newTemp(ty); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2721 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2722 | assign( t1, getIReg(sz, R_EAX) ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2723 | |
| 2724 | switch (ty) { |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2725 | case Ity_I32: { |
| 2726 | IRTemp res64 = newTemp(Ity_I64); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2727 | IRTemp resHi = newTemp(Ity_I32); |
| 2728 | IRTemp resLo = newTemp(Ity_I32); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2729 | IROp mulOp = syned ? Iop_MullS32 : Iop_MullU32; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2730 | UInt tBaseOp = syned ? X86G_CC_OP_SMULB : X86G_CC_OP_UMULB; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2731 | setFlags_MUL ( Ity_I32, t1, tmp, tBaseOp ); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2732 | assign( res64, binop(mulOp, mkexpr(t1), mkexpr(tmp)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2733 | assign( resHi, unop(Iop_64HIto32,mkexpr(res64))); |
| 2734 | assign( resLo, unop(Iop_64to32,mkexpr(res64))); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2735 | putIReg(4, R_EDX, mkexpr(resHi)); |
| 2736 | putIReg(4, R_EAX, mkexpr(resLo)); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2737 | break; |
| 2738 | } |
| 2739 | case Ity_I16: { |
| 2740 | IRTemp res32 = newTemp(Ity_I32); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2741 | IRTemp resHi = newTemp(Ity_I16); |
| 2742 | IRTemp resLo = newTemp(Ity_I16); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2743 | IROp mulOp = syned ? Iop_MullS16 : Iop_MullU16; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2744 | UInt tBaseOp = syned ? X86G_CC_OP_SMULB : X86G_CC_OP_UMULB; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2745 | setFlags_MUL ( Ity_I16, t1, tmp, tBaseOp ); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2746 | assign( res32, binop(mulOp, mkexpr(t1), mkexpr(tmp)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2747 | assign( resHi, unop(Iop_32HIto16,mkexpr(res32))); |
| 2748 | assign( resLo, unop(Iop_32to16,mkexpr(res32))); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2749 | putIReg(2, R_EDX, mkexpr(resHi)); |
| 2750 | putIReg(2, R_EAX, mkexpr(resLo)); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2751 | break; |
| 2752 | } |
| 2753 | case Ity_I8: { |
| 2754 | IRTemp res16 = newTemp(Ity_I16); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2755 | IRTemp resHi = newTemp(Ity_I8); |
| 2756 | IRTemp resLo = newTemp(Ity_I8); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2757 | IROp mulOp = syned ? Iop_MullS8 : Iop_MullU8; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2758 | UInt tBaseOp = syned ? X86G_CC_OP_SMULB : X86G_CC_OP_UMULB; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2759 | setFlags_MUL ( Ity_I8, t1, tmp, tBaseOp ); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2760 | assign( res16, binop(mulOp, mkexpr(t1), mkexpr(tmp)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2761 | assign( resHi, unop(Iop_16HIto8,mkexpr(res16))); |
| 2762 | assign( resLo, unop(Iop_16to8,mkexpr(res16))); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2763 | putIReg(2, R_EAX, mkexpr(res16)); |
| 2764 | break; |
| 2765 | } |
| 2766 | default: |
| 2767 | vpanic("codegen_mulL_A_D(x86)"); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2768 | } |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2769 | DIP("%s%c %s\n", syned ? "imul" : "mul", nameISize(sz), tmp_txt); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2770 | } |
| 2771 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2772 | |
| 2773 | /* Group 3 extended opcodes. */ |
| 2774 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2775 | UInt dis_Grp3 ( UChar sorb, Bool locked, Int sz, Int delta, Bool* decode_OK ) |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2776 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2777 | UInt d32; |
| 2778 | UChar modrm; |
| 2779 | HChar dis_buf[50]; |
| 2780 | Int len; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2781 | IRTemp addr; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2782 | IRType ty = szToITy(sz); |
| 2783 | IRTemp t1 = newTemp(ty); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2784 | IRTemp dst1, src, dst0; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2785 | |
| 2786 | *decode_OK = True; /* may change this later */ |
| 2787 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2788 | modrm = getIByte(delta); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2789 | |
| 2790 | if (locked && (gregOfRM(modrm) != 2 && gregOfRM(modrm) != 3)) { |
| 2791 | /* LOCK prefix only allowed with not and neg subopcodes */ |
| 2792 | *decode_OK = False; |
| 2793 | return delta; |
| 2794 | } |
| 2795 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2796 | if (epartIsReg(modrm)) { |
| 2797 | switch (gregOfRM(modrm)) { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2798 | case 0: { /* TEST */ |
| 2799 | delta++; d32 = getUDisp(sz, delta); delta += sz; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2800 | dst1 = newTemp(ty); |
| 2801 | assign(dst1, binop(mkSizedOp(ty,Iop_And8), |
| 2802 | getIReg(sz,eregOfRM(modrm)), |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2803 | mkU(ty,d32))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2804 | setFlags_DEP1( Iop_And8, dst1, ty ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2805 | DIP("test%c $0x%x, %s\n", nameISize(sz), d32, |
| 2806 | nameIReg(sz, eregOfRM(modrm))); |
| 2807 | break; |
| 2808 | } |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2809 | case 1: /* UNDEFINED */ |
| 2810 | /* The Intel docs imply this insn is undefined and binutils |
| 2811 | agrees. Unfortunately Core 2 will run it (with who |
| 2812 | knows what result?) sandpile.org reckons it's an alias |
| 2813 | for case 0. We play safe. */ |
| 2814 | *decode_OK = False; |
| 2815 | break; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2816 | case 2: /* NOT */ |
| 2817 | delta++; |
| 2818 | putIReg(sz, eregOfRM(modrm), |
| 2819 | unop(mkSizedOp(ty,Iop_Not8), |
| 2820 | getIReg(sz, eregOfRM(modrm)))); |
| 2821 | DIP("not%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2822 | break; |
| 2823 | case 3: /* NEG */ |
| 2824 | delta++; |
| 2825 | dst0 = newTemp(ty); |
| 2826 | src = newTemp(ty); |
| 2827 | dst1 = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2828 | assign(dst0, mkU(ty,0)); |
sewardj | a511afc | 2004-07-29 22:26:03 +0000 | [diff] [blame] | 2829 | assign(src, getIReg(sz,eregOfRM(modrm))); |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 2830 | assign(dst1, binop(mkSizedOp(ty,Iop_Sub8), mkexpr(dst0), mkexpr(src))); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2831 | setFlags_DEP1_DEP2(Iop_Sub8, dst0, src, ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2832 | putIReg(sz, eregOfRM(modrm), mkexpr(dst1)); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2833 | DIP("neg%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2834 | break; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2835 | case 4: /* MUL (unsigned widening) */ |
| 2836 | delta++; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2837 | src = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2838 | assign(src, getIReg(sz,eregOfRM(modrm))); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2839 | codegen_mulL_A_D ( sz, False, src, nameIReg(sz,eregOfRM(modrm)) ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2840 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2841 | case 5: /* IMUL (signed widening) */ |
| 2842 | delta++; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2843 | src = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2844 | assign(src, getIReg(sz,eregOfRM(modrm))); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2845 | codegen_mulL_A_D ( sz, True, src, nameIReg(sz,eregOfRM(modrm)) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2846 | break; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2847 | case 6: /* DIV */ |
| 2848 | delta++; |
| 2849 | assign( t1, getIReg(sz, eregOfRM(modrm)) ); |
| 2850 | codegen_div ( sz, t1, False ); |
| 2851 | DIP("div%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2852 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2853 | case 7: /* IDIV */ |
| 2854 | delta++; |
| 2855 | assign( t1, getIReg(sz, eregOfRM(modrm)) ); |
| 2856 | codegen_div ( sz, t1, True ); |
| 2857 | DIP("idiv%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2858 | break; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2859 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2860 | /* This can't happen - gregOfRM should return 0 .. 7 only */ |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2861 | vpanic("Grp3(x86)"); |
| 2862 | } |
| 2863 | } else { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2864 | addr = disAMode ( &len, sorb, delta, dis_buf ); |
| 2865 | t1 = newTemp(ty); |
| 2866 | delta += len; |
| 2867 | assign(t1, loadLE(ty,mkexpr(addr))); |
| 2868 | switch (gregOfRM(modrm)) { |
| 2869 | case 0: { /* TEST */ |
| 2870 | d32 = getUDisp(sz, delta); delta += sz; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2871 | dst1 = newTemp(ty); |
| 2872 | assign(dst1, binop(mkSizedOp(ty,Iop_And8), |
| 2873 | mkexpr(t1), mkU(ty,d32))); |
| 2874 | setFlags_DEP1( Iop_And8, dst1, ty ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2875 | DIP("test%c $0x%x, %s\n", nameISize(sz), d32, dis_buf); |
| 2876 | break; |
| 2877 | } |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2878 | case 1: /* UNDEFINED */ |
| 2879 | /* See comment above on R case */ |
| 2880 | *decode_OK = False; |
| 2881 | break; |
sewardj | 78fe791 | 2004-08-20 23:38:07 +0000 | [diff] [blame] | 2882 | case 2: /* NOT */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2883 | dst1 = newTemp(ty); |
| 2884 | assign(dst1, unop(mkSizedOp(ty,Iop_Not8), mkexpr(t1))); |
| 2885 | if (locked) { |
| 2886 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(dst1)/*new*/, |
| 2887 | guest_EIP_curr_instr ); |
| 2888 | } else { |
| 2889 | storeLE( mkexpr(addr), mkexpr(dst1) ); |
| 2890 | } |
sewardj | 78fe791 | 2004-08-20 23:38:07 +0000 | [diff] [blame] | 2891 | DIP("not%c %s\n", nameISize(sz), dis_buf); |
| 2892 | break; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 2893 | case 3: /* NEG */ |
| 2894 | dst0 = newTemp(ty); |
| 2895 | src = newTemp(ty); |
| 2896 | dst1 = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2897 | assign(dst0, mkU(ty,0)); |
sewardj | a511afc | 2004-07-29 22:26:03 +0000 | [diff] [blame] | 2898 | assign(src, mkexpr(t1)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2899 | assign(dst1, binop(mkSizedOp(ty,Iop_Sub8), |
| 2900 | mkexpr(dst0), mkexpr(src))); |
| 2901 | if (locked) { |
| 2902 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(dst1)/*new*/, |
| 2903 | guest_EIP_curr_instr ); |
| 2904 | } else { |
| 2905 | storeLE( mkexpr(addr), mkexpr(dst1) ); |
| 2906 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2907 | setFlags_DEP1_DEP2(Iop_Sub8, dst0, src, ty); |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 2908 | DIP("neg%c %s\n", nameISize(sz), dis_buf); |
| 2909 | break; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2910 | case 4: /* MUL */ |
| 2911 | codegen_mulL_A_D ( sz, False, t1, dis_buf ); |
| 2912 | break; |
| 2913 | case 5: /* IMUL */ |
| 2914 | codegen_mulL_A_D ( sz, True, t1, dis_buf ); |
| 2915 | break; |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2916 | case 6: /* DIV */ |
| 2917 | codegen_div ( sz, t1, False ); |
| 2918 | DIP("div%c %s\n", nameISize(sz), dis_buf); |
| 2919 | break; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2920 | case 7: /* IDIV */ |
| 2921 | codegen_div ( sz, t1, True ); |
| 2922 | DIP("idiv%c %s\n", nameISize(sz), dis_buf); |
| 2923 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2924 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2925 | /* This can't happen - gregOfRM should return 0 .. 7 only */ |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2926 | vpanic("Grp3(x86)"); |
| 2927 | } |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2928 | } |
| 2929 | return delta; |
| 2930 | } |
| 2931 | |
| 2932 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2933 | /* Group 4 extended opcodes. */ |
| 2934 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2935 | UInt dis_Grp4 ( UChar sorb, Bool locked, Int delta, Bool* decode_OK ) |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2936 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2937 | Int alen; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2938 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2939 | HChar dis_buf[50]; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2940 | IRType ty = Ity_I8; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2941 | IRTemp t1 = newTemp(ty); |
| 2942 | IRTemp t2 = newTemp(ty); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2943 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2944 | *decode_OK = True; |
| 2945 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2946 | modrm = getIByte(delta); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2947 | |
| 2948 | if (locked && (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1)) { |
| 2949 | /* LOCK prefix only allowed with inc and dec subopcodes */ |
| 2950 | *decode_OK = False; |
| 2951 | return delta; |
| 2952 | } |
| 2953 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2954 | if (epartIsReg(modrm)) { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2955 | assign(t1, getIReg(1, eregOfRM(modrm))); |
| 2956 | switch (gregOfRM(modrm)) { |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2957 | case 0: /* INC */ |
| 2958 | assign(t2, binop(Iop_Add8, mkexpr(t1), mkU8(1))); |
| 2959 | putIReg(1, eregOfRM(modrm), mkexpr(t2)); |
| 2960 | setFlags_INC_DEC( True, t2, ty ); |
| 2961 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2962 | case 1: /* DEC */ |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2963 | assign(t2, binop(Iop_Sub8, mkexpr(t1), mkU8(1))); |
| 2964 | putIReg(1, eregOfRM(modrm), mkexpr(t2)); |
| 2965 | setFlags_INC_DEC( False, t2, ty ); |
| 2966 | break; |
| 2967 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2968 | *decode_OK = False; |
| 2969 | return delta; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2970 | } |
| 2971 | delta++; |
| 2972 | DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)), |
| 2973 | nameIReg(1, eregOfRM(modrm))); |
| 2974 | } else { |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2975 | IRTemp addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 2976 | assign( t1, loadLE(ty, mkexpr(addr)) ); |
| 2977 | switch (gregOfRM(modrm)) { |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 2978 | case 0: /* INC */ |
| 2979 | assign(t2, binop(Iop_Add8, mkexpr(t1), mkU8(1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2980 | if (locked) { |
| 2981 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(t2)/*new*/, |
| 2982 | guest_EIP_curr_instr ); |
| 2983 | } else { |
| 2984 | storeLE( mkexpr(addr), mkexpr(t2) ); |
| 2985 | } |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 2986 | setFlags_INC_DEC( True, t2, ty ); |
| 2987 | break; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2988 | case 1: /* DEC */ |
| 2989 | assign(t2, binop(Iop_Sub8, mkexpr(t1), mkU8(1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2990 | if (locked) { |
| 2991 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(t2)/*new*/, |
| 2992 | guest_EIP_curr_instr ); |
| 2993 | } else { |
| 2994 | storeLE( mkexpr(addr), mkexpr(t2) ); |
| 2995 | } |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2996 | setFlags_INC_DEC( False, t2, ty ); |
| 2997 | break; |
| 2998 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2999 | *decode_OK = False; |
| 3000 | return delta; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 3001 | } |
| 3002 | delta += alen; |
| 3003 | DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)), dis_buf); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3004 | } |
| 3005 | return delta; |
| 3006 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3007 | |
| 3008 | |
| 3009 | /* Group 5 extended opcodes. */ |
| 3010 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3011 | UInt dis_Grp5 ( UChar sorb, Bool locked, Int sz, Int delta, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3012 | DisResult* dres, Bool* decode_OK ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3013 | { |
| 3014 | Int len; |
| 3015 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3016 | HChar dis_buf[50]; |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 3017 | IRTemp addr = IRTemp_INVALID; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3018 | IRType ty = szToITy(sz); |
| 3019 | IRTemp t1 = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 3020 | IRTemp t2 = IRTemp_INVALID; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3021 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3022 | *decode_OK = True; |
| 3023 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3024 | modrm = getIByte(delta); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3025 | |
| 3026 | if (locked && (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1)) { |
| 3027 | /* LOCK prefix only allowed with inc and dec subopcodes */ |
| 3028 | *decode_OK = False; |
| 3029 | return delta; |
| 3030 | } |
| 3031 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3032 | if (epartIsReg(modrm)) { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 3033 | assign(t1, getIReg(sz,eregOfRM(modrm))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3034 | switch (gregOfRM(modrm)) { |
sewardj | 59ff5d4 | 2005-10-05 10:39:58 +0000 | [diff] [blame] | 3035 | case 0: /* INC */ |
| 3036 | vassert(sz == 2 || sz == 4); |
| 3037 | t2 = newTemp(ty); |
| 3038 | assign(t2, binop(mkSizedOp(ty,Iop_Add8), |
| 3039 | mkexpr(t1), mkU(ty,1))); |
| 3040 | setFlags_INC_DEC( True, t2, ty ); |
| 3041 | putIReg(sz,eregOfRM(modrm),mkexpr(t2)); |
| 3042 | break; |
| 3043 | case 1: /* DEC */ |
| 3044 | vassert(sz == 2 || sz == 4); |
| 3045 | t2 = newTemp(ty); |
| 3046 | assign(t2, binop(mkSizedOp(ty,Iop_Sub8), |
| 3047 | mkexpr(t1), mkU(ty,1))); |
| 3048 | setFlags_INC_DEC( False, t2, ty ); |
| 3049 | putIReg(sz,eregOfRM(modrm),mkexpr(t2)); |
| 3050 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3051 | case 2: /* call Ev */ |
| 3052 | vassert(sz == 4); |
| 3053 | t2 = newTemp(Ity_I32); |
| 3054 | assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 3055 | putIReg(4, R_ESP, mkexpr(t2)); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3056 | storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta+1)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 3057 | jmp_treg(Ijk_Call,t1); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3058 | dres->whatNext = Dis_StopHere; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3059 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3060 | case 4: /* jmp Ev */ |
| 3061 | vassert(sz == 4); |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 3062 | jmp_treg(Ijk_Boring,t1); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3063 | dres->whatNext = Dis_StopHere; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3064 | break; |
sewardj | 2890582 | 2006-11-18 22:56:46 +0000 | [diff] [blame] | 3065 | case 6: /* PUSH Ev */ |
| 3066 | vassert(sz == 4 || sz == 2); |
| 3067 | t2 = newTemp(Ity_I32); |
| 3068 | assign( t2, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 3069 | putIReg(4, R_ESP, mkexpr(t2) ); |
| 3070 | storeLE( mkexpr(t2), mkexpr(t1) ); |
| 3071 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3072 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3073 | *decode_OK = False; |
| 3074 | return delta; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3075 | } |
| 3076 | delta++; |
| 3077 | DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)), |
| 3078 | nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 3079 | } else { |
| 3080 | addr = disAMode ( &len, sorb, delta, dis_buf ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 3081 | assign(t1, loadLE(ty,mkexpr(addr))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3082 | switch (gregOfRM(modrm)) { |
| 3083 | case 0: /* INC */ |
| 3084 | t2 = newTemp(ty); |
| 3085 | assign(t2, binop(mkSizedOp(ty,Iop_Add8), |
| 3086 | mkexpr(t1), mkU(ty,1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3087 | if (locked) { |
| 3088 | casLE( mkexpr(addr), |
| 3089 | mkexpr(t1), mkexpr(t2), guest_EIP_curr_instr ); |
| 3090 | } else { |
| 3091 | storeLE(mkexpr(addr),mkexpr(t2)); |
| 3092 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3093 | setFlags_INC_DEC( True, t2, ty ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3094 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3095 | case 1: /* DEC */ |
| 3096 | t2 = newTemp(ty); |
| 3097 | assign(t2, binop(mkSizedOp(ty,Iop_Sub8), |
| 3098 | mkexpr(t1), mkU(ty,1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3099 | if (locked) { |
| 3100 | casLE( mkexpr(addr), |
| 3101 | mkexpr(t1), mkexpr(t2), guest_EIP_curr_instr ); |
| 3102 | } else { |
| 3103 | storeLE(mkexpr(addr),mkexpr(t2)); |
| 3104 | } |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3105 | setFlags_INC_DEC( False, t2, ty ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3106 | break; |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 3107 | case 2: /* call Ev */ |
| 3108 | vassert(sz == 4); |
| 3109 | t2 = newTemp(Ity_I32); |
| 3110 | assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 3111 | putIReg(4, R_ESP, mkexpr(t2)); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3112 | storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta+len)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 3113 | jmp_treg(Ijk_Call,t1); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3114 | dres->whatNext = Dis_StopHere; |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 3115 | break; |
| 3116 | case 4: /* JMP Ev */ |
| 3117 | vassert(sz == 4); |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 3118 | jmp_treg(Ijk_Boring,t1); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3119 | dres->whatNext = Dis_StopHere; |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 3120 | break; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 3121 | case 6: /* PUSH Ev */ |
| 3122 | vassert(sz == 4 || sz == 2); |
| 3123 | t2 = newTemp(Ity_I32); |
| 3124 | assign( t2, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 3125 | putIReg(4, R_ESP, mkexpr(t2) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 3126 | storeLE( mkexpr(t2), mkexpr(t1) ); |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 3127 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3128 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3129 | *decode_OK = False; |
| 3130 | return delta; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3131 | } |
| 3132 | delta += len; |
| 3133 | DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)), |
| 3134 | nameISize(sz), dis_buf); |
| 3135 | } |
| 3136 | return delta; |
| 3137 | } |
| 3138 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 3139 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3140 | /*------------------------------------------------------------*/ |
| 3141 | /*--- Disassembling string ops (including REP prefixes) ---*/ |
| 3142 | /*------------------------------------------------------------*/ |
| 3143 | |
| 3144 | /* Code shared by all the string ops */ |
| 3145 | static |
| 3146 | void dis_string_op_increment(Int sz, Int t_inc) |
| 3147 | { |
| 3148 | if (sz == 4 || sz == 2) { |
| 3149 | assign( t_inc, |
| 3150 | binop(Iop_Shl32, IRExpr_Get( OFFB_DFLAG, Ity_I32 ), |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3151 | mkU8(sz/2) ) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3152 | } else { |
| 3153 | assign( t_inc, |
| 3154 | IRExpr_Get( OFFB_DFLAG, Ity_I32 ) ); |
| 3155 | } |
| 3156 | } |
| 3157 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3158 | static |
| 3159 | void dis_string_op( void (*dis_OP)( Int, IRTemp ), |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3160 | Int sz, HChar* name, UChar sorb ) |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3161 | { |
| 3162 | IRTemp t_inc = newTemp(Ity_I32); |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 3163 | vassert(sorb == 0); /* hmm. so what was the point of passing it in? */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3164 | dis_string_op_increment(sz, t_inc); |
| 3165 | dis_OP( sz, t_inc ); |
| 3166 | DIP("%s%c\n", name, nameISize(sz)); |
| 3167 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3168 | |
| 3169 | static |
| 3170 | void dis_MOVS ( Int sz, IRTemp t_inc ) |
| 3171 | { |
| 3172 | IRType ty = szToITy(sz); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3173 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3174 | IRTemp ts = newTemp(Ity_I32); /* ESI */ |
| 3175 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3176 | assign( td, getIReg(4, R_EDI) ); |
| 3177 | assign( ts, getIReg(4, R_ESI) ); |
| 3178 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3179 | storeLE( mkexpr(td), loadLE(ty,mkexpr(ts)) ); |
| 3180 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3181 | putIReg( 4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
| 3182 | putIReg( 4, R_ESI, binop(Iop_Add32, mkexpr(ts), mkexpr(t_inc)) ); |
| 3183 | } |
| 3184 | |
sewardj | 10ca4eb | 2005-05-30 11:19:54 +0000 | [diff] [blame] | 3185 | static |
| 3186 | void dis_LODS ( Int sz, IRTemp t_inc ) |
| 3187 | { |
| 3188 | IRType ty = szToITy(sz); |
| 3189 | IRTemp ts = newTemp(Ity_I32); /* ESI */ |
| 3190 | |
| 3191 | assign( ts, getIReg(4, R_ESI) ); |
| 3192 | |
| 3193 | putIReg( sz, R_EAX, loadLE(ty, mkexpr(ts)) ); |
| 3194 | |
| 3195 | putIReg( 4, R_ESI, binop(Iop_Add32, mkexpr(ts), mkexpr(t_inc)) ); |
| 3196 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3197 | |
| 3198 | static |
| 3199 | void dis_STOS ( Int sz, IRTemp t_inc ) |
| 3200 | { |
| 3201 | IRType ty = szToITy(sz); |
| 3202 | IRTemp ta = newTemp(ty); /* EAX */ |
| 3203 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3204 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3205 | assign( ta, getIReg(sz, R_EAX) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3206 | assign( td, getIReg(4, R_EDI) ); |
| 3207 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3208 | storeLE( mkexpr(td), mkexpr(ta) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3209 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3210 | putIReg( 4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
| 3211 | } |
| 3212 | |
| 3213 | static |
| 3214 | void dis_CMPS ( Int sz, IRTemp t_inc ) |
| 3215 | { |
| 3216 | IRType ty = szToITy(sz); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3217 | IRTemp tdv = newTemp(ty); /* (EDI) */ |
| 3218 | IRTemp tsv = newTemp(ty); /* (ESI) */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3219 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3220 | IRTemp ts = newTemp(Ity_I32); /* ESI */ |
| 3221 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3222 | assign( td, getIReg(4, R_EDI) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3223 | assign( ts, getIReg(4, R_ESI) ); |
| 3224 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3225 | assign( tdv, loadLE(ty,mkexpr(td)) ); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 3226 | assign( tsv, loadLE(ty,mkexpr(ts)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3227 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3228 | setFlags_DEP1_DEP2 ( Iop_Sub8, tsv, tdv, ty ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3229 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3230 | putIReg(4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3231 | putIReg(4, R_ESI, binop(Iop_Add32, mkexpr(ts), mkexpr(t_inc)) ); |
| 3232 | } |
| 3233 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3234 | static |
| 3235 | void dis_SCAS ( Int sz, IRTemp t_inc ) |
| 3236 | { |
| 3237 | IRType ty = szToITy(sz); |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 3238 | IRTemp ta = newTemp(ty); /* EAX */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3239 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3240 | IRTemp tdv = newTemp(ty); /* (EDI) */ |
| 3241 | |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 3242 | assign( ta, getIReg(sz, R_EAX) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3243 | assign( td, getIReg(4, R_EDI) ); |
| 3244 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3245 | assign( tdv, loadLE(ty,mkexpr(td)) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3246 | setFlags_DEP1_DEP2 ( Iop_Sub8, ta, tdv, ty ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3247 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3248 | putIReg(4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
| 3249 | } |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 3250 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3251 | |
| 3252 | /* Wrap the appropriate string op inside a REP/REPE/REPNE. |
| 3253 | We assume the insn is the last one in the basic block, and so emit a jump |
| 3254 | to the next insn, rather than just falling through. */ |
| 3255 | static |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3256 | void dis_REP_op ( X86Condcode cond, |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3257 | void (*dis_OP)(Int, IRTemp), |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3258 | Int sz, Addr32 eip, Addr32 eip_next, HChar* name ) |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3259 | { |
| 3260 | IRTemp t_inc = newTemp(Ity_I32); |
| 3261 | IRTemp tc = newTemp(Ity_I32); /* ECX */ |
| 3262 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3263 | assign( tc, getIReg(4,R_ECX) ); |
| 3264 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3265 | stmt( IRStmt_Exit( binop(Iop_CmpEQ32,mkexpr(tc),mkU32(0)), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3266 | Ijk_Boring, |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3267 | IRConst_U32(eip_next) ) ); |
| 3268 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3269 | putIReg(4, R_ECX, binop(Iop_Sub32, mkexpr(tc), mkU32(1)) ); |
| 3270 | |
| 3271 | dis_string_op_increment(sz, t_inc); |
| 3272 | dis_OP (sz, t_inc); |
| 3273 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3274 | if (cond == X86CondAlways) { |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 3275 | jmp_lit(Ijk_Boring,eip); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3276 | } else { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3277 | stmt( IRStmt_Exit( mk_x86g_calculate_condition(cond), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3278 | Ijk_Boring, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 3279 | IRConst_U32(eip) ) ); |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 3280 | jmp_lit(Ijk_Boring,eip_next); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3281 | } |
| 3282 | DIP("%s%c\n", name, nameISize(sz)); |
| 3283 | } |
| 3284 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 3285 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3286 | /*------------------------------------------------------------*/ |
| 3287 | /*--- Arithmetic, etc. ---*/ |
| 3288 | /*------------------------------------------------------------*/ |
| 3289 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3290 | /* IMUL E, G. Supplied eip points to the modR/M byte. */ |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3291 | static |
| 3292 | UInt dis_mul_E_G ( UChar sorb, |
| 3293 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 3294 | Int delta0 ) |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3295 | { |
sewardj | 71a6536 | 2004-07-28 01:48:34 +0000 | [diff] [blame] | 3296 | Int alen; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3297 | HChar dis_buf[50]; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3298 | UChar rm = getIByte(delta0); |
| 3299 | IRType ty = szToITy(size); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3300 | IRTemp te = newTemp(ty); |
| 3301 | IRTemp tg = newTemp(ty); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3302 | IRTemp resLo = newTemp(ty); |
sewardj | 71a6536 | 2004-07-28 01:48:34 +0000 | [diff] [blame] | 3303 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3304 | assign( tg, getIReg(size, gregOfRM(rm)) ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3305 | if (epartIsReg(rm)) { |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3306 | assign( te, getIReg(size, eregOfRM(rm)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3307 | } else { |
| 3308 | IRTemp addr = disAMode( &alen, sorb, delta0, dis_buf ); |
| 3309 | assign( te, loadLE(ty,mkexpr(addr)) ); |
| 3310 | } |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3311 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3312 | setFlags_MUL ( ty, te, tg, X86G_CC_OP_SMULB ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3313 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3314 | assign( resLo, binop( mkSizedOp(ty, Iop_Mul8), mkexpr(te), mkexpr(tg) ) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3315 | |
| 3316 | putIReg(size, gregOfRM(rm), mkexpr(resLo) ); |
| 3317 | |
| 3318 | if (epartIsReg(rm)) { |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3319 | DIP("imul%c %s, %s\n", nameISize(size), |
| 3320 | nameIReg(size,eregOfRM(rm)), |
| 3321 | nameIReg(size,gregOfRM(rm))); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3322 | return 1+delta0; |
| 3323 | } else { |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3324 | DIP("imul%c %s, %s\n", nameISize(size), |
| 3325 | dis_buf, nameIReg(size,gregOfRM(rm))); |
sewardj | 71a6536 | 2004-07-28 01:48:34 +0000 | [diff] [blame] | 3326 | return alen+delta0; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3327 | } |
| 3328 | } |
| 3329 | |
| 3330 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3331 | /* IMUL I * E -> G. Supplied eip points to the modR/M byte. */ |
| 3332 | static |
| 3333 | UInt dis_imul_I_E_G ( UChar sorb, |
| 3334 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 3335 | Int delta, |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3336 | Int litsize ) |
| 3337 | { |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3338 | Int d32, alen; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3339 | HChar dis_buf[50]; |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 3340 | UChar rm = getIByte(delta); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3341 | IRType ty = szToITy(size); |
| 3342 | IRTemp te = newTemp(ty); |
| 3343 | IRTemp tl = newTemp(ty); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3344 | IRTemp resLo = newTemp(ty); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3345 | |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 3346 | vassert(size == 1 || size == 2 || size == 4); |
| 3347 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3348 | if (epartIsReg(rm)) { |
| 3349 | assign(te, getIReg(size, eregOfRM(rm))); |
| 3350 | delta++; |
| 3351 | } else { |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3352 | IRTemp addr = disAMode( &alen, sorb, delta, dis_buf ); |
| 3353 | assign(te, loadLE(ty, mkexpr(addr))); |
| 3354 | delta += alen; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3355 | } |
| 3356 | d32 = getSDisp(litsize,delta); |
| 3357 | delta += litsize; |
| 3358 | |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 3359 | if (size == 1) d32 &= 0xFF; |
| 3360 | if (size == 2) d32 &= 0xFFFF; |
| 3361 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3362 | assign(tl, mkU(ty,d32)); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3363 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3364 | assign( resLo, binop( mkSizedOp(ty, Iop_Mul8), mkexpr(te), mkexpr(tl) )); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3365 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3366 | setFlags_MUL ( ty, te, tl, X86G_CC_OP_SMULB ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3367 | |
| 3368 | putIReg(size, gregOfRM(rm), mkexpr(resLo)); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3369 | |
| 3370 | DIP("imul %d, %s, %s\n", d32, |
| 3371 | ( epartIsReg(rm) ? nameIReg(size,eregOfRM(rm)) : dis_buf ), |
| 3372 | nameIReg(size,gregOfRM(rm)) ); |
| 3373 | return delta; |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3374 | } |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3375 | |
| 3376 | |
sewardj | 9a660ea | 2010-07-29 11:34:38 +0000 | [diff] [blame] | 3377 | /* Generate an IR sequence to do a count-leading-zeroes operation on |
| 3378 | the supplied IRTemp, and return a new IRTemp holding the result. |
| 3379 | 'ty' may be Ity_I16 or Ity_I32 only. In the case where the |
| 3380 | argument is zero, return the number of bits in the word (the |
| 3381 | natural semantics). */ |
| 3382 | static IRTemp gen_LZCNT ( IRType ty, IRTemp src ) |
| 3383 | { |
| 3384 | vassert(ty == Ity_I32 || ty == Ity_I16); |
| 3385 | |
| 3386 | IRTemp src32 = newTemp(Ity_I32); |
| 3387 | assign(src32, widenUto32( mkexpr(src) )); |
| 3388 | |
| 3389 | IRTemp src32x = newTemp(Ity_I32); |
| 3390 | assign(src32x, |
| 3391 | binop(Iop_Shl32, mkexpr(src32), |
| 3392 | mkU8(32 - 8 * sizeofIRType(ty)))); |
| 3393 | |
| 3394 | // Clz32 has undefined semantics when its input is zero, so |
| 3395 | // special-case around that. |
| 3396 | IRTemp res32 = newTemp(Ity_I32); |
| 3397 | assign(res32, |
| 3398 | IRExpr_Mux0X( |
| 3399 | unop(Iop_1Uto8, |
| 3400 | binop(Iop_CmpEQ32, mkexpr(src32x), mkU32(0))), |
| 3401 | unop(Iop_Clz32, mkexpr(src32x)), |
| 3402 | mkU32(8 * sizeofIRType(ty)) |
| 3403 | )); |
| 3404 | |
| 3405 | IRTemp res = newTemp(ty); |
| 3406 | assign(res, narrowTo(ty, mkexpr(res32))); |
| 3407 | return res; |
| 3408 | } |
| 3409 | |
| 3410 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3411 | /*------------------------------------------------------------*/ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 3412 | /*--- ---*/ |
| 3413 | /*--- x87 FLOATING POINT INSTRUCTIONS ---*/ |
| 3414 | /*--- ---*/ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3415 | /*------------------------------------------------------------*/ |
| 3416 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3417 | /* --- Helper functions for dealing with the register stack. --- */ |
| 3418 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3419 | /* --- Set the emulation-warning pseudo-register. --- */ |
| 3420 | |
| 3421 | static void put_emwarn ( IRExpr* e /* :: Ity_I32 */ ) |
| 3422 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3423 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3424 | stmt( IRStmt_Put( OFFB_EMWARN, e ) ); |
| 3425 | } |
| 3426 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3427 | /* --- Produce an IRExpr* denoting a 64-bit QNaN. --- */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3428 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3429 | static IRExpr* mkQNaN64 ( void ) |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3430 | { |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3431 | /* QNaN is 0 2047 1 0(51times) |
| 3432 | == 0b 11111111111b 1 0(51times) |
| 3433 | == 0x7FF8 0000 0000 0000 |
| 3434 | */ |
| 3435 | return IRExpr_Const(IRConst_F64i(0x7FF8000000000000ULL)); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3436 | } |
| 3437 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3438 | /* --------- Get/put the top-of-stack pointer. --------- */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3439 | |
| 3440 | static IRExpr* get_ftop ( void ) |
| 3441 | { |
| 3442 | return IRExpr_Get( OFFB_FTOP, Ity_I32 ); |
| 3443 | } |
| 3444 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3445 | static void put_ftop ( IRExpr* e ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3446 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3447 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3448 | stmt( IRStmt_Put( OFFB_FTOP, e ) ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3449 | } |
| 3450 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3451 | /* --------- Get/put the C3210 bits. --------- */ |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3452 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3453 | static IRExpr* get_C3210 ( void ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3454 | { |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3455 | return IRExpr_Get( OFFB_FC3210, Ity_I32 ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3456 | } |
| 3457 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3458 | static void put_C3210 ( IRExpr* e ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3459 | { |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3460 | stmt( IRStmt_Put( OFFB_FC3210, e ) ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3461 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3462 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3463 | /* --------- Get/put the FPU rounding mode. --------- */ |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3464 | static IRExpr* /* :: Ity_I32 */ get_fpround ( void ) |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3465 | { |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3466 | return IRExpr_Get( OFFB_FPROUND, Ity_I32 ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3467 | } |
| 3468 | |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3469 | static void put_fpround ( IRExpr* /* :: Ity_I32 */ e ) |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3470 | { |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3471 | stmt( IRStmt_Put( OFFB_FPROUND, e ) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3472 | } |
| 3473 | |
| 3474 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3475 | /* --------- Synthesise a 2-bit FPU rounding mode. --------- */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3476 | /* Produces a value in 0 .. 3, which is encoded as per the type |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3477 | IRRoundingMode. Since the guest_FPROUND value is also encoded as |
| 3478 | per IRRoundingMode, we merely need to get it and mask it for |
| 3479 | safety. |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3480 | */ |
| 3481 | static IRExpr* /* :: Ity_I32 */ get_roundingmode ( void ) |
| 3482 | { |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3483 | return binop( Iop_And32, get_fpround(), mkU32(3) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3484 | } |
| 3485 | |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3486 | static IRExpr* /* :: Ity_I32 */ get_FAKE_roundingmode ( void ) |
| 3487 | { |
| 3488 | return mkU32(Irrm_NEAREST); |
| 3489 | } |
| 3490 | |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3491 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3492 | /* --------- Get/set FP register tag bytes. --------- */ |
| 3493 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3494 | /* Given i, and some expression e, generate 'ST_TAG(i) = e'. */ |
| 3495 | |
| 3496 | static void put_ST_TAG ( Int i, IRExpr* value ) |
| 3497 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3498 | IRRegArray* descr; |
| 3499 | vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_I8); |
| 3500 | descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3501 | stmt( IRStmt_PutI( descr, get_ftop(), i, value ) ); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3502 | } |
| 3503 | |
| 3504 | /* Given i, generate an expression yielding 'ST_TAG(i)'. This will be |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3505 | zero to indicate "Empty" and nonzero to indicate "NonEmpty". */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3506 | |
| 3507 | static IRExpr* get_ST_TAG ( Int i ) |
| 3508 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3509 | IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3510 | return IRExpr_GetI( descr, get_ftop(), i ); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3511 | } |
| 3512 | |
| 3513 | |
| 3514 | /* --------- Get/set FP registers. --------- */ |
| 3515 | |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3516 | /* Given i, and some expression e, emit 'ST(i) = e' and set the |
| 3517 | register's tag to indicate the register is full. The previous |
| 3518 | state of the register is not checked. */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3519 | |
| 3520 | static void put_ST_UNCHECKED ( Int i, IRExpr* value ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3521 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3522 | IRRegArray* descr; |
| 3523 | vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_F64); |
| 3524 | descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3525 | stmt( IRStmt_PutI( descr, get_ftop(), i, value ) ); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3526 | /* Mark the register as in-use. */ |
| 3527 | put_ST_TAG(i, mkU8(1)); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3528 | } |
| 3529 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3530 | /* Given i, and some expression e, emit |
| 3531 | ST(i) = is_full(i) ? NaN : e |
| 3532 | and set the tag accordingly. |
| 3533 | */ |
| 3534 | |
| 3535 | static void put_ST ( Int i, IRExpr* value ) |
| 3536 | { |
| 3537 | put_ST_UNCHECKED( i, |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3538 | IRExpr_Mux0X( get_ST_TAG(i), |
| 3539 | /* 0 means empty */ |
| 3540 | value, |
| 3541 | /* non-0 means full */ |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3542 | mkQNaN64() |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3543 | ) |
| 3544 | ); |
| 3545 | } |
| 3546 | |
| 3547 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3548 | /* Given i, generate an expression yielding 'ST(i)'. */ |
| 3549 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3550 | static IRExpr* get_ST_UNCHECKED ( Int i ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3551 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3552 | IRRegArray* descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3553 | return IRExpr_GetI( descr, get_ftop(), i ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3554 | } |
| 3555 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3556 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3557 | /* Given i, generate an expression yielding |
| 3558 | is_full(i) ? ST(i) : NaN |
| 3559 | */ |
| 3560 | |
| 3561 | static IRExpr* get_ST ( Int i ) |
| 3562 | { |
| 3563 | return |
| 3564 | IRExpr_Mux0X( get_ST_TAG(i), |
| 3565 | /* 0 means empty */ |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3566 | mkQNaN64(), |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3567 | /* non-0 means full */ |
| 3568 | get_ST_UNCHECKED(i)); |
| 3569 | } |
| 3570 | |
| 3571 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3572 | /* Adjust FTOP downwards by one register. */ |
| 3573 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3574 | static void fp_push ( void ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3575 | { |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3576 | put_ftop( binop(Iop_Sub32, get_ftop(), mkU32(1)) ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3577 | } |
| 3578 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3579 | /* Adjust FTOP upwards by one register, and mark the vacated register |
| 3580 | as empty. */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3581 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3582 | static void fp_pop ( void ) |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3583 | { |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3584 | put_ST_TAG(0, mkU8(0)); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3585 | put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) ); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3586 | } |
| 3587 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 3588 | /* Clear the C2 bit of the FPU status register, for |
| 3589 | sin/cos/tan/sincos. */ |
| 3590 | |
| 3591 | static void clear_C2 ( void ) |
| 3592 | { |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 3593 | put_C3210( binop(Iop_And32, get_C3210(), mkU32(~X86G_FC_MASK_C2)) ); |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 3594 | } |
| 3595 | |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 3596 | /* Invent a plausible-looking FPU status word value: |
| 3597 | ((ftop & 7) << 11) | (c3210 & 0x4700) |
| 3598 | */ |
| 3599 | static IRExpr* get_FPU_sw ( void ) |
| 3600 | { |
| 3601 | return |
| 3602 | unop(Iop_32to16, |
| 3603 | binop(Iop_Or32, |
| 3604 | binop(Iop_Shl32, |
| 3605 | binop(Iop_And32, get_ftop(), mkU32(7)), |
| 3606 | mkU8(11)), |
| 3607 | binop(Iop_And32, get_C3210(), mkU32(0x4700)) |
| 3608 | )); |
| 3609 | } |
| 3610 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 3611 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3612 | /* ------------------------------------------------------- */ |
| 3613 | /* Given all that stack-mangling junk, we can now go ahead |
| 3614 | and describe FP instructions. |
| 3615 | */ |
| 3616 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3617 | /* ST(0) = ST(0) `op` mem64/32(addr) |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3618 | Need to check ST(0)'s tag on read, but not on write. |
| 3619 | */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3620 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3621 | void fp_do_op_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf, |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3622 | IROp op, Bool dbl ) |
| 3623 | { |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3624 | DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3625 | if (dbl) { |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3626 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3627 | triop( op, |
| 3628 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3629 | get_ST(0), |
| 3630 | loadLE(Ity_F64,mkexpr(addr)) |
| 3631 | )); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3632 | } else { |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3633 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3634 | triop( op, |
| 3635 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3636 | get_ST(0), |
| 3637 | unop(Iop_F32toF64, loadLE(Ity_F32,mkexpr(addr))) |
| 3638 | )); |
| 3639 | } |
| 3640 | } |
| 3641 | |
| 3642 | |
| 3643 | /* ST(0) = mem64/32(addr) `op` ST(0) |
| 3644 | Need to check ST(0)'s tag on read, but not on write. |
| 3645 | */ |
| 3646 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3647 | void fp_do_oprev_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf, |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3648 | IROp op, Bool dbl ) |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3649 | { |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3650 | DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf); |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3651 | if (dbl) { |
| 3652 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3653 | triop( op, |
| 3654 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3655 | loadLE(Ity_F64,mkexpr(addr)), |
| 3656 | get_ST(0) |
| 3657 | )); |
| 3658 | } else { |
| 3659 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3660 | triop( op, |
| 3661 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3662 | unop(Iop_F32toF64, loadLE(Ity_F32,mkexpr(addr))), |
| 3663 | get_ST(0) |
| 3664 | )); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3665 | } |
| 3666 | } |
| 3667 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3668 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3669 | /* ST(dst) = ST(dst) `op` ST(src). |
| 3670 | Check dst and src tags when reading but not on write. |
| 3671 | */ |
| 3672 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3673 | void fp_do_op_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst, |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3674 | Bool pop_after ) |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3675 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3676 | DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"", |
| 3677 | (Int)st_src, (Int)st_dst ); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3678 | put_ST_UNCHECKED( |
| 3679 | st_dst, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3680 | triop( op, |
| 3681 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 3682 | get_ST(st_dst), |
| 3683 | get_ST(st_src) ) |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3684 | ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3685 | if (pop_after) |
| 3686 | fp_pop(); |
| 3687 | } |
| 3688 | |
| 3689 | /* ST(dst) = ST(src) `op` ST(dst). |
| 3690 | Check dst and src tags when reading but not on write. |
| 3691 | */ |
| 3692 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3693 | void fp_do_oprev_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst, |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3694 | Bool pop_after ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3695 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3696 | DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"", |
| 3697 | (Int)st_src, (Int)st_dst ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3698 | put_ST_UNCHECKED( |
| 3699 | st_dst, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3700 | triop( op, |
| 3701 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 3702 | get_ST(st_src), |
| 3703 | get_ST(st_dst) ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3704 | ); |
| 3705 | if (pop_after) |
| 3706 | fp_pop(); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3707 | } |
| 3708 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3709 | /* %eflags(Z,P,C) = UCOMI( st(0), st(i) ) */ |
| 3710 | static void fp_do_ucomi_ST0_STi ( UInt i, Bool pop_after ) |
| 3711 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3712 | DIP("fucomi%s %%st(0),%%st(%d)\n", pop_after ? "p" : "", (Int)i ); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3713 | /* This is a bit of a hack (and isn't really right). It sets |
| 3714 | Z,P,C,O correctly, but forces A and S to zero, whereas the Intel |
| 3715 | documentation implies A and S are unchanged. |
| 3716 | */ |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 3717 | /* It's also fishy in that it is used both for COMIP and |
| 3718 | UCOMIP, and they aren't the same (although similar). */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3719 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3720 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 3721 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3722 | binop( Iop_And32, |
| 3723 | binop(Iop_CmpF64, get_ST(0), get_ST(i)), |
| 3724 | mkU32(0x45) |
| 3725 | ))); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 3726 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 3727 | elimination of previous stores to this field work better. */ |
| 3728 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3729 | if (pop_after) |
| 3730 | fp_pop(); |
| 3731 | } |
| 3732 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3733 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3734 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 3735 | UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3736 | { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3737 | Int len; |
| 3738 | UInt r_src, r_dst; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3739 | HChar dis_buf[50]; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3740 | IRTemp t1, t2; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3741 | |
| 3742 | /* On entry, delta points at the second byte of the insn (the modrm |
| 3743 | byte).*/ |
| 3744 | UChar first_opcode = getIByte(delta-1); |
| 3745 | UChar modrm = getIByte(delta+0); |
| 3746 | |
| 3747 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xD8 opcodes +-+-+-+-+-+-+-+ */ |
| 3748 | |
| 3749 | if (first_opcode == 0xD8) { |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3750 | if (modrm < 0xC0) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3751 | |
| 3752 | /* bits 5,4,3 are an opcode extension, and the modRM also |
| 3753 | specifies an address. */ |
| 3754 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 3755 | delta += len; |
| 3756 | |
| 3757 | switch (gregOfRM(modrm)) { |
| 3758 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3759 | case 0: /* FADD single-real */ |
| 3760 | fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64, False ); |
| 3761 | break; |
| 3762 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3763 | case 1: /* FMUL single-real */ |
| 3764 | fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, False ); |
| 3765 | break; |
| 3766 | |
sewardj | 7ca37d9 | 2004-10-25 02:58:30 +0000 | [diff] [blame] | 3767 | case 2: /* FCOM single-real */ |
| 3768 | DIP("fcoms %s\n", dis_buf); |
| 3769 | /* This forces C1 to zero, which isn't right. */ |
| 3770 | put_C3210( |
| 3771 | binop( Iop_And32, |
| 3772 | binop(Iop_Shl32, |
| 3773 | binop(Iop_CmpF64, |
| 3774 | get_ST(0), |
| 3775 | unop(Iop_F32toF64, |
| 3776 | loadLE(Ity_F32,mkexpr(addr)))), |
| 3777 | mkU8(8)), |
| 3778 | mkU32(0x4500) |
| 3779 | )); |
| 3780 | break; |
| 3781 | |
| 3782 | case 3: /* FCOMP single-real */ |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 3783 | DIP("fcomps %s\n", dis_buf); |
| 3784 | /* This forces C1 to zero, which isn't right. */ |
| 3785 | put_C3210( |
| 3786 | binop( Iop_And32, |
| 3787 | binop(Iop_Shl32, |
| 3788 | binop(Iop_CmpF64, |
| 3789 | get_ST(0), |
| 3790 | unop(Iop_F32toF64, |
| 3791 | loadLE(Ity_F32,mkexpr(addr)))), |
| 3792 | mkU8(8)), |
| 3793 | mkU32(0x4500) |
| 3794 | )); |
| 3795 | fp_pop(); |
| 3796 | break; |
| 3797 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 3798 | case 4: /* FSUB single-real */ |
| 3799 | fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, False ); |
| 3800 | break; |
| 3801 | |
| 3802 | case 5: /* FSUBR single-real */ |
| 3803 | fp_do_oprev_mem_ST_0 ( addr, "subr", dis_buf, Iop_SubF64, False ); |
| 3804 | break; |
| 3805 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3806 | case 6: /* FDIV single-real */ |
| 3807 | fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64, False ); |
| 3808 | break; |
| 3809 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3810 | case 7: /* FDIVR single-real */ |
| 3811 | fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_DivF64, False ); |
| 3812 | break; |
| 3813 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3814 | default: |
| 3815 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 3816 | vex_printf("first_opcode == 0xD8\n"); |
| 3817 | goto decode_fail; |
| 3818 | } |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3819 | } else { |
| 3820 | delta++; |
| 3821 | switch (modrm) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3822 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3823 | case 0xC0 ... 0xC7: /* FADD %st(?),%st(0) */ |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3824 | fp_do_op_ST_ST ( "add", Iop_AddF64, modrm - 0xC0, 0, False ); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3825 | break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3826 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3827 | case 0xC8 ... 0xCF: /* FMUL %st(?),%st(0) */ |
| 3828 | fp_do_op_ST_ST ( "mul", Iop_MulF64, modrm - 0xC8, 0, False ); |
| 3829 | break; |
| 3830 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 3831 | /* Dunno if this is right */ |
| 3832 | case 0xD0 ... 0xD7: /* FCOM %st(?),%st(0) */ |
| 3833 | r_dst = (UInt)modrm - 0xD0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3834 | DIP("fcom %%st(0),%%st(%d)\n", (Int)r_dst); |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 3835 | /* This forces C1 to zero, which isn't right. */ |
| 3836 | put_C3210( |
| 3837 | binop( Iop_And32, |
| 3838 | binop(Iop_Shl32, |
| 3839 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 3840 | mkU8(8)), |
| 3841 | mkU32(0x4500) |
| 3842 | )); |
| 3843 | break; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3844 | |
sewardj | 98169c5 | 2004-10-24 13:11:39 +0000 | [diff] [blame] | 3845 | /* Dunno if this is right */ |
| 3846 | case 0xD8 ... 0xDF: /* FCOMP %st(?),%st(0) */ |
| 3847 | r_dst = (UInt)modrm - 0xD8; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3848 | DIP("fcomp %%st(0),%%st(%d)\n", (Int)r_dst); |
sewardj | 98169c5 | 2004-10-24 13:11:39 +0000 | [diff] [blame] | 3849 | /* This forces C1 to zero, which isn't right. */ |
| 3850 | put_C3210( |
| 3851 | binop( Iop_And32, |
| 3852 | binop(Iop_Shl32, |
| 3853 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 3854 | mkU8(8)), |
| 3855 | mkU32(0x4500) |
| 3856 | )); |
| 3857 | fp_pop(); |
| 3858 | break; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3859 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3860 | case 0xE0 ... 0xE7: /* FSUB %st(?),%st(0) */ |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3861 | fp_do_op_ST_ST ( "sub", Iop_SubF64, modrm - 0xE0, 0, False ); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3862 | break; |
| 3863 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3864 | case 0xE8 ... 0xEF: /* FSUBR %st(?),%st(0) */ |
| 3865 | fp_do_oprev_ST_ST ( "subr", Iop_SubF64, modrm - 0xE8, 0, False ); |
| 3866 | break; |
| 3867 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3868 | case 0xF0 ... 0xF7: /* FDIV %st(?),%st(0) */ |
| 3869 | fp_do_op_ST_ST ( "div", Iop_DivF64, modrm - 0xF0, 0, False ); |
| 3870 | break; |
| 3871 | |
| 3872 | case 0xF8 ... 0xFF: /* FDIVR %st(?),%st(0) */ |
| 3873 | fp_do_oprev_ST_ST ( "divr", Iop_DivF64, modrm - 0xF8, 0, False ); |
| 3874 | break; |
| 3875 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3876 | default: |
| 3877 | goto decode_fail; |
| 3878 | } |
| 3879 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3880 | } |
| 3881 | |
| 3882 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xD9 opcodes +-+-+-+-+-+-+-+ */ |
| 3883 | else |
| 3884 | if (first_opcode == 0xD9) { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 3885 | if (modrm < 0xC0) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3886 | |
| 3887 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 3888 | specifies an address. */ |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3889 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 3890 | delta += len; |
| 3891 | |
| 3892 | switch (gregOfRM(modrm)) { |
| 3893 | |
| 3894 | case 0: /* FLD single-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3895 | DIP("flds %s\n", dis_buf); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3896 | fp_push(); |
| 3897 | put_ST(0, unop(Iop_F32toF64, |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3898 | loadLE(Ity_F32, mkexpr(addr)))); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3899 | break; |
| 3900 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 3901 | case 2: /* FST single-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3902 | DIP("fsts %s\n", dis_buf); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 3903 | storeLE(mkexpr(addr), |
| 3904 | binop(Iop_F64toF32, get_roundingmode(), get_ST(0))); |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 3905 | break; |
| 3906 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3907 | case 3: /* FSTP single-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3908 | DIP("fstps %s\n", dis_buf); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 3909 | storeLE(mkexpr(addr), |
| 3910 | binop(Iop_F64toF32, get_roundingmode(), get_ST(0))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 3911 | fp_pop(); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3912 | break; |
| 3913 | |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 3914 | case 4: { /* FLDENV m28 */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3915 | /* Uses dirty helper: |
sewardj | 4017a3b | 2005-06-13 12:17:27 +0000 | [diff] [blame] | 3916 | VexEmWarn x86g_do_FLDENV ( VexGuestX86State*, HWord ) */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3917 | IRTemp ew = newTemp(Ity_I32); |
| 3918 | IRDirty* d = unsafeIRDirty_0_N ( |
| 3919 | 0/*regparms*/, |
| 3920 | "x86g_dirtyhelper_FLDENV", |
| 3921 | &x86g_dirtyhelper_FLDENV, |
| 3922 | mkIRExprVec_1( mkexpr(addr) ) |
| 3923 | ); |
| 3924 | d->needsBBP = True; |
| 3925 | d->tmp = ew; |
| 3926 | /* declare we're reading memory */ |
| 3927 | d->mFx = Ifx_Read; |
| 3928 | d->mAddr = mkexpr(addr); |
| 3929 | d->mSize = 28; |
| 3930 | |
| 3931 | /* declare we're writing guest state */ |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 3932 | d->nFxState = 4; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3933 | |
| 3934 | d->fxState[0].fx = Ifx_Write; |
| 3935 | d->fxState[0].offset = OFFB_FTOP; |
| 3936 | d->fxState[0].size = sizeof(UInt); |
| 3937 | |
| 3938 | d->fxState[1].fx = Ifx_Write; |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 3939 | d->fxState[1].offset = OFFB_FPTAGS; |
| 3940 | d->fxState[1].size = 8 * sizeof(UChar); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3941 | |
| 3942 | d->fxState[2].fx = Ifx_Write; |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 3943 | d->fxState[2].offset = OFFB_FPROUND; |
| 3944 | d->fxState[2].size = sizeof(UInt); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3945 | |
| 3946 | d->fxState[3].fx = Ifx_Write; |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 3947 | d->fxState[3].offset = OFFB_FC3210; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3948 | d->fxState[3].size = sizeof(UInt); |
| 3949 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3950 | stmt( IRStmt_Dirty(d) ); |
| 3951 | |
| 3952 | /* ew contains any emulation warning we may need to |
| 3953 | issue. If needed, side-exit to the next insn, |
| 3954 | reporting the warning, so that Valgrind's dispatcher |
| 3955 | sees the warning. */ |
| 3956 | put_emwarn( mkexpr(ew) ); |
| 3957 | stmt( |
| 3958 | IRStmt_Exit( |
| 3959 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 3960 | Ijk_EmWarn, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3961 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3962 | ) |
| 3963 | ); |
| 3964 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3965 | DIP("fldenv %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 3966 | break; |
| 3967 | } |
| 3968 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3969 | case 5: {/* FLDCW */ |
| 3970 | /* The only thing we observe in the control word is the |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3971 | rounding mode. Therefore, pass the 16-bit value |
| 3972 | (x87 native-format control word) to a clean helper, |
| 3973 | getting back a 64-bit value, the lower half of which |
| 3974 | is the FPROUND value to store, and the upper half of |
| 3975 | which is the emulation-warning token which may be |
| 3976 | generated. |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3977 | */ |
| 3978 | /* ULong x86h_check_fldcw ( UInt ); */ |
| 3979 | IRTemp t64 = newTemp(Ity_I64); |
| 3980 | IRTemp ew = newTemp(Ity_I32); |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3981 | DIP("fldcw %s\n", dis_buf); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3982 | assign( t64, mkIRExprCCall( |
| 3983 | Ity_I64, 0/*regparms*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 3984 | "x86g_check_fldcw", |
| 3985 | &x86g_check_fldcw, |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3986 | mkIRExprVec_1( |
| 3987 | unop( Iop_16Uto32, |
| 3988 | loadLE(Ity_I16, mkexpr(addr))) |
| 3989 | ) |
| 3990 | ) |
| 3991 | ); |
| 3992 | |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3993 | put_fpround( unop(Iop_64to32, mkexpr(t64)) ); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3994 | assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) ); |
| 3995 | put_emwarn( mkexpr(ew) ); |
| 3996 | /* Finally, if an emulation warning was reported, |
| 3997 | side-exit to the next insn, reporting the warning, |
| 3998 | so that Valgrind's dispatcher sees the warning. */ |
| 3999 | stmt( |
| 4000 | IRStmt_Exit( |
| 4001 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 4002 | Ijk_EmWarn, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 4003 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4004 | ) |
| 4005 | ); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4006 | break; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4007 | } |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4008 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4009 | case 6: { /* FNSTENV m28 */ |
| 4010 | /* Uses dirty helper: |
sewardj | 4017a3b | 2005-06-13 12:17:27 +0000 | [diff] [blame] | 4011 | void x86g_do_FSTENV ( VexGuestX86State*, HWord ) */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4012 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4013 | 0/*regparms*/, |
| 4014 | "x86g_dirtyhelper_FSTENV", |
| 4015 | &x86g_dirtyhelper_FSTENV, |
| 4016 | mkIRExprVec_1( mkexpr(addr) ) |
| 4017 | ); |
| 4018 | d->needsBBP = True; |
| 4019 | /* declare we're writing memory */ |
| 4020 | d->mFx = Ifx_Write; |
| 4021 | d->mAddr = mkexpr(addr); |
| 4022 | d->mSize = 28; |
| 4023 | |
| 4024 | /* declare we're reading guest state */ |
| 4025 | d->nFxState = 4; |
| 4026 | |
| 4027 | d->fxState[0].fx = Ifx_Read; |
| 4028 | d->fxState[0].offset = OFFB_FTOP; |
| 4029 | d->fxState[0].size = sizeof(UInt); |
| 4030 | |
| 4031 | d->fxState[1].fx = Ifx_Read; |
| 4032 | d->fxState[1].offset = OFFB_FPTAGS; |
| 4033 | d->fxState[1].size = 8 * sizeof(UChar); |
| 4034 | |
| 4035 | d->fxState[2].fx = Ifx_Read; |
| 4036 | d->fxState[2].offset = OFFB_FPROUND; |
| 4037 | d->fxState[2].size = sizeof(UInt); |
| 4038 | |
| 4039 | d->fxState[3].fx = Ifx_Read; |
| 4040 | d->fxState[3].offset = OFFB_FC3210; |
| 4041 | d->fxState[3].size = sizeof(UInt); |
| 4042 | |
| 4043 | stmt( IRStmt_Dirty(d) ); |
| 4044 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4045 | DIP("fnstenv %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4046 | break; |
| 4047 | } |
| 4048 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 4049 | case 7: /* FNSTCW */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4050 | /* Fake up a native x87 FPU control word. The only |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4051 | thing it depends on is FPROUND[1:0], so call a clean |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4052 | helper to cook it up. */ |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4053 | /* UInt x86h_create_fpucw ( UInt fpround ) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4054 | DIP("fnstcw %s\n", dis_buf); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4055 | storeLE( |
| 4056 | mkexpr(addr), |
| 4057 | unop( Iop_32to16, |
| 4058 | mkIRExprCCall( |
| 4059 | Ity_I32, 0/*regp*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 4060 | "x86g_create_fpucw", &x86g_create_fpucw, |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4061 | mkIRExprVec_1( get_fpround() ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4062 | ) |
| 4063 | ) |
| 4064 | ); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4065 | break; |
| 4066 | |
| 4067 | default: |
| 4068 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 4069 | vex_printf("first_opcode == 0xD9\n"); |
| 4070 | goto decode_fail; |
| 4071 | } |
| 4072 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4073 | } else { |
| 4074 | delta++; |
| 4075 | switch (modrm) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4076 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4077 | case 0xC0 ... 0xC7: /* FLD %st(?) */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4078 | r_src = (UInt)modrm - 0xC0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4079 | DIP("fld %%st(%d)\n", (Int)r_src); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4080 | t1 = newTemp(Ity_F64); |
| 4081 | assign(t1, get_ST(r_src)); |
| 4082 | fp_push(); |
| 4083 | put_ST(0, mkexpr(t1)); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4084 | break; |
| 4085 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4086 | case 0xC8 ... 0xCF: /* FXCH %st(?) */ |
| 4087 | r_src = (UInt)modrm - 0xC8; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4088 | DIP("fxch %%st(%d)\n", (Int)r_src); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4089 | t1 = newTemp(Ity_F64); |
| 4090 | t2 = newTemp(Ity_F64); |
| 4091 | assign(t1, get_ST(0)); |
| 4092 | assign(t2, get_ST(r_src)); |
| 4093 | put_ST_UNCHECKED(0, mkexpr(t2)); |
| 4094 | put_ST_UNCHECKED(r_src, mkexpr(t1)); |
| 4095 | break; |
| 4096 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4097 | case 0xE0: /* FCHS */ |
| 4098 | DIP("fchs\n"); |
| 4099 | put_ST_UNCHECKED(0, unop(Iop_NegF64, get_ST(0))); |
| 4100 | break; |
| 4101 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4102 | case 0xE1: /* FABS */ |
| 4103 | DIP("fabs\n"); |
| 4104 | put_ST_UNCHECKED(0, unop(Iop_AbsF64, get_ST(0))); |
| 4105 | break; |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4106 | |
sewardj | 1c31877 | 2005-03-19 14:27:04 +0000 | [diff] [blame] | 4107 | case 0xE4: /* FTST */ |
| 4108 | DIP("ftst\n"); |
| 4109 | /* This forces C1 to zero, which isn't right. */ |
| 4110 | /* Well, in fact the Intel docs say (bizarrely): "C1 is |
| 4111 | set to 0 if stack underflow occurred; otherwise, set |
| 4112 | to 0" which is pretty nonsensical. I guess it's a |
| 4113 | typo. */ |
| 4114 | put_C3210( |
| 4115 | binop( Iop_And32, |
| 4116 | binop(Iop_Shl32, |
| 4117 | binop(Iop_CmpF64, |
| 4118 | get_ST(0), |
| 4119 | IRExpr_Const(IRConst_F64i(0x0ULL))), |
| 4120 | mkU8(8)), |
| 4121 | mkU32(0x4500) |
| 4122 | )); |
| 4123 | break; |
| 4124 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4125 | case 0xE5: { /* FXAM */ |
| 4126 | /* This is an interesting one. It examines %st(0), |
| 4127 | regardless of whether the tag says it's empty or not. |
| 4128 | Here, just pass both the tag (in our format) and the |
| 4129 | value (as a double, actually a ULong) to a helper |
| 4130 | function. */ |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 4131 | IRExpr** args |
| 4132 | = mkIRExprVec_2( unop(Iop_8Uto32, get_ST_TAG(0)), |
| 4133 | unop(Iop_ReinterpF64asI64, |
| 4134 | get_ST_UNCHECKED(0)) ); |
| 4135 | put_C3210(mkIRExprCCall( |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4136 | Ity_I32, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 4137 | 0/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4138 | "x86g_calculate_FXAM", &x86g_calculate_FXAM, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4139 | args |
| 4140 | )); |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4141 | DIP("fxam\n"); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4142 | break; |
| 4143 | } |
| 4144 | |
| 4145 | case 0xE8: /* FLD1 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4146 | DIP("fld1\n"); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4147 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4148 | /* put_ST(0, IRExpr_Const(IRConst_F64(1.0))); */ |
| 4149 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL))); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4150 | break; |
| 4151 | |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4152 | case 0xE9: /* FLDL2T */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4153 | DIP("fldl2t\n"); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4154 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4155 | /* put_ST(0, IRExpr_Const(IRConst_F64(3.32192809488736234781))); */ |
| 4156 | put_ST(0, IRExpr_Const(IRConst_F64i(0x400a934f0979a371ULL))); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4157 | break; |
| 4158 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4159 | case 0xEA: /* FLDL2E */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4160 | DIP("fldl2e\n"); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4161 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4162 | /* put_ST(0, IRExpr_Const(IRConst_F64(1.44269504088896340739))); */ |
| 4163 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff71547652b82feULL))); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4164 | break; |
| 4165 | |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4166 | case 0xEB: /* FLDPI */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4167 | DIP("fldpi\n"); |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4168 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4169 | /* put_ST(0, IRExpr_Const(IRConst_F64(3.14159265358979323851))); */ |
| 4170 | put_ST(0, IRExpr_Const(IRConst_F64i(0x400921fb54442d18ULL))); |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4171 | break; |
| 4172 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4173 | case 0xEC: /* FLDLG2 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4174 | DIP("fldlg2\n"); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4175 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4176 | /* put_ST(0, IRExpr_Const(IRConst_F64(0.301029995663981143))); */ |
| 4177 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3fd34413509f79ffULL))); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4178 | break; |
| 4179 | |
| 4180 | case 0xED: /* FLDLN2 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4181 | DIP("fldln2\n"); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4182 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4183 | /* put_ST(0, IRExpr_Const(IRConst_F64(0.69314718055994530942))); */ |
| 4184 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3fe62e42fefa39efULL))); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4185 | break; |
| 4186 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4187 | case 0xEE: /* FLDZ */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4188 | DIP("fldz\n"); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4189 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4190 | /* put_ST(0, IRExpr_Const(IRConst_F64(0.0))); */ |
| 4191 | put_ST(0, IRExpr_Const(IRConst_F64i(0x0000000000000000ULL))); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4192 | break; |
| 4193 | |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4194 | case 0xF0: /* F2XM1 */ |
| 4195 | DIP("f2xm1\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4196 | put_ST_UNCHECKED(0, |
| 4197 | binop(Iop_2xm1F64, |
| 4198 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4199 | get_ST(0))); |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4200 | break; |
| 4201 | |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 4202 | case 0xF1: /* FYL2X */ |
| 4203 | DIP("fyl2x\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4204 | put_ST_UNCHECKED(1, |
| 4205 | triop(Iop_Yl2xF64, |
| 4206 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4207 | get_ST(1), |
| 4208 | get_ST(0))); |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 4209 | fp_pop(); |
| 4210 | break; |
| 4211 | |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 4212 | case 0xF2: /* FPTAN */ |
| 4213 | DIP("ftan\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4214 | put_ST_UNCHECKED(0, |
| 4215 | binop(Iop_TanF64, |
| 4216 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4217 | get_ST(0))); |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 4218 | fp_push(); |
| 4219 | put_ST(0, IRExpr_Const(IRConst_F64(1.0))); |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 4220 | clear_C2(); /* HACK */ |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 4221 | break; |
| 4222 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4223 | case 0xF3: /* FPATAN */ |
| 4224 | DIP("fpatan\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4225 | put_ST_UNCHECKED(1, |
| 4226 | triop(Iop_AtanF64, |
| 4227 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4228 | get_ST(1), |
| 4229 | get_ST(0))); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4230 | fp_pop(); |
| 4231 | break; |
| 4232 | |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4233 | case 0xF4: { /* FXTRACT */ |
sewardj | fda10af | 2005-10-03 01:02:40 +0000 | [diff] [blame] | 4234 | IRTemp argF = newTemp(Ity_F64); |
| 4235 | IRTemp sigF = newTemp(Ity_F64); |
| 4236 | IRTemp expF = newTemp(Ity_F64); |
| 4237 | IRTemp argI = newTemp(Ity_I64); |
| 4238 | IRTemp sigI = newTemp(Ity_I64); |
| 4239 | IRTemp expI = newTemp(Ity_I64); |
| 4240 | DIP("fxtract\n"); |
| 4241 | assign( argF, get_ST(0) ); |
| 4242 | assign( argI, unop(Iop_ReinterpF64asI64, mkexpr(argF))); |
| 4243 | assign( sigI, |
sewardj | 879cee0 | 2006-03-07 01:15:50 +0000 | [diff] [blame] | 4244 | mkIRExprCCall( |
| 4245 | Ity_I64, 0/*regparms*/, |
| 4246 | "x86amd64g_calculate_FXTRACT", |
| 4247 | &x86amd64g_calculate_FXTRACT, |
| 4248 | mkIRExprVec_2( mkexpr(argI), |
| 4249 | mkIRExpr_HWord(0)/*sig*/ )) |
| 4250 | ); |
sewardj | fda10af | 2005-10-03 01:02:40 +0000 | [diff] [blame] | 4251 | assign( expI, |
sewardj | 879cee0 | 2006-03-07 01:15:50 +0000 | [diff] [blame] | 4252 | mkIRExprCCall( |
| 4253 | Ity_I64, 0/*regparms*/, |
| 4254 | "x86amd64g_calculate_FXTRACT", |
| 4255 | &x86amd64g_calculate_FXTRACT, |
| 4256 | mkIRExprVec_2( mkexpr(argI), |
| 4257 | mkIRExpr_HWord(1)/*exp*/ )) |
| 4258 | ); |
sewardj | fda10af | 2005-10-03 01:02:40 +0000 | [diff] [blame] | 4259 | assign( sigF, unop(Iop_ReinterpI64asF64, mkexpr(sigI)) ); |
| 4260 | assign( expF, unop(Iop_ReinterpI64asF64, mkexpr(expI)) ); |
| 4261 | /* exponent */ |
| 4262 | put_ST_UNCHECKED(0, mkexpr(expF) ); |
| 4263 | fp_push(); |
| 4264 | /* significand */ |
| 4265 | put_ST(0, mkexpr(sigF) ); |
| 4266 | break; |
| 4267 | } |
| 4268 | |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 4269 | case 0xF5: { /* FPREM1 -- IEEE compliant */ |
| 4270 | IRTemp a1 = newTemp(Ity_F64); |
| 4271 | IRTemp a2 = newTemp(Ity_F64); |
| 4272 | DIP("fprem1\n"); |
| 4273 | /* Do FPREM1 twice, once to get the remainder, and once |
| 4274 | to get the C3210 flag values. */ |
| 4275 | assign( a1, get_ST(0) ); |
| 4276 | assign( a2, get_ST(1) ); |
sewardj | f47286e | 2006-02-04 15:20:13 +0000 | [diff] [blame] | 4277 | put_ST_UNCHECKED(0, |
| 4278 | triop(Iop_PRem1F64, |
| 4279 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4280 | mkexpr(a1), |
| 4281 | mkexpr(a2))); |
| 4282 | put_C3210( |
| 4283 | triop(Iop_PRem1C3210F64, |
| 4284 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4285 | mkexpr(a1), |
| 4286 | mkexpr(a2)) ); |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 4287 | break; |
| 4288 | } |
| 4289 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4290 | case 0xF7: /* FINCSTP */ |
| 4291 | DIP("fprem\n"); |
| 4292 | put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) ); |
| 4293 | break; |
| 4294 | |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 4295 | case 0xF8: { /* FPREM -- not IEEE compliant */ |
| 4296 | IRTemp a1 = newTemp(Ity_F64); |
| 4297 | IRTemp a2 = newTemp(Ity_F64); |
| 4298 | DIP("fprem\n"); |
| 4299 | /* Do FPREM twice, once to get the remainder, and once |
| 4300 | to get the C3210 flag values. */ |
| 4301 | assign( a1, get_ST(0) ); |
| 4302 | assign( a2, get_ST(1) ); |
sewardj | f47286e | 2006-02-04 15:20:13 +0000 | [diff] [blame] | 4303 | put_ST_UNCHECKED(0, |
| 4304 | triop(Iop_PRemF64, |
| 4305 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4306 | mkexpr(a1), |
| 4307 | mkexpr(a2))); |
| 4308 | put_C3210( |
| 4309 | triop(Iop_PRemC3210F64, |
| 4310 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4311 | mkexpr(a1), |
| 4312 | mkexpr(a2)) ); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 4313 | break; |
| 4314 | } |
| 4315 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4316 | case 0xF9: /* FYL2XP1 */ |
| 4317 | DIP("fyl2xp1\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4318 | put_ST_UNCHECKED(1, |
| 4319 | triop(Iop_Yl2xp1F64, |
| 4320 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4321 | get_ST(1), |
| 4322 | get_ST(0))); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4323 | fp_pop(); |
| 4324 | break; |
| 4325 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4326 | case 0xFA: /* FSQRT */ |
| 4327 | DIP("fsqrt\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4328 | put_ST_UNCHECKED(0, |
| 4329 | binop(Iop_SqrtF64, |
| 4330 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4331 | get_ST(0))); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4332 | break; |
| 4333 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4334 | case 0xFB: { /* FSINCOS */ |
| 4335 | IRTemp a1 = newTemp(Ity_F64); |
| 4336 | assign( a1, get_ST(0) ); |
| 4337 | DIP("fsincos\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4338 | put_ST_UNCHECKED(0, |
| 4339 | binop(Iop_SinF64, |
| 4340 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4341 | mkexpr(a1))); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4342 | fp_push(); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4343 | put_ST(0, |
| 4344 | binop(Iop_CosF64, |
| 4345 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4346 | mkexpr(a1))); |
sewardj | 88a6924 | 2005-04-01 20:19:20 +0000 | [diff] [blame] | 4347 | clear_C2(); /* HACK */ |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4348 | break; |
| 4349 | } |
| 4350 | |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 4351 | case 0xFC: /* FRNDINT */ |
| 4352 | DIP("frndint\n"); |
| 4353 | put_ST_UNCHECKED(0, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4354 | binop(Iop_RoundF64toInt, get_roundingmode(), get_ST(0)) ); |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 4355 | break; |
| 4356 | |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4357 | case 0xFD: /* FSCALE */ |
| 4358 | DIP("fscale\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4359 | put_ST_UNCHECKED(0, |
| 4360 | triop(Iop_ScaleF64, |
| 4361 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4362 | get_ST(0), |
| 4363 | get_ST(1))); |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4364 | break; |
| 4365 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4366 | case 0xFE: /* FSIN */ |
| 4367 | DIP("fsin\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4368 | put_ST_UNCHECKED(0, |
| 4369 | binop(Iop_SinF64, |
| 4370 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4371 | get_ST(0))); |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 4372 | clear_C2(); /* HACK */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4373 | break; |
| 4374 | |
| 4375 | case 0xFF: /* FCOS */ |
| 4376 | DIP("fcos\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4377 | put_ST_UNCHECKED(0, |
| 4378 | binop(Iop_CosF64, |
| 4379 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4380 | get_ST(0))); |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 4381 | clear_C2(); /* HACK */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4382 | break; |
| 4383 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4384 | default: |
| 4385 | goto decode_fail; |
| 4386 | } |
| 4387 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4388 | } |
| 4389 | |
| 4390 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDA opcodes +-+-+-+-+-+-+-+ */ |
| 4391 | else |
| 4392 | if (first_opcode == 0xDA) { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4393 | |
| 4394 | if (modrm < 0xC0) { |
| 4395 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4396 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4397 | specifies an address. */ |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4398 | IROp fop; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4399 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4400 | delta += len; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4401 | switch (gregOfRM(modrm)) { |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4402 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4403 | case 0: /* FIADD m32int */ /* ST(0) += m32int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4404 | DIP("fiaddl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4405 | fop = Iop_AddF64; |
| 4406 | goto do_fop_m32; |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4407 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4408 | case 1: /* FIMUL m32int */ /* ST(0) *= m32int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4409 | DIP("fimull %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4410 | fop = Iop_MulF64; |
| 4411 | goto do_fop_m32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4412 | |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 4413 | case 2: /* FICOM m32int */ |
| 4414 | DIP("ficoml %s\n", dis_buf); |
| 4415 | /* This forces C1 to zero, which isn't right. */ |
| 4416 | put_C3210( |
| 4417 | binop( Iop_And32, |
| 4418 | binop(Iop_Shl32, |
| 4419 | binop(Iop_CmpF64, |
| 4420 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4421 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 4422 | loadLE(Ity_I32,mkexpr(addr)))), |
| 4423 | mkU8(8)), |
| 4424 | mkU32(0x4500) |
| 4425 | )); |
| 4426 | break; |
| 4427 | |
| 4428 | case 3: /* FICOMP m32int */ |
| 4429 | DIP("ficompl %s\n", dis_buf); |
| 4430 | /* This forces C1 to zero, which isn't right. */ |
| 4431 | put_C3210( |
| 4432 | binop( Iop_And32, |
| 4433 | binop(Iop_Shl32, |
| 4434 | binop(Iop_CmpF64, |
| 4435 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4436 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 4437 | loadLE(Ity_I32,mkexpr(addr)))), |
| 4438 | mkU8(8)), |
| 4439 | mkU32(0x4500) |
| 4440 | )); |
| 4441 | fp_pop(); |
| 4442 | break; |
| 4443 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4444 | case 4: /* FISUB m32int */ /* ST(0) -= m32int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4445 | DIP("fisubl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4446 | fop = Iop_SubF64; |
| 4447 | goto do_fop_m32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4448 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4449 | case 5: /* FISUBR m32int */ /* ST(0) = m32int - ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4450 | DIP("fisubrl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4451 | fop = Iop_SubF64; |
| 4452 | goto do_foprev_m32; |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4453 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4454 | case 6: /* FIDIV m32int */ /* ST(0) /= m32int */ |
sewardj | 36917e9 | 2005-03-21 00:12:15 +0000 | [diff] [blame] | 4455 | DIP("fidivl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4456 | fop = Iop_DivF64; |
| 4457 | goto do_fop_m32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4458 | |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4459 | case 7: /* FIDIVR m32int */ /* ST(0) = m32int / ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4460 | DIP("fidivrl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4461 | fop = Iop_DivF64; |
| 4462 | goto do_foprev_m32; |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4463 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4464 | do_fop_m32: |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4465 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4466 | triop(fop, |
| 4467 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4468 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4469 | unop(Iop_I32StoF64, |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4470 | loadLE(Ity_I32, mkexpr(addr))))); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4471 | break; |
| 4472 | |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4473 | do_foprev_m32: |
| 4474 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4475 | triop(fop, |
| 4476 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4477 | unop(Iop_I32StoF64, |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4478 | loadLE(Ity_I32, mkexpr(addr))), |
| 4479 | get_ST(0))); |
| 4480 | break; |
| 4481 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4482 | default: |
| 4483 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 4484 | vex_printf("first_opcode == 0xDA\n"); |
| 4485 | goto decode_fail; |
| 4486 | } |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 4487 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4488 | } else { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4489 | |
| 4490 | delta++; |
| 4491 | switch (modrm) { |
| 4492 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4493 | case 0xC0 ... 0xC7: /* FCMOVB ST(i), ST(0) */ |
| 4494 | r_src = (UInt)modrm - 0xC0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4495 | DIP("fcmovb %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4496 | put_ST_UNCHECKED(0, |
| 4497 | IRExpr_Mux0X( |
| 4498 | unop(Iop_1Uto8, |
| 4499 | mk_x86g_calculate_condition(X86CondB)), |
| 4500 | get_ST(0), get_ST(r_src)) ); |
| 4501 | break; |
| 4502 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4503 | case 0xC8 ... 0xCF: /* FCMOVE(Z) ST(i), ST(0) */ |
| 4504 | r_src = (UInt)modrm - 0xC8; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4505 | DIP("fcmovz %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4506 | put_ST_UNCHECKED(0, |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4507 | IRExpr_Mux0X( |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4508 | unop(Iop_1Uto8, |
| 4509 | mk_x86g_calculate_condition(X86CondZ)), |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4510 | get_ST(0), get_ST(r_src)) ); |
| 4511 | break; |
| 4512 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4513 | case 0xD0 ... 0xD7: /* FCMOVBE ST(i), ST(0) */ |
| 4514 | r_src = (UInt)modrm - 0xD0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4515 | DIP("fcmovbe %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4516 | put_ST_UNCHECKED(0, |
| 4517 | IRExpr_Mux0X( |
| 4518 | unop(Iop_1Uto8, |
| 4519 | mk_x86g_calculate_condition(X86CondBE)), |
| 4520 | get_ST(0), get_ST(r_src)) ); |
| 4521 | break; |
| 4522 | |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4523 | case 0xD8 ... 0xDF: /* FCMOVU ST(i), ST(0) */ |
| 4524 | r_src = (UInt)modrm - 0xD8; |
sewardj | d8862cf | 2006-03-06 19:17:17 +0000 | [diff] [blame] | 4525 | DIP("fcmovu %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4526 | put_ST_UNCHECKED(0, |
| 4527 | IRExpr_Mux0X( |
| 4528 | unop(Iop_1Uto8, |
| 4529 | mk_x86g_calculate_condition(X86CondP)), |
| 4530 | get_ST(0), get_ST(r_src)) ); |
| 4531 | break; |
| 4532 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4533 | case 0xE9: /* FUCOMPP %st(0),%st(1) */ |
| 4534 | DIP("fucompp %%st(0),%%st(1)\n"); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4535 | /* This forces C1 to zero, which isn't right. */ |
| 4536 | put_C3210( |
| 4537 | binop( Iop_And32, |
| 4538 | binop(Iop_Shl32, |
| 4539 | binop(Iop_CmpF64, get_ST(0), get_ST(1)), |
| 4540 | mkU8(8)), |
| 4541 | mkU32(0x4500) |
| 4542 | )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4543 | fp_pop(); |
| 4544 | fp_pop(); |
| 4545 | break; |
| 4546 | |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4547 | default: |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4548 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4549 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4550 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4551 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4552 | } |
| 4553 | |
| 4554 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDB opcodes +-+-+-+-+-+-+-+ */ |
| 4555 | else |
| 4556 | if (first_opcode == 0xDB) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4557 | if (modrm < 0xC0) { |
| 4558 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4559 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4560 | specifies an address. */ |
| 4561 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4562 | delta += len; |
| 4563 | |
| 4564 | switch (gregOfRM(modrm)) { |
| 4565 | |
| 4566 | case 0: /* FILD m32int */ |
| 4567 | DIP("fildl %s\n", dis_buf); |
| 4568 | fp_push(); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4569 | put_ST(0, unop(Iop_I32StoF64, |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4570 | loadLE(Ity_I32, mkexpr(addr)))); |
| 4571 | break; |
| 4572 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 4573 | case 1: /* FISTTPL m32 (SSE3) */ |
| 4574 | DIP("fisttpl %s\n", dis_buf); |
| 4575 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4576 | binop(Iop_F64toI32S, mkU32(Irrm_ZERO), get_ST(0)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 4577 | fp_pop(); |
| 4578 | break; |
| 4579 | |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4580 | case 2: /* FIST m32 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4581 | DIP("fistl %s\n", dis_buf); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4582 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4583 | binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4584 | break; |
| 4585 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4586 | case 3: /* FISTP m32 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4587 | DIP("fistpl %s\n", dis_buf); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4588 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4589 | binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4590 | fp_pop(); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4591 | break; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4592 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4593 | case 5: { /* FLD extended-real */ |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 4594 | /* Uses dirty helper: |
sewardj | 5657923 | 2005-03-26 21:49:42 +0000 | [diff] [blame] | 4595 | ULong x86g_loadF80le ( UInt ) |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 4596 | addr holds the address. First, do a dirty call to |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4597 | get hold of the data. */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4598 | IRTemp val = newTemp(Ity_I64); |
| 4599 | IRExpr** args = mkIRExprVec_1 ( mkexpr(addr) ); |
| 4600 | |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4601 | IRDirty* d = unsafeIRDirty_1_N ( |
| 4602 | val, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4603 | 0/*regparms*/, |
sewardj | 8f40b07 | 2005-08-23 19:30:58 +0000 | [diff] [blame] | 4604 | "x86g_dirtyhelper_loadF80le", |
| 4605 | &x86g_dirtyhelper_loadF80le, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4606 | args |
| 4607 | ); |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4608 | /* declare that we're reading memory */ |
| 4609 | d->mFx = Ifx_Read; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4610 | d->mAddr = mkexpr(addr); |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4611 | d->mSize = 10; |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4612 | |
| 4613 | /* execute the dirty call, dumping the result in val. */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4614 | stmt( IRStmt_Dirty(d) ); |
| 4615 | fp_push(); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4616 | put_ST(0, unop(Iop_ReinterpI64asF64, mkexpr(val))); |
| 4617 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4618 | DIP("fldt %s\n", dis_buf); |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4619 | break; |
| 4620 | } |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4621 | |
| 4622 | case 7: { /* FSTP extended-real */ |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4623 | /* Uses dirty helper: void x86g_storeF80le ( UInt, ULong ) */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4624 | IRExpr** args |
| 4625 | = mkIRExprVec_2( mkexpr(addr), |
| 4626 | unop(Iop_ReinterpF64asI64, get_ST(0)) ); |
| 4627 | |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4628 | IRDirty* d = unsafeIRDirty_0_N ( |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 4629 | 0/*regparms*/, |
sewardj | 8f40b07 | 2005-08-23 19:30:58 +0000 | [diff] [blame] | 4630 | "x86g_dirtyhelper_storeF80le", |
| 4631 | &x86g_dirtyhelper_storeF80le, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4632 | args |
| 4633 | ); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4634 | /* declare we're writing memory */ |
| 4635 | d->mFx = Ifx_Write; |
| 4636 | d->mAddr = mkexpr(addr); |
| 4637 | d->mSize = 10; |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4638 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4639 | /* execute the dirty call. */ |
| 4640 | stmt( IRStmt_Dirty(d) ); |
| 4641 | fp_pop(); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4642 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4643 | DIP("fstpt\n %s", dis_buf); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4644 | break; |
| 4645 | } |
| 4646 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4647 | default: |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4648 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 4649 | vex_printf("first_opcode == 0xDB\n"); |
| 4650 | goto decode_fail; |
| 4651 | } |
| 4652 | |
| 4653 | } else { |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4654 | |
| 4655 | delta++; |
| 4656 | switch (modrm) { |
| 4657 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4658 | case 0xC0 ... 0xC7: /* FCMOVNB ST(i), ST(0) */ |
| 4659 | r_src = (UInt)modrm - 0xC0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4660 | DIP("fcmovnb %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4661 | put_ST_UNCHECKED(0, |
| 4662 | IRExpr_Mux0X( |
| 4663 | unop(Iop_1Uto8, |
| 4664 | mk_x86g_calculate_condition(X86CondNB)), |
| 4665 | get_ST(0), get_ST(r_src)) ); |
| 4666 | break; |
| 4667 | |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 4668 | case 0xC8 ... 0xCF: /* FCMOVNE(NZ) ST(i), ST(0) */ |
| 4669 | r_src = (UInt)modrm - 0xC8; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4670 | DIP("fcmovnz %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4671 | put_ST_UNCHECKED(0, |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 4672 | IRExpr_Mux0X( |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4673 | unop(Iop_1Uto8, |
| 4674 | mk_x86g_calculate_condition(X86CondNZ)), |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 4675 | get_ST(0), get_ST(r_src)) ); |
| 4676 | break; |
| 4677 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4678 | case 0xD0 ... 0xD7: /* FCMOVNBE ST(i), ST(0) */ |
| 4679 | r_src = (UInt)modrm - 0xD0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 4680 | DIP("fcmovnbe %%st(%d), %%st(0)\n", (Int)r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4681 | put_ST_UNCHECKED(0, |
| 4682 | IRExpr_Mux0X( |
| 4683 | unop(Iop_1Uto8, |
| 4684 | mk_x86g_calculate_condition(X86CondNBE)), |
| 4685 | get_ST(0), get_ST(r_src)) ); |
| 4686 | break; |
| 4687 | |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4688 | case 0xD8 ... 0xDF: /* FCMOVNU ST(i), ST(0) */ |
| 4689 | r_src = (UInt)modrm - 0xD8; |
| 4690 | DIP("fcmovnu %%st(%d), %%st(0)\n", (Int)r_src); |
| 4691 | put_ST_UNCHECKED(0, |
| 4692 | IRExpr_Mux0X( |
| 4693 | unop(Iop_1Uto8, |
| 4694 | mk_x86g_calculate_condition(X86CondNP)), |
| 4695 | get_ST(0), get_ST(r_src)) ); |
| 4696 | break; |
| 4697 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4698 | case 0xE2: |
| 4699 | DIP("fnclex\n"); |
| 4700 | break; |
| 4701 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4702 | case 0xE3: { |
| 4703 | /* Uses dirty helper: |
| 4704 | void x86g_do_FINIT ( VexGuestX86State* ) */ |
| 4705 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4706 | 0/*regparms*/, |
| 4707 | "x86g_dirtyhelper_FINIT", |
| 4708 | &x86g_dirtyhelper_FINIT, |
| 4709 | mkIRExprVec_0() |
| 4710 | ); |
| 4711 | d->needsBBP = True; |
| 4712 | |
| 4713 | /* declare we're writing guest state */ |
| 4714 | d->nFxState = 5; |
| 4715 | |
| 4716 | d->fxState[0].fx = Ifx_Write; |
| 4717 | d->fxState[0].offset = OFFB_FTOP; |
| 4718 | d->fxState[0].size = sizeof(UInt); |
| 4719 | |
| 4720 | d->fxState[1].fx = Ifx_Write; |
| 4721 | d->fxState[1].offset = OFFB_FPREGS; |
| 4722 | d->fxState[1].size = 8 * sizeof(ULong); |
| 4723 | |
| 4724 | d->fxState[2].fx = Ifx_Write; |
| 4725 | d->fxState[2].offset = OFFB_FPTAGS; |
| 4726 | d->fxState[2].size = 8 * sizeof(UChar); |
| 4727 | |
| 4728 | d->fxState[3].fx = Ifx_Write; |
| 4729 | d->fxState[3].offset = OFFB_FPROUND; |
| 4730 | d->fxState[3].size = sizeof(UInt); |
| 4731 | |
| 4732 | d->fxState[4].fx = Ifx_Write; |
| 4733 | d->fxState[4].offset = OFFB_FC3210; |
| 4734 | d->fxState[4].size = sizeof(UInt); |
| 4735 | |
| 4736 | stmt( IRStmt_Dirty(d) ); |
| 4737 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4738 | DIP("fninit\n"); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4739 | break; |
| 4740 | } |
| 4741 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4742 | case 0xE8 ... 0xEF: /* FUCOMI %st(0),%st(?) */ |
| 4743 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xE8, False ); |
| 4744 | break; |
| 4745 | |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4746 | case 0xF0 ... 0xF7: /* FCOMI %st(0),%st(?) */ |
| 4747 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xF0, False ); |
| 4748 | break; |
| 4749 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4750 | default: |
| 4751 | goto decode_fail; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4752 | } |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4753 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4754 | } |
| 4755 | |
| 4756 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDC opcodes +-+-+-+-+-+-+-+ */ |
| 4757 | else |
| 4758 | if (first_opcode == 0xDC) { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4759 | if (modrm < 0xC0) { |
| 4760 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4761 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4762 | specifies an address. */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4763 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4764 | delta += len; |
| 4765 | |
| 4766 | switch (gregOfRM(modrm)) { |
| 4767 | |
| 4768 | case 0: /* FADD double-real */ |
| 4769 | fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64, True ); |
| 4770 | break; |
| 4771 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4772 | case 1: /* FMUL double-real */ |
| 4773 | fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, True ); |
| 4774 | break; |
| 4775 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 4776 | case 2: /* FCOM double-real */ |
| 4777 | DIP("fcoml %s\n", dis_buf); |
| 4778 | /* This forces C1 to zero, which isn't right. */ |
| 4779 | put_C3210( |
| 4780 | binop( Iop_And32, |
| 4781 | binop(Iop_Shl32, |
| 4782 | binop(Iop_CmpF64, |
| 4783 | get_ST(0), |
| 4784 | loadLE(Ity_F64,mkexpr(addr))), |
| 4785 | mkU8(8)), |
| 4786 | mkU32(0x4500) |
| 4787 | )); |
| 4788 | break; |
| 4789 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4790 | case 3: /* FCOMP double-real */ |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 4791 | DIP("fcompl %s\n", dis_buf); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4792 | /* This forces C1 to zero, which isn't right. */ |
| 4793 | put_C3210( |
| 4794 | binop( Iop_And32, |
| 4795 | binop(Iop_Shl32, |
| 4796 | binop(Iop_CmpF64, |
| 4797 | get_ST(0), |
| 4798 | loadLE(Ity_F64,mkexpr(addr))), |
| 4799 | mkU8(8)), |
| 4800 | mkU32(0x4500) |
| 4801 | )); |
| 4802 | fp_pop(); |
| 4803 | break; |
| 4804 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4805 | case 4: /* FSUB double-real */ |
| 4806 | fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, True ); |
| 4807 | break; |
| 4808 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4809 | case 5: /* FSUBR double-real */ |
| 4810 | fp_do_oprev_mem_ST_0 ( addr, "subr", dis_buf, Iop_SubF64, True ); |
| 4811 | break; |
| 4812 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4813 | case 6: /* FDIV double-real */ |
| 4814 | fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64, True ); |
| 4815 | break; |
| 4816 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4817 | case 7: /* FDIVR double-real */ |
| 4818 | fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_DivF64, True ); |
| 4819 | break; |
| 4820 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4821 | default: |
| 4822 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 4823 | vex_printf("first_opcode == 0xDC\n"); |
| 4824 | goto decode_fail; |
| 4825 | } |
| 4826 | |
| 4827 | } else { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4828 | |
| 4829 | delta++; |
| 4830 | switch (modrm) { |
| 4831 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4832 | case 0xC0 ... 0xC7: /* FADD %st(0),%st(?) */ |
| 4833 | fp_do_op_ST_ST ( "add", Iop_AddF64, 0, modrm - 0xC0, False ); |
| 4834 | break; |
| 4835 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4836 | case 0xC8 ... 0xCF: /* FMUL %st(0),%st(?) */ |
| 4837 | fp_do_op_ST_ST ( "mul", Iop_MulF64, 0, modrm - 0xC8, False ); |
| 4838 | break; |
| 4839 | |
sewardj | 4734104 | 2004-09-19 11:55:46 +0000 | [diff] [blame] | 4840 | case 0xE0 ... 0xE7: /* FSUBR %st(0),%st(?) */ |
| 4841 | fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, False ); |
| 4842 | break; |
| 4843 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4844 | case 0xE8 ... 0xEF: /* FSUB %st(0),%st(?) */ |
| 4845 | fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8, False ); |
| 4846 | break; |
| 4847 | |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4848 | case 0xF0 ... 0xF7: /* FDIVR %st(0),%st(?) */ |
| 4849 | fp_do_oprev_ST_ST ( "divr", Iop_DivF64, 0, modrm - 0xF0, False ); |
| 4850 | break; |
| 4851 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4852 | case 0xF8 ... 0xFF: /* FDIV %st(0),%st(?) */ |
| 4853 | fp_do_op_ST_ST ( "div", Iop_DivF64, 0, modrm - 0xF8, False ); |
| 4854 | break; |
| 4855 | |
| 4856 | default: |
| 4857 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4858 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4859 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4860 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4861 | } |
| 4862 | |
| 4863 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDD opcodes +-+-+-+-+-+-+-+ */ |
| 4864 | else |
| 4865 | if (first_opcode == 0xDD) { |
| 4866 | |
| 4867 | if (modrm < 0xC0) { |
| 4868 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4869 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4870 | specifies an address. */ |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4871 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4872 | delta += len; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4873 | |
| 4874 | switch (gregOfRM(modrm)) { |
| 4875 | |
| 4876 | case 0: /* FLD double-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4877 | DIP("fldl %s\n", dis_buf); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4878 | fp_push(); |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 4879 | put_ST(0, loadLE(Ity_F64, mkexpr(addr))); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4880 | break; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4881 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 4882 | case 1: /* FISTTPQ m64 (SSE3) */ |
| 4883 | DIP("fistppll %s\n", dis_buf); |
| 4884 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4885 | binop(Iop_F64toI64S, mkU32(Irrm_ZERO), get_ST(0)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 4886 | fp_pop(); |
| 4887 | break; |
| 4888 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4889 | case 2: /* FST double-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4890 | DIP("fstl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4891 | storeLE(mkexpr(addr), get_ST(0)); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4892 | break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4893 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4894 | case 3: /* FSTP double-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4895 | DIP("fstpl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4896 | storeLE(mkexpr(addr), get_ST(0)); |
| 4897 | fp_pop(); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4898 | break; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4899 | |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4900 | case 4: { /* FRSTOR m108 */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4901 | /* Uses dirty helper: |
| 4902 | VexEmWarn x86g_do_FRSTOR ( VexGuestX86State*, Addr32 ) */ |
| 4903 | IRTemp ew = newTemp(Ity_I32); |
| 4904 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4905 | 0/*regparms*/, |
| 4906 | "x86g_dirtyhelper_FRSTOR", |
| 4907 | &x86g_dirtyhelper_FRSTOR, |
| 4908 | mkIRExprVec_1( mkexpr(addr) ) |
| 4909 | ); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4910 | d->needsBBP = True; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4911 | d->tmp = ew; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4912 | /* declare we're reading memory */ |
| 4913 | d->mFx = Ifx_Read; |
| 4914 | d->mAddr = mkexpr(addr); |
| 4915 | d->mSize = 108; |
| 4916 | |
| 4917 | /* declare we're writing guest state */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4918 | d->nFxState = 5; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4919 | |
| 4920 | d->fxState[0].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4921 | d->fxState[0].offset = OFFB_FTOP; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4922 | d->fxState[0].size = sizeof(UInt); |
| 4923 | |
| 4924 | d->fxState[1].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4925 | d->fxState[1].offset = OFFB_FPREGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4926 | d->fxState[1].size = 8 * sizeof(ULong); |
| 4927 | |
| 4928 | d->fxState[2].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4929 | d->fxState[2].offset = OFFB_FPTAGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4930 | d->fxState[2].size = 8 * sizeof(UChar); |
| 4931 | |
| 4932 | d->fxState[3].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4933 | d->fxState[3].offset = OFFB_FPROUND; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4934 | d->fxState[3].size = sizeof(UInt); |
| 4935 | |
| 4936 | d->fxState[4].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4937 | d->fxState[4].offset = OFFB_FC3210; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4938 | d->fxState[4].size = sizeof(UInt); |
| 4939 | |
| 4940 | stmt( IRStmt_Dirty(d) ); |
| 4941 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4942 | /* ew contains any emulation warning we may need to |
| 4943 | issue. If needed, side-exit to the next insn, |
| 4944 | reporting the warning, so that Valgrind's dispatcher |
| 4945 | sees the warning. */ |
| 4946 | put_emwarn( mkexpr(ew) ); |
| 4947 | stmt( |
| 4948 | IRStmt_Exit( |
| 4949 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 4950 | Ijk_EmWarn, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 4951 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4952 | ) |
| 4953 | ); |
| 4954 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4955 | DIP("frstor %s\n", dis_buf); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4956 | break; |
| 4957 | } |
| 4958 | |
| 4959 | case 6: { /* FNSAVE m108 */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4960 | /* Uses dirty helper: |
| 4961 | void x86g_do_FSAVE ( VexGuestX86State*, UInt ) */ |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4962 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4963 | 0/*regparms*/, |
| 4964 | "x86g_dirtyhelper_FSAVE", |
| 4965 | &x86g_dirtyhelper_FSAVE, |
| 4966 | mkIRExprVec_1( mkexpr(addr) ) |
| 4967 | ); |
| 4968 | d->needsBBP = True; |
| 4969 | /* declare we're writing memory */ |
| 4970 | d->mFx = Ifx_Write; |
| 4971 | d->mAddr = mkexpr(addr); |
| 4972 | d->mSize = 108; |
| 4973 | |
| 4974 | /* declare we're reading guest state */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4975 | d->nFxState = 5; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4976 | |
| 4977 | d->fxState[0].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4978 | d->fxState[0].offset = OFFB_FTOP; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4979 | d->fxState[0].size = sizeof(UInt); |
| 4980 | |
| 4981 | d->fxState[1].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4982 | d->fxState[1].offset = OFFB_FPREGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4983 | d->fxState[1].size = 8 * sizeof(ULong); |
| 4984 | |
| 4985 | d->fxState[2].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4986 | d->fxState[2].offset = OFFB_FPTAGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4987 | d->fxState[2].size = 8 * sizeof(UChar); |
| 4988 | |
| 4989 | d->fxState[3].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4990 | d->fxState[3].offset = OFFB_FPROUND; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4991 | d->fxState[3].size = sizeof(UInt); |
| 4992 | |
| 4993 | d->fxState[4].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 4994 | d->fxState[4].offset = OFFB_FC3210; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4995 | d->fxState[4].size = sizeof(UInt); |
| 4996 | |
| 4997 | stmt( IRStmt_Dirty(d) ); |
| 4998 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4999 | DIP("fnsave %s\n", dis_buf); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5000 | break; |
| 5001 | } |
| 5002 | |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 5003 | case 7: { /* FNSTSW m16 */ |
| 5004 | IRExpr* sw = get_FPU_sw(); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5005 | vassert(typeOfIRExpr(irsb->tyenv, sw) == Ity_I16); |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 5006 | storeLE( mkexpr(addr), sw ); |
| 5007 | DIP("fnstsw %s\n", dis_buf); |
| 5008 | break; |
| 5009 | } |
| 5010 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5011 | default: |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 5012 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 5013 | vex_printf("first_opcode == 0xDD\n"); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5014 | goto decode_fail; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 5015 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5016 | } else { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5017 | delta++; |
| 5018 | switch (modrm) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5019 | |
sewardj | 3ddedc4 | 2005-03-25 20:30:00 +0000 | [diff] [blame] | 5020 | case 0xC0 ... 0xC7: /* FFREE %st(?) */ |
| 5021 | r_dst = (UInt)modrm - 0xC0; |
sewardj | 4a6f384 | 2005-03-26 11:59:23 +0000 | [diff] [blame] | 5022 | DIP("ffree %%st(%d)\n", (Int)r_dst); |
sewardj | 3ddedc4 | 2005-03-25 20:30:00 +0000 | [diff] [blame] | 5023 | put_ST_TAG ( r_dst, mkU8(0) ); |
| 5024 | break; |
| 5025 | |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 5026 | case 0xD0 ... 0xD7: /* FST %st(0),%st(?) */ |
| 5027 | r_dst = (UInt)modrm - 0xD0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5028 | DIP("fst %%st(0),%%st(%d)\n", (Int)r_dst); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5029 | /* P4 manual says: "If the destination operand is a |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 5030 | non-empty register, the invalid-operation exception |
| 5031 | is not generated. Hence put_ST_UNCHECKED. */ |
| 5032 | put_ST_UNCHECKED(r_dst, get_ST(0)); |
| 5033 | break; |
| 5034 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5035 | case 0xD8 ... 0xDF: /* FSTP %st(0),%st(?) */ |
| 5036 | r_dst = (UInt)modrm - 0xD8; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5037 | DIP("fstp %%st(0),%%st(%d)\n", (Int)r_dst); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5038 | /* P4 manual says: "If the destination operand is a |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 5039 | non-empty register, the invalid-operation exception |
| 5040 | is not generated. Hence put_ST_UNCHECKED. */ |
| 5041 | put_ST_UNCHECKED(r_dst, get_ST(0)); |
| 5042 | fp_pop(); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5043 | break; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5044 | |
| 5045 | case 0xE0 ... 0xE7: /* FUCOM %st(0),%st(?) */ |
| 5046 | r_dst = (UInt)modrm - 0xE0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5047 | DIP("fucom %%st(0),%%st(%d)\n", (Int)r_dst); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 5048 | /* This forces C1 to zero, which isn't right. */ |
| 5049 | put_C3210( |
| 5050 | binop( Iop_And32, |
| 5051 | binop(Iop_Shl32, |
| 5052 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 5053 | mkU8(8)), |
| 5054 | mkU32(0x4500) |
| 5055 | )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5056 | break; |
| 5057 | |
| 5058 | case 0xE8 ... 0xEF: /* FUCOMP %st(0),%st(?) */ |
| 5059 | r_dst = (UInt)modrm - 0xE8; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5060 | DIP("fucomp %%st(0),%%st(%d)\n", (Int)r_dst); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 5061 | /* This forces C1 to zero, which isn't right. */ |
| 5062 | put_C3210( |
| 5063 | binop( Iop_And32, |
| 5064 | binop(Iop_Shl32, |
| 5065 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 5066 | mkU8(8)), |
| 5067 | mkU32(0x4500) |
| 5068 | )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5069 | fp_pop(); |
| 5070 | break; |
| 5071 | |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5072 | default: |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5073 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5074 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5075 | } |
| 5076 | } |
| 5077 | |
| 5078 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDE opcodes +-+-+-+-+-+-+-+ */ |
| 5079 | else |
| 5080 | if (first_opcode == 0xDE) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5081 | |
| 5082 | if (modrm < 0xC0) { |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5083 | |
| 5084 | /* bits 5,4,3 are an opcode extension, and the modRM also |
| 5085 | specifies an address. */ |
| 5086 | IROp fop; |
| 5087 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5088 | delta += len; |
| 5089 | |
| 5090 | switch (gregOfRM(modrm)) { |
| 5091 | |
| 5092 | case 0: /* FIADD m16int */ /* ST(0) += m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5093 | DIP("fiaddw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5094 | fop = Iop_AddF64; |
| 5095 | goto do_fop_m16; |
| 5096 | |
| 5097 | case 1: /* FIMUL m16int */ /* ST(0) *= m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5098 | DIP("fimulw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5099 | fop = Iop_MulF64; |
| 5100 | goto do_fop_m16; |
| 5101 | |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5102 | case 2: /* FICOM m16int */ |
| 5103 | DIP("ficomw %s\n", dis_buf); |
| 5104 | /* This forces C1 to zero, which isn't right. */ |
| 5105 | put_C3210( |
| 5106 | binop( Iop_And32, |
| 5107 | binop(Iop_Shl32, |
| 5108 | binop(Iop_CmpF64, |
| 5109 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5110 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5111 | unop(Iop_16Sto32, |
| 5112 | loadLE(Ity_I16,mkexpr(addr))))), |
| 5113 | mkU8(8)), |
| 5114 | mkU32(0x4500) |
| 5115 | )); |
| 5116 | break; |
| 5117 | |
| 5118 | case 3: /* FICOMP m16int */ |
| 5119 | DIP("ficompw %s\n", dis_buf); |
| 5120 | /* This forces C1 to zero, which isn't right. */ |
| 5121 | put_C3210( |
| 5122 | binop( Iop_And32, |
| 5123 | binop(Iop_Shl32, |
| 5124 | binop(Iop_CmpF64, |
| 5125 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5126 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5127 | unop(Iop_16Sto32, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 5128 | loadLE(Ity_I16,mkexpr(addr))))), |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5129 | mkU8(8)), |
| 5130 | mkU32(0x4500) |
| 5131 | )); |
| 5132 | fp_pop(); |
| 5133 | break; |
| 5134 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5135 | case 4: /* FISUB m16int */ /* ST(0) -= m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5136 | DIP("fisubw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5137 | fop = Iop_SubF64; |
| 5138 | goto do_fop_m16; |
| 5139 | |
| 5140 | case 5: /* FISUBR m16int */ /* ST(0) = m16int - ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5141 | DIP("fisubrw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5142 | fop = Iop_SubF64; |
| 5143 | goto do_foprev_m16; |
| 5144 | |
| 5145 | case 6: /* FIDIV m16int */ /* ST(0) /= m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5146 | DIP("fisubw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5147 | fop = Iop_DivF64; |
| 5148 | goto do_fop_m16; |
| 5149 | |
| 5150 | case 7: /* FIDIVR m16int */ /* ST(0) = m16int / ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5151 | DIP("fidivrw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5152 | fop = Iop_DivF64; |
| 5153 | goto do_foprev_m16; |
| 5154 | |
| 5155 | do_fop_m16: |
| 5156 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 5157 | triop(fop, |
| 5158 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5159 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5160 | unop(Iop_I32StoF64, |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5161 | unop(Iop_16Sto32, |
| 5162 | loadLE(Ity_I16, mkexpr(addr)))))); |
| 5163 | break; |
| 5164 | |
| 5165 | do_foprev_m16: |
| 5166 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 5167 | triop(fop, |
| 5168 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5169 | unop(Iop_I32StoF64, |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5170 | unop(Iop_16Sto32, |
| 5171 | loadLE(Ity_I16, mkexpr(addr)))), |
| 5172 | get_ST(0))); |
| 5173 | break; |
| 5174 | |
| 5175 | default: |
| 5176 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 5177 | vex_printf("first_opcode == 0xDE\n"); |
| 5178 | goto decode_fail; |
| 5179 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5180 | |
| 5181 | } else { |
| 5182 | |
| 5183 | delta++; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5184 | switch (modrm) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5185 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5186 | case 0xC0 ... 0xC7: /* FADDP %st(0),%st(?) */ |
| 5187 | fp_do_op_ST_ST ( "add", Iop_AddF64, 0, modrm - 0xC0, True ); |
| 5188 | break; |
| 5189 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5190 | case 0xC8 ... 0xCF: /* FMULP %st(0),%st(?) */ |
| 5191 | fp_do_op_ST_ST ( "mul", Iop_MulF64, 0, modrm - 0xC8, True ); |
| 5192 | break; |
| 5193 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 5194 | case 0xD9: /* FCOMPP %st(0),%st(1) */ |
| 5195 | DIP("fuompp %%st(0),%%st(1)\n"); |
| 5196 | /* This forces C1 to zero, which isn't right. */ |
| 5197 | put_C3210( |
| 5198 | binop( Iop_And32, |
| 5199 | binop(Iop_Shl32, |
| 5200 | binop(Iop_CmpF64, get_ST(0), get_ST(1)), |
| 5201 | mkU8(8)), |
| 5202 | mkU32(0x4500) |
| 5203 | )); |
| 5204 | fp_pop(); |
| 5205 | fp_pop(); |
| 5206 | break; |
| 5207 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5208 | case 0xE0 ... 0xE7: /* FSUBRP %st(0),%st(?) */ |
| 5209 | fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, True ); |
| 5210 | break; |
| 5211 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 5212 | case 0xE8 ... 0xEF: /* FSUBP %st(0),%st(?) */ |
| 5213 | fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8, True ); |
| 5214 | break; |
| 5215 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5216 | case 0xF0 ... 0xF7: /* FDIVRP %st(0),%st(?) */ |
| 5217 | fp_do_oprev_ST_ST ( "divr", Iop_DivF64, 0, modrm - 0xF0, True ); |
| 5218 | break; |
| 5219 | |
| 5220 | case 0xF8 ... 0xFF: /* FDIVP %st(0),%st(?) */ |
| 5221 | fp_do_op_ST_ST ( "div", Iop_DivF64, 0, modrm - 0xF8, True ); |
| 5222 | break; |
| 5223 | |
| 5224 | default: |
| 5225 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5226 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5227 | |
| 5228 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5229 | } |
| 5230 | |
| 5231 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDF opcodes +-+-+-+-+-+-+-+ */ |
| 5232 | else |
| 5233 | if (first_opcode == 0xDF) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5234 | |
| 5235 | if (modrm < 0xC0) { |
| 5236 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5237 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5238 | specifies an address. */ |
| 5239 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5240 | delta += len; |
| 5241 | |
| 5242 | switch (gregOfRM(modrm)) { |
| 5243 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5244 | case 0: /* FILD m16int */ |
| 5245 | DIP("fildw %s\n", dis_buf); |
| 5246 | fp_push(); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5247 | put_ST(0, unop(Iop_I32StoF64, |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5248 | unop(Iop_16Sto32, |
| 5249 | loadLE(Ity_I16, mkexpr(addr))))); |
| 5250 | break; |
| 5251 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 5252 | case 1: /* FISTTPS m16 (SSE3) */ |
| 5253 | DIP("fisttps %s\n", dis_buf); |
| 5254 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5255 | binop(Iop_F64toI16S, mkU32(Irrm_ZERO), get_ST(0)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 5256 | fp_pop(); |
| 5257 | break; |
| 5258 | |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 5259 | case 2: /* FIST m16 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5260 | DIP("fistp %s\n", dis_buf); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 5261 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5262 | binop(Iop_F64toI16S, get_roundingmode(), get_ST(0)) ); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 5263 | break; |
| 5264 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5265 | case 3: /* FISTP m16 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5266 | DIP("fistps %s\n", dis_buf); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 5267 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5268 | binop(Iop_F64toI16S, get_roundingmode(), get_ST(0)) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 5269 | fp_pop(); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5270 | break; |
| 5271 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5272 | case 5: /* FILD m64 */ |
| 5273 | DIP("fildll %s\n", dis_buf); |
| 5274 | fp_push(); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5275 | put_ST(0, binop(Iop_I64StoF64, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5276 | get_roundingmode(), |
| 5277 | loadLE(Ity_I64, mkexpr(addr)))); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5278 | break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5279 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5280 | case 7: /* FISTP m64 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5281 | DIP("fistpll %s\n", dis_buf); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5282 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5283 | binop(Iop_F64toI64S, get_roundingmode(), get_ST(0)) ); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5284 | fp_pop(); |
| 5285 | break; |
| 5286 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5287 | default: |
| 5288 | vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm)); |
| 5289 | vex_printf("first_opcode == 0xDF\n"); |
| 5290 | goto decode_fail; |
| 5291 | } |
| 5292 | |
| 5293 | } else { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5294 | |
| 5295 | delta++; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5296 | switch (modrm) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5297 | |
sewardj | 8fb8869 | 2005-07-29 11:57:00 +0000 | [diff] [blame] | 5298 | case 0xC0: /* FFREEP %st(0) */ |
| 5299 | DIP("ffreep %%st(%d)\n", 0); |
| 5300 | put_ST_TAG ( 0, mkU8(0) ); |
| 5301 | fp_pop(); |
| 5302 | break; |
| 5303 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5304 | case 0xE0: /* FNSTSW %ax */ |
| 5305 | DIP("fnstsw %%ax\n"); |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 5306 | /* Get the FPU status word value and dump it in %AX. */ |
sewardj | 1d2e77f | 2008-06-04 09:10:38 +0000 | [diff] [blame] | 5307 | if (0) { |
| 5308 | /* The obvious thing to do is simply dump the 16-bit |
| 5309 | status word value in %AX. However, due to a |
| 5310 | limitation in Memcheck's origin tracking |
| 5311 | machinery, this causes Memcheck not to track the |
| 5312 | origin of any undefinedness into %AH (only into |
| 5313 | %AL/%AX/%EAX), which means origins are lost in |
| 5314 | the sequence "fnstsw %ax; test $M,%ah; jcond .." */ |
| 5315 | putIReg(2, R_EAX, get_FPU_sw()); |
| 5316 | } else { |
| 5317 | /* So a somewhat lame kludge is to make it very |
| 5318 | clear to Memcheck that the value is written to |
| 5319 | both %AH and %AL. This generates marginally |
| 5320 | worse code, but I don't think it matters much. */ |
| 5321 | IRTemp t16 = newTemp(Ity_I16); |
| 5322 | assign(t16, get_FPU_sw()); |
| 5323 | putIReg( 1, R_AL, unop(Iop_16to8, mkexpr(t16)) ); |
| 5324 | putIReg( 1, R_AH, unop(Iop_16HIto8, mkexpr(t16)) ); |
| 5325 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5326 | break; |
| 5327 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5328 | case 0xE8 ... 0xEF: /* FUCOMIP %st(0),%st(?) */ |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 5329 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xE8, True ); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5330 | break; |
| 5331 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5332 | case 0xF0 ... 0xF7: /* FCOMIP %st(0),%st(?) */ |
| 5333 | /* not really right since COMIP != UCOMIP */ |
| 5334 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xF0, True ); |
| 5335 | break; |
| 5336 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5337 | default: |
| 5338 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5339 | } |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5340 | } |
| 5341 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5342 | } |
| 5343 | |
| 5344 | else |
| 5345 | vpanic("dis_FPU(x86): invalid primary opcode"); |
| 5346 | |
sewardj | 69d9d66 | 2004-10-14 21:58:52 +0000 | [diff] [blame] | 5347 | *decode_ok = True; |
| 5348 | return delta; |
| 5349 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5350 | decode_fail: |
| 5351 | *decode_ok = False; |
| 5352 | return delta; |
| 5353 | } |
| 5354 | |
| 5355 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5356 | /*------------------------------------------------------------*/ |
| 5357 | /*--- ---*/ |
| 5358 | /*--- MMX INSTRUCTIONS ---*/ |
| 5359 | /*--- ---*/ |
| 5360 | /*------------------------------------------------------------*/ |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 5361 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5362 | /* Effect of MMX insns on x87 FPU state (table 11-2 of |
| 5363 | IA32 arch manual, volume 3): |
| 5364 | |
| 5365 | Read from, or write to MMX register (viz, any insn except EMMS): |
| 5366 | * All tags set to Valid (non-empty) -- FPTAGS[i] := nonzero |
| 5367 | * FP stack pointer set to zero |
| 5368 | |
| 5369 | EMMS: |
| 5370 | * All tags set to Invalid (empty) -- FPTAGS[i] := zero |
| 5371 | * FP stack pointer set to zero |
| 5372 | */ |
| 5373 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5374 | static void do_MMX_preamble ( void ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5375 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5376 | Int i; |
| 5377 | IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
| 5378 | IRExpr* zero = mkU32(0); |
| 5379 | IRExpr* tag1 = mkU8(1); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5380 | put_ftop(zero); |
| 5381 | for (i = 0; i < 8; i++) |
| 5382 | stmt( IRStmt_PutI( descr, zero, i, tag1 ) ); |
| 5383 | } |
| 5384 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5385 | static void do_EMMS_preamble ( void ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5386 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5387 | Int i; |
| 5388 | IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
| 5389 | IRExpr* zero = mkU32(0); |
| 5390 | IRExpr* tag0 = mkU8(0); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5391 | put_ftop(zero); |
| 5392 | for (i = 0; i < 8; i++) |
| 5393 | stmt( IRStmt_PutI( descr, zero, i, tag0 ) ); |
| 5394 | } |
| 5395 | |
| 5396 | |
| 5397 | static IRExpr* getMMXReg ( UInt archreg ) |
| 5398 | { |
| 5399 | vassert(archreg < 8); |
| 5400 | return IRExpr_Get( OFFB_FPREGS + 8 * archreg, Ity_I64 ); |
| 5401 | } |
| 5402 | |
| 5403 | |
| 5404 | static void putMMXReg ( UInt archreg, IRExpr* e ) |
| 5405 | { |
| 5406 | vassert(archreg < 8); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5407 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5408 | stmt( IRStmt_Put( OFFB_FPREGS + 8 * archreg, e ) ); |
| 5409 | } |
| 5410 | |
| 5411 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5412 | /* Helper for non-shift MMX insns. Note this is incomplete in the |
| 5413 | sense that it does not first call do_MMX_preamble() -- that is the |
| 5414 | responsibility of its caller. */ |
| 5415 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5416 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5417 | UInt dis_MMXop_regmem_to_reg ( UChar sorb, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5418 | Int delta, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5419 | UChar opc, |
| 5420 | HChar* name, |
| 5421 | Bool show_granularity ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5422 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5423 | HChar dis_buf[50]; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5424 | UChar modrm = getIByte(delta); |
| 5425 | Bool isReg = epartIsReg(modrm); |
| 5426 | IRExpr* argL = NULL; |
| 5427 | IRExpr* argR = NULL; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5428 | IRExpr* argG = NULL; |
| 5429 | IRExpr* argE = NULL; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5430 | IRTemp res = newTemp(Ity_I64); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5431 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5432 | Bool invG = False; |
| 5433 | IROp op = Iop_INVALID; |
| 5434 | void* hAddr = NULL; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5435 | HChar* hName = NULL; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5436 | Bool eLeft = False; |
| 5437 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5438 | # define XXX(_name) do { hAddr = &_name; hName = #_name; } while (0) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5439 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5440 | switch (opc) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 5441 | /* Original MMX ones */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5442 | case 0xFC: op = Iop_Add8x8; break; |
| 5443 | case 0xFD: op = Iop_Add16x4; break; |
| 5444 | case 0xFE: op = Iop_Add32x2; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5445 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5446 | case 0xEC: op = Iop_QAdd8Sx8; break; |
| 5447 | case 0xED: op = Iop_QAdd16Sx4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5448 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5449 | case 0xDC: op = Iop_QAdd8Ux8; break; |
| 5450 | case 0xDD: op = Iop_QAdd16Ux4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5451 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5452 | case 0xF8: op = Iop_Sub8x8; break; |
| 5453 | case 0xF9: op = Iop_Sub16x4; break; |
| 5454 | case 0xFA: op = Iop_Sub32x2; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5455 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5456 | case 0xE8: op = Iop_QSub8Sx8; break; |
| 5457 | case 0xE9: op = Iop_QSub16Sx4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5458 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5459 | case 0xD8: op = Iop_QSub8Ux8; break; |
| 5460 | case 0xD9: op = Iop_QSub16Ux4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5461 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5462 | case 0xE5: op = Iop_MulHi16Sx4; break; |
| 5463 | case 0xD5: op = Iop_Mul16x4; break; |
| 5464 | case 0xF5: XXX(x86g_calculate_mmx_pmaddwd); break; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5465 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5466 | case 0x74: op = Iop_CmpEQ8x8; break; |
| 5467 | case 0x75: op = Iop_CmpEQ16x4; break; |
| 5468 | case 0x76: op = Iop_CmpEQ32x2; break; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5469 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5470 | case 0x64: op = Iop_CmpGT8Sx8; break; |
| 5471 | case 0x65: op = Iop_CmpGT16Sx4; break; |
| 5472 | case 0x66: op = Iop_CmpGT32Sx2; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5473 | |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 5474 | case 0x6B: op = Iop_QNarrowBin32Sto16Sx4; eLeft = True; break; |
| 5475 | case 0x63: op = Iop_QNarrowBin16Sto8Sx8; eLeft = True; break; |
| 5476 | case 0x67: op = Iop_QNarrowBin16Sto8Ux8; eLeft = True; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5477 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5478 | case 0x68: op = Iop_InterleaveHI8x8; eLeft = True; break; |
| 5479 | case 0x69: op = Iop_InterleaveHI16x4; eLeft = True; break; |
| 5480 | case 0x6A: op = Iop_InterleaveHI32x2; eLeft = True; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5481 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5482 | case 0x60: op = Iop_InterleaveLO8x8; eLeft = True; break; |
| 5483 | case 0x61: op = Iop_InterleaveLO16x4; eLeft = True; break; |
| 5484 | case 0x62: op = Iop_InterleaveLO32x2; eLeft = True; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5485 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5486 | case 0xDB: op = Iop_And64; break; |
| 5487 | case 0xDF: op = Iop_And64; invG = True; break; |
| 5488 | case 0xEB: op = Iop_Or64; break; |
| 5489 | case 0xEF: /* Possibly do better here if argL and argR are the |
| 5490 | same reg */ |
| 5491 | op = Iop_Xor64; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5492 | |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 5493 | /* Introduced in SSE1 */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5494 | case 0xE0: op = Iop_Avg8Ux8; break; |
| 5495 | case 0xE3: op = Iop_Avg16Ux4; break; |
| 5496 | case 0xEE: op = Iop_Max16Sx4; break; |
| 5497 | case 0xDE: op = Iop_Max8Ux8; break; |
| 5498 | case 0xEA: op = Iop_Min16Sx4; break; |
| 5499 | case 0xDA: op = Iop_Min8Ux8; break; |
| 5500 | case 0xE4: op = Iop_MulHi16Ux4; break; |
| 5501 | case 0xF6: XXX(x86g_calculate_mmx_psadbw); break; |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 5502 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 5503 | /* Introduced in SSE2 */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5504 | case 0xD4: op = Iop_Add64; break; |
| 5505 | case 0xFB: op = Iop_Sub64; break; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 5506 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5507 | default: |
| 5508 | vex_printf("\n0x%x\n", (Int)opc); |
| 5509 | vpanic("dis_MMXop_regmem_to_reg"); |
| 5510 | } |
| 5511 | |
| 5512 | # undef XXX |
| 5513 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5514 | argG = getMMXReg(gregOfRM(modrm)); |
| 5515 | if (invG) |
| 5516 | argG = unop(Iop_Not64, argG); |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5517 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5518 | if (isReg) { |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5519 | delta++; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5520 | argE = getMMXReg(eregOfRM(modrm)); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5521 | } else { |
| 5522 | Int len; |
| 5523 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5524 | delta += len; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5525 | argE = loadLE(Ity_I64, mkexpr(addr)); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5526 | } |
| 5527 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5528 | if (eLeft) { |
| 5529 | argL = argE; |
| 5530 | argR = argG; |
| 5531 | } else { |
| 5532 | argL = argG; |
| 5533 | argR = argE; |
| 5534 | } |
| 5535 | |
| 5536 | if (op != Iop_INVALID) { |
| 5537 | vassert(hName == NULL); |
| 5538 | vassert(hAddr == NULL); |
| 5539 | assign(res, binop(op, argL, argR)); |
| 5540 | } else { |
| 5541 | vassert(hName != NULL); |
| 5542 | vassert(hAddr != NULL); |
| 5543 | assign( res, |
| 5544 | mkIRExprCCall( |
| 5545 | Ity_I64, |
| 5546 | 0/*regparms*/, hName, hAddr, |
| 5547 | mkIRExprVec_2( argL, argR ) |
| 5548 | ) |
| 5549 | ); |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5550 | } |
| 5551 | |
| 5552 | putMMXReg( gregOfRM(modrm), mkexpr(res) ); |
| 5553 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5554 | DIP("%s%s %s, %s\n", |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5555 | name, show_granularity ? nameMMXGran(opc & 3) : "", |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5556 | ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ), |
| 5557 | nameMMXReg(gregOfRM(modrm)) ); |
| 5558 | |
| 5559 | return delta; |
| 5560 | } |
| 5561 | |
| 5562 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5563 | /* Vector by scalar shift of G by the amount specified at the bottom |
| 5564 | of E. This is a straight copy of dis_SSE_shiftG_byE. */ |
| 5565 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5566 | static UInt dis_MMX_shiftG_byE ( UChar sorb, Int delta, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5567 | HChar* opname, IROp op ) |
| 5568 | { |
| 5569 | HChar dis_buf[50]; |
| 5570 | Int alen, size; |
| 5571 | IRTemp addr; |
| 5572 | Bool shl, shr, sar; |
| 5573 | UChar rm = getIByte(delta); |
| 5574 | IRTemp g0 = newTemp(Ity_I64); |
| 5575 | IRTemp g1 = newTemp(Ity_I64); |
| 5576 | IRTemp amt = newTemp(Ity_I32); |
| 5577 | IRTemp amt8 = newTemp(Ity_I8); |
| 5578 | |
| 5579 | if (epartIsReg(rm)) { |
| 5580 | assign( amt, unop(Iop_64to32, getMMXReg(eregOfRM(rm))) ); |
| 5581 | DIP("%s %s,%s\n", opname, |
| 5582 | nameMMXReg(eregOfRM(rm)), |
| 5583 | nameMMXReg(gregOfRM(rm)) ); |
| 5584 | delta++; |
| 5585 | } else { |
| 5586 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 5587 | assign( amt, loadLE(Ity_I32, mkexpr(addr)) ); |
| 5588 | DIP("%s %s,%s\n", opname, |
| 5589 | dis_buf, |
| 5590 | nameMMXReg(gregOfRM(rm)) ); |
| 5591 | delta += alen; |
| 5592 | } |
| 5593 | assign( g0, getMMXReg(gregOfRM(rm)) ); |
| 5594 | assign( amt8, unop(Iop_32to8, mkexpr(amt)) ); |
| 5595 | |
| 5596 | shl = shr = sar = False; |
| 5597 | size = 0; |
| 5598 | switch (op) { |
| 5599 | case Iop_ShlN16x4: shl = True; size = 32; break; |
| 5600 | case Iop_ShlN32x2: shl = True; size = 32; break; |
| 5601 | case Iop_Shl64: shl = True; size = 64; break; |
| 5602 | case Iop_ShrN16x4: shr = True; size = 16; break; |
| 5603 | case Iop_ShrN32x2: shr = True; size = 32; break; |
| 5604 | case Iop_Shr64: shr = True; size = 64; break; |
| 5605 | case Iop_SarN16x4: sar = True; size = 16; break; |
| 5606 | case Iop_SarN32x2: sar = True; size = 32; break; |
| 5607 | default: vassert(0); |
| 5608 | } |
| 5609 | |
| 5610 | if (shl || shr) { |
| 5611 | assign( |
| 5612 | g1, |
| 5613 | IRExpr_Mux0X( |
| 5614 | unop(Iop_1Uto8,binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size))), |
| 5615 | mkU64(0), |
| 5616 | binop(op, mkexpr(g0), mkexpr(amt8)) |
| 5617 | ) |
| 5618 | ); |
| 5619 | } else |
| 5620 | if (sar) { |
| 5621 | assign( |
| 5622 | g1, |
| 5623 | IRExpr_Mux0X( |
| 5624 | unop(Iop_1Uto8,binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size))), |
| 5625 | binop(op, mkexpr(g0), mkU8(size-1)), |
| 5626 | binop(op, mkexpr(g0), mkexpr(amt8)) |
| 5627 | ) |
| 5628 | ); |
| 5629 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5630 | /*NOTREACHED*/ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5631 | vassert(0); |
| 5632 | } |
| 5633 | |
| 5634 | putMMXReg( gregOfRM(rm), mkexpr(g1) ); |
| 5635 | return delta; |
| 5636 | } |
| 5637 | |
| 5638 | |
| 5639 | /* Vector by scalar shift of E by an immediate byte. This is a |
| 5640 | straight copy of dis_SSE_shiftE_imm. */ |
| 5641 | |
| 5642 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5643 | UInt dis_MMX_shiftE_imm ( Int delta, HChar* opname, IROp op ) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5644 | { |
| 5645 | Bool shl, shr, sar; |
| 5646 | UChar rm = getIByte(delta); |
| 5647 | IRTemp e0 = newTemp(Ity_I64); |
| 5648 | IRTemp e1 = newTemp(Ity_I64); |
| 5649 | UChar amt, size; |
| 5650 | vassert(epartIsReg(rm)); |
| 5651 | vassert(gregOfRM(rm) == 2 |
| 5652 | || gregOfRM(rm) == 4 || gregOfRM(rm) == 6); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5653 | amt = getIByte(delta+1); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5654 | delta += 2; |
| 5655 | DIP("%s $%d,%s\n", opname, |
| 5656 | (Int)amt, |
| 5657 | nameMMXReg(eregOfRM(rm)) ); |
| 5658 | |
| 5659 | assign( e0, getMMXReg(eregOfRM(rm)) ); |
| 5660 | |
| 5661 | shl = shr = sar = False; |
| 5662 | size = 0; |
| 5663 | switch (op) { |
| 5664 | case Iop_ShlN16x4: shl = True; size = 16; break; |
| 5665 | case Iop_ShlN32x2: shl = True; size = 32; break; |
| 5666 | case Iop_Shl64: shl = True; size = 64; break; |
| 5667 | case Iop_SarN16x4: sar = True; size = 16; break; |
| 5668 | case Iop_SarN32x2: sar = True; size = 32; break; |
| 5669 | case Iop_ShrN16x4: shr = True; size = 16; break; |
| 5670 | case Iop_ShrN32x2: shr = True; size = 32; break; |
| 5671 | case Iop_Shr64: shr = True; size = 64; break; |
| 5672 | default: vassert(0); |
| 5673 | } |
| 5674 | |
| 5675 | if (shl || shr) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5676 | assign( e1, amt >= size |
| 5677 | ? mkU64(0) |
| 5678 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 5679 | ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5680 | } else |
| 5681 | if (sar) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5682 | assign( e1, amt >= size |
| 5683 | ? binop(op, mkexpr(e0), mkU8(size-1)) |
| 5684 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 5685 | ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5686 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5687 | /*NOTREACHED*/ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5688 | vassert(0); |
| 5689 | } |
| 5690 | |
| 5691 | putMMXReg( eregOfRM(rm), mkexpr(e1) ); |
| 5692 | return delta; |
| 5693 | } |
| 5694 | |
| 5695 | |
| 5696 | /* Completely handle all MMX instructions except emms. */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5697 | |
| 5698 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5699 | UInt dis_MMX ( Bool* decode_ok, UChar sorb, Int sz, Int delta ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5700 | { |
| 5701 | Int len; |
| 5702 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5703 | HChar dis_buf[50]; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5704 | UChar opc = getIByte(delta); |
| 5705 | delta++; |
| 5706 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5707 | /* dis_MMX handles all insns except emms. */ |
| 5708 | do_MMX_preamble(); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5709 | |
| 5710 | switch (opc) { |
| 5711 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5712 | case 0x6E: |
| 5713 | /* MOVD (src)ireg-or-mem (E), (dst)mmxreg (G)*/ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5714 | if (sz != 4) |
| 5715 | goto mmx_decode_failure; |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5716 | modrm = getIByte(delta); |
| 5717 | if (epartIsReg(modrm)) { |
| 5718 | delta++; |
| 5719 | putMMXReg( |
| 5720 | gregOfRM(modrm), |
| 5721 | binop( Iop_32HLto64, |
| 5722 | mkU32(0), |
| 5723 | getIReg(4, eregOfRM(modrm)) ) ); |
| 5724 | DIP("movd %s, %s\n", |
| 5725 | nameIReg(4,eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm))); |
| 5726 | } else { |
| 5727 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5728 | delta += len; |
| 5729 | putMMXReg( |
| 5730 | gregOfRM(modrm), |
| 5731 | binop( Iop_32HLto64, |
| 5732 | mkU32(0), |
| 5733 | loadLE(Ity_I32, mkexpr(addr)) ) ); |
| 5734 | DIP("movd %s, %s\n", dis_buf, nameMMXReg(gregOfRM(modrm))); |
| 5735 | } |
| 5736 | break; |
| 5737 | |
| 5738 | case 0x7E: /* MOVD (src)mmxreg (G), (dst)ireg-or-mem (E) */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5739 | if (sz != 4) |
| 5740 | goto mmx_decode_failure; |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5741 | modrm = getIByte(delta); |
| 5742 | if (epartIsReg(modrm)) { |
| 5743 | delta++; |
| 5744 | putIReg( 4, eregOfRM(modrm), |
| 5745 | unop(Iop_64to32, getMMXReg(gregOfRM(modrm)) ) ); |
| 5746 | DIP("movd %s, %s\n", |
| 5747 | nameMMXReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm))); |
| 5748 | } else { |
| 5749 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5750 | delta += len; |
| 5751 | storeLE( mkexpr(addr), |
| 5752 | unop(Iop_64to32, getMMXReg(gregOfRM(modrm)) ) ); |
| 5753 | DIP("movd %s, %s\n", nameMMXReg(gregOfRM(modrm)), dis_buf); |
| 5754 | } |
| 5755 | break; |
| 5756 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5757 | case 0x6F: |
| 5758 | /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5759 | if (sz != 4) |
| 5760 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5761 | modrm = getIByte(delta); |
| 5762 | if (epartIsReg(modrm)) { |
| 5763 | delta++; |
| 5764 | putMMXReg( gregOfRM(modrm), getMMXReg(eregOfRM(modrm)) ); |
| 5765 | DIP("movq %s, %s\n", |
| 5766 | nameMMXReg(eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm))); |
| 5767 | } else { |
| 5768 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5769 | delta += len; |
| 5770 | putMMXReg( gregOfRM(modrm), loadLE(Ity_I64, mkexpr(addr)) ); |
| 5771 | DIP("movq %s, %s\n", |
| 5772 | dis_buf, nameMMXReg(gregOfRM(modrm))); |
| 5773 | } |
| 5774 | break; |
| 5775 | |
| 5776 | case 0x7F: |
| 5777 | /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5778 | if (sz != 4) |
| 5779 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5780 | modrm = getIByte(delta); |
| 5781 | if (epartIsReg(modrm)) { |
sewardj | 9ca2640 | 2005-10-03 02:44:01 +0000 | [diff] [blame] | 5782 | delta++; |
| 5783 | putMMXReg( eregOfRM(modrm), getMMXReg(gregOfRM(modrm)) ); |
| 5784 | DIP("movq %s, %s\n", |
| 5785 | nameMMXReg(gregOfRM(modrm)), nameMMXReg(eregOfRM(modrm))); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5786 | } else { |
| 5787 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5788 | delta += len; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5789 | storeLE( mkexpr(addr), getMMXReg(gregOfRM(modrm)) ); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5790 | DIP("mov(nt)q %s, %s\n", |
| 5791 | nameMMXReg(gregOfRM(modrm)), dis_buf); |
| 5792 | } |
| 5793 | break; |
| 5794 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5795 | case 0xFC: |
| 5796 | case 0xFD: |
| 5797 | case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5798 | if (sz != 4) |
| 5799 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5800 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "padd", True ); |
| 5801 | break; |
| 5802 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5803 | case 0xEC: |
| 5804 | case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5805 | if (sz != 4) |
| 5806 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5807 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "padds", True ); |
| 5808 | break; |
| 5809 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5810 | case 0xDC: |
| 5811 | case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5812 | if (sz != 4) |
| 5813 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5814 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "paddus", True ); |
| 5815 | break; |
| 5816 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5817 | case 0xF8: |
| 5818 | case 0xF9: |
| 5819 | case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5820 | if (sz != 4) |
| 5821 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5822 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psub", True ); |
| 5823 | break; |
| 5824 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5825 | case 0xE8: |
| 5826 | case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5827 | if (sz != 4) |
| 5828 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5829 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psubs", True ); |
| 5830 | break; |
| 5831 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5832 | case 0xD8: |
| 5833 | case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5834 | if (sz != 4) |
| 5835 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5836 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psubus", True ); |
| 5837 | break; |
| 5838 | |
| 5839 | case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5840 | if (sz != 4) |
| 5841 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5842 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmulhw", False ); |
| 5843 | break; |
| 5844 | |
| 5845 | case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5846 | if (sz != 4) |
| 5847 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5848 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmullw", False ); |
| 5849 | break; |
| 5850 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5851 | case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */ |
| 5852 | vassert(sz == 4); |
| 5853 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmaddwd", False ); |
| 5854 | break; |
| 5855 | |
| 5856 | case 0x74: |
| 5857 | case 0x75: |
| 5858 | case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5859 | if (sz != 4) |
| 5860 | goto mmx_decode_failure; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5861 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pcmpeq", True ); |
| 5862 | break; |
| 5863 | |
| 5864 | case 0x64: |
| 5865 | case 0x65: |
| 5866 | case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5867 | if (sz != 4) |
| 5868 | goto mmx_decode_failure; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5869 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pcmpgt", True ); |
| 5870 | break; |
| 5871 | |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5872 | case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5873 | if (sz != 4) |
| 5874 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5875 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "packssdw", False ); |
| 5876 | break; |
| 5877 | |
| 5878 | case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5879 | if (sz != 4) |
| 5880 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5881 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "packsswb", False ); |
| 5882 | break; |
| 5883 | |
| 5884 | case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5885 | if (sz != 4) |
| 5886 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5887 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "packuswb", False ); |
| 5888 | break; |
| 5889 | |
| 5890 | case 0x68: |
| 5891 | case 0x69: |
| 5892 | case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5893 | if (sz != 4) |
| 5894 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5895 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "punpckh", True ); |
| 5896 | break; |
| 5897 | |
| 5898 | case 0x60: |
| 5899 | case 0x61: |
| 5900 | case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5901 | if (sz != 4) |
| 5902 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5903 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "punpckl", True ); |
| 5904 | break; |
| 5905 | |
| 5906 | case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5907 | if (sz != 4) |
| 5908 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5909 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pand", False ); |
| 5910 | break; |
| 5911 | |
| 5912 | case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5913 | if (sz != 4) |
| 5914 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5915 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pandn", False ); |
| 5916 | break; |
| 5917 | |
| 5918 | case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5919 | if (sz != 4) |
| 5920 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5921 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "por", False ); |
| 5922 | break; |
| 5923 | |
| 5924 | case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5925 | if (sz != 4) |
| 5926 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5927 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pxor", False ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5928 | break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5929 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5930 | # define SHIFT_BY_REG(_name,_op) \ |
| 5931 | delta = dis_MMX_shiftG_byE(sorb, delta, _name, _op); \ |
| 5932 | break; |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 5933 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5934 | /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 5935 | case 0xF1: SHIFT_BY_REG("psllw", Iop_ShlN16x4); |
| 5936 | case 0xF2: SHIFT_BY_REG("pslld", Iop_ShlN32x2); |
| 5937 | case 0xF3: SHIFT_BY_REG("psllq", Iop_Shl64); |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 5938 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5939 | /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 5940 | case 0xD1: SHIFT_BY_REG("psrlw", Iop_ShrN16x4); |
| 5941 | case 0xD2: SHIFT_BY_REG("psrld", Iop_ShrN32x2); |
| 5942 | case 0xD3: SHIFT_BY_REG("psrlq", Iop_Shr64); |
| 5943 | |
| 5944 | /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 5945 | case 0xE1: SHIFT_BY_REG("psraw", Iop_SarN16x4); |
| 5946 | case 0xE2: SHIFT_BY_REG("psrad", Iop_SarN32x2); |
| 5947 | |
| 5948 | # undef SHIFT_BY_REG |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 5949 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5950 | case 0x71: |
| 5951 | case 0x72: |
| 5952 | case 0x73: { |
| 5953 | /* (sz==4): PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */ |
sewardj | a8415ff | 2005-01-21 20:55:36 +0000 | [diff] [blame] | 5954 | UChar byte2, subopc; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5955 | if (sz != 4) |
| 5956 | goto mmx_decode_failure; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5957 | byte2 = getIByte(delta); /* amode / sub-opcode */ |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 5958 | subopc = toUChar( (byte2 >> 3) & 7 ); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5959 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5960 | # define SHIFT_BY_IMM(_name,_op) \ |
| 5961 | do { delta = dis_MMX_shiftE_imm(delta,_name,_op); \ |
| 5962 | } while (0) |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5963 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5964 | if (subopc == 2 /*SRL*/ && opc == 0x71) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5965 | SHIFT_BY_IMM("psrlw", Iop_ShrN16x4); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5966 | else if (subopc == 2 /*SRL*/ && opc == 0x72) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5967 | SHIFT_BY_IMM("psrld", Iop_ShrN32x2); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5968 | else if (subopc == 2 /*SRL*/ && opc == 0x73) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5969 | SHIFT_BY_IMM("psrlq", Iop_Shr64); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5970 | |
| 5971 | else if (subopc == 4 /*SAR*/ && opc == 0x71) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5972 | SHIFT_BY_IMM("psraw", Iop_SarN16x4); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5973 | else if (subopc == 4 /*SAR*/ && opc == 0x72) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5974 | SHIFT_BY_IMM("psrad", Iop_SarN32x2); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5975 | |
| 5976 | else if (subopc == 6 /*SHL*/ && opc == 0x71) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5977 | SHIFT_BY_IMM("psllw", Iop_ShlN16x4); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5978 | else if (subopc == 6 /*SHL*/ && opc == 0x72) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5979 | SHIFT_BY_IMM("pslld", Iop_ShlN32x2); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5980 | else if (subopc == 6 /*SHL*/ && opc == 0x73) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5981 | SHIFT_BY_IMM("psllq", Iop_Shl64); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5982 | |
| 5983 | else goto mmx_decode_failure; |
| 5984 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5985 | # undef SHIFT_BY_IMM |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5986 | break; |
| 5987 | } |
| 5988 | |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 5989 | case 0xF7: { |
| 5990 | IRTemp addr = newTemp(Ity_I32); |
| 5991 | IRTemp regD = newTemp(Ity_I64); |
| 5992 | IRTemp regM = newTemp(Ity_I64); |
| 5993 | IRTemp mask = newTemp(Ity_I64); |
| 5994 | IRTemp olddata = newTemp(Ity_I64); |
| 5995 | IRTemp newdata = newTemp(Ity_I64); |
| 5996 | |
| 5997 | modrm = getIByte(delta); |
| 5998 | if (sz != 4 || (!epartIsReg(modrm))) |
| 5999 | goto mmx_decode_failure; |
| 6000 | delta++; |
| 6001 | |
| 6002 | assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) )); |
| 6003 | assign( regM, getMMXReg( eregOfRM(modrm) )); |
| 6004 | assign( regD, getMMXReg( gregOfRM(modrm) )); |
| 6005 | assign( mask, binop(Iop_SarN8x8, mkexpr(regM), mkU8(7)) ); |
| 6006 | assign( olddata, loadLE( Ity_I64, mkexpr(addr) )); |
| 6007 | assign( newdata, |
| 6008 | binop(Iop_Or64, |
| 6009 | binop(Iop_And64, |
| 6010 | mkexpr(regD), |
| 6011 | mkexpr(mask) ), |
| 6012 | binop(Iop_And64, |
| 6013 | mkexpr(olddata), |
| 6014 | unop(Iop_Not64, mkexpr(mask)))) ); |
| 6015 | storeLE( mkexpr(addr), mkexpr(newdata) ); |
| 6016 | DIP("maskmovq %s,%s\n", nameMMXReg( eregOfRM(modrm) ), |
| 6017 | nameMMXReg( gregOfRM(modrm) ) ); |
| 6018 | break; |
| 6019 | } |
| 6020 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6021 | /* --- MMX decode failure --- */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 6022 | default: |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6023 | mmx_decode_failure: |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 6024 | *decode_ok = False; |
| 6025 | return delta; /* ignored */ |
| 6026 | |
| 6027 | } |
| 6028 | |
| 6029 | *decode_ok = True; |
| 6030 | return delta; |
| 6031 | } |
| 6032 | |
| 6033 | |
| 6034 | /*------------------------------------------------------------*/ |
| 6035 | /*--- More misc arithmetic and other obscure insns. ---*/ |
| 6036 | /*------------------------------------------------------------*/ |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6037 | |
| 6038 | /* Double length left and right shifts. Apparently only required in |
| 6039 | v-size (no b- variant). */ |
| 6040 | static |
| 6041 | UInt dis_SHLRD_Gv_Ev ( UChar sorb, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6042 | Int delta, UChar modrm, |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6043 | Int sz, |
| 6044 | IRExpr* shift_amt, |
| 6045 | Bool amt_is_literal, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 6046 | HChar* shift_amt_txt, |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6047 | Bool left_shift ) |
| 6048 | { |
| 6049 | /* shift_amt :: Ity_I8 is the amount to shift. shift_amt_txt is used |
| 6050 | for printing it. And eip on entry points at the modrm byte. */ |
| 6051 | Int len; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6052 | HChar dis_buf[50]; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6053 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 6054 | IRType ty = szToITy(sz); |
| 6055 | IRTemp gsrc = newTemp(ty); |
| 6056 | IRTemp esrc = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 6057 | IRTemp addr = IRTemp_INVALID; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 6058 | IRTemp tmpSH = newTemp(Ity_I8); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 6059 | IRTemp tmpL = IRTemp_INVALID; |
| 6060 | IRTemp tmpRes = IRTemp_INVALID; |
| 6061 | IRTemp tmpSubSh = IRTemp_INVALID; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6062 | IROp mkpair; |
| 6063 | IROp getres; |
| 6064 | IROp shift; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6065 | IRExpr* mask = NULL; |
| 6066 | |
| 6067 | vassert(sz == 2 || sz == 4); |
| 6068 | |
| 6069 | /* The E-part is the destination; this is shifted. The G-part |
| 6070 | supplies bits to be shifted into the E-part, but is not |
| 6071 | changed. |
| 6072 | |
| 6073 | If shifting left, form a double-length word with E at the top |
| 6074 | and G at the bottom, and shift this left. The result is then in |
| 6075 | the high part. |
| 6076 | |
| 6077 | If shifting right, form a double-length word with G at the top |
| 6078 | and E at the bottom, and shift this right. The result is then |
| 6079 | at the bottom. */ |
| 6080 | |
| 6081 | /* Fetch the operands. */ |
| 6082 | |
| 6083 | assign( gsrc, getIReg(sz, gregOfRM(modrm)) ); |
| 6084 | |
| 6085 | if (epartIsReg(modrm)) { |
| 6086 | delta++; |
| 6087 | assign( esrc, getIReg(sz, eregOfRM(modrm)) ); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 6088 | DIP("sh%cd%c %s, %s, %s\n", |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6089 | ( left_shift ? 'l' : 'r' ), nameISize(sz), |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 6090 | shift_amt_txt, |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6091 | nameIReg(sz, gregOfRM(modrm)), nameIReg(sz, eregOfRM(modrm))); |
| 6092 | } else { |
| 6093 | addr = disAMode ( &len, sorb, delta, dis_buf ); |
| 6094 | delta += len; |
| 6095 | assign( esrc, loadLE(ty, mkexpr(addr)) ); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 6096 | DIP("sh%cd%c %s, %s, %s\n", |
| 6097 | ( left_shift ? 'l' : 'r' ), nameISize(sz), |
| 6098 | shift_amt_txt, |
| 6099 | nameIReg(sz, gregOfRM(modrm)), dis_buf); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6100 | } |
| 6101 | |
| 6102 | /* Round up the relevant primops. */ |
| 6103 | |
| 6104 | if (sz == 4) { |
| 6105 | tmpL = newTemp(Ity_I64); |
| 6106 | tmpRes = newTemp(Ity_I32); |
| 6107 | tmpSubSh = newTemp(Ity_I32); |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 6108 | mkpair = Iop_32HLto64; |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 6109 | getres = left_shift ? Iop_64HIto32 : Iop_64to32; |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 6110 | shift = left_shift ? Iop_Shl64 : Iop_Shr64; |
| 6111 | mask = mkU8(31); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6112 | } else { |
| 6113 | /* sz == 2 */ |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 6114 | tmpL = newTemp(Ity_I32); |
| 6115 | tmpRes = newTemp(Ity_I16); |
| 6116 | tmpSubSh = newTemp(Ity_I16); |
| 6117 | mkpair = Iop_16HLto32; |
| 6118 | getres = left_shift ? Iop_32HIto16 : Iop_32to16; |
| 6119 | shift = left_shift ? Iop_Shl32 : Iop_Shr32; |
| 6120 | mask = mkU8(15); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6121 | } |
| 6122 | |
| 6123 | /* Do the shift, calculate the subshift value, and set |
| 6124 | the flag thunk. */ |
| 6125 | |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 6126 | assign( tmpSH, binop(Iop_And8, shift_amt, mask) ); |
| 6127 | |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6128 | if (left_shift) |
| 6129 | assign( tmpL, binop(mkpair, mkexpr(esrc), mkexpr(gsrc)) ); |
| 6130 | else |
| 6131 | assign( tmpL, binop(mkpair, mkexpr(gsrc), mkexpr(esrc)) ); |
| 6132 | |
| 6133 | assign( tmpRes, unop(getres, binop(shift, mkexpr(tmpL), mkexpr(tmpSH)) ) ); |
| 6134 | assign( tmpSubSh, |
| 6135 | unop(getres, |
| 6136 | binop(shift, |
| 6137 | mkexpr(tmpL), |
| 6138 | binop(Iop_And8, |
| 6139 | binop(Iop_Sub8, mkexpr(tmpSH), mkU8(1) ), |
| 6140 | mask))) ); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6141 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6142 | setFlags_DEP1_DEP2_shift ( left_shift ? Iop_Shl32 : Iop_Sar32, |
| 6143 | tmpRes, tmpSubSh, ty, tmpSH ); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6144 | |
| 6145 | /* Put result back. */ |
| 6146 | |
| 6147 | if (epartIsReg(modrm)) { |
| 6148 | putIReg(sz, eregOfRM(modrm), mkexpr(tmpRes)); |
| 6149 | } else { |
| 6150 | storeLE( mkexpr(addr), mkexpr(tmpRes) ); |
| 6151 | } |
| 6152 | |
| 6153 | if (amt_is_literal) delta++; |
| 6154 | return delta; |
| 6155 | } |
| 6156 | |
| 6157 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6158 | /* Handle BT/BTS/BTR/BTC Gv, Ev. Apparently b-size is not |
| 6159 | required. */ |
| 6160 | |
| 6161 | typedef enum { BtOpNone, BtOpSet, BtOpReset, BtOpComp } BtOp; |
| 6162 | |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 6163 | static HChar* nameBtOp ( BtOp op ) |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6164 | { |
| 6165 | switch (op) { |
| 6166 | case BtOpNone: return ""; |
| 6167 | case BtOpSet: return "s"; |
| 6168 | case BtOpReset: return "r"; |
| 6169 | case BtOpComp: return "c"; |
| 6170 | default: vpanic("nameBtOp(x86)"); |
| 6171 | } |
| 6172 | } |
| 6173 | |
| 6174 | |
| 6175 | static |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 6176 | UInt dis_bt_G_E ( VexAbiInfo* vbi, |
| 6177 | UChar sorb, Bool locked, Int sz, Int delta, BtOp op ) |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6178 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6179 | HChar dis_buf[50]; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6180 | UChar modrm; |
| 6181 | Int len; |
| 6182 | IRTemp t_fetched, t_bitno0, t_bitno1, t_bitno2, t_addr0, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6183 | t_addr1, t_esp, t_mask, t_new; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6184 | |
| 6185 | vassert(sz == 2 || sz == 4); |
| 6186 | |
| 6187 | t_fetched = t_bitno0 = t_bitno1 = t_bitno2 |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6188 | = t_addr0 = t_addr1 = t_esp |
| 6189 | = t_mask = t_new = IRTemp_INVALID; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6190 | |
| 6191 | t_fetched = newTemp(Ity_I8); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6192 | t_new = newTemp(Ity_I8); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6193 | t_bitno0 = newTemp(Ity_I32); |
| 6194 | t_bitno1 = newTemp(Ity_I32); |
| 6195 | t_bitno2 = newTemp(Ity_I8); |
| 6196 | t_addr1 = newTemp(Ity_I32); |
| 6197 | modrm = getIByte(delta); |
| 6198 | |
sewardj | 9ed1680 | 2005-08-24 10:46:19 +0000 | [diff] [blame] | 6199 | assign( t_bitno0, widenSto32(getIReg(sz, gregOfRM(modrm))) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6200 | |
| 6201 | if (epartIsReg(modrm)) { |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6202 | delta++; |
| 6203 | /* Get it onto the client's stack. */ |
| 6204 | t_esp = newTemp(Ity_I32); |
| 6205 | t_addr0 = newTemp(Ity_I32); |
| 6206 | |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 6207 | /* For the choice of the value 128, see comment in dis_bt_G_E in |
| 6208 | guest_amd64_toIR.c. We point out here only that 128 is |
| 6209 | fast-cased in Memcheck and is > 0, so seems like a good |
| 6210 | choice. */ |
| 6211 | vassert(vbi->guest_stack_redzone_size == 0); |
| 6212 | assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(128)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6213 | putIReg(4, R_ESP, mkexpr(t_esp)); |
| 6214 | |
| 6215 | storeLE( mkexpr(t_esp), getIReg(sz, eregOfRM(modrm)) ); |
| 6216 | |
| 6217 | /* Make t_addr0 point at it. */ |
| 6218 | assign( t_addr0, mkexpr(t_esp) ); |
| 6219 | |
| 6220 | /* Mask out upper bits of the shift amount, since we're doing a |
| 6221 | reg. */ |
| 6222 | assign( t_bitno1, binop(Iop_And32, |
| 6223 | mkexpr(t_bitno0), |
| 6224 | mkU32(sz == 4 ? 31 : 15)) ); |
| 6225 | |
| 6226 | } else { |
| 6227 | t_addr0 = disAMode ( &len, sorb, delta, dis_buf ); |
| 6228 | delta += len; |
| 6229 | assign( t_bitno1, mkexpr(t_bitno0) ); |
| 6230 | } |
| 6231 | |
| 6232 | /* At this point: t_addr0 is the address being operated on. If it |
| 6233 | was a reg, we will have pushed it onto the client's stack. |
| 6234 | t_bitno1 is the bit number, suitably masked in the case of a |
| 6235 | reg. */ |
| 6236 | |
| 6237 | /* Now the main sequence. */ |
| 6238 | assign( t_addr1, |
| 6239 | binop(Iop_Add32, |
| 6240 | mkexpr(t_addr0), |
| 6241 | binop(Iop_Sar32, mkexpr(t_bitno1), mkU8(3))) ); |
| 6242 | |
| 6243 | /* t_addr1 now holds effective address */ |
| 6244 | |
| 6245 | assign( t_bitno2, |
| 6246 | unop(Iop_32to8, |
| 6247 | binop(Iop_And32, mkexpr(t_bitno1), mkU32(7))) ); |
| 6248 | |
| 6249 | /* t_bitno2 contains offset of bit within byte */ |
| 6250 | |
| 6251 | if (op != BtOpNone) { |
| 6252 | t_mask = newTemp(Ity_I8); |
| 6253 | assign( t_mask, binop(Iop_Shl8, mkU8(1), mkexpr(t_bitno2)) ); |
| 6254 | } |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 6255 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6256 | /* t_mask is now a suitable byte mask */ |
| 6257 | |
| 6258 | assign( t_fetched, loadLE(Ity_I8, mkexpr(t_addr1)) ); |
| 6259 | |
| 6260 | if (op != BtOpNone) { |
| 6261 | switch (op) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6262 | case BtOpSet: |
| 6263 | assign( t_new, |
| 6264 | binop(Iop_Or8, mkexpr(t_fetched), mkexpr(t_mask)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6265 | break; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6266 | case BtOpComp: |
| 6267 | assign( t_new, |
| 6268 | binop(Iop_Xor8, mkexpr(t_fetched), mkexpr(t_mask)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6269 | break; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6270 | case BtOpReset: |
| 6271 | assign( t_new, |
| 6272 | binop(Iop_And8, mkexpr(t_fetched), |
| 6273 | unop(Iop_Not8, mkexpr(t_mask))) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6274 | break; |
| 6275 | default: |
| 6276 | vpanic("dis_bt_G_E(x86)"); |
| 6277 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6278 | if (locked && !epartIsReg(modrm)) { |
| 6279 | casLE( mkexpr(t_addr1), mkexpr(t_fetched)/*expd*/, |
| 6280 | mkexpr(t_new)/*new*/, |
| 6281 | guest_EIP_curr_instr ); |
| 6282 | } else { |
| 6283 | storeLE( mkexpr(t_addr1), mkexpr(t_new) ); |
| 6284 | } |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6285 | } |
| 6286 | |
| 6287 | /* Side effect done; now get selected bit into Carry flag */ |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6288 | /* Flags: C=selected bit, O,S,Z,A,P undefined, so are set to zero. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6289 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6290 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6291 | stmt( IRStmt_Put( |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6292 | OFFB_CC_DEP1, |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6293 | binop(Iop_And32, |
| 6294 | binop(Iop_Shr32, |
| 6295 | unop(Iop_8Uto32, mkexpr(t_fetched)), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 6296 | mkexpr(t_bitno2)), |
| 6297 | mkU32(1))) |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6298 | ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 6299 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 6300 | elimination of previous stores to this field work better. */ |
| 6301 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6302 | |
| 6303 | /* Move reg operand from stack back to reg */ |
| 6304 | if (epartIsReg(modrm)) { |
| 6305 | /* t_esp still points at it. */ |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 6306 | putIReg(sz, eregOfRM(modrm), loadLE(szToITy(sz), mkexpr(t_esp)) ); |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 6307 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(128)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6308 | } |
| 6309 | |
| 6310 | DIP("bt%s%c %s, %s\n", |
| 6311 | nameBtOp(op), nameISize(sz), nameIReg(sz, gregOfRM(modrm)), |
| 6312 | ( epartIsReg(modrm) ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ) ); |
| 6313 | |
| 6314 | return delta; |
| 6315 | } |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6316 | |
| 6317 | |
| 6318 | |
| 6319 | /* Handle BSF/BSR. Only v-size seems necessary. */ |
| 6320 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6321 | UInt dis_bs_E_G ( UChar sorb, Int sz, Int delta, Bool fwds ) |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6322 | { |
| 6323 | Bool isReg; |
| 6324 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6325 | HChar dis_buf[50]; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6326 | |
| 6327 | IRType ty = szToITy(sz); |
| 6328 | IRTemp src = newTemp(ty); |
| 6329 | IRTemp dst = newTemp(ty); |
| 6330 | |
| 6331 | IRTemp src32 = newTemp(Ity_I32); |
| 6332 | IRTemp dst32 = newTemp(Ity_I32); |
| 6333 | IRTemp src8 = newTemp(Ity_I8); |
| 6334 | |
| 6335 | vassert(sz == 4 || sz == 2); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6336 | |
| 6337 | modrm = getIByte(delta); |
| 6338 | |
| 6339 | isReg = epartIsReg(modrm); |
| 6340 | if (isReg) { |
| 6341 | delta++; |
| 6342 | assign( src, getIReg(sz, eregOfRM(modrm)) ); |
| 6343 | } else { |
| 6344 | Int len; |
| 6345 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 6346 | delta += len; |
| 6347 | assign( src, loadLE(ty, mkexpr(addr)) ); |
| 6348 | } |
| 6349 | |
| 6350 | DIP("bs%c%c %s, %s\n", |
| 6351 | fwds ? 'f' : 'r', nameISize(sz), |
| 6352 | ( isReg ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ), |
| 6353 | nameIReg(sz, gregOfRM(modrm))); |
| 6354 | |
| 6355 | /* Generate an 8-bit expression which is zero iff the |
| 6356 | original is zero, and nonzero otherwise */ |
| 6357 | assign( src8, |
| 6358 | unop(Iop_1Uto8, binop(mkSizedOp(ty,Iop_CmpNE8), |
| 6359 | mkexpr(src), mkU(ty,0))) ); |
| 6360 | |
| 6361 | /* Flags: Z is 1 iff source value is zero. All others |
| 6362 | are undefined -- we force them to zero. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6363 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6364 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6365 | stmt( IRStmt_Put( |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6366 | OFFB_CC_DEP1, |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6367 | IRExpr_Mux0X( mkexpr(src8), |
| 6368 | /* src==0 */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6369 | mkU32(X86G_CC_MASK_Z), |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6370 | /* src!=0 */ |
| 6371 | mkU32(0) |
| 6372 | ) |
| 6373 | )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 6374 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 6375 | elimination of previous stores to this field work better. */ |
| 6376 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6377 | |
| 6378 | /* Result: iff source value is zero, we can't use |
| 6379 | Iop_Clz32/Iop_Ctz32 as they have no defined result in that case. |
| 6380 | But anyway, Intel x86 semantics say the result is undefined in |
| 6381 | such situations. Hence handle the zero case specially. */ |
| 6382 | |
| 6383 | /* Bleh. What we compute: |
| 6384 | |
| 6385 | bsf32: if src == 0 then 0 else Ctz32(src) |
| 6386 | bsr32: if src == 0 then 0 else 31 - Clz32(src) |
| 6387 | |
| 6388 | bsf16: if src == 0 then 0 else Ctz32(16Uto32(src)) |
| 6389 | bsr16: if src == 0 then 0 else 31 - Clz32(16Uto32(src)) |
| 6390 | |
| 6391 | First, widen src to 32 bits if it is not already. |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 6392 | |
| 6393 | Postscript 15 Oct 04: it seems that at least VIA Nehemiah leaves the |
| 6394 | dst register unchanged when src == 0. Hence change accordingly. |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6395 | */ |
| 6396 | if (sz == 2) |
| 6397 | assign( src32, unop(Iop_16Uto32, mkexpr(src)) ); |
| 6398 | else |
| 6399 | assign( src32, mkexpr(src) ); |
| 6400 | |
| 6401 | /* The main computation, guarding against zero. */ |
| 6402 | assign( dst32, |
| 6403 | IRExpr_Mux0X( |
| 6404 | mkexpr(src8), |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 6405 | /* src == 0 -- leave dst unchanged */ |
| 6406 | widenUto32( getIReg( sz, gregOfRM(modrm) ) ), |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6407 | /* src != 0 */ |
| 6408 | fwds ? unop(Iop_Ctz32, mkexpr(src32)) |
| 6409 | : binop(Iop_Sub32, |
| 6410 | mkU32(31), |
| 6411 | unop(Iop_Clz32, mkexpr(src32))) |
| 6412 | ) |
| 6413 | ); |
| 6414 | |
| 6415 | if (sz == 2) |
| 6416 | assign( dst, unop(Iop_32to16, mkexpr(dst32)) ); |
| 6417 | else |
| 6418 | assign( dst, mkexpr(dst32) ); |
| 6419 | |
| 6420 | /* dump result back */ |
| 6421 | putIReg( sz, gregOfRM(modrm), mkexpr(dst) ); |
| 6422 | |
| 6423 | return delta; |
| 6424 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 6425 | |
| 6426 | |
| 6427 | static |
| 6428 | void codegen_xchg_eAX_Reg ( Int sz, Int reg ) |
| 6429 | { |
| 6430 | IRType ty = szToITy(sz); |
| 6431 | IRTemp t1 = newTemp(ty); |
| 6432 | IRTemp t2 = newTemp(ty); |
| 6433 | vassert(sz == 2 || sz == 4); |
| 6434 | assign( t1, getIReg(sz, R_EAX) ); |
| 6435 | assign( t2, getIReg(sz, reg) ); |
| 6436 | putIReg( sz, R_EAX, mkexpr(t2) ); |
| 6437 | putIReg( sz, reg, mkexpr(t1) ); |
| 6438 | DIP("xchg%c %s, %s\n", |
| 6439 | nameISize(sz), nameIReg(sz, R_EAX), nameIReg(sz, reg)); |
| 6440 | } |
| 6441 | |
| 6442 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6443 | static |
| 6444 | void codegen_SAHF ( void ) |
| 6445 | { |
| 6446 | /* Set the flags to: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6447 | (x86g_calculate_flags_all() & X86G_CC_MASK_O) -- retain the old O flag |
| 6448 | | (%AH & (X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A |
| 6449 | |X86G_CC_MASK_P|X86G_CC_MASK_C) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6450 | */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6451 | UInt mask_SZACP = X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A |
| 6452 | |X86G_CC_MASK_C|X86G_CC_MASK_P; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6453 | IRTemp oldflags = newTemp(Ity_I32); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6454 | assign( oldflags, mk_x86g_calculate_eflags_all() ); |
| 6455 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 905edbd | 2007-04-07 12:25:37 +0000 | [diff] [blame] | 6456 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6457 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 6458 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6459 | binop(Iop_Or32, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6460 | binop(Iop_And32, mkexpr(oldflags), mkU32(X86G_CC_MASK_O)), |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6461 | binop(Iop_And32, |
| 6462 | binop(Iop_Shr32, getIReg(4, R_EAX), mkU8(8)), |
| 6463 | mkU32(mask_SZACP)) |
| 6464 | ) |
| 6465 | )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 6466 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 6467 | elimination of previous stores to this field work better. */ |
| 6468 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6469 | } |
| 6470 | |
| 6471 | |
sewardj | 8dfdc8a | 2005-10-03 11:39:02 +0000 | [diff] [blame] | 6472 | static |
| 6473 | void codegen_LAHF ( void ) |
| 6474 | { |
| 6475 | /* AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF) */ |
| 6476 | IRExpr* eax_with_hole; |
| 6477 | IRExpr* new_byte; |
| 6478 | IRExpr* new_eax; |
| 6479 | UInt mask_SZACP = X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A |
| 6480 | |X86G_CC_MASK_C|X86G_CC_MASK_P; |
| 6481 | |
| 6482 | IRTemp flags = newTemp(Ity_I32); |
| 6483 | assign( flags, mk_x86g_calculate_eflags_all() ); |
| 6484 | |
| 6485 | eax_with_hole |
| 6486 | = binop(Iop_And32, getIReg(4, R_EAX), mkU32(0xFFFF00FF)); |
| 6487 | new_byte |
| 6488 | = binop(Iop_Or32, binop(Iop_And32, mkexpr(flags), mkU32(mask_SZACP)), |
| 6489 | mkU32(1<<1)); |
| 6490 | new_eax |
| 6491 | = binop(Iop_Or32, eax_with_hole, |
| 6492 | binop(Iop_Shl32, new_byte, mkU8(8))); |
| 6493 | putIReg(4, R_EAX, new_eax); |
| 6494 | } |
| 6495 | |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6496 | |
| 6497 | static |
| 6498 | UInt dis_cmpxchg_G_E ( UChar sorb, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6499 | Bool locked, |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6500 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6501 | Int delta0 ) |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6502 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6503 | HChar dis_buf[50]; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6504 | Int len; |
| 6505 | |
| 6506 | IRType ty = szToITy(size); |
| 6507 | IRTemp acc = newTemp(ty); |
| 6508 | IRTemp src = newTemp(ty); |
| 6509 | IRTemp dest = newTemp(ty); |
| 6510 | IRTemp dest2 = newTemp(ty); |
| 6511 | IRTemp acc2 = newTemp(ty); |
| 6512 | IRTemp cond8 = newTemp(Ity_I8); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 6513 | IRTemp addr = IRTemp_INVALID; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6514 | UChar rm = getUChar(delta0); |
| 6515 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6516 | /* There are 3 cases to consider: |
| 6517 | |
| 6518 | reg-reg: ignore any lock prefix, generate sequence based |
| 6519 | on Mux0X |
| 6520 | |
| 6521 | reg-mem, not locked: ignore any lock prefix, generate sequence |
| 6522 | based on Mux0X |
| 6523 | |
| 6524 | reg-mem, locked: use IRCAS |
| 6525 | */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6526 | if (epartIsReg(rm)) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6527 | /* case 1 */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6528 | assign( dest, getIReg(size, eregOfRM(rm)) ); |
| 6529 | delta0++; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6530 | assign( src, getIReg(size, gregOfRM(rm)) ); |
| 6531 | assign( acc, getIReg(size, R_EAX) ); |
| 6532 | setFlags_DEP1_DEP2(Iop_Sub8, acc, dest, ty); |
| 6533 | assign( cond8, unop(Iop_1Uto8, mk_x86g_calculate_condition(X86CondZ)) ); |
| 6534 | assign( dest2, IRExpr_Mux0X(mkexpr(cond8), mkexpr(dest), mkexpr(src)) ); |
| 6535 | assign( acc2, IRExpr_Mux0X(mkexpr(cond8), mkexpr(dest), mkexpr(acc)) ); |
| 6536 | putIReg(size, R_EAX, mkexpr(acc2)); |
| 6537 | putIReg(size, eregOfRM(rm), mkexpr(dest2)); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6538 | DIP("cmpxchg%c %s,%s\n", nameISize(size), |
| 6539 | nameIReg(size,gregOfRM(rm)), |
| 6540 | nameIReg(size,eregOfRM(rm)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6541 | } |
| 6542 | else if (!epartIsReg(rm) && !locked) { |
| 6543 | /* case 2 */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6544 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6545 | assign( dest, loadLE(ty, mkexpr(addr)) ); |
| 6546 | delta0 += len; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6547 | assign( src, getIReg(size, gregOfRM(rm)) ); |
| 6548 | assign( acc, getIReg(size, R_EAX) ); |
| 6549 | setFlags_DEP1_DEP2(Iop_Sub8, acc, dest, ty); |
| 6550 | assign( cond8, unop(Iop_1Uto8, mk_x86g_calculate_condition(X86CondZ)) ); |
| 6551 | assign( dest2, IRExpr_Mux0X(mkexpr(cond8), mkexpr(dest), mkexpr(src)) ); |
| 6552 | assign( acc2, IRExpr_Mux0X(mkexpr(cond8), mkexpr(dest), mkexpr(acc)) ); |
| 6553 | putIReg(size, R_EAX, mkexpr(acc2)); |
| 6554 | storeLE( mkexpr(addr), mkexpr(dest2) ); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6555 | DIP("cmpxchg%c %s,%s\n", nameISize(size), |
| 6556 | nameIReg(size,gregOfRM(rm)), dis_buf); |
| 6557 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6558 | else if (!epartIsReg(rm) && locked) { |
| 6559 | /* case 3 */ |
| 6560 | /* src is new value. acc is expected value. dest is old value. |
| 6561 | Compute success from the output of the IRCAS, and steer the |
| 6562 | new value for EAX accordingly: in case of success, EAX is |
| 6563 | unchanged. */ |
| 6564 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6565 | delta0 += len; |
| 6566 | assign( src, getIReg(size, gregOfRM(rm)) ); |
| 6567 | assign( acc, getIReg(size, R_EAX) ); |
| 6568 | stmt( IRStmt_CAS( |
| 6569 | mkIRCAS( IRTemp_INVALID, dest, Iend_LE, mkexpr(addr), |
| 6570 | NULL, mkexpr(acc), NULL, mkexpr(src) ) |
| 6571 | )); |
| 6572 | setFlags_DEP1_DEP2(Iop_Sub8, acc, dest, ty); |
| 6573 | assign( cond8, unop(Iop_1Uto8, mk_x86g_calculate_condition(X86CondZ)) ); |
| 6574 | assign( acc2, IRExpr_Mux0X(mkexpr(cond8), mkexpr(dest), mkexpr(acc)) ); |
| 6575 | putIReg(size, R_EAX, mkexpr(acc2)); |
sewardj | 40d1d21 | 2009-07-12 13:01:17 +0000 | [diff] [blame] | 6576 | DIP("cmpxchg%c %s,%s\n", nameISize(size), |
| 6577 | nameIReg(size,gregOfRM(rm)), dis_buf); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6578 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6579 | else vassert(0); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6580 | |
| 6581 | return delta0; |
| 6582 | } |
| 6583 | |
| 6584 | |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6585 | /* Handle conditional move instructions of the form |
| 6586 | cmovcc E(reg-or-mem), G(reg) |
| 6587 | |
| 6588 | E(src) is reg-or-mem |
| 6589 | G(dst) is reg. |
| 6590 | |
| 6591 | If E is reg, --> GET %E, tmps |
| 6592 | GET %G, tmpd |
| 6593 | CMOVcc tmps, tmpd |
| 6594 | PUT tmpd, %G |
| 6595 | |
| 6596 | If E is mem --> (getAddr E) -> tmpa |
| 6597 | LD (tmpa), tmps |
| 6598 | GET %G, tmpd |
| 6599 | CMOVcc tmps, tmpd |
| 6600 | PUT tmpd, %G |
| 6601 | */ |
| 6602 | static |
| 6603 | UInt dis_cmov_E_G ( UChar sorb, |
| 6604 | Int sz, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6605 | X86Condcode cond, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6606 | Int delta0 ) |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6607 | { |
| 6608 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6609 | HChar dis_buf[50]; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6610 | Int len; |
| 6611 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6612 | IRType ty = szToITy(sz); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6613 | IRTemp tmps = newTemp(ty); |
| 6614 | IRTemp tmpd = newTemp(ty); |
| 6615 | |
| 6616 | if (epartIsReg(rm)) { |
| 6617 | assign( tmps, getIReg(sz, eregOfRM(rm)) ); |
| 6618 | assign( tmpd, getIReg(sz, gregOfRM(rm)) ); |
| 6619 | |
| 6620 | putIReg(sz, gregOfRM(rm), |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6621 | IRExpr_Mux0X( unop(Iop_1Uto8, |
| 6622 | mk_x86g_calculate_condition(cond)), |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6623 | mkexpr(tmpd), |
| 6624 | mkexpr(tmps) ) |
| 6625 | ); |
| 6626 | DIP("cmov%c%s %s,%s\n", nameISize(sz), |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6627 | name_X86Condcode(cond), |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6628 | nameIReg(sz,eregOfRM(rm)), |
| 6629 | nameIReg(sz,gregOfRM(rm))); |
| 6630 | return 1+delta0; |
| 6631 | } |
| 6632 | |
| 6633 | /* E refers to memory */ |
| 6634 | { |
| 6635 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6636 | assign( tmps, loadLE(ty, mkexpr(addr)) ); |
| 6637 | assign( tmpd, getIReg(sz, gregOfRM(rm)) ); |
| 6638 | |
| 6639 | putIReg(sz, gregOfRM(rm), |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6640 | IRExpr_Mux0X( unop(Iop_1Uto8, |
| 6641 | mk_x86g_calculate_condition(cond)), |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6642 | mkexpr(tmpd), |
| 6643 | mkexpr(tmps) ) |
| 6644 | ); |
| 6645 | |
| 6646 | DIP("cmov%c%s %s,%s\n", nameISize(sz), |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6647 | name_X86Condcode(cond), |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6648 | dis_buf, |
| 6649 | nameIReg(sz,gregOfRM(rm))); |
| 6650 | return len+delta0; |
| 6651 | } |
| 6652 | } |
| 6653 | |
| 6654 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6655 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6656 | UInt dis_xadd_G_E ( UChar sorb, Bool locked, Int sz, Int delta0, |
| 6657 | Bool* decodeOK ) |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6658 | { |
| 6659 | Int len; |
| 6660 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6661 | HChar dis_buf[50]; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6662 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6663 | IRType ty = szToITy(sz); |
| 6664 | IRTemp tmpd = newTemp(ty); |
| 6665 | IRTemp tmpt0 = newTemp(ty); |
| 6666 | IRTemp tmpt1 = newTemp(ty); |
| 6667 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6668 | /* There are 3 cases to consider: |
| 6669 | |
sewardj | c2433a8 | 2010-05-10 20:51:22 +0000 | [diff] [blame] | 6670 | reg-reg: ignore any lock prefix, |
| 6671 | generate 'naive' (non-atomic) sequence |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6672 | |
| 6673 | reg-mem, not locked: ignore any lock prefix, generate 'naive' |
| 6674 | (non-atomic) sequence |
| 6675 | |
| 6676 | reg-mem, locked: use IRCAS |
| 6677 | */ |
| 6678 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6679 | if (epartIsReg(rm)) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6680 | /* case 1 */ |
sewardj | c2433a8 | 2010-05-10 20:51:22 +0000 | [diff] [blame] | 6681 | assign( tmpd, getIReg(sz, eregOfRM(rm))); |
| 6682 | assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); |
| 6683 | assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), |
| 6684 | mkexpr(tmpd), mkexpr(tmpt0)) ); |
| 6685 | setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); |
| 6686 | putIReg(sz, eregOfRM(rm), mkexpr(tmpt1)); |
| 6687 | putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); |
| 6688 | DIP("xadd%c %s, %s\n", |
| 6689 | nameISize(sz), nameIReg(sz,gregOfRM(rm)), |
| 6690 | nameIReg(sz,eregOfRM(rm))); |
| 6691 | *decodeOK = True; |
| 6692 | return 1+delta0; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6693 | } |
| 6694 | else if (!epartIsReg(rm) && !locked) { |
| 6695 | /* case 2 */ |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6696 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6697 | assign( tmpd, loadLE(ty, mkexpr(addr)) ); |
| 6698 | assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6699 | assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), |
| 6700 | mkexpr(tmpd), mkexpr(tmpt0)) ); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6701 | storeLE( mkexpr(addr), mkexpr(tmpt1) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6702 | setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6703 | putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); |
| 6704 | DIP("xadd%c %s, %s\n", |
| 6705 | nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf); |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 6706 | *decodeOK = True; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6707 | return len+delta0; |
| 6708 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6709 | else if (!epartIsReg(rm) && locked) { |
| 6710 | /* case 3 */ |
| 6711 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6712 | assign( tmpd, loadLE(ty, mkexpr(addr)) ); |
| 6713 | assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); |
| 6714 | assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), |
| 6715 | mkexpr(tmpd), mkexpr(tmpt0)) ); |
| 6716 | casLE( mkexpr(addr), mkexpr(tmpd)/*expVal*/, |
| 6717 | mkexpr(tmpt1)/*newVal*/, guest_EIP_curr_instr ); |
| 6718 | setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); |
| 6719 | putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); |
| 6720 | DIP("xadd%c %s, %s\n", |
| 6721 | nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf); |
| 6722 | *decodeOK = True; |
| 6723 | return len+delta0; |
| 6724 | } |
| 6725 | /*UNREACHED*/ |
| 6726 | vassert(0); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6727 | } |
| 6728 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6729 | /* Move 16 bits from Ew (ireg or mem) to G (a segment register). */ |
| 6730 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6731 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6732 | UInt dis_mov_Ew_Sw ( UChar sorb, Int delta0 ) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6733 | { |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6734 | Int len; |
| 6735 | IRTemp addr; |
| 6736 | UChar rm = getIByte(delta0); |
| 6737 | HChar dis_buf[50]; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6738 | |
| 6739 | if (epartIsReg(rm)) { |
| 6740 | putSReg( gregOfRM(rm), getIReg(2, eregOfRM(rm)) ); |
| 6741 | DIP("movw %s,%s\n", nameIReg(2,eregOfRM(rm)), nameSReg(gregOfRM(rm))); |
| 6742 | return 1+delta0; |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6743 | } else { |
| 6744 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6745 | putSReg( gregOfRM(rm), loadLE(Ity_I16, mkexpr(addr)) ); |
| 6746 | DIP("movw %s,%s\n", dis_buf, nameSReg(gregOfRM(rm))); |
| 6747 | return len+delta0; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6748 | } |
| 6749 | } |
| 6750 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6751 | /* Move 16 bits from G (a segment register) to Ew (ireg or mem). If |
| 6752 | dst is ireg and sz==4, zero out top half of it. */ |
| 6753 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6754 | static |
| 6755 | UInt dis_mov_Sw_Ew ( UChar sorb, |
| 6756 | Int sz, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6757 | Int delta0 ) |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6758 | { |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6759 | Int len; |
| 6760 | IRTemp addr; |
| 6761 | UChar rm = getIByte(delta0); |
| 6762 | HChar dis_buf[50]; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6763 | |
| 6764 | vassert(sz == 2 || sz == 4); |
| 6765 | |
| 6766 | if (epartIsReg(rm)) { |
| 6767 | if (sz == 4) |
| 6768 | putIReg(4, eregOfRM(rm), unop(Iop_16Uto32, getSReg(gregOfRM(rm)))); |
| 6769 | else |
| 6770 | putIReg(2, eregOfRM(rm), getSReg(gregOfRM(rm))); |
| 6771 | |
| 6772 | DIP("mov %s,%s\n", nameSReg(gregOfRM(rm)), nameIReg(sz,eregOfRM(rm))); |
| 6773 | return 1+delta0; |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6774 | } else { |
| 6775 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6776 | storeLE( mkexpr(addr), getSReg(gregOfRM(rm)) ); |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6777 | DIP("mov %s,%s\n", nameSReg(gregOfRM(rm)), dis_buf); |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6778 | return len+delta0; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6779 | } |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6780 | } |
| 6781 | |
| 6782 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6783 | static |
| 6784 | void dis_push_segreg ( UInt sreg, Int sz ) |
| 6785 | { |
| 6786 | IRTemp t1 = newTemp(Ity_I16); |
| 6787 | IRTemp ta = newTemp(Ity_I32); |
| 6788 | vassert(sz == 2 || sz == 4); |
| 6789 | |
| 6790 | assign( t1, getSReg(sreg) ); |
| 6791 | assign( ta, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz)) ); |
| 6792 | putIReg(4, R_ESP, mkexpr(ta)); |
| 6793 | storeLE( mkexpr(ta), mkexpr(t1) ); |
| 6794 | |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 6795 | DIP("push%c %s\n", sz==2 ? 'w' : 'l', nameSReg(sreg)); |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6796 | } |
| 6797 | |
| 6798 | static |
| 6799 | void dis_pop_segreg ( UInt sreg, Int sz ) |
| 6800 | { |
| 6801 | IRTemp t1 = newTemp(Ity_I16); |
| 6802 | IRTemp ta = newTemp(Ity_I32); |
| 6803 | vassert(sz == 2 || sz == 4); |
| 6804 | |
| 6805 | assign( ta, getIReg(4, R_ESP) ); |
| 6806 | assign( t1, loadLE(Ity_I16, mkexpr(ta)) ); |
| 6807 | |
| 6808 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(ta), mkU32(sz)) ); |
| 6809 | putSReg( sreg, mkexpr(t1) ); |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 6810 | DIP("pop%c %s\n", sz==2 ? 'w' : 'l', nameSReg(sreg)); |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6811 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 6812 | |
| 6813 | static |
| 6814 | void dis_ret ( UInt d32 ) |
| 6815 | { |
| 6816 | IRTemp t1 = newTemp(Ity_I32), t2 = newTemp(Ity_I32); |
| 6817 | assign(t1, getIReg(4,R_ESP)); |
| 6818 | assign(t2, loadLE(Ity_I32,mkexpr(t1))); |
| 6819 | putIReg(4, R_ESP,binop(Iop_Add32, mkexpr(t1), mkU32(4+d32))); |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 6820 | jmp_treg(Ijk_Ret,t2); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 6821 | } |
| 6822 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 6823 | /*------------------------------------------------------------*/ |
| 6824 | /*--- SSE/SSE2/SSE3 helpers ---*/ |
| 6825 | /*------------------------------------------------------------*/ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6826 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6827 | /* Worker function; do not call directly. |
| 6828 | Handles full width G = G `op` E and G = (not G) `op` E. |
| 6829 | */ |
| 6830 | |
| 6831 | static UInt dis_SSE_E_to_G_all_wrk ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6832 | UChar sorb, Int delta, |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6833 | HChar* opname, IROp op, |
| 6834 | Bool invertG |
| 6835 | ) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6836 | { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6837 | HChar dis_buf[50]; |
| 6838 | Int alen; |
| 6839 | IRTemp addr; |
| 6840 | UChar rm = getIByte(delta); |
| 6841 | IRExpr* gpart |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 6842 | = invertG ? unop(Iop_NotV128, getXMMReg(gregOfRM(rm))) |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6843 | : getXMMReg(gregOfRM(rm)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6844 | if (epartIsReg(rm)) { |
| 6845 | putXMMReg( gregOfRM(rm), |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6846 | binop(op, gpart, |
| 6847 | getXMMReg(eregOfRM(rm))) ); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6848 | DIP("%s %s,%s\n", opname, |
| 6849 | nameXMMReg(eregOfRM(rm)), |
| 6850 | nameXMMReg(gregOfRM(rm)) ); |
| 6851 | return delta+1; |
| 6852 | } else { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6853 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 6854 | putXMMReg( gregOfRM(rm), |
| 6855 | binop(op, gpart, |
| 6856 | loadLE(Ity_V128, mkexpr(addr))) ); |
| 6857 | DIP("%s %s,%s\n", opname, |
| 6858 | dis_buf, |
| 6859 | nameXMMReg(gregOfRM(rm)) ); |
| 6860 | return delta+alen; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6861 | } |
| 6862 | } |
| 6863 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6864 | |
| 6865 | /* All lanes SSE binary operation, G = G `op` E. */ |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6866 | |
| 6867 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6868 | UInt dis_SSE_E_to_G_all ( UChar sorb, Int delta, HChar* opname, IROp op ) |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6869 | { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6870 | return dis_SSE_E_to_G_all_wrk( sorb, delta, opname, op, False ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6871 | } |
| 6872 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6873 | /* All lanes SSE binary operation, G = (not G) `op` E. */ |
| 6874 | |
| 6875 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6876 | UInt dis_SSE_E_to_G_all_invG ( UChar sorb, Int delta, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6877 | HChar* opname, IROp op ) |
| 6878 | { |
| 6879 | return dis_SSE_E_to_G_all_wrk( sorb, delta, opname, op, True ); |
| 6880 | } |
| 6881 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 6882 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6883 | /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */ |
| 6884 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6885 | static UInt dis_SSE_E_to_G_lo32 ( UChar sorb, Int delta, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6886 | HChar* opname, IROp op ) |
| 6887 | { |
| 6888 | HChar dis_buf[50]; |
| 6889 | Int alen; |
| 6890 | IRTemp addr; |
| 6891 | UChar rm = getIByte(delta); |
| 6892 | IRExpr* gpart = getXMMReg(gregOfRM(rm)); |
| 6893 | if (epartIsReg(rm)) { |
| 6894 | putXMMReg( gregOfRM(rm), |
| 6895 | binop(op, gpart, |
| 6896 | getXMMReg(eregOfRM(rm))) ); |
| 6897 | DIP("%s %s,%s\n", opname, |
| 6898 | nameXMMReg(eregOfRM(rm)), |
| 6899 | nameXMMReg(gregOfRM(rm)) ); |
| 6900 | return delta+1; |
| 6901 | } else { |
| 6902 | /* We can only do a 32-bit memory read, so the upper 3/4 of the |
| 6903 | E operand needs to be made simply of zeroes. */ |
| 6904 | IRTemp epart = newTemp(Ity_V128); |
| 6905 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 6906 | assign( epart, unop( Iop_32UtoV128, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6907 | loadLE(Ity_I32, mkexpr(addr))) ); |
| 6908 | putXMMReg( gregOfRM(rm), |
| 6909 | binop(op, gpart, mkexpr(epart)) ); |
| 6910 | DIP("%s %s,%s\n", opname, |
| 6911 | dis_buf, |
| 6912 | nameXMMReg(gregOfRM(rm)) ); |
| 6913 | return delta+alen; |
| 6914 | } |
| 6915 | } |
| 6916 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 6917 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 6918 | /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */ |
| 6919 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6920 | static UInt dis_SSE_E_to_G_lo64 ( UChar sorb, Int delta, |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 6921 | HChar* opname, IROp op ) |
| 6922 | { |
| 6923 | HChar dis_buf[50]; |
| 6924 | Int alen; |
| 6925 | IRTemp addr; |
| 6926 | UChar rm = getIByte(delta); |
| 6927 | IRExpr* gpart = getXMMReg(gregOfRM(rm)); |
| 6928 | if (epartIsReg(rm)) { |
| 6929 | putXMMReg( gregOfRM(rm), |
| 6930 | binop(op, gpart, |
| 6931 | getXMMReg(eregOfRM(rm))) ); |
| 6932 | DIP("%s %s,%s\n", opname, |
| 6933 | nameXMMReg(eregOfRM(rm)), |
| 6934 | nameXMMReg(gregOfRM(rm)) ); |
| 6935 | return delta+1; |
| 6936 | } else { |
| 6937 | /* We can only do a 64-bit memory read, so the upper half of the |
| 6938 | E operand needs to be made simply of zeroes. */ |
| 6939 | IRTemp epart = newTemp(Ity_V128); |
| 6940 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 6941 | assign( epart, unop( Iop_64UtoV128, |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 6942 | loadLE(Ity_I64, mkexpr(addr))) ); |
| 6943 | putXMMReg( gregOfRM(rm), |
| 6944 | binop(op, gpart, mkexpr(epart)) ); |
| 6945 | DIP("%s %s,%s\n", opname, |
| 6946 | dis_buf, |
| 6947 | nameXMMReg(gregOfRM(rm)) ); |
| 6948 | return delta+alen; |
| 6949 | } |
| 6950 | } |
| 6951 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 6952 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6953 | /* All lanes unary SSE operation, G = op(E). */ |
| 6954 | |
| 6955 | static UInt dis_SSE_E_to_G_unary_all ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6956 | UChar sorb, Int delta, |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 6957 | HChar* opname, IROp op |
| 6958 | ) |
| 6959 | { |
| 6960 | HChar dis_buf[50]; |
| 6961 | Int alen; |
| 6962 | IRTemp addr; |
| 6963 | UChar rm = getIByte(delta); |
| 6964 | if (epartIsReg(rm)) { |
| 6965 | putXMMReg( gregOfRM(rm), |
| 6966 | unop(op, getXMMReg(eregOfRM(rm))) ); |
| 6967 | DIP("%s %s,%s\n", opname, |
| 6968 | nameXMMReg(eregOfRM(rm)), |
| 6969 | nameXMMReg(gregOfRM(rm)) ); |
| 6970 | return delta+1; |
| 6971 | } else { |
| 6972 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 6973 | putXMMReg( gregOfRM(rm), |
| 6974 | unop(op, loadLE(Ity_V128, mkexpr(addr))) ); |
| 6975 | DIP("%s %s,%s\n", opname, |
| 6976 | dis_buf, |
| 6977 | nameXMMReg(gregOfRM(rm)) ); |
| 6978 | return delta+alen; |
| 6979 | } |
| 6980 | } |
| 6981 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 6982 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6983 | /* Lowest 32-bit lane only unary SSE operation, G = op(E). */ |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 6984 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6985 | static UInt dis_SSE_E_to_G_unary_lo32 ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6986 | UChar sorb, Int delta, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6987 | HChar* opname, IROp op |
| 6988 | ) |
| 6989 | { |
| 6990 | /* First we need to get the old G value and patch the low 32 bits |
| 6991 | of the E operand into it. Then apply op and write back to G. */ |
| 6992 | HChar dis_buf[50]; |
| 6993 | Int alen; |
| 6994 | IRTemp addr; |
| 6995 | UChar rm = getIByte(delta); |
| 6996 | IRTemp oldG0 = newTemp(Ity_V128); |
| 6997 | IRTemp oldG1 = newTemp(Ity_V128); |
| 6998 | |
| 6999 | assign( oldG0, getXMMReg(gregOfRM(rm)) ); |
| 7000 | |
| 7001 | if (epartIsReg(rm)) { |
| 7002 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7003 | binop( Iop_SetV128lo32, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7004 | mkexpr(oldG0), |
sewardj | 35579be | 2004-12-06 00:36:25 +0000 | [diff] [blame] | 7005 | getXMMRegLane32(eregOfRM(rm), 0)) ); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7006 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7007 | DIP("%s %s,%s\n", opname, |
| 7008 | nameXMMReg(eregOfRM(rm)), |
| 7009 | nameXMMReg(gregOfRM(rm)) ); |
| 7010 | return delta+1; |
| 7011 | } else { |
| 7012 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7013 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7014 | binop( Iop_SetV128lo32, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7015 | mkexpr(oldG0), |
| 7016 | loadLE(Ity_I32, mkexpr(addr)) )); |
| 7017 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7018 | DIP("%s %s,%s\n", opname, |
| 7019 | dis_buf, |
| 7020 | nameXMMReg(gregOfRM(rm)) ); |
| 7021 | return delta+alen; |
| 7022 | } |
| 7023 | } |
| 7024 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7025 | |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7026 | /* Lowest 64-bit lane only unary SSE operation, G = op(E). */ |
| 7027 | |
| 7028 | static UInt dis_SSE_E_to_G_unary_lo64 ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7029 | UChar sorb, Int delta, |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7030 | HChar* opname, IROp op |
| 7031 | ) |
| 7032 | { |
| 7033 | /* First we need to get the old G value and patch the low 64 bits |
| 7034 | of the E operand into it. Then apply op and write back to G. */ |
| 7035 | HChar dis_buf[50]; |
| 7036 | Int alen; |
| 7037 | IRTemp addr; |
| 7038 | UChar rm = getIByte(delta); |
| 7039 | IRTemp oldG0 = newTemp(Ity_V128); |
| 7040 | IRTemp oldG1 = newTemp(Ity_V128); |
| 7041 | |
| 7042 | assign( oldG0, getXMMReg(gregOfRM(rm)) ); |
| 7043 | |
| 7044 | if (epartIsReg(rm)) { |
| 7045 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7046 | binop( Iop_SetV128lo64, |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7047 | mkexpr(oldG0), |
| 7048 | getXMMRegLane64(eregOfRM(rm), 0)) ); |
| 7049 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7050 | DIP("%s %s,%s\n", opname, |
| 7051 | nameXMMReg(eregOfRM(rm)), |
| 7052 | nameXMMReg(gregOfRM(rm)) ); |
| 7053 | return delta+1; |
| 7054 | } else { |
| 7055 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7056 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7057 | binop( Iop_SetV128lo64, |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7058 | mkexpr(oldG0), |
| 7059 | loadLE(Ity_I64, mkexpr(addr)) )); |
| 7060 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7061 | DIP("%s %s,%s\n", opname, |
| 7062 | dis_buf, |
| 7063 | nameXMMReg(gregOfRM(rm)) ); |
| 7064 | return delta+alen; |
| 7065 | } |
| 7066 | } |
| 7067 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7068 | |
| 7069 | /* SSE integer binary operation: |
| 7070 | G = G `op` E (eLeft == False) |
| 7071 | G = E `op` G (eLeft == True) |
| 7072 | */ |
| 7073 | static UInt dis_SSEint_E_to_G( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7074 | UChar sorb, Int delta, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7075 | HChar* opname, IROp op, |
| 7076 | Bool eLeft |
| 7077 | ) |
| 7078 | { |
| 7079 | HChar dis_buf[50]; |
| 7080 | Int alen; |
| 7081 | IRTemp addr; |
| 7082 | UChar rm = getIByte(delta); |
| 7083 | IRExpr* gpart = getXMMReg(gregOfRM(rm)); |
| 7084 | IRExpr* epart = NULL; |
| 7085 | if (epartIsReg(rm)) { |
| 7086 | epart = getXMMReg(eregOfRM(rm)); |
| 7087 | DIP("%s %s,%s\n", opname, |
| 7088 | nameXMMReg(eregOfRM(rm)), |
| 7089 | nameXMMReg(gregOfRM(rm)) ); |
| 7090 | delta += 1; |
| 7091 | } else { |
| 7092 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7093 | epart = loadLE(Ity_V128, mkexpr(addr)); |
| 7094 | DIP("%s %s,%s\n", opname, |
| 7095 | dis_buf, |
| 7096 | nameXMMReg(gregOfRM(rm)) ); |
| 7097 | delta += alen; |
| 7098 | } |
| 7099 | putXMMReg( gregOfRM(rm), |
| 7100 | eLeft ? binop(op, epart, gpart) |
| 7101 | : binop(op, gpart, epart) ); |
| 7102 | return delta; |
| 7103 | } |
| 7104 | |
| 7105 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 7106 | /* Helper for doing SSE FP comparisons. */ |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7107 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7108 | static void findSSECmpOp ( Bool* needNot, IROp* op, |
| 7109 | Int imm8, Bool all_lanes, Int sz ) |
| 7110 | { |
| 7111 | imm8 &= 7; |
| 7112 | *needNot = False; |
| 7113 | *op = Iop_INVALID; |
| 7114 | if (imm8 >= 4) { |
| 7115 | *needNot = True; |
| 7116 | imm8 -= 4; |
| 7117 | } |
| 7118 | |
| 7119 | if (sz == 4 && all_lanes) { |
| 7120 | switch (imm8) { |
| 7121 | case 0: *op = Iop_CmpEQ32Fx4; return; |
| 7122 | case 1: *op = Iop_CmpLT32Fx4; return; |
| 7123 | case 2: *op = Iop_CmpLE32Fx4; return; |
| 7124 | case 3: *op = Iop_CmpUN32Fx4; return; |
| 7125 | default: break; |
| 7126 | } |
| 7127 | } |
| 7128 | if (sz == 4 && !all_lanes) { |
| 7129 | switch (imm8) { |
| 7130 | case 0: *op = Iop_CmpEQ32F0x4; return; |
| 7131 | case 1: *op = Iop_CmpLT32F0x4; return; |
| 7132 | case 2: *op = Iop_CmpLE32F0x4; return; |
| 7133 | case 3: *op = Iop_CmpUN32F0x4; return; |
| 7134 | default: break; |
| 7135 | } |
| 7136 | } |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 7137 | if (sz == 8 && all_lanes) { |
| 7138 | switch (imm8) { |
| 7139 | case 0: *op = Iop_CmpEQ64Fx2; return; |
| 7140 | case 1: *op = Iop_CmpLT64Fx2; return; |
| 7141 | case 2: *op = Iop_CmpLE64Fx2; return; |
| 7142 | case 3: *op = Iop_CmpUN64Fx2; return; |
| 7143 | default: break; |
| 7144 | } |
| 7145 | } |
| 7146 | if (sz == 8 && !all_lanes) { |
| 7147 | switch (imm8) { |
| 7148 | case 0: *op = Iop_CmpEQ64F0x2; return; |
| 7149 | case 1: *op = Iop_CmpLT64F0x2; return; |
| 7150 | case 2: *op = Iop_CmpLE64F0x2; return; |
| 7151 | case 3: *op = Iop_CmpUN64F0x2; return; |
| 7152 | default: break; |
| 7153 | } |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7154 | } |
| 7155 | vpanic("findSSECmpOp(x86,guest)"); |
| 7156 | } |
| 7157 | |
sewardj | 33c69e5 | 2006-01-01 17:15:19 +0000 | [diff] [blame] | 7158 | /* Handles SSE 32F/64F comparisons. */ |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7159 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7160 | static UInt dis_SSEcmp_E_to_G ( UChar sorb, Int delta, |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7161 | HChar* opname, Bool all_lanes, Int sz ) |
| 7162 | { |
| 7163 | HChar dis_buf[50]; |
| 7164 | Int alen, imm8; |
| 7165 | IRTemp addr; |
| 7166 | Bool needNot = False; |
| 7167 | IROp op = Iop_INVALID; |
| 7168 | IRTemp plain = newTemp(Ity_V128); |
| 7169 | UChar rm = getIByte(delta); |
| 7170 | UShort mask = 0; |
| 7171 | vassert(sz == 4 || sz == 8); |
| 7172 | if (epartIsReg(rm)) { |
| 7173 | imm8 = getIByte(delta+1); |
| 7174 | findSSECmpOp(&needNot, &op, imm8, all_lanes, sz); |
| 7175 | assign( plain, binop(op, getXMMReg(gregOfRM(rm)), |
| 7176 | getXMMReg(eregOfRM(rm))) ); |
| 7177 | delta += 2; |
| 7178 | DIP("%s $%d,%s,%s\n", opname, |
| 7179 | (Int)imm8, |
| 7180 | nameXMMReg(eregOfRM(rm)), |
| 7181 | nameXMMReg(gregOfRM(rm)) ); |
| 7182 | } else { |
| 7183 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7184 | imm8 = getIByte(delta+alen); |
| 7185 | findSSECmpOp(&needNot, &op, imm8, all_lanes, sz); |
sewardj | 33c69e5 | 2006-01-01 17:15:19 +0000 | [diff] [blame] | 7186 | assign( plain, |
| 7187 | binop( |
| 7188 | op, |
| 7189 | getXMMReg(gregOfRM(rm)), |
| 7190 | all_lanes ? loadLE(Ity_V128, mkexpr(addr)) |
| 7191 | : sz == 8 ? unop( Iop_64UtoV128, loadLE(Ity_I64, mkexpr(addr))) |
| 7192 | : /*sz==4*/ unop( Iop_32UtoV128, loadLE(Ity_I32, mkexpr(addr))) |
| 7193 | ) |
| 7194 | ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7195 | delta += alen+1; |
| 7196 | DIP("%s $%d,%s,%s\n", opname, |
| 7197 | (Int)imm8, |
| 7198 | dis_buf, |
| 7199 | nameXMMReg(gregOfRM(rm)) ); |
| 7200 | } |
| 7201 | |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7202 | if (needNot && all_lanes) { |
| 7203 | putXMMReg( gregOfRM(rm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7204 | unop(Iop_NotV128, mkexpr(plain)) ); |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7205 | } |
| 7206 | else |
| 7207 | if (needNot && !all_lanes) { |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 7208 | mask = toUShort( sz==4 ? 0x000F : 0x00FF ); |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7209 | putXMMReg( gregOfRM(rm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7210 | binop(Iop_XorV128, mkexpr(plain), mkV128(mask)) ); |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7211 | } |
| 7212 | else { |
| 7213 | putXMMReg( gregOfRM(rm), mkexpr(plain) ); |
| 7214 | } |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7215 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7216 | return delta; |
| 7217 | } |
| 7218 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7219 | |
| 7220 | /* Vector by scalar shift of G by the amount specified at the bottom |
| 7221 | of E. */ |
| 7222 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7223 | static UInt dis_SSE_shiftG_byE ( UChar sorb, Int delta, |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7224 | HChar* opname, IROp op ) |
| 7225 | { |
| 7226 | HChar dis_buf[50]; |
| 7227 | Int alen, size; |
| 7228 | IRTemp addr; |
| 7229 | Bool shl, shr, sar; |
| 7230 | UChar rm = getIByte(delta); |
| 7231 | IRTemp g0 = newTemp(Ity_V128); |
| 7232 | IRTemp g1 = newTemp(Ity_V128); |
| 7233 | IRTemp amt = newTemp(Ity_I32); |
| 7234 | IRTemp amt8 = newTemp(Ity_I8); |
| 7235 | if (epartIsReg(rm)) { |
| 7236 | assign( amt, getXMMRegLane32(eregOfRM(rm), 0) ); |
| 7237 | DIP("%s %s,%s\n", opname, |
| 7238 | nameXMMReg(eregOfRM(rm)), |
| 7239 | nameXMMReg(gregOfRM(rm)) ); |
| 7240 | delta++; |
| 7241 | } else { |
| 7242 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7243 | assign( amt, loadLE(Ity_I32, mkexpr(addr)) ); |
| 7244 | DIP("%s %s,%s\n", opname, |
| 7245 | dis_buf, |
| 7246 | nameXMMReg(gregOfRM(rm)) ); |
| 7247 | delta += alen; |
| 7248 | } |
| 7249 | assign( g0, getXMMReg(gregOfRM(rm)) ); |
| 7250 | assign( amt8, unop(Iop_32to8, mkexpr(amt)) ); |
| 7251 | |
| 7252 | shl = shr = sar = False; |
| 7253 | size = 0; |
| 7254 | switch (op) { |
| 7255 | case Iop_ShlN16x8: shl = True; size = 32; break; |
| 7256 | case Iop_ShlN32x4: shl = True; size = 32; break; |
| 7257 | case Iop_ShlN64x2: shl = True; size = 64; break; |
| 7258 | case Iop_SarN16x8: sar = True; size = 16; break; |
| 7259 | case Iop_SarN32x4: sar = True; size = 32; break; |
| 7260 | case Iop_ShrN16x8: shr = True; size = 16; break; |
| 7261 | case Iop_ShrN32x4: shr = True; size = 32; break; |
| 7262 | case Iop_ShrN64x2: shr = True; size = 64; break; |
| 7263 | default: vassert(0); |
| 7264 | } |
| 7265 | |
| 7266 | if (shl || shr) { |
| 7267 | assign( |
| 7268 | g1, |
| 7269 | IRExpr_Mux0X( |
| 7270 | unop(Iop_1Uto8,binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size))), |
| 7271 | mkV128(0x0000), |
| 7272 | binop(op, mkexpr(g0), mkexpr(amt8)) |
| 7273 | ) |
| 7274 | ); |
| 7275 | } else |
| 7276 | if (sar) { |
| 7277 | assign( |
| 7278 | g1, |
| 7279 | IRExpr_Mux0X( |
| 7280 | unop(Iop_1Uto8,binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size))), |
| 7281 | binop(op, mkexpr(g0), mkU8(size-1)), |
| 7282 | binop(op, mkexpr(g0), mkexpr(amt8)) |
| 7283 | ) |
| 7284 | ); |
| 7285 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7286 | /*NOTREACHED*/ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7287 | vassert(0); |
| 7288 | } |
| 7289 | |
| 7290 | putXMMReg( gregOfRM(rm), mkexpr(g1) ); |
| 7291 | return delta; |
| 7292 | } |
| 7293 | |
| 7294 | |
| 7295 | /* Vector by scalar shift of E by an immediate byte. */ |
| 7296 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7297 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7298 | UInt dis_SSE_shiftE_imm ( Int delta, HChar* opname, IROp op ) |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7299 | { |
| 7300 | Bool shl, shr, sar; |
| 7301 | UChar rm = getIByte(delta); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7302 | IRTemp e0 = newTemp(Ity_V128); |
| 7303 | IRTemp e1 = newTemp(Ity_V128); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7304 | UChar amt, size; |
| 7305 | vassert(epartIsReg(rm)); |
| 7306 | vassert(gregOfRM(rm) == 2 |
| 7307 | || gregOfRM(rm) == 4 || gregOfRM(rm) == 6); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 7308 | amt = getIByte(delta+1); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7309 | delta += 2; |
| 7310 | DIP("%s $%d,%s\n", opname, |
| 7311 | (Int)amt, |
| 7312 | nameXMMReg(eregOfRM(rm)) ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7313 | assign( e0, getXMMReg(eregOfRM(rm)) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7314 | |
| 7315 | shl = shr = sar = False; |
| 7316 | size = 0; |
| 7317 | switch (op) { |
| 7318 | case Iop_ShlN16x8: shl = True; size = 16; break; |
| 7319 | case Iop_ShlN32x4: shl = True; size = 32; break; |
| 7320 | case Iop_ShlN64x2: shl = True; size = 64; break; |
| 7321 | case Iop_SarN16x8: sar = True; size = 16; break; |
| 7322 | case Iop_SarN32x4: sar = True; size = 32; break; |
| 7323 | case Iop_ShrN16x8: shr = True; size = 16; break; |
| 7324 | case Iop_ShrN32x4: shr = True; size = 32; break; |
| 7325 | case Iop_ShrN64x2: shr = True; size = 64; break; |
| 7326 | default: vassert(0); |
| 7327 | } |
| 7328 | |
| 7329 | if (shl || shr) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7330 | assign( e1, amt >= size |
| 7331 | ? mkV128(0x0000) |
| 7332 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 7333 | ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7334 | } else |
| 7335 | if (sar) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7336 | assign( e1, amt >= size |
| 7337 | ? binop(op, mkexpr(e0), mkU8(size-1)) |
| 7338 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 7339 | ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7340 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7341 | /*NOTREACHED*/ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7342 | vassert(0); |
| 7343 | } |
| 7344 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7345 | putXMMReg( eregOfRM(rm), mkexpr(e1) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7346 | return delta; |
| 7347 | } |
| 7348 | |
| 7349 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7350 | /* Get the current SSE rounding mode. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7351 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 7352 | static IRExpr* /* :: Ity_I32 */ get_sse_roundingmode ( void ) |
| 7353 | { |
| 7354 | return binop( Iop_And32, |
| 7355 | IRExpr_Get( OFFB_SSEROUND, Ity_I32 ), |
| 7356 | mkU32(3) ); |
| 7357 | } |
| 7358 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7359 | static void put_sse_roundingmode ( IRExpr* sseround ) |
| 7360 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 7361 | vassert(typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7362 | stmt( IRStmt_Put( OFFB_SSEROUND, sseround ) ); |
| 7363 | } |
| 7364 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7365 | /* Break a 128-bit value up into four 32-bit ints. */ |
| 7366 | |
| 7367 | static void breakup128to32s ( IRTemp t128, |
| 7368 | /*OUTs*/ |
| 7369 | IRTemp* t3, IRTemp* t2, |
| 7370 | IRTemp* t1, IRTemp* t0 ) |
| 7371 | { |
| 7372 | IRTemp hi64 = newTemp(Ity_I64); |
| 7373 | IRTemp lo64 = newTemp(Ity_I64); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7374 | assign( hi64, unop(Iop_V128HIto64, mkexpr(t128)) ); |
| 7375 | assign( lo64, unop(Iop_V128to64, mkexpr(t128)) ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7376 | |
| 7377 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 7378 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 7379 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 7380 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 7381 | |
| 7382 | *t0 = newTemp(Ity_I32); |
| 7383 | *t1 = newTemp(Ity_I32); |
| 7384 | *t2 = newTemp(Ity_I32); |
| 7385 | *t3 = newTemp(Ity_I32); |
| 7386 | assign( *t0, unop(Iop_64to32, mkexpr(lo64)) ); |
| 7387 | assign( *t1, unop(Iop_64HIto32, mkexpr(lo64)) ); |
| 7388 | assign( *t2, unop(Iop_64to32, mkexpr(hi64)) ); |
| 7389 | assign( *t3, unop(Iop_64HIto32, mkexpr(hi64)) ); |
| 7390 | } |
| 7391 | |
| 7392 | /* Construct a 128-bit value from four 32-bit ints. */ |
| 7393 | |
| 7394 | static IRExpr* mk128from32s ( IRTemp t3, IRTemp t2, |
| 7395 | IRTemp t1, IRTemp t0 ) |
| 7396 | { |
| 7397 | return |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7398 | binop( Iop_64HLtoV128, |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7399 | binop(Iop_32HLto64, mkexpr(t3), mkexpr(t2)), |
| 7400 | binop(Iop_32HLto64, mkexpr(t1), mkexpr(t0)) |
| 7401 | ); |
| 7402 | } |
| 7403 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7404 | /* Break a 64-bit value up into four 16-bit ints. */ |
| 7405 | |
| 7406 | static void breakup64to16s ( IRTemp t64, |
| 7407 | /*OUTs*/ |
| 7408 | IRTemp* t3, IRTemp* t2, |
| 7409 | IRTemp* t1, IRTemp* t0 ) |
| 7410 | { |
| 7411 | IRTemp hi32 = newTemp(Ity_I32); |
| 7412 | IRTemp lo32 = newTemp(Ity_I32); |
| 7413 | assign( hi32, unop(Iop_64HIto32, mkexpr(t64)) ); |
| 7414 | assign( lo32, unop(Iop_64to32, mkexpr(t64)) ); |
| 7415 | |
| 7416 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 7417 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 7418 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 7419 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 7420 | |
| 7421 | *t0 = newTemp(Ity_I16); |
| 7422 | *t1 = newTemp(Ity_I16); |
| 7423 | *t2 = newTemp(Ity_I16); |
| 7424 | *t3 = newTemp(Ity_I16); |
| 7425 | assign( *t0, unop(Iop_32to16, mkexpr(lo32)) ); |
| 7426 | assign( *t1, unop(Iop_32HIto16, mkexpr(lo32)) ); |
| 7427 | assign( *t2, unop(Iop_32to16, mkexpr(hi32)) ); |
| 7428 | assign( *t3, unop(Iop_32HIto16, mkexpr(hi32)) ); |
| 7429 | } |
| 7430 | |
| 7431 | /* Construct a 64-bit value from four 16-bit ints. */ |
| 7432 | |
| 7433 | static IRExpr* mk64from16s ( IRTemp t3, IRTemp t2, |
| 7434 | IRTemp t1, IRTemp t0 ) |
| 7435 | { |
| 7436 | return |
| 7437 | binop( Iop_32HLto64, |
| 7438 | binop(Iop_16HLto32, mkexpr(t3), mkexpr(t2)), |
| 7439 | binop(Iop_16HLto32, mkexpr(t1), mkexpr(t0)) |
| 7440 | ); |
| 7441 | } |
| 7442 | |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7443 | /* Generate IR to set the guest %EFLAGS from the pushfl-format image |
| 7444 | in the given 32-bit temporary. The flags that are set are: O S Z A |
| 7445 | C P D ID AC. |
| 7446 | |
| 7447 | In all cases, code to set AC is generated. However, VEX actually |
| 7448 | ignores the AC value and so can optionally emit an emulation |
| 7449 | warning when it is enabled. In this routine, an emulation warning |
| 7450 | is only emitted if emit_AC_emwarn is True, in which case |
| 7451 | next_insn_EIP must be correct (this allows for correct code |
| 7452 | generation for popfl/popfw). If emit_AC_emwarn is False, |
| 7453 | next_insn_EIP is unimportant (this allows for easy if kludgey code |
| 7454 | generation for IRET.) */ |
| 7455 | |
| 7456 | static |
| 7457 | void set_EFLAGS_from_value ( IRTemp t1, |
| 7458 | Bool emit_AC_emwarn, |
| 7459 | Addr32 next_insn_EIP ) |
| 7460 | { |
| 7461 | vassert(typeOfIRTemp(irsb->tyenv,t1) == Ity_I32); |
| 7462 | |
| 7463 | /* t1 is the flag word. Mask out everything except OSZACP and set |
| 7464 | the flags thunk to X86G_CC_OP_COPY. */ |
| 7465 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 7466 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 7467 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
| 7468 | binop(Iop_And32, |
| 7469 | mkexpr(t1), |
| 7470 | mkU32( X86G_CC_MASK_C | X86G_CC_MASK_P |
| 7471 | | X86G_CC_MASK_A | X86G_CC_MASK_Z |
| 7472 | | X86G_CC_MASK_S| X86G_CC_MASK_O ) |
| 7473 | ) |
| 7474 | ) |
| 7475 | ); |
| 7476 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 7477 | elimination of previous stores to this field work better. */ |
| 7478 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 7479 | |
| 7480 | /* Also need to set the D flag, which is held in bit 10 of t1. |
| 7481 | If zero, put 1 in OFFB_DFLAG, else -1 in OFFB_DFLAG. */ |
| 7482 | stmt( IRStmt_Put( |
| 7483 | OFFB_DFLAG, |
| 7484 | IRExpr_Mux0X( |
| 7485 | unop(Iop_32to8, |
| 7486 | binop(Iop_And32, |
| 7487 | binop(Iop_Shr32, mkexpr(t1), mkU8(10)), |
| 7488 | mkU32(1))), |
| 7489 | mkU32(1), |
| 7490 | mkU32(0xFFFFFFFF))) |
| 7491 | ); |
| 7492 | |
| 7493 | /* Set the ID flag */ |
| 7494 | stmt( IRStmt_Put( |
| 7495 | OFFB_IDFLAG, |
| 7496 | IRExpr_Mux0X( |
| 7497 | unop(Iop_32to8, |
| 7498 | binop(Iop_And32, |
| 7499 | binop(Iop_Shr32, mkexpr(t1), mkU8(21)), |
| 7500 | mkU32(1))), |
| 7501 | mkU32(0), |
| 7502 | mkU32(1))) |
| 7503 | ); |
| 7504 | |
| 7505 | /* And set the AC flag. If setting it 1 to, possibly emit an |
| 7506 | emulation warning. */ |
| 7507 | stmt( IRStmt_Put( |
| 7508 | OFFB_ACFLAG, |
| 7509 | IRExpr_Mux0X( |
| 7510 | unop(Iop_32to8, |
| 7511 | binop(Iop_And32, |
| 7512 | binop(Iop_Shr32, mkexpr(t1), mkU8(18)), |
| 7513 | mkU32(1))), |
| 7514 | mkU32(0), |
| 7515 | mkU32(1))) |
| 7516 | ); |
| 7517 | |
| 7518 | if (emit_AC_emwarn) { |
| 7519 | put_emwarn( mkU32(EmWarn_X86_acFlag) ); |
| 7520 | stmt( |
| 7521 | IRStmt_Exit( |
| 7522 | binop( Iop_CmpNE32, |
| 7523 | binop(Iop_And32, mkexpr(t1), mkU32(1<<18)), |
| 7524 | mkU32(0) ), |
| 7525 | Ijk_EmWarn, |
| 7526 | IRConst_U32( next_insn_EIP ) |
| 7527 | ) |
| 7528 | ); |
| 7529 | } |
| 7530 | } |
| 7531 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 7532 | |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 7533 | /* Helper for the SSSE3 (not SSE3) PMULHRSW insns. Given two 64-bit |
| 7534 | values (aa,bb), computes, for each of the 4 16-bit lanes: |
| 7535 | |
| 7536 | (((aa_lane *s32 bb_lane) >>u 14) + 1) >>u 1 |
| 7537 | */ |
| 7538 | static IRExpr* dis_PMULHRSW_helper ( IRExpr* aax, IRExpr* bbx ) |
| 7539 | { |
| 7540 | IRTemp aa = newTemp(Ity_I64); |
| 7541 | IRTemp bb = newTemp(Ity_I64); |
| 7542 | IRTemp aahi32s = newTemp(Ity_I64); |
| 7543 | IRTemp aalo32s = newTemp(Ity_I64); |
| 7544 | IRTemp bbhi32s = newTemp(Ity_I64); |
| 7545 | IRTemp bblo32s = newTemp(Ity_I64); |
| 7546 | IRTemp rHi = newTemp(Ity_I64); |
| 7547 | IRTemp rLo = newTemp(Ity_I64); |
| 7548 | IRTemp one32x2 = newTemp(Ity_I64); |
| 7549 | assign(aa, aax); |
| 7550 | assign(bb, bbx); |
| 7551 | assign( aahi32s, |
| 7552 | binop(Iop_SarN32x2, |
| 7553 | binop(Iop_InterleaveHI16x4, mkexpr(aa), mkexpr(aa)), |
| 7554 | mkU8(16) )); |
| 7555 | assign( aalo32s, |
| 7556 | binop(Iop_SarN32x2, |
| 7557 | binop(Iop_InterleaveLO16x4, mkexpr(aa), mkexpr(aa)), |
| 7558 | mkU8(16) )); |
| 7559 | assign( bbhi32s, |
| 7560 | binop(Iop_SarN32x2, |
| 7561 | binop(Iop_InterleaveHI16x4, mkexpr(bb), mkexpr(bb)), |
| 7562 | mkU8(16) )); |
| 7563 | assign( bblo32s, |
| 7564 | binop(Iop_SarN32x2, |
| 7565 | binop(Iop_InterleaveLO16x4, mkexpr(bb), mkexpr(bb)), |
| 7566 | mkU8(16) )); |
| 7567 | assign(one32x2, mkU64( (1ULL << 32) + 1 )); |
| 7568 | assign( |
| 7569 | rHi, |
| 7570 | binop( |
| 7571 | Iop_ShrN32x2, |
| 7572 | binop( |
| 7573 | Iop_Add32x2, |
| 7574 | binop( |
| 7575 | Iop_ShrN32x2, |
| 7576 | binop(Iop_Mul32x2, mkexpr(aahi32s), mkexpr(bbhi32s)), |
| 7577 | mkU8(14) |
| 7578 | ), |
| 7579 | mkexpr(one32x2) |
| 7580 | ), |
| 7581 | mkU8(1) |
| 7582 | ) |
| 7583 | ); |
| 7584 | assign( |
| 7585 | rLo, |
| 7586 | binop( |
| 7587 | Iop_ShrN32x2, |
| 7588 | binop( |
| 7589 | Iop_Add32x2, |
| 7590 | binop( |
| 7591 | Iop_ShrN32x2, |
| 7592 | binop(Iop_Mul32x2, mkexpr(aalo32s), mkexpr(bblo32s)), |
| 7593 | mkU8(14) |
| 7594 | ), |
| 7595 | mkexpr(one32x2) |
| 7596 | ), |
| 7597 | mkU8(1) |
| 7598 | ) |
| 7599 | ); |
| 7600 | return |
| 7601 | binop(Iop_CatEvenLanes16x4, mkexpr(rHi), mkexpr(rLo)); |
| 7602 | } |
| 7603 | |
| 7604 | /* Helper for the SSSE3 (not SSE3) PSIGN{B,W,D} insns. Given two 64-bit |
| 7605 | values (aa,bb), computes, for each lane: |
| 7606 | |
| 7607 | if aa_lane < 0 then - bb_lane |
| 7608 | else if aa_lane > 0 then bb_lane |
| 7609 | else 0 |
| 7610 | */ |
| 7611 | static IRExpr* dis_PSIGN_helper ( IRExpr* aax, IRExpr* bbx, Int laneszB ) |
| 7612 | { |
| 7613 | IRTemp aa = newTemp(Ity_I64); |
| 7614 | IRTemp bb = newTemp(Ity_I64); |
| 7615 | IRTemp zero = newTemp(Ity_I64); |
| 7616 | IRTemp bbNeg = newTemp(Ity_I64); |
| 7617 | IRTemp negMask = newTemp(Ity_I64); |
| 7618 | IRTemp posMask = newTemp(Ity_I64); |
| 7619 | IROp opSub = Iop_INVALID; |
| 7620 | IROp opCmpGTS = Iop_INVALID; |
| 7621 | |
| 7622 | switch (laneszB) { |
| 7623 | case 1: opSub = Iop_Sub8x8; opCmpGTS = Iop_CmpGT8Sx8; break; |
| 7624 | case 2: opSub = Iop_Sub16x4; opCmpGTS = Iop_CmpGT16Sx4; break; |
| 7625 | case 4: opSub = Iop_Sub32x2; opCmpGTS = Iop_CmpGT32Sx2; break; |
| 7626 | default: vassert(0); |
| 7627 | } |
| 7628 | |
| 7629 | assign( aa, aax ); |
| 7630 | assign( bb, bbx ); |
| 7631 | assign( zero, mkU64(0) ); |
| 7632 | assign( bbNeg, binop(opSub, mkexpr(zero), mkexpr(bb)) ); |
| 7633 | assign( negMask, binop(opCmpGTS, mkexpr(zero), mkexpr(aa)) ); |
| 7634 | assign( posMask, binop(opCmpGTS, mkexpr(aa), mkexpr(zero)) ); |
| 7635 | |
| 7636 | return |
| 7637 | binop(Iop_Or64, |
| 7638 | binop(Iop_And64, mkexpr(bb), mkexpr(posMask)), |
| 7639 | binop(Iop_And64, mkexpr(bbNeg), mkexpr(negMask)) ); |
| 7640 | |
| 7641 | } |
| 7642 | |
| 7643 | /* Helper for the SSSE3 (not SSE3) PABS{B,W,D} insns. Given a 64-bit |
| 7644 | value aa, computes, for each lane |
| 7645 | |
| 7646 | if aa < 0 then -aa else aa |
| 7647 | |
| 7648 | Note that the result is interpreted as unsigned, so that the |
| 7649 | absolute value of the most negative signed input can be |
| 7650 | represented. |
| 7651 | */ |
| 7652 | static IRExpr* dis_PABS_helper ( IRExpr* aax, Int laneszB ) |
| 7653 | { |
| 7654 | IRTemp aa = newTemp(Ity_I64); |
| 7655 | IRTemp zero = newTemp(Ity_I64); |
| 7656 | IRTemp aaNeg = newTemp(Ity_I64); |
| 7657 | IRTemp negMask = newTemp(Ity_I64); |
| 7658 | IRTemp posMask = newTemp(Ity_I64); |
| 7659 | IROp opSub = Iop_INVALID; |
| 7660 | IROp opSarN = Iop_INVALID; |
| 7661 | |
| 7662 | switch (laneszB) { |
| 7663 | case 1: opSub = Iop_Sub8x8; opSarN = Iop_SarN8x8; break; |
| 7664 | case 2: opSub = Iop_Sub16x4; opSarN = Iop_SarN16x4; break; |
| 7665 | case 4: opSub = Iop_Sub32x2; opSarN = Iop_SarN32x2; break; |
| 7666 | default: vassert(0); |
| 7667 | } |
| 7668 | |
| 7669 | assign( aa, aax ); |
| 7670 | assign( negMask, binop(opSarN, mkexpr(aa), mkU8(8*laneszB-1)) ); |
| 7671 | assign( posMask, unop(Iop_Not64, mkexpr(negMask)) ); |
| 7672 | assign( zero, mkU64(0) ); |
| 7673 | assign( aaNeg, binop(opSub, mkexpr(zero), mkexpr(aa)) ); |
| 7674 | return |
| 7675 | binop(Iop_Or64, |
| 7676 | binop(Iop_And64, mkexpr(aa), mkexpr(posMask)), |
| 7677 | binop(Iop_And64, mkexpr(aaNeg), mkexpr(negMask)) ); |
| 7678 | } |
| 7679 | |
| 7680 | static IRExpr* dis_PALIGNR_XMM_helper ( IRTemp hi64, |
| 7681 | IRTemp lo64, Int byteShift ) |
| 7682 | { |
| 7683 | vassert(byteShift >= 1 && byteShift <= 7); |
| 7684 | return |
| 7685 | binop(Iop_Or64, |
| 7686 | binop(Iop_Shl64, mkexpr(hi64), mkU8(8*(8-byteShift))), |
| 7687 | binop(Iop_Shr64, mkexpr(lo64), mkU8(8*byteShift)) |
| 7688 | ); |
| 7689 | } |
| 7690 | |
| 7691 | /* Generate a SIGSEGV followed by a restart of the current instruction |
| 7692 | if effective_addr is not 16-aligned. This is required behaviour |
| 7693 | for some SSE3 instructions and all 128-bit SSSE3 instructions. |
| 7694 | This assumes that guest_RIP_curr_instr is set correctly! */ |
| 7695 | static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr ) |
| 7696 | { |
| 7697 | stmt( |
| 7698 | IRStmt_Exit( |
| 7699 | binop(Iop_CmpNE32, |
| 7700 | binop(Iop_And32,mkexpr(effective_addr),mkU32(0xF)), |
| 7701 | mkU32(0)), |
| 7702 | Ijk_SigSEGV, |
| 7703 | IRConst_U32(guest_EIP_curr_instr) |
| 7704 | ) |
| 7705 | ); |
| 7706 | } |
| 7707 | |
| 7708 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7709 | /* Helper for deciding whether a given insn (starting at the opcode |
| 7710 | byte) may validly be used with a LOCK prefix. The following insns |
| 7711 | may be used with LOCK when their destination operand is in memory. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7712 | AFAICS this is exactly the same for both 32-bit and 64-bit mode. |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7713 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7714 | ADD 80 /0, 81 /0, 82 /0, 83 /0, 00, 01 |
| 7715 | OR 80 /1, 81 /1, 82 /x, 83 /1, 08, 09 |
| 7716 | ADC 80 /2, 81 /2, 82 /2, 83 /2, 10, 11 |
| 7717 | SBB 81 /3, 81 /3, 82 /x, 83 /3, 18, 19 |
| 7718 | AND 80 /4, 81 /4, 82 /x, 83 /4, 20, 21 |
| 7719 | SUB 80 /5, 81 /5, 82 /x, 83 /5, 28, 29 |
| 7720 | XOR 80 /6, 81 /6, 82 /x, 83 /6, 30, 31 |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7721 | |
| 7722 | DEC FE /1, FF /1 |
| 7723 | INC FE /0, FF /0 |
| 7724 | |
| 7725 | NEG F6 /3, F7 /3 |
| 7726 | NOT F6 /2, F7 /2 |
| 7727 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7728 | XCHG 86, 87 |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7729 | |
| 7730 | BTC 0F BB, 0F BA /7 |
| 7731 | BTR 0F B3, 0F BA /6 |
| 7732 | BTS 0F AB, 0F BA /5 |
| 7733 | |
| 7734 | CMPXCHG 0F B0, 0F B1 |
| 7735 | CMPXCHG8B 0F C7 /1 |
| 7736 | |
| 7737 | XADD 0F C0, 0F C1 |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7738 | |
| 7739 | ------------------------------ |
| 7740 | |
| 7741 | 80 /0 = addb $imm8, rm8 |
| 7742 | 81 /0 = addl $imm32, rm32 and addw $imm16, rm16 |
| 7743 | 82 /0 = addb $imm8, rm8 |
| 7744 | 83 /0 = addl $simm8, rm32 and addw $simm8, rm16 |
| 7745 | |
| 7746 | 00 = addb r8, rm8 |
| 7747 | 01 = addl r32, rm32 and addw r16, rm16 |
| 7748 | |
| 7749 | Same for ADD OR ADC SBB AND SUB XOR |
| 7750 | |
| 7751 | FE /1 = dec rm8 |
| 7752 | FF /1 = dec rm32 and dec rm16 |
| 7753 | |
| 7754 | FE /0 = inc rm8 |
| 7755 | FF /0 = inc rm32 and inc rm16 |
| 7756 | |
| 7757 | F6 /3 = neg rm8 |
| 7758 | F7 /3 = neg rm32 and neg rm16 |
| 7759 | |
| 7760 | F6 /2 = not rm8 |
| 7761 | F7 /2 = not rm32 and not rm16 |
| 7762 | |
| 7763 | 0F BB = btcw r16, rm16 and btcl r32, rm32 |
| 7764 | OF BA /7 = btcw $imm8, rm16 and btcw $imm8, rm32 |
| 7765 | |
| 7766 | Same for BTS, BTR |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7767 | */ |
| 7768 | static Bool can_be_used_with_LOCK_prefix ( UChar* opc ) |
| 7769 | { |
| 7770 | switch (opc[0]) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7771 | case 0x00: case 0x01: case 0x08: case 0x09: |
| 7772 | case 0x10: case 0x11: case 0x18: case 0x19: |
| 7773 | case 0x20: case 0x21: case 0x28: case 0x29: |
| 7774 | case 0x30: case 0x31: |
| 7775 | if (!epartIsReg(opc[1])) |
| 7776 | return True; |
| 7777 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7778 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7779 | case 0x80: case 0x81: case 0x82: case 0x83: |
| 7780 | if (gregOfRM(opc[1]) >= 0 && gregOfRM(opc[1]) <= 6 |
| 7781 | && !epartIsReg(opc[1])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7782 | return True; |
| 7783 | break; |
| 7784 | |
| 7785 | case 0xFE: case 0xFF: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7786 | if (gregOfRM(opc[1]) >= 0 && gregOfRM(opc[1]) <= 1 |
| 7787 | && !epartIsReg(opc[1])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7788 | return True; |
| 7789 | break; |
| 7790 | |
| 7791 | case 0xF6: case 0xF7: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7792 | if (gregOfRM(opc[1]) >= 2 && gregOfRM(opc[1]) <= 3 |
| 7793 | && !epartIsReg(opc[1])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7794 | return True; |
| 7795 | break; |
| 7796 | |
| 7797 | case 0x86: case 0x87: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7798 | if (!epartIsReg(opc[1])) |
| 7799 | return True; |
| 7800 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7801 | |
| 7802 | case 0x0F: { |
| 7803 | switch (opc[1]) { |
| 7804 | case 0xBB: case 0xB3: case 0xAB: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7805 | if (!epartIsReg(opc[2])) |
| 7806 | return True; |
| 7807 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7808 | case 0xBA: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7809 | if (gregOfRM(opc[2]) >= 5 && gregOfRM(opc[2]) <= 7 |
| 7810 | && !epartIsReg(opc[2])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7811 | return True; |
| 7812 | break; |
| 7813 | case 0xB0: case 0xB1: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7814 | if (!epartIsReg(opc[2])) |
| 7815 | return True; |
| 7816 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7817 | case 0xC7: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7818 | if (gregOfRM(opc[2]) == 1 && !epartIsReg(opc[2]) ) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7819 | return True; |
| 7820 | break; |
| 7821 | case 0xC0: case 0xC1: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7822 | if (!epartIsReg(opc[2])) |
| 7823 | return True; |
| 7824 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7825 | default: |
| 7826 | break; |
| 7827 | } /* switch (opc[1]) */ |
| 7828 | break; |
| 7829 | } |
| 7830 | |
| 7831 | default: |
| 7832 | break; |
| 7833 | } /* switch (opc[0]) */ |
| 7834 | |
| 7835 | return False; |
| 7836 | } |
| 7837 | |
| 7838 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7839 | /*------------------------------------------------------------*/ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 7840 | /*--- Disassemble a single instruction ---*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7841 | /*------------------------------------------------------------*/ |
| 7842 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7843 | /* Disassemble a single instruction into IR. The instruction is |
| 7844 | located in host memory at &guest_code[delta]. *expect_CAS is set |
| 7845 | to True if the resulting IR is expected to contain an IRCAS |
| 7846 | statement, and False if it's not expected to. This makes it |
| 7847 | possible for the caller of disInstr_X86_WRK to check that |
| 7848 | LOCK-prefixed instructions are at least plausibly translated, in |
| 7849 | that it becomes possible to check that a (validly) LOCK-prefixed |
| 7850 | instruction generates a translation containing an IRCAS, and |
| 7851 | instructions without LOCK prefixes don't generate translations |
| 7852 | containing an IRCAS. |
| 7853 | */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7854 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7855 | DisResult disInstr_X86_WRK ( |
| 7856 | /*OUT*/Bool* expect_CAS, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7857 | Bool put_IP, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 7858 | Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 7859 | Bool resteerCisOk, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 7860 | void* callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7861 | Long delta64, |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 7862 | VexArchInfo* archinfo, |
| 7863 | VexAbiInfo* vbi |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7864 | ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7865 | { |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 7866 | IRType ty; |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 7867 | IRTemp addr, t0, t1, t2, t3, t4, t5, t6; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 7868 | Int alen; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7869 | UChar opc, modrm, abyte, pre; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 7870 | UInt d32; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 7871 | HChar dis_buf[50]; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7872 | Int am_sz, d_sz, n_prefixes; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7873 | DisResult dres; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 7874 | UChar* insn; /* used in SSE decoders */ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 7875 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7876 | /* The running delta */ |
| 7877 | Int delta = (Int)delta64; |
| 7878 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7879 | /* Holds eip at the start of the insn, so that we can print |
| 7880 | consistent error messages for unimplemented insns. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7881 | Int delta_start = delta; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7882 | |
| 7883 | /* sz denotes the nominal data-op size of the insn; we change it to |
| 7884 | 2 if an 0x66 prefix is seen */ |
| 7885 | Int sz = 4; |
| 7886 | |
| 7887 | /* sorb holds the segment-override-prefix byte, if any. Zero if no |
| 7888 | prefix has been seen, else one of {0x26, 0x3E, 0x64, 0x65} |
| 7889 | indicating the prefix. */ |
| 7890 | UChar sorb = 0; |
| 7891 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7892 | /* Gets set to True if a LOCK prefix is seen. */ |
| 7893 | Bool pfx_lock = False; |
| 7894 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7895 | /* Set result defaults. */ |
| 7896 | dres.whatNext = Dis_Continue; |
| 7897 | dres.len = 0; |
| 7898 | dres.continueAt = 0; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 7899 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7900 | *expect_CAS = False; |
| 7901 | |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 7902 | addr = t0 = t1 = t2 = t3 = t4 = t5 = t6 = IRTemp_INVALID; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7903 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7904 | vassert(guest_EIP_bbstart + delta == guest_EIP_curr_instr); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 7905 | DIP("\t0x%x: ", guest_EIP_bbstart+delta); |
| 7906 | |
| 7907 | /* We may be asked to update the guest EIP before going further. */ |
| 7908 | if (put_IP) |
| 7909 | stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_curr_instr)) ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7910 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 7911 | /* Spot "Special" instructions (see comment at top of file). */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 7912 | { |
| 7913 | UChar* code = (UChar*)(guest_code + delta); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 7914 | /* Spot the 12-byte preamble: |
| 7915 | C1C703 roll $3, %edi |
| 7916 | C1C70D roll $13, %edi |
| 7917 | C1C71D roll $29, %edi |
| 7918 | C1C713 roll $19, %edi |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 7919 | */ |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 7920 | if (code[ 0] == 0xC1 && code[ 1] == 0xC7 && code[ 2] == 0x03 && |
| 7921 | code[ 3] == 0xC1 && code[ 4] == 0xC7 && code[ 5] == 0x0D && |
| 7922 | code[ 6] == 0xC1 && code[ 7] == 0xC7 && code[ 8] == 0x1D && |
| 7923 | code[ 9] == 0xC1 && code[10] == 0xC7 && code[11] == 0x13) { |
| 7924 | /* Got a "Special" instruction preamble. Which one is it? */ |
| 7925 | if (code[12] == 0x87 && code[13] == 0xDB /* xchgl %ebx,%ebx */) { |
| 7926 | /* %EDX = client_request ( %EAX ) */ |
| 7927 | DIP("%%edx = client_request ( %%eax )\n"); |
| 7928 | delta += 14; |
| 7929 | jmp_lit(Ijk_ClientReq, guest_EIP_bbstart+delta); |
| 7930 | dres.whatNext = Dis_StopHere; |
| 7931 | goto decode_success; |
| 7932 | } |
| 7933 | else |
| 7934 | if (code[12] == 0x87 && code[13] == 0xC9 /* xchgl %ecx,%ecx */) { |
| 7935 | /* %EAX = guest_NRADDR */ |
| 7936 | DIP("%%eax = guest_NRADDR\n"); |
| 7937 | delta += 14; |
| 7938 | putIReg(4, R_EAX, IRExpr_Get( OFFB_NRADDR, Ity_I32 )); |
| 7939 | goto decode_success; |
| 7940 | } |
| 7941 | else |
| 7942 | if (code[12] == 0x87 && code[13] == 0xD2 /* xchgl %edx,%edx */) { |
| 7943 | /* call-noredir *%EAX */ |
| 7944 | DIP("call-noredir *%%eax\n"); |
| 7945 | delta += 14; |
| 7946 | t1 = newTemp(Ity_I32); |
| 7947 | assign(t1, getIReg(4,R_EAX)); |
| 7948 | t2 = newTemp(Ity_I32); |
| 7949 | assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 7950 | putIReg(4, R_ESP, mkexpr(t2)); |
| 7951 | storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta)); |
| 7952 | jmp_treg(Ijk_NoRedir,t1); |
| 7953 | dres.whatNext = Dis_StopHere; |
| 7954 | goto decode_success; |
| 7955 | } |
| 7956 | /* We don't know what it is. */ |
| 7957 | goto decode_failure; |
| 7958 | /*NOTREACHED*/ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 7959 | } |
| 7960 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7961 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7962 | /* Handle a couple of weird-ass NOPs that have been observed in the |
| 7963 | wild. */ |
| 7964 | { |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 7965 | UChar* code = (UChar*)(guest_code + delta); |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7966 | /* Sun's JVM 1.5.0 uses the following as a NOP: |
| 7967 | 26 2E 64 65 90 %es:%cs:%fs:%gs:nop */ |
| 7968 | if (code[0] == 0x26 && code[1] == 0x2E && code[2] == 0x64 |
| 7969 | && code[3] == 0x65 && code[4] == 0x90) { |
| 7970 | DIP("%%es:%%cs:%%fs:%%gs:nop\n"); |
| 7971 | delta += 5; |
| 7972 | goto decode_success; |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 7973 | } |
sewardj | deceef8 | 2010-05-03 21:58:22 +0000 | [diff] [blame] | 7974 | /* Don't barf on recent binutils padding, |
| 7975 | all variants of which are: nopw %cs:0x0(%eax,%eax,1) |
| 7976 | 66 2e 0f 1f 84 00 00 00 00 00 |
| 7977 | 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 7978 | 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 7979 | 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 7980 | 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 7981 | 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 7982 | */ |
| 7983 | if (code[0] == 0x66) { |
| 7984 | Int data16_cnt; |
| 7985 | for (data16_cnt = 1; data16_cnt < 6; data16_cnt++) |
| 7986 | if (code[data16_cnt] != 0x66) |
| 7987 | break; |
| 7988 | if (code[data16_cnt] == 0x2E && code[data16_cnt + 1] == 0x0F |
| 7989 | && code[data16_cnt + 2] == 0x1F && code[data16_cnt + 3] == 0x84 |
| 7990 | && code[data16_cnt + 4] == 0x00 && code[data16_cnt + 5] == 0x00 |
| 7991 | && code[data16_cnt + 6] == 0x00 && code[data16_cnt + 7] == 0x00 |
| 7992 | && code[data16_cnt + 8] == 0x00 ) { |
| 7993 | DIP("nopw %%cs:0x0(%%eax,%%eax,1)\n"); |
| 7994 | delta += 9 + data16_cnt; |
| 7995 | goto decode_success; |
| 7996 | } |
sewardj | ce4a282 | 2005-01-07 13:25:28 +0000 | [diff] [blame] | 7997 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7998 | } |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 7999 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8000 | /* Normal instruction handling starts here. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8001 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8002 | /* Deal with some but not all prefixes: |
| 8003 | 66(oso) |
| 8004 | F0(lock) |
| 8005 | 2E(cs:) 3E(ds:) 26(es:) 64(fs:) 65(gs:) 36(ss:) |
| 8006 | Not dealt with (left in place): |
| 8007 | F2 F3 |
| 8008 | */ |
| 8009 | n_prefixes = 0; |
| 8010 | while (True) { |
| 8011 | if (n_prefixes > 7) goto decode_failure; |
| 8012 | pre = getUChar(delta); |
| 8013 | switch (pre) { |
| 8014 | case 0x66: |
| 8015 | sz = 2; |
| 8016 | break; |
| 8017 | case 0xF0: |
| 8018 | pfx_lock = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8019 | *expect_CAS = True; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8020 | break; |
| 8021 | case 0x3E: /* %DS: */ |
| 8022 | case 0x26: /* %ES: */ |
| 8023 | case 0x64: /* %FS: */ |
| 8024 | case 0x65: /* %GS: */ |
| 8025 | if (sorb != 0) |
| 8026 | goto decode_failure; /* only one seg override allowed */ |
| 8027 | sorb = pre; |
| 8028 | break; |
| 8029 | case 0x2E: { /* %CS: */ |
| 8030 | /* 2E prefix on a conditional branch instruction is a |
| 8031 | branch-prediction hint, which can safely be ignored. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8032 | UChar op1 = getIByte(delta+1); |
| 8033 | UChar op2 = getIByte(delta+2); |
| 8034 | if ((op1 >= 0x70 && op1 <= 0x7F) |
| 8035 | || (op1 == 0xE3) |
| 8036 | || (op1 == 0x0F && op2 >= 0x80 && op2 <= 0x8F)) { |
sewardj | 4dfb199 | 2005-03-13 18:56:28 +0000 | [diff] [blame] | 8037 | if (0) vex_printf("vex x86->IR: ignoring branch hint\n"); |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8038 | } else { |
| 8039 | /* All other CS override cases are not handled */ |
| 8040 | goto decode_failure; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8041 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8042 | break; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8043 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8044 | case 0x36: /* %SS: */ |
| 8045 | /* SS override cases are not handled */ |
| 8046 | goto decode_failure; |
| 8047 | default: |
| 8048 | goto not_a_prefix; |
| 8049 | } |
| 8050 | n_prefixes++; |
| 8051 | delta++; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8052 | } |
| 8053 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8054 | not_a_prefix: |
| 8055 | |
| 8056 | /* Now we should be looking at the primary opcode byte or the |
| 8057 | leading F2 or F3. Check that any LOCK prefix is actually |
| 8058 | allowed. */ |
| 8059 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8060 | if (pfx_lock) { |
| 8061 | if (can_be_used_with_LOCK_prefix( (UChar*)&guest_code[delta] )) { |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8062 | DIP("lock "); |
| 8063 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8064 | *expect_CAS = False; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8065 | goto decode_failure; |
| 8066 | } |
| 8067 | } |
| 8068 | |
| 8069 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8070 | /* ---------------------------------------------------- */ |
| 8071 | /* --- The SSE decoder. --- */ |
| 8072 | /* ---------------------------------------------------- */ |
| 8073 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8074 | /* What did I do to deserve SSE ? Perhaps I was really bad in a |
| 8075 | previous life? */ |
| 8076 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8077 | /* Note, this doesn't handle SSE2 or SSE3. That is handled in a |
| 8078 | later section, further on. */ |
| 8079 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8080 | insn = (UChar*)&guest_code[delta]; |
| 8081 | |
| 8082 | /* Treat fxsave specially. It should be doable even on an SSE0 |
| 8083 | (Pentium-II class) CPU. Hence be prepared to handle it on |
| 8084 | any subarchitecture variant. |
| 8085 | */ |
| 8086 | |
| 8087 | /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory */ |
| 8088 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE |
| 8089 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 0) { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 8090 | IRDirty* d; |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8091 | modrm = getIByte(delta+2); |
| 8092 | vassert(sz == 4); |
| 8093 | vassert(!epartIsReg(modrm)); |
| 8094 | |
| 8095 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8096 | delta += 2+alen; |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8097 | gen_SEGV_if_not_16_aligned(addr); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8098 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 8099 | DIP("fxsave %s\n", dis_buf); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8100 | |
| 8101 | /* Uses dirty helper: |
| 8102 | void x86g_do_FXSAVE ( VexGuestX86State*, UInt ) */ |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 8103 | d = unsafeIRDirty_0_N ( |
| 8104 | 0/*regparms*/, |
| 8105 | "x86g_dirtyhelper_FXSAVE", |
| 8106 | &x86g_dirtyhelper_FXSAVE, |
| 8107 | mkIRExprVec_1( mkexpr(addr) ) |
| 8108 | ); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8109 | d->needsBBP = True; |
| 8110 | |
| 8111 | /* declare we're writing memory */ |
| 8112 | d->mFx = Ifx_Write; |
| 8113 | d->mAddr = mkexpr(addr); |
| 8114 | d->mSize = 512; |
| 8115 | |
| 8116 | /* declare we're reading guest state */ |
| 8117 | d->nFxState = 7; |
| 8118 | |
| 8119 | d->fxState[0].fx = Ifx_Read; |
| 8120 | d->fxState[0].offset = OFFB_FTOP; |
| 8121 | d->fxState[0].size = sizeof(UInt); |
| 8122 | |
| 8123 | d->fxState[1].fx = Ifx_Read; |
| 8124 | d->fxState[1].offset = OFFB_FPREGS; |
| 8125 | d->fxState[1].size = 8 * sizeof(ULong); |
| 8126 | |
| 8127 | d->fxState[2].fx = Ifx_Read; |
| 8128 | d->fxState[2].offset = OFFB_FPTAGS; |
| 8129 | d->fxState[2].size = 8 * sizeof(UChar); |
| 8130 | |
| 8131 | d->fxState[3].fx = Ifx_Read; |
| 8132 | d->fxState[3].offset = OFFB_FPROUND; |
| 8133 | d->fxState[3].size = sizeof(UInt); |
| 8134 | |
| 8135 | d->fxState[4].fx = Ifx_Read; |
| 8136 | d->fxState[4].offset = OFFB_FC3210; |
| 8137 | d->fxState[4].size = sizeof(UInt); |
| 8138 | |
| 8139 | d->fxState[5].fx = Ifx_Read; |
| 8140 | d->fxState[5].offset = OFFB_XMM0; |
| 8141 | d->fxState[5].size = 8 * sizeof(U128); |
| 8142 | |
| 8143 | d->fxState[6].fx = Ifx_Read; |
| 8144 | d->fxState[6].offset = OFFB_SSEROUND; |
| 8145 | d->fxState[6].size = sizeof(UInt); |
| 8146 | |
| 8147 | /* Be paranoid ... this assertion tries to ensure the 8 %xmm |
| 8148 | images are packed back-to-back. If not, the value of |
| 8149 | d->fxState[5].size is wrong. */ |
| 8150 | vassert(16 == sizeof(U128)); |
| 8151 | vassert(OFFB_XMM7 == (OFFB_XMM0 + 7 * 16)); |
| 8152 | |
| 8153 | stmt( IRStmt_Dirty(d) ); |
| 8154 | |
| 8155 | goto decode_success; |
| 8156 | } |
| 8157 | |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8158 | /* 0F AE /1 = FXRSTOR m512 -- read x87 and SSE state from memory */ |
| 8159 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE |
| 8160 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 1) { |
| 8161 | IRDirty* d; |
| 8162 | modrm = getIByte(delta+2); |
| 8163 | vassert(sz == 4); |
| 8164 | vassert(!epartIsReg(modrm)); |
| 8165 | |
| 8166 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8167 | delta += 2+alen; |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8168 | gen_SEGV_if_not_16_aligned(addr); |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8169 | |
| 8170 | DIP("fxrstor %s\n", dis_buf); |
| 8171 | |
| 8172 | /* Uses dirty helper: |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8173 | VexEmWarn x86g_do_FXRSTOR ( VexGuestX86State*, UInt ) |
| 8174 | NOTE: |
| 8175 | the VexEmWarn value is simply ignored (unlike for FRSTOR) |
| 8176 | */ |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8177 | d = unsafeIRDirty_0_N ( |
| 8178 | 0/*regparms*/, |
| 8179 | "x86g_dirtyhelper_FXRSTOR", |
| 8180 | &x86g_dirtyhelper_FXRSTOR, |
| 8181 | mkIRExprVec_1( mkexpr(addr) ) |
| 8182 | ); |
| 8183 | d->needsBBP = True; |
| 8184 | |
| 8185 | /* declare we're reading memory */ |
| 8186 | d->mFx = Ifx_Read; |
| 8187 | d->mAddr = mkexpr(addr); |
| 8188 | d->mSize = 512; |
| 8189 | |
| 8190 | /* declare we're writing guest state */ |
| 8191 | d->nFxState = 7; |
| 8192 | |
| 8193 | d->fxState[0].fx = Ifx_Write; |
| 8194 | d->fxState[0].offset = OFFB_FTOP; |
| 8195 | d->fxState[0].size = sizeof(UInt); |
| 8196 | |
| 8197 | d->fxState[1].fx = Ifx_Write; |
| 8198 | d->fxState[1].offset = OFFB_FPREGS; |
| 8199 | d->fxState[1].size = 8 * sizeof(ULong); |
| 8200 | |
| 8201 | d->fxState[2].fx = Ifx_Write; |
| 8202 | d->fxState[2].offset = OFFB_FPTAGS; |
| 8203 | d->fxState[2].size = 8 * sizeof(UChar); |
| 8204 | |
| 8205 | d->fxState[3].fx = Ifx_Write; |
| 8206 | d->fxState[3].offset = OFFB_FPROUND; |
| 8207 | d->fxState[3].size = sizeof(UInt); |
| 8208 | |
| 8209 | d->fxState[4].fx = Ifx_Write; |
| 8210 | d->fxState[4].offset = OFFB_FC3210; |
| 8211 | d->fxState[4].size = sizeof(UInt); |
| 8212 | |
| 8213 | d->fxState[5].fx = Ifx_Write; |
| 8214 | d->fxState[5].offset = OFFB_XMM0; |
| 8215 | d->fxState[5].size = 8 * sizeof(U128); |
| 8216 | |
| 8217 | d->fxState[6].fx = Ifx_Write; |
| 8218 | d->fxState[6].offset = OFFB_SSEROUND; |
| 8219 | d->fxState[6].size = sizeof(UInt); |
| 8220 | |
| 8221 | /* Be paranoid ... this assertion tries to ensure the 8 %xmm |
| 8222 | images are packed back-to-back. If not, the value of |
| 8223 | d->fxState[5].size is wrong. */ |
| 8224 | vassert(16 == sizeof(U128)); |
| 8225 | vassert(OFFB_XMM7 == (OFFB_XMM0 + 7 * 16)); |
| 8226 | |
| 8227 | stmt( IRStmt_Dirty(d) ); |
| 8228 | |
| 8229 | goto decode_success; |
| 8230 | } |
| 8231 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8232 | /* ------ SSE decoder main ------ */ |
| 8233 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8234 | /* Skip parts of the decoder which don't apply given the stated |
| 8235 | guest subarchitecture. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8236 | if (archinfo->hwcaps == 0/*baseline, no sse at all*/) |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8237 | goto after_sse_decoders; |
| 8238 | |
| 8239 | /* Otherwise we must be doing sse1 or sse2, so we can at least try |
| 8240 | for SSE1 here. */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8241 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8242 | /* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8243 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x58) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8244 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "addps", Iop_Add32Fx4 ); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8245 | goto decode_success; |
| 8246 | } |
| 8247 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8248 | /* F3 0F 58 = ADDSS -- add 32F0x4 from R/M to R */ |
| 8249 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x58) { |
| 8250 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8251 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "addss", Iop_Add32F0x4 ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8252 | goto decode_success; |
| 8253 | } |
| 8254 | |
| 8255 | /* 0F 55 = ANDNPS -- G = (not G) and E */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8256 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x55) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 8257 | delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "andnps", Iop_AndV128 ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8258 | goto decode_success; |
| 8259 | } |
| 8260 | |
| 8261 | /* 0F 54 = ANDPS -- G = G and E */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8262 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x54) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 8263 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "andps", Iop_AndV128 ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8264 | goto decode_success; |
| 8265 | } |
| 8266 | |
| 8267 | /* 0F C2 = CMPPS -- 32Fx4 comparison from R/M to R */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8268 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC2) { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8269 | delta = dis_SSEcmp_E_to_G( sorb, delta+2, "cmpps", True, 4 ); |
| 8270 | goto decode_success; |
| 8271 | } |
| 8272 | |
| 8273 | /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */ |
| 8274 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xC2) { |
| 8275 | vassert(sz == 4); |
| 8276 | delta = dis_SSEcmp_E_to_G( sorb, delta+3, "cmpss", False, 4 ); |
| 8277 | goto decode_success; |
| 8278 | } |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8279 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8280 | /* 0F 2F = COMISS -- 32F0x4 comparison G,E, and set ZCP */ |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 8281 | /* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8282 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) { |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8283 | IRTemp argL = newTemp(Ity_F32); |
| 8284 | IRTemp argR = newTemp(Ity_F32); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8285 | modrm = getIByte(delta+2); |
| 8286 | if (epartIsReg(modrm)) { |
| 8287 | assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 8288 | delta += 2+1; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 8289 | DIP("[u]comiss %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 8290 | nameXMMReg(gregOfRM(modrm)) ); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8291 | } else { |
| 8292 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8293 | assign( argR, loadLE(Ity_F32, mkexpr(addr)) ); |
| 8294 | delta += 2+alen; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 8295 | DIP("[u]comiss %s,%s\n", dis_buf, |
| 8296 | nameXMMReg(gregOfRM(modrm)) ); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8297 | } |
| 8298 | assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 8299 | |
| 8300 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 8301 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 8302 | stmt( IRStmt_Put( |
| 8303 | OFFB_CC_DEP1, |
| 8304 | binop( Iop_And32, |
| 8305 | binop(Iop_CmpF64, |
| 8306 | unop(Iop_F32toF64,mkexpr(argL)), |
| 8307 | unop(Iop_F32toF64,mkexpr(argR))), |
| 8308 | mkU32(0x45) |
| 8309 | ))); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 8310 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 8311 | elimination of previous stores to this field work better. */ |
| 8312 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8313 | goto decode_success; |
| 8314 | } |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8315 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8316 | /* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low |
| 8317 | half xmm */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8318 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x2A) { |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8319 | IRTemp arg64 = newTemp(Ity_I64); |
| 8320 | IRTemp rmode = newTemp(Ity_I32); |
| 8321 | vassert(sz == 4); |
| 8322 | |
| 8323 | modrm = getIByte(delta+2); |
| 8324 | do_MMX_preamble(); |
| 8325 | if (epartIsReg(modrm)) { |
| 8326 | assign( arg64, getMMXReg(eregOfRM(modrm)) ); |
| 8327 | delta += 2+1; |
| 8328 | DIP("cvtpi2ps %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 8329 | nameXMMReg(gregOfRM(modrm))); |
| 8330 | } else { |
| 8331 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8332 | assign( arg64, loadLE(Ity_I64, mkexpr(addr)) ); |
| 8333 | delta += 2+alen; |
| 8334 | DIP("cvtpi2ps %s,%s\n", dis_buf, |
| 8335 | nameXMMReg(gregOfRM(modrm)) ); |
| 8336 | } |
| 8337 | |
| 8338 | assign( rmode, get_sse_roundingmode() ); |
| 8339 | |
| 8340 | putXMMRegLane32F( |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8341 | gregOfRM(modrm), 0, |
| 8342 | binop(Iop_F64toF32, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8343 | mkexpr(rmode), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8344 | unop(Iop_I32StoF64, |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8345 | unop(Iop_64to32, mkexpr(arg64)) )) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8346 | |
| 8347 | putXMMRegLane32F( |
| 8348 | gregOfRM(modrm), 1, |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8349 | binop(Iop_F64toF32, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8350 | mkexpr(rmode), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8351 | unop(Iop_I32StoF64, |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8352 | unop(Iop_64HIto32, mkexpr(arg64)) )) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8353 | |
| 8354 | goto decode_success; |
| 8355 | } |
| 8356 | |
| 8357 | /* F3 0F 2A = CVTSI2SS -- convert I32 in mem/ireg to F32 in low |
| 8358 | quarter xmm */ |
| 8359 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x2A) { |
| 8360 | IRTemp arg32 = newTemp(Ity_I32); |
| 8361 | IRTemp rmode = newTemp(Ity_I32); |
| 8362 | vassert(sz == 4); |
| 8363 | |
| 8364 | modrm = getIByte(delta+3); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8365 | if (epartIsReg(modrm)) { |
| 8366 | assign( arg32, getIReg(4, eregOfRM(modrm)) ); |
| 8367 | delta += 3+1; |
| 8368 | DIP("cvtsi2ss %s,%s\n", nameIReg(4, eregOfRM(modrm)), |
| 8369 | nameXMMReg(gregOfRM(modrm))); |
| 8370 | } else { |
| 8371 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 8372 | assign( arg32, loadLE(Ity_I32, mkexpr(addr)) ); |
| 8373 | delta += 3+alen; |
| 8374 | DIP("cvtsi2ss %s,%s\n", dis_buf, |
| 8375 | nameXMMReg(gregOfRM(modrm)) ); |
| 8376 | } |
| 8377 | |
| 8378 | assign( rmode, get_sse_roundingmode() ); |
| 8379 | |
| 8380 | putXMMRegLane32F( |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8381 | gregOfRM(modrm), 0, |
| 8382 | binop(Iop_F64toF32, |
| 8383 | mkexpr(rmode), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8384 | unop(Iop_I32StoF64, mkexpr(arg32)) ) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8385 | |
| 8386 | goto decode_success; |
| 8387 | } |
| 8388 | |
| 8389 | /* 0F 2D = CVTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x |
| 8390 | I32 in mmx, according to prevailing SSE rounding mode */ |
| 8391 | /* 0F 2C = CVTTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x |
| 8392 | I32 in mmx, rounding towards zero */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8393 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) { |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8394 | IRTemp dst64 = newTemp(Ity_I64); |
| 8395 | IRTemp rmode = newTemp(Ity_I32); |
| 8396 | IRTemp f32lo = newTemp(Ity_F32); |
| 8397 | IRTemp f32hi = newTemp(Ity_F32); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 8398 | Bool r2zero = toBool(insn[1] == 0x2C); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8399 | |
| 8400 | do_MMX_preamble(); |
| 8401 | modrm = getIByte(delta+2); |
| 8402 | |
| 8403 | if (epartIsReg(modrm)) { |
| 8404 | delta += 2+1; |
| 8405 | assign(f32lo, getXMMRegLane32F(eregOfRM(modrm), 0)); |
| 8406 | assign(f32hi, getXMMRegLane32F(eregOfRM(modrm), 1)); |
| 8407 | DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "", |
| 8408 | nameXMMReg(eregOfRM(modrm)), |
| 8409 | nameMMXReg(gregOfRM(modrm))); |
| 8410 | } else { |
| 8411 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8412 | assign(f32lo, loadLE(Ity_F32, mkexpr(addr))); |
| 8413 | assign(f32hi, loadLE(Ity_F32, binop( Iop_Add32, |
| 8414 | mkexpr(addr), |
| 8415 | mkU32(4) ))); |
| 8416 | delta += 2+alen; |
| 8417 | DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "", |
| 8418 | dis_buf, |
| 8419 | nameMMXReg(gregOfRM(modrm))); |
| 8420 | } |
| 8421 | |
| 8422 | if (r2zero) { |
| 8423 | assign(rmode, mkU32((UInt)Irrm_ZERO) ); |
| 8424 | } else { |
| 8425 | assign( rmode, get_sse_roundingmode() ); |
| 8426 | } |
| 8427 | |
| 8428 | assign( |
| 8429 | dst64, |
| 8430 | binop( Iop_32HLto64, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8431 | binop( Iop_F64toI32S, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8432 | mkexpr(rmode), |
| 8433 | unop( Iop_F32toF64, mkexpr(f32hi) ) ), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8434 | binop( Iop_F64toI32S, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8435 | mkexpr(rmode), |
| 8436 | unop( Iop_F32toF64, mkexpr(f32lo) ) ) |
| 8437 | ) |
| 8438 | ); |
| 8439 | |
| 8440 | putMMXReg(gregOfRM(modrm), mkexpr(dst64)); |
| 8441 | goto decode_success; |
| 8442 | } |
| 8443 | |
| 8444 | /* F3 0F 2D = CVTSS2SI -- convert F32 in mem/low quarter xmm to |
| 8445 | I32 in ireg, according to prevailing SSE rounding mode */ |
| 8446 | /* F3 0F 2C = CVTTSS2SI -- convert F32 in mem/low quarter xmm to |
sewardj | 0b21044 | 2005-02-23 13:28:27 +0000 | [diff] [blame] | 8447 | I32 in ireg, rounding towards zero */ |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8448 | if (insn[0] == 0xF3 && insn[1] == 0x0F |
| 8449 | && (insn[2] == 0x2D || insn[2] == 0x2C)) { |
| 8450 | IRTemp rmode = newTemp(Ity_I32); |
| 8451 | IRTemp f32lo = newTemp(Ity_F32); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 8452 | Bool r2zero = toBool(insn[2] == 0x2C); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8453 | vassert(sz == 4); |
| 8454 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8455 | modrm = getIByte(delta+3); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8456 | if (epartIsReg(modrm)) { |
| 8457 | delta += 3+1; |
| 8458 | assign(f32lo, getXMMRegLane32F(eregOfRM(modrm), 0)); |
| 8459 | DIP("cvt%sss2si %s,%s\n", r2zero ? "t" : "", |
| 8460 | nameXMMReg(eregOfRM(modrm)), |
| 8461 | nameIReg(4, gregOfRM(modrm))); |
| 8462 | } else { |
| 8463 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 8464 | assign(f32lo, loadLE(Ity_F32, mkexpr(addr))); |
| 8465 | delta += 3+alen; |
| 8466 | DIP("cvt%sss2si %s,%s\n", r2zero ? "t" : "", |
| 8467 | dis_buf, |
| 8468 | nameIReg(4, gregOfRM(modrm))); |
| 8469 | } |
| 8470 | |
| 8471 | if (r2zero) { |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8472 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8473 | } else { |
| 8474 | assign( rmode, get_sse_roundingmode() ); |
| 8475 | } |
| 8476 | |
| 8477 | putIReg(4, gregOfRM(modrm), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8478 | binop( Iop_F64toI32S, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8479 | mkexpr(rmode), |
| 8480 | unop( Iop_F32toF64, mkexpr(f32lo) ) ) |
| 8481 | ); |
| 8482 | |
| 8483 | goto decode_success; |
| 8484 | } |
| 8485 | |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8486 | /* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8487 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5E) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8488 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "divps", Iop_Div32Fx4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8489 | goto decode_success; |
| 8490 | } |
| 8491 | |
| 8492 | /* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */ |
| 8493 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5E) { |
| 8494 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8495 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "divss", Iop_Div32F0x4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8496 | goto decode_success; |
| 8497 | } |
| 8498 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8499 | /* 0F AE /2 = LDMXCSR m32 -- load %mxcsr */ |
| 8500 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 8501 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 2) { |
| 8502 | |
| 8503 | IRTemp t64 = newTemp(Ity_I64); |
| 8504 | IRTemp ew = newTemp(Ity_I32); |
| 8505 | |
| 8506 | modrm = getIByte(delta+2); |
| 8507 | vassert(!epartIsReg(modrm)); |
| 8508 | vassert(sz == 4); |
| 8509 | |
| 8510 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8511 | delta += 2+alen; |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 8512 | DIP("ldmxcsr %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8513 | |
| 8514 | /* The only thing we observe in %mxcsr is the rounding mode. |
| 8515 | Therefore, pass the 32-bit value (SSE native-format control |
| 8516 | word) to a clean helper, getting back a 64-bit value, the |
| 8517 | lower half of which is the SSEROUND value to store, and the |
| 8518 | upper half of which is the emulation-warning token which may |
| 8519 | be generated. |
| 8520 | */ |
| 8521 | /* ULong x86h_check_ldmxcsr ( UInt ); */ |
| 8522 | assign( t64, mkIRExprCCall( |
| 8523 | Ity_I64, 0/*regparms*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 8524 | "x86g_check_ldmxcsr", |
| 8525 | &x86g_check_ldmxcsr, |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8526 | mkIRExprVec_1( loadLE(Ity_I32, mkexpr(addr)) ) |
| 8527 | ) |
| 8528 | ); |
| 8529 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8530 | put_sse_roundingmode( unop(Iop_64to32, mkexpr(t64)) ); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8531 | assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) ); |
| 8532 | put_emwarn( mkexpr(ew) ); |
| 8533 | /* Finally, if an emulation warning was reported, side-exit to |
| 8534 | the next insn, reporting the warning, so that Valgrind's |
| 8535 | dispatcher sees the warning. */ |
| 8536 | stmt( |
| 8537 | IRStmt_Exit( |
| 8538 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 8539 | Ijk_EmWarn, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8540 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8541 | ) |
| 8542 | ); |
| 8543 | goto decode_success; |
| 8544 | } |
| 8545 | |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 8546 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8547 | /* 0F F7 = MASKMOVQ -- 8x8 masked store */ |
| 8548 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xF7) { |
| 8549 | Bool ok = False; |
| 8550 | delta = dis_MMX( &ok, sorb, sz, delta+1 ); |
| 8551 | if (!ok) |
| 8552 | goto decode_failure; |
| 8553 | goto decode_success; |
| 8554 | } |
| 8555 | |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8556 | /* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8557 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5F) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8558 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "maxps", Iop_Max32Fx4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8559 | goto decode_success; |
| 8560 | } |
| 8561 | |
| 8562 | /* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */ |
| 8563 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5F) { |
| 8564 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8565 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "maxss", Iop_Max32F0x4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8566 | goto decode_success; |
| 8567 | } |
| 8568 | |
| 8569 | /* 0F 5D = MINPS -- min 32Fx4 from R/M to R */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8570 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5D) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8571 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "minps", Iop_Min32Fx4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8572 | goto decode_success; |
| 8573 | } |
| 8574 | |
| 8575 | /* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */ |
| 8576 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5D) { |
| 8577 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8578 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "minss", Iop_Min32F0x4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8579 | goto decode_success; |
| 8580 | } |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8581 | |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8582 | /* 0F 28 = MOVAPS -- move from E (mem or xmm) to G (xmm). */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8583 | /* 0F 10 = MOVUPS -- move from E (mem or xmm) to G (xmm). */ |
| 8584 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x28 || insn[1] == 0x10)) { |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8585 | modrm = getIByte(delta+2); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8586 | if (epartIsReg(modrm)) { |
| 8587 | putXMMReg( gregOfRM(modrm), |
| 8588 | getXMMReg( eregOfRM(modrm) )); |
| 8589 | DIP("mov[ua]ps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 8590 | nameXMMReg(gregOfRM(modrm))); |
| 8591 | delta += 2+1; |
| 8592 | } else { |
| 8593 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 8594 | if (insn[1] == 0x28/*movaps*/) |
| 8595 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8596 | putXMMReg( gregOfRM(modrm), |
| 8597 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 8598 | DIP("mov[ua]ps %s,%s\n", dis_buf, |
| 8599 | nameXMMReg(gregOfRM(modrm))); |
| 8600 | delta += 2+alen; |
| 8601 | } |
| 8602 | goto decode_success; |
| 8603 | } |
| 8604 | |
sewardj | 09f4155 | 2004-12-15 12:35:00 +0000 | [diff] [blame] | 8605 | /* 0F 29 = MOVAPS -- move from G (xmm) to E (mem or xmm). */ |
sewardj | 3ed5484 | 2005-08-25 21:34:24 +0000 | [diff] [blame] | 8606 | /* 0F 11 = MOVUPS -- move from G (xmm) to E (mem or xmm). */ |
| 8607 | if (sz == 4 && insn[0] == 0x0F |
| 8608 | && (insn[1] == 0x29 || insn[1] == 0x11)) { |
sewardj | 09f4155 | 2004-12-15 12:35:00 +0000 | [diff] [blame] | 8609 | modrm = getIByte(delta+2); |
sewardj | 09f4155 | 2004-12-15 12:35:00 +0000 | [diff] [blame] | 8610 | if (epartIsReg(modrm)) { |
| 8611 | /* fall through; awaiting test case */ |
| 8612 | } else { |
| 8613 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 8614 | if (insn[1] == 0x29/*movaps*/) |
| 8615 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 09f4155 | 2004-12-15 12:35:00 +0000 | [diff] [blame] | 8616 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
sewardj | 3ed5484 | 2005-08-25 21:34:24 +0000 | [diff] [blame] | 8617 | DIP("mov[ua]ps %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
| 8618 | dis_buf ); |
sewardj | 09f4155 | 2004-12-15 12:35:00 +0000 | [diff] [blame] | 8619 | delta += 2+alen; |
| 8620 | goto decode_success; |
| 8621 | } |
| 8622 | } |
| 8623 | |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8624 | /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */ |
| 8625 | /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8626 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x16) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8627 | modrm = getIByte(delta+2); |
| 8628 | if (epartIsReg(modrm)) { |
| 8629 | delta += 2+1; |
| 8630 | putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, |
| 8631 | getXMMRegLane64( eregOfRM(modrm), 0 ) ); |
| 8632 | DIP("movhps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 8633 | nameXMMReg(gregOfRM(modrm))); |
| 8634 | } else { |
| 8635 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8636 | delta += 2+alen; |
| 8637 | putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, |
| 8638 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 8639 | DIP("movhps %s,%s\n", dis_buf, |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8640 | nameXMMReg( gregOfRM(modrm) )); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8641 | } |
| 8642 | goto decode_success; |
| 8643 | } |
| 8644 | |
| 8645 | /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8646 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x17) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8647 | if (!epartIsReg(insn[2])) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8648 | delta += 2; |
| 8649 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 8650 | delta += alen; |
| 8651 | storeLE( mkexpr(addr), |
| 8652 | getXMMRegLane64( gregOfRM(insn[2]), |
| 8653 | 1/*upper lane*/ ) ); |
| 8654 | DIP("movhps %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 8655 | dis_buf); |
| 8656 | goto decode_success; |
| 8657 | } |
| 8658 | /* else fall through */ |
| 8659 | } |
| 8660 | |
| 8661 | /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */ |
| 8662 | /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8663 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x12) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8664 | modrm = getIByte(delta+2); |
| 8665 | if (epartIsReg(modrm)) { |
| 8666 | delta += 2+1; |
| 8667 | putXMMRegLane64( gregOfRM(modrm), |
| 8668 | 0/*lower lane*/, |
| 8669 | getXMMRegLane64( eregOfRM(modrm), 1 )); |
| 8670 | DIP("movhlps %s, %s\n", nameXMMReg(eregOfRM(modrm)), |
| 8671 | nameXMMReg(gregOfRM(modrm))); |
| 8672 | } else { |
| 8673 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8674 | delta += 2+alen; |
| 8675 | putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/, |
| 8676 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 8677 | DIP("movlps %s, %s\n", |
| 8678 | dis_buf, nameXMMReg( gregOfRM(modrm) )); |
| 8679 | } |
| 8680 | goto decode_success; |
| 8681 | } |
| 8682 | |
| 8683 | /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8684 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x13) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8685 | if (!epartIsReg(insn[2])) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8686 | delta += 2; |
| 8687 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 8688 | delta += alen; |
| 8689 | storeLE( mkexpr(addr), |
| 8690 | getXMMRegLane64( gregOfRM(insn[2]), |
| 8691 | 0/*lower lane*/ ) ); |
| 8692 | DIP("movlps %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 8693 | dis_buf); |
| 8694 | goto decode_success; |
| 8695 | } |
| 8696 | /* else fall through */ |
| 8697 | } |
| 8698 | |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8699 | /* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E) |
| 8700 | to 4 lowest bits of ireg(G) */ |
| 8701 | if (insn[0] == 0x0F && insn[1] == 0x50) { |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8702 | modrm = getIByte(delta+2); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8703 | if (sz == 4 && epartIsReg(modrm)) { |
| 8704 | Int src; |
| 8705 | t0 = newTemp(Ity_I32); |
| 8706 | t1 = newTemp(Ity_I32); |
| 8707 | t2 = newTemp(Ity_I32); |
| 8708 | t3 = newTemp(Ity_I32); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8709 | delta += 2+1; |
| 8710 | src = eregOfRM(modrm); |
| 8711 | assign( t0, binop( Iop_And32, |
| 8712 | binop(Iop_Shr32, getXMMRegLane32(src,0), mkU8(31)), |
| 8713 | mkU32(1) )); |
| 8714 | assign( t1, binop( Iop_And32, |
| 8715 | binop(Iop_Shr32, getXMMRegLane32(src,1), mkU8(30)), |
| 8716 | mkU32(2) )); |
| 8717 | assign( t2, binop( Iop_And32, |
| 8718 | binop(Iop_Shr32, getXMMRegLane32(src,2), mkU8(29)), |
| 8719 | mkU32(4) )); |
| 8720 | assign( t3, binop( Iop_And32, |
| 8721 | binop(Iop_Shr32, getXMMRegLane32(src,3), mkU8(28)), |
| 8722 | mkU32(8) )); |
| 8723 | putIReg(4, gregOfRM(modrm), |
| 8724 | binop(Iop_Or32, |
| 8725 | binop(Iop_Or32, mkexpr(t0), mkexpr(t1)), |
| 8726 | binop(Iop_Or32, mkexpr(t2), mkexpr(t3)) |
| 8727 | ) |
| 8728 | ); |
| 8729 | DIP("movmskps %s,%s\n", nameXMMReg(src), |
| 8730 | nameIReg(4, gregOfRM(modrm))); |
| 8731 | goto decode_success; |
| 8732 | } |
| 8733 | /* else fall through */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8734 | } |
| 8735 | |
| 8736 | /* 0F 2B = MOVNTPS -- for us, just a plain SSE store. */ |
sewardj | 703d6d6 | 2005-05-11 02:55:00 +0000 | [diff] [blame] | 8737 | /* 66 0F 2B = MOVNTPD -- for us, just a plain SSE store. */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8738 | if (insn[0] == 0x0F && insn[1] == 0x2B) { |
| 8739 | modrm = getIByte(delta+2); |
| 8740 | if (!epartIsReg(modrm)) { |
| 8741 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 8742 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8743 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
sewardj | 703d6d6 | 2005-05-11 02:55:00 +0000 | [diff] [blame] | 8744 | DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s", |
| 8745 | dis_buf, |
| 8746 | nameXMMReg(gregOfRM(modrm))); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8747 | delta += 2+alen; |
| 8748 | goto decode_success; |
| 8749 | } |
| 8750 | /* else fall through */ |
| 8751 | } |
| 8752 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8753 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8754 | /* 0F E7 = MOVNTQ -- for us, just a plain MMX store. Note, the |
| 8755 | Intel manual does not say anything about the usual business of |
| 8756 | the FP reg tags getting trashed whenever an MMX insn happens. |
| 8757 | So we just leave them alone. |
| 8758 | */ |
| 8759 | if (insn[0] == 0x0F && insn[1] == 0xE7) { |
| 8760 | modrm = getIByte(delta+2); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8761 | if (sz == 4 && !epartIsReg(modrm)) { |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 8762 | /* do_MMX_preamble(); Intel docs don't specify this */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8763 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8764 | storeLE( mkexpr(addr), getMMXReg(gregOfRM(modrm)) ); |
| 8765 | DIP("movntq %s,%s\n", dis_buf, |
| 8766 | nameMMXReg(gregOfRM(modrm))); |
| 8767 | delta += 2+alen; |
| 8768 | goto decode_success; |
| 8769 | } |
| 8770 | /* else fall through */ |
| 8771 | } |
| 8772 | |
| 8773 | /* F3 0F 10 = MOVSS -- move 32 bits from E (mem or lo 1/4 xmm) to G |
| 8774 | (lo 1/4 xmm). If E is mem, upper 3/4 of G is zeroed out. */ |
| 8775 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x10) { |
| 8776 | vassert(sz == 4); |
| 8777 | modrm = getIByte(delta+3); |
| 8778 | if (epartIsReg(modrm)) { |
| 8779 | putXMMRegLane32( gregOfRM(modrm), 0, |
| 8780 | getXMMRegLane32( eregOfRM(modrm), 0 )); |
| 8781 | DIP("movss %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 8782 | nameXMMReg(gregOfRM(modrm))); |
| 8783 | delta += 3+1; |
| 8784 | } else { |
| 8785 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
sewardj | ad50db0 | 2005-04-06 01:45:44 +0000 | [diff] [blame] | 8786 | /* zero bits 127:64 */ |
| 8787 | putXMMRegLane64( gregOfRM(modrm), 1, mkU64(0) ); |
| 8788 | /* zero bits 63:32 */ |
| 8789 | putXMMRegLane32( gregOfRM(modrm), 1, mkU32(0) ); |
| 8790 | /* write bits 31:0 */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8791 | putXMMRegLane32( gregOfRM(modrm), 0, |
| 8792 | loadLE(Ity_I32, mkexpr(addr)) ); |
| 8793 | DIP("movss %s,%s\n", dis_buf, |
| 8794 | nameXMMReg(gregOfRM(modrm))); |
| 8795 | delta += 3+alen; |
| 8796 | } |
| 8797 | goto decode_success; |
| 8798 | } |
| 8799 | |
| 8800 | /* F3 0F 11 = MOVSS -- move 32 bits from G (lo 1/4 xmm) to E (mem |
| 8801 | or lo 1/4 xmm). */ |
| 8802 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x11) { |
| 8803 | vassert(sz == 4); |
| 8804 | modrm = getIByte(delta+3); |
| 8805 | if (epartIsReg(modrm)) { |
| 8806 | /* fall through, we don't yet have a test case */ |
| 8807 | } else { |
| 8808 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 8809 | storeLE( mkexpr(addr), |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 8810 | getXMMRegLane32(gregOfRM(modrm), 0) ); |
| 8811 | DIP("movss %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8812 | dis_buf); |
| 8813 | delta += 3+alen; |
| 8814 | goto decode_success; |
| 8815 | } |
| 8816 | } |
| 8817 | |
| 8818 | /* 0F 59 = MULPS -- mul 32Fx4 from R/M to R */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 8819 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x59) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8820 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "mulps", Iop_Mul32Fx4 ); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8821 | goto decode_success; |
| 8822 | } |
| 8823 | |
| 8824 | /* F3 0F 59 = MULSS -- mul 32F0x4 from R/M to R */ |
| 8825 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x59) { |
| 8826 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8827 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "mulss", Iop_Mul32F0x4 ); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8828 | goto decode_success; |
| 8829 | } |
| 8830 | |
| 8831 | /* 0F 56 = ORPS -- G = G and E */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 8832 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x56) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 8833 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "orps", Iop_OrV128 ); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8834 | goto decode_success; |
| 8835 | } |
| 8836 | |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8837 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8838 | /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */ |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 8839 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE0) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8840 | do_MMX_preamble(); |
| 8841 | delta = dis_MMXop_regmem_to_reg ( |
| 8842 | sorb, delta+2, insn[1], "pavgb", False ); |
| 8843 | goto decode_success; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8844 | } |
| 8845 | |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8846 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8847 | /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */ |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 8848 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE3) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8849 | do_MMX_preamble(); |
| 8850 | delta = dis_MMXop_regmem_to_reg ( |
| 8851 | sorb, delta+2, insn[1], "pavgw", False ); |
| 8852 | goto decode_success; |
| 8853 | } |
| 8854 | |
| 8855 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8856 | /* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put |
| 8857 | zero-extend of it in ireg(G). */ |
| 8858 | if (insn[0] == 0x0F && insn[1] == 0xC5) { |
| 8859 | modrm = insn[2]; |
| 8860 | if (sz == 4 && epartIsReg(modrm)) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8861 | IRTemp sV = newTemp(Ity_I64); |
| 8862 | t5 = newTemp(Ity_I16); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8863 | do_MMX_preamble(); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8864 | assign(sV, getMMXReg(eregOfRM(modrm))); |
| 8865 | breakup64to16s( sV, &t3, &t2, &t1, &t0 ); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8866 | switch (insn[3] & 3) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8867 | case 0: assign(t5, mkexpr(t0)); break; |
| 8868 | case 1: assign(t5, mkexpr(t1)); break; |
| 8869 | case 2: assign(t5, mkexpr(t2)); break; |
| 8870 | case 3: assign(t5, mkexpr(t3)); break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 8871 | default: vassert(0); /*NOTREACHED*/ |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8872 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8873 | putIReg(4, gregOfRM(modrm), unop(Iop_16Uto32, mkexpr(t5))); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8874 | DIP("pextrw $%d,%s,%s\n", |
| 8875 | (Int)insn[3], nameMMXReg(eregOfRM(modrm)), |
| 8876 | nameIReg(4,gregOfRM(modrm))); |
| 8877 | delta += 4; |
| 8878 | goto decode_success; |
| 8879 | } |
| 8880 | /* else fall through */ |
| 8881 | } |
| 8882 | |
| 8883 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8884 | /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and |
| 8885 | put it into the specified lane of mmx(G). */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8886 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC4) { |
| 8887 | /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the |
| 8888 | mmx reg. t4 is the new lane value. t5 is the original |
| 8889 | mmx value. t6 is the new mmx value. */ |
| 8890 | Int lane; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8891 | t4 = newTemp(Ity_I16); |
| 8892 | t5 = newTemp(Ity_I64); |
| 8893 | t6 = newTemp(Ity_I64); |
| 8894 | modrm = insn[2]; |
| 8895 | do_MMX_preamble(); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8896 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8897 | assign(t5, getMMXReg(gregOfRM(modrm))); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8898 | breakup64to16s( t5, &t3, &t2, &t1, &t0 ); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8899 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8900 | if (epartIsReg(modrm)) { |
| 8901 | assign(t4, getIReg(2, eregOfRM(modrm))); |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 8902 | delta += 3+1; |
| 8903 | lane = insn[3+1-1]; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8904 | DIP("pinsrw $%d,%s,%s\n", (Int)lane, |
| 8905 | nameIReg(2,eregOfRM(modrm)), |
| 8906 | nameMMXReg(gregOfRM(modrm))); |
| 8907 | } else { |
sewardj | 7420b09 | 2005-03-13 20:19:19 +0000 | [diff] [blame] | 8908 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8909 | delta += 3+alen; |
| 8910 | lane = insn[3+alen-1]; |
| 8911 | assign(t4, loadLE(Ity_I16, mkexpr(addr))); |
| 8912 | DIP("pinsrw $%d,%s,%s\n", (Int)lane, |
| 8913 | dis_buf, |
| 8914 | nameMMXReg(gregOfRM(modrm))); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8915 | } |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8916 | |
| 8917 | switch (lane & 3) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8918 | case 0: assign(t6, mk64from16s(t3,t2,t1,t4)); break; |
| 8919 | case 1: assign(t6, mk64from16s(t3,t2,t4,t0)); break; |
| 8920 | case 2: assign(t6, mk64from16s(t3,t4,t1,t0)); break; |
| 8921 | case 3: assign(t6, mk64from16s(t4,t2,t1,t0)); break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 8922 | default: vassert(0); /*NOTREACHED*/ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8923 | } |
| 8924 | putMMXReg(gregOfRM(modrm), mkexpr(t6)); |
| 8925 | goto decode_success; |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8926 | } |
| 8927 | |
| 8928 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8929 | /* 0F EE = PMAXSW -- 16x4 signed max */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8930 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xEE) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8931 | do_MMX_preamble(); |
| 8932 | delta = dis_MMXop_regmem_to_reg ( |
| 8933 | sorb, delta+2, insn[1], "pmaxsw", False ); |
| 8934 | goto decode_success; |
| 8935 | } |
| 8936 | |
| 8937 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8938 | /* 0F DE = PMAXUB -- 8x8 unsigned max */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8939 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xDE) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8940 | do_MMX_preamble(); |
| 8941 | delta = dis_MMXop_regmem_to_reg ( |
| 8942 | sorb, delta+2, insn[1], "pmaxub", False ); |
| 8943 | goto decode_success; |
| 8944 | } |
| 8945 | |
| 8946 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8947 | /* 0F EA = PMINSW -- 16x4 signed min */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8948 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xEA) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8949 | do_MMX_preamble(); |
| 8950 | delta = dis_MMXop_regmem_to_reg ( |
| 8951 | sorb, delta+2, insn[1], "pminsw", False ); |
| 8952 | goto decode_success; |
| 8953 | } |
| 8954 | |
| 8955 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8956 | /* 0F DA = PMINUB -- 8x8 unsigned min */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8957 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xDA) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8958 | do_MMX_preamble(); |
| 8959 | delta = dis_MMXop_regmem_to_reg ( |
| 8960 | sorb, delta+2, insn[1], "pminub", False ); |
| 8961 | goto decode_success; |
| 8962 | } |
| 8963 | |
| 8964 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8965 | /* 0F D7 = PMOVMSKB -- extract sign bits from each of 8 lanes in |
| 8966 | mmx(G), turn them into a byte, and put zero-extend of it in |
| 8967 | ireg(G). */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8968 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xD7) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8969 | modrm = insn[2]; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8970 | if (epartIsReg(modrm)) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8971 | do_MMX_preamble(); |
| 8972 | t0 = newTemp(Ity_I64); |
| 8973 | t1 = newTemp(Ity_I32); |
| 8974 | assign(t0, getMMXReg(eregOfRM(modrm))); |
| 8975 | assign(t1, mkIRExprCCall( |
| 8976 | Ity_I32, 0/*regparms*/, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 8977 | "x86g_calculate_mmx_pmovmskb", |
| 8978 | &x86g_calculate_mmx_pmovmskb, |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8979 | mkIRExprVec_1(mkexpr(t0)))); |
| 8980 | putIReg(4, gregOfRM(modrm), mkexpr(t1)); |
| 8981 | DIP("pmovmskb %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 8982 | nameIReg(4,gregOfRM(modrm))); |
| 8983 | delta += 3; |
| 8984 | goto decode_success; |
| 8985 | } |
| 8986 | /* else fall through */ |
| 8987 | } |
| 8988 | |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8989 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8990 | /* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8991 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE4) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8992 | do_MMX_preamble(); |
| 8993 | delta = dis_MMXop_regmem_to_reg ( |
| 8994 | sorb, delta+2, insn[1], "pmuluh", False ); |
| 8995 | goto decode_success; |
| 8996 | } |
| 8997 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8998 | /* 0F 18 /0 = PREFETCHNTA -- prefetch into caches, */ |
| 8999 | /* 0F 18 /1 = PREFETCH0 -- with various different hints */ |
| 9000 | /* 0F 18 /2 = PREFETCH1 */ |
| 9001 | /* 0F 18 /3 = PREFETCH2 */ |
| 9002 | if (insn[0] == 0x0F && insn[1] == 0x18 |
| 9003 | && !epartIsReg(insn[2]) |
| 9004 | && gregOfRM(insn[2]) >= 0 && gregOfRM(insn[2]) <= 3) { |
| 9005 | HChar* hintstr = "??"; |
| 9006 | |
| 9007 | modrm = getIByte(delta+2); |
| 9008 | vassert(!epartIsReg(modrm)); |
| 9009 | |
| 9010 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9011 | delta += 2+alen; |
| 9012 | |
| 9013 | switch (gregOfRM(modrm)) { |
| 9014 | case 0: hintstr = "nta"; break; |
| 9015 | case 1: hintstr = "t0"; break; |
| 9016 | case 2: hintstr = "t1"; break; |
| 9017 | case 3: hintstr = "t2"; break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 9018 | default: vassert(0); /*NOTREACHED*/ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9019 | } |
| 9020 | |
| 9021 | DIP("prefetch%s %s\n", hintstr, dis_buf); |
| 9022 | goto decode_success; |
| 9023 | } |
| 9024 | |
sewardj | 8531768 | 2006-03-06 14:07:58 +0000 | [diff] [blame] | 9025 | /* 0F 0D /0 = PREFETCH m8 -- 3DNow! prefetch */ |
| 9026 | /* 0F 0D /1 = PREFETCHW m8 -- ditto, with some other hint */ |
| 9027 | if (insn[0] == 0x0F && insn[1] == 0x0D |
| 9028 | && !epartIsReg(insn[2]) |
| 9029 | && gregOfRM(insn[2]) >= 0 && gregOfRM(insn[2]) <= 1) { |
| 9030 | HChar* hintstr = "??"; |
| 9031 | |
| 9032 | modrm = getIByte(delta+2); |
| 9033 | vassert(!epartIsReg(modrm)); |
| 9034 | |
| 9035 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9036 | delta += 2+alen; |
| 9037 | |
| 9038 | switch (gregOfRM(modrm)) { |
| 9039 | case 0: hintstr = ""; break; |
| 9040 | case 1: hintstr = "w"; break; |
| 9041 | default: vassert(0); /*NOTREACHED*/ |
| 9042 | } |
| 9043 | |
| 9044 | DIP("prefetch%s %s\n", hintstr, dis_buf); |
| 9045 | goto decode_success; |
| 9046 | } |
| 9047 | |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9048 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 9049 | /* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */ |
sewardj | 7b5b998 | 2005-10-04 11:43:37 +0000 | [diff] [blame] | 9050 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xF6) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9051 | do_MMX_preamble(); |
| 9052 | delta = dis_MMXop_regmem_to_reg ( |
| 9053 | sorb, delta+2, insn[1], "psadbw", False ); |
| 9054 | goto decode_success; |
| 9055 | } |
| 9056 | |
| 9057 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 9058 | /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9059 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x70) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9060 | Int order; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9061 | IRTemp sV, dV, s3, s2, s1, s0; |
| 9062 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 9063 | sV = newTemp(Ity_I64); |
| 9064 | dV = newTemp(Ity_I64); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9065 | do_MMX_preamble(); |
| 9066 | modrm = insn[2]; |
| 9067 | if (epartIsReg(modrm)) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9068 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9069 | order = (Int)insn[3]; |
| 9070 | delta += 2+2; |
| 9071 | DIP("pshufw $%d,%s,%s\n", order, |
| 9072 | nameMMXReg(eregOfRM(modrm)), |
| 9073 | nameMMXReg(gregOfRM(modrm))); |
| 9074 | } else { |
| 9075 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9076 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9077 | order = (Int)insn[2+alen]; |
| 9078 | delta += 3+alen; |
| 9079 | DIP("pshufw $%d,%s,%s\n", order, |
| 9080 | dis_buf, |
| 9081 | nameMMXReg(gregOfRM(modrm))); |
| 9082 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9083 | breakup64to16s( sV, &s3, &s2, &s1, &s0 ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9084 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9085 | # define SEL(n) \ |
| 9086 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 9087 | assign(dV, |
| 9088 | mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 9089 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9090 | ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9091 | putMMXReg(gregOfRM(modrm), mkexpr(dV)); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9092 | # undef SEL |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9093 | goto decode_success; |
| 9094 | } |
| 9095 | |
| 9096 | /* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */ |
| 9097 | if (insn[0] == 0x0F && insn[1] == 0x53) { |
| 9098 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 9099 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
| 9100 | "rcpps", Iop_Recip32Fx4 ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9101 | goto decode_success; |
| 9102 | } |
| 9103 | |
| 9104 | /* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */ |
| 9105 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x53) { |
| 9106 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 9107 | delta = dis_SSE_E_to_G_unary_lo32( sorb, delta+3, |
| 9108 | "rcpss", Iop_Recip32F0x4 ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9109 | goto decode_success; |
| 9110 | } |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 9111 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9112 | /* 0F 52 = RSQRTPS -- approx reciprocal sqrt 32Fx4 from R/M to R */ |
| 9113 | if (insn[0] == 0x0F && insn[1] == 0x52) { |
| 9114 | vassert(sz == 4); |
| 9115 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
| 9116 | "rsqrtps", Iop_RSqrt32Fx4 ); |
| 9117 | goto decode_success; |
| 9118 | } |
| 9119 | |
| 9120 | /* F3 0F 52 = RSQRTSS -- approx reciprocal sqrt 32F0x4 from R/M to R */ |
| 9121 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x52) { |
| 9122 | vassert(sz == 4); |
| 9123 | delta = dis_SSE_E_to_G_unary_lo32( sorb, delta+3, |
| 9124 | "rsqrtss", Iop_RSqrt32F0x4 ); |
| 9125 | goto decode_success; |
| 9126 | } |
| 9127 | |
| 9128 | /* 0F AE /7 = SFENCE -- flush pending operations to memory */ |
| 9129 | if (insn[0] == 0x0F && insn[1] == 0xAE |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 9130 | && epartIsReg(insn[2]) && gregOfRM(insn[2]) == 7) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9131 | vassert(sz == 4); |
| 9132 | delta += 3; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 9133 | /* Insert a memory fence. It's sometimes important that these |
| 9134 | are carried through to the generated code. */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 9135 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9136 | DIP("sfence\n"); |
| 9137 | goto decode_success; |
| 9138 | } |
| 9139 | |
| 9140 | /* 0F C6 /r ib = SHUFPS -- shuffle packed F32s */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9141 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC6) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9142 | Int select; |
| 9143 | IRTemp sV, dV; |
| 9144 | IRTemp s3, s2, s1, s0, d3, d2, d1, d0; |
| 9145 | sV = newTemp(Ity_V128); |
| 9146 | dV = newTemp(Ity_V128); |
| 9147 | s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9148 | modrm = insn[2]; |
| 9149 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 9150 | |
| 9151 | if (epartIsReg(modrm)) { |
| 9152 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 9153 | select = (Int)insn[3]; |
| 9154 | delta += 2+2; |
| 9155 | DIP("shufps $%d,%s,%s\n", select, |
| 9156 | nameXMMReg(eregOfRM(modrm)), |
| 9157 | nameXMMReg(gregOfRM(modrm))); |
| 9158 | } else { |
| 9159 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9160 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9161 | select = (Int)insn[2+alen]; |
| 9162 | delta += 3+alen; |
| 9163 | DIP("shufps $%d,%s,%s\n", select, |
| 9164 | dis_buf, |
| 9165 | nameXMMReg(gregOfRM(modrm))); |
| 9166 | } |
| 9167 | |
| 9168 | breakup128to32s( dV, &d3, &d2, &d1, &d0 ); |
| 9169 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 9170 | |
| 9171 | # define SELD(n) ((n)==0 ? d0 : ((n)==1 ? d1 : ((n)==2 ? d2 : d3))) |
| 9172 | # define SELS(n) ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 9173 | |
| 9174 | putXMMReg( |
| 9175 | gregOfRM(modrm), |
| 9176 | mk128from32s( SELS((select>>6)&3), SELS((select>>4)&3), |
| 9177 | SELD((select>>2)&3), SELD((select>>0)&3) ) |
| 9178 | ); |
| 9179 | |
| 9180 | # undef SELD |
| 9181 | # undef SELS |
| 9182 | |
| 9183 | goto decode_success; |
| 9184 | } |
| 9185 | |
| 9186 | /* 0F 51 = SQRTPS -- approx sqrt 32Fx4 from R/M to R */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9187 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x51) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9188 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
| 9189 | "sqrtps", Iop_Sqrt32Fx4 ); |
| 9190 | goto decode_success; |
| 9191 | } |
| 9192 | |
| 9193 | /* F3 0F 51 = SQRTSS -- approx sqrt 32F0x4 from R/M to R */ |
| 9194 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x51) { |
| 9195 | vassert(sz == 4); |
| 9196 | delta = dis_SSE_E_to_G_unary_lo32( sorb, delta+3, |
| 9197 | "sqrtss", Iop_Sqrt32F0x4 ); |
| 9198 | goto decode_success; |
| 9199 | } |
| 9200 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 9201 | /* 0F AE /3 = STMXCSR m32 -- store %mxcsr */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9202 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 9203 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 3) { |
| 9204 | modrm = getIByte(delta+2); |
| 9205 | vassert(sz == 4); |
| 9206 | vassert(!epartIsReg(modrm)); |
| 9207 | |
| 9208 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9209 | delta += 2+alen; |
| 9210 | |
| 9211 | /* Fake up a native SSE mxcsr word. The only thing it depends |
| 9212 | on is SSEROUND[1:0], so call a clean helper to cook it up. |
| 9213 | */ |
| 9214 | /* UInt x86h_create_mxcsr ( UInt sseround ) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 9215 | DIP("stmxcsr %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9216 | storeLE( mkexpr(addr), |
| 9217 | mkIRExprCCall( |
| 9218 | Ity_I32, 0/*regp*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 9219 | "x86g_create_mxcsr", &x86g_create_mxcsr, |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 9220 | mkIRExprVec_1( get_sse_roundingmode() ) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9221 | ) |
| 9222 | ); |
| 9223 | goto decode_success; |
| 9224 | } |
| 9225 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9226 | /* 0F 5C = SUBPS -- sub 32Fx4 from R/M to R */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9227 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5C) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9228 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "subps", Iop_Sub32Fx4 ); |
| 9229 | goto decode_success; |
| 9230 | } |
| 9231 | |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9232 | /* F3 0F 5C = SUBSS -- sub 32F0x4 from R/M to R */ |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9233 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5C) { |
| 9234 | vassert(sz == 4); |
| 9235 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "subss", Iop_Sub32F0x4 ); |
| 9236 | goto decode_success; |
| 9237 | } |
| 9238 | |
| 9239 | /* 0F 15 = UNPCKHPS -- unpack and interleave high part F32s */ |
| 9240 | /* 0F 14 = UNPCKLPS -- unpack and interleave low part F32s */ |
| 9241 | /* These just appear to be special cases of SHUFPS */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9242 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9243 | IRTemp sV, dV; |
| 9244 | IRTemp s3, s2, s1, s0, d3, d2, d1, d0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 9245 | Bool hi = toBool(insn[1] == 0x15); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9246 | sV = newTemp(Ity_V128); |
| 9247 | dV = newTemp(Ity_V128); |
| 9248 | s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9249 | modrm = insn[2]; |
| 9250 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 9251 | |
| 9252 | if (epartIsReg(modrm)) { |
| 9253 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 9254 | delta += 2+1; |
| 9255 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 9256 | nameXMMReg(eregOfRM(modrm)), |
| 9257 | nameXMMReg(gregOfRM(modrm))); |
| 9258 | } else { |
| 9259 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9260 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9261 | delta += 2+alen; |
| 9262 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 9263 | dis_buf, |
| 9264 | nameXMMReg(gregOfRM(modrm))); |
| 9265 | } |
| 9266 | |
| 9267 | breakup128to32s( dV, &d3, &d2, &d1, &d0 ); |
| 9268 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 9269 | |
| 9270 | if (hi) { |
| 9271 | putXMMReg( gregOfRM(modrm), mk128from32s( s3, d3, s2, d2 ) ); |
| 9272 | } else { |
| 9273 | putXMMReg( gregOfRM(modrm), mk128from32s( s1, d1, s0, d0 ) ); |
| 9274 | } |
| 9275 | |
| 9276 | goto decode_success; |
| 9277 | } |
| 9278 | |
| 9279 | /* 0F 57 = XORPS -- G = G and E */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9280 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x57) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9281 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "xorps", Iop_XorV128 ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9282 | goto decode_success; |
| 9283 | } |
| 9284 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9285 | /* ---------------------------------------------------- */ |
| 9286 | /* --- end of the SSE decoder. --- */ |
| 9287 | /* ---------------------------------------------------- */ |
| 9288 | |
| 9289 | /* ---------------------------------------------------- */ |
| 9290 | /* --- start of the SSE2 decoder. --- */ |
| 9291 | /* ---------------------------------------------------- */ |
| 9292 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 9293 | /* Skip parts of the decoder which don't apply given the stated |
| 9294 | guest subarchitecture. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9295 | if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2)) |
| 9296 | goto after_sse_decoders; /* no SSE2 capabilities */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 9297 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9298 | insn = (UChar*)&guest_code[delta]; |
| 9299 | |
| 9300 | /* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */ |
| 9301 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x58) { |
| 9302 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "addpd", Iop_Add64Fx2 ); |
| 9303 | goto decode_success; |
| 9304 | } |
| 9305 | |
| 9306 | /* F2 0F 58 = ADDSD -- add 64F0x2 from R/M to R */ |
| 9307 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x58) { |
| 9308 | vassert(sz == 4); |
| 9309 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "addsd", Iop_Add64F0x2 ); |
| 9310 | goto decode_success; |
| 9311 | } |
| 9312 | |
| 9313 | /* 66 0F 55 = ANDNPD -- G = (not G) and E */ |
| 9314 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x55) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9315 | delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "andnpd", Iop_AndV128 ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9316 | goto decode_success; |
| 9317 | } |
| 9318 | |
| 9319 | /* 66 0F 54 = ANDPD -- G = G and E */ |
| 9320 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x54) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9321 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "andpd", Iop_AndV128 ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9322 | goto decode_success; |
| 9323 | } |
| 9324 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9325 | /* 66 0F C2 = CMPPD -- 64Fx2 comparison from R/M to R */ |
| 9326 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC2) { |
| 9327 | delta = dis_SSEcmp_E_to_G( sorb, delta+2, "cmppd", True, 8 ); |
| 9328 | goto decode_success; |
| 9329 | } |
| 9330 | |
| 9331 | /* F2 0F C2 = CMPSD -- 64F0x2 comparison from R/M to R */ |
| 9332 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xC2) { |
| 9333 | vassert(sz == 4); |
| 9334 | delta = dis_SSEcmp_E_to_G( sorb, delta+3, "cmpsd", False, 8 ); |
| 9335 | goto decode_success; |
| 9336 | } |
| 9337 | |
| 9338 | /* 66 0F 2F = COMISD -- 64F0x2 comparison G,E, and set ZCP */ |
| 9339 | /* 66 0F 2E = UCOMISD -- 64F0x2 comparison G,E, and set ZCP */ |
| 9340 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) { |
| 9341 | IRTemp argL = newTemp(Ity_F64); |
| 9342 | IRTemp argR = newTemp(Ity_F64); |
| 9343 | modrm = getIByte(delta+2); |
| 9344 | if (epartIsReg(modrm)) { |
| 9345 | assign( argR, getXMMRegLane64F( eregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 9346 | delta += 2+1; |
| 9347 | DIP("[u]comisd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9348 | nameXMMReg(gregOfRM(modrm)) ); |
| 9349 | } else { |
| 9350 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9351 | assign( argR, loadLE(Ity_F64, mkexpr(addr)) ); |
| 9352 | delta += 2+alen; |
| 9353 | DIP("[u]comisd %s,%s\n", dis_buf, |
| 9354 | nameXMMReg(gregOfRM(modrm)) ); |
| 9355 | } |
| 9356 | assign( argL, getXMMRegLane64F( gregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 9357 | |
| 9358 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 9359 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 9360 | stmt( IRStmt_Put( |
| 9361 | OFFB_CC_DEP1, |
| 9362 | binop( Iop_And32, |
| 9363 | binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)), |
| 9364 | mkU32(0x45) |
| 9365 | ))); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 9366 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 9367 | elimination of previous stores to this field work better. */ |
| 9368 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9369 | goto decode_success; |
| 9370 | } |
| 9371 | |
| 9372 | /* F3 0F E6 = CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x |
| 9373 | F64 in xmm(G) */ |
| 9374 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xE6) { |
| 9375 | IRTemp arg64 = newTemp(Ity_I64); |
| 9376 | vassert(sz == 4); |
| 9377 | |
| 9378 | modrm = getIByte(delta+3); |
| 9379 | if (epartIsReg(modrm)) { |
| 9380 | assign( arg64, getXMMRegLane64(eregOfRM(modrm), 0) ); |
| 9381 | delta += 3+1; |
| 9382 | DIP("cvtdq2pd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9383 | nameXMMReg(gregOfRM(modrm))); |
| 9384 | } else { |
| 9385 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9386 | assign( arg64, loadLE(Ity_I64, mkexpr(addr)) ); |
| 9387 | delta += 3+alen; |
| 9388 | DIP("cvtdq2pd %s,%s\n", dis_buf, |
| 9389 | nameXMMReg(gregOfRM(modrm)) ); |
| 9390 | } |
| 9391 | |
| 9392 | putXMMRegLane64F( |
| 9393 | gregOfRM(modrm), 0, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9394 | unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64))) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9395 | ); |
| 9396 | |
| 9397 | putXMMRegLane64F( |
| 9398 | gregOfRM(modrm), 1, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9399 | unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64))) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9400 | ); |
| 9401 | |
| 9402 | goto decode_success; |
| 9403 | } |
| 9404 | |
| 9405 | /* 0F 5B = CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 in |
| 9406 | xmm(G) */ |
| 9407 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5B) { |
| 9408 | IRTemp argV = newTemp(Ity_V128); |
| 9409 | IRTemp rmode = newTemp(Ity_I32); |
| 9410 | |
| 9411 | modrm = getIByte(delta+2); |
| 9412 | if (epartIsReg(modrm)) { |
| 9413 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9414 | delta += 2+1; |
| 9415 | DIP("cvtdq2ps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9416 | nameXMMReg(gregOfRM(modrm))); |
| 9417 | } else { |
| 9418 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9419 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9420 | delta += 2+alen; |
| 9421 | DIP("cvtdq2ps %s,%s\n", dis_buf, |
| 9422 | nameXMMReg(gregOfRM(modrm)) ); |
| 9423 | } |
| 9424 | |
| 9425 | assign( rmode, get_sse_roundingmode() ); |
| 9426 | breakup128to32s( argV, &t3, &t2, &t1, &t0 ); |
| 9427 | |
| 9428 | # define CVT(_t) binop( Iop_F64toF32, \ |
| 9429 | mkexpr(rmode), \ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9430 | unop(Iop_I32StoF64,mkexpr(_t))) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9431 | |
| 9432 | putXMMRegLane32F( gregOfRM(modrm), 3, CVT(t3) ); |
| 9433 | putXMMRegLane32F( gregOfRM(modrm), 2, CVT(t2) ); |
| 9434 | putXMMRegLane32F( gregOfRM(modrm), 1, CVT(t1) ); |
| 9435 | putXMMRegLane32F( gregOfRM(modrm), 0, CVT(t0) ); |
| 9436 | |
| 9437 | # undef CVT |
| 9438 | |
| 9439 | goto decode_success; |
| 9440 | } |
| 9441 | |
| 9442 | /* F2 0F E6 = CVTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in |
| 9443 | lo half xmm(G), and zero upper half */ |
| 9444 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xE6) { |
| 9445 | IRTemp argV = newTemp(Ity_V128); |
| 9446 | IRTemp rmode = newTemp(Ity_I32); |
| 9447 | vassert(sz == 4); |
| 9448 | |
| 9449 | modrm = getIByte(delta+3); |
| 9450 | if (epartIsReg(modrm)) { |
| 9451 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9452 | delta += 3+1; |
| 9453 | DIP("cvtpd2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9454 | nameXMMReg(gregOfRM(modrm))); |
| 9455 | } else { |
| 9456 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9457 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9458 | delta += 3+alen; |
| 9459 | DIP("cvtpd2dq %s,%s\n", dis_buf, |
| 9460 | nameXMMReg(gregOfRM(modrm)) ); |
| 9461 | } |
| 9462 | |
| 9463 | assign( rmode, get_sse_roundingmode() ); |
| 9464 | t0 = newTemp(Ity_F64); |
| 9465 | t1 = newTemp(Ity_F64); |
| 9466 | assign( t0, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9467 | unop(Iop_V128to64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9468 | assign( t1, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9469 | unop(Iop_V128HIto64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9470 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9471 | # define CVT(_t) binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9472 | mkexpr(rmode), \ |
| 9473 | mkexpr(_t) ) |
| 9474 | |
| 9475 | putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); |
| 9476 | putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); |
| 9477 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 9478 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 9479 | |
| 9480 | # undef CVT |
| 9481 | |
| 9482 | goto decode_success; |
| 9483 | } |
| 9484 | |
| 9485 | /* 66 0F 2D = CVTPD2PI -- convert 2 x F64 in mem/xmm to 2 x |
| 9486 | I32 in mmx, according to prevailing SSE rounding mode */ |
| 9487 | /* 66 0F 2C = CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x |
| 9488 | I32 in mmx, rounding towards zero */ |
| 9489 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) { |
| 9490 | IRTemp dst64 = newTemp(Ity_I64); |
| 9491 | IRTemp rmode = newTemp(Ity_I32); |
| 9492 | IRTemp f64lo = newTemp(Ity_F64); |
| 9493 | IRTemp f64hi = newTemp(Ity_F64); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 9494 | Bool r2zero = toBool(insn[1] == 0x2C); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9495 | |
| 9496 | do_MMX_preamble(); |
| 9497 | modrm = getIByte(delta+2); |
| 9498 | |
| 9499 | if (epartIsReg(modrm)) { |
| 9500 | delta += 2+1; |
| 9501 | assign(f64lo, getXMMRegLane64F(eregOfRM(modrm), 0)); |
| 9502 | assign(f64hi, getXMMRegLane64F(eregOfRM(modrm), 1)); |
| 9503 | DIP("cvt%spd2pi %s,%s\n", r2zero ? "t" : "", |
| 9504 | nameXMMReg(eregOfRM(modrm)), |
| 9505 | nameMMXReg(gregOfRM(modrm))); |
| 9506 | } else { |
| 9507 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9508 | assign(f64lo, loadLE(Ity_F64, mkexpr(addr))); |
| 9509 | assign(f64hi, loadLE(Ity_F64, binop( Iop_Add32, |
| 9510 | mkexpr(addr), |
| 9511 | mkU32(8) ))); |
| 9512 | delta += 2+alen; |
| 9513 | DIP("cvt%spf2pi %s,%s\n", r2zero ? "t" : "", |
| 9514 | dis_buf, |
| 9515 | nameMMXReg(gregOfRM(modrm))); |
| 9516 | } |
| 9517 | |
| 9518 | if (r2zero) { |
| 9519 | assign(rmode, mkU32((UInt)Irrm_ZERO) ); |
| 9520 | } else { |
| 9521 | assign( rmode, get_sse_roundingmode() ); |
| 9522 | } |
| 9523 | |
| 9524 | assign( |
| 9525 | dst64, |
| 9526 | binop( Iop_32HLto64, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9527 | binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64hi) ), |
| 9528 | binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo) ) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9529 | ) |
| 9530 | ); |
| 9531 | |
| 9532 | putMMXReg(gregOfRM(modrm), mkexpr(dst64)); |
| 9533 | goto decode_success; |
| 9534 | } |
| 9535 | |
| 9536 | /* 66 0F 5A = CVTPD2PS -- convert 2 x F64 in mem/xmm to 2 x F32 in |
| 9537 | lo half xmm(G), and zero upper half */ |
| 9538 | /* Note, this is practically identical to CVTPD2DQ. It would have |
| 9539 | been nicer to merge them together, but the insn[] offsets differ |
| 9540 | by one. */ |
| 9541 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5A) { |
| 9542 | IRTemp argV = newTemp(Ity_V128); |
| 9543 | IRTemp rmode = newTemp(Ity_I32); |
| 9544 | |
| 9545 | modrm = getIByte(delta+2); |
| 9546 | if (epartIsReg(modrm)) { |
| 9547 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9548 | delta += 2+1; |
| 9549 | DIP("cvtpd2ps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9550 | nameXMMReg(gregOfRM(modrm))); |
| 9551 | } else { |
| 9552 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9553 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9554 | delta += 2+alen; |
| 9555 | DIP("cvtpd2ps %s,%s\n", dis_buf, |
| 9556 | nameXMMReg(gregOfRM(modrm)) ); |
| 9557 | } |
| 9558 | |
| 9559 | assign( rmode, get_sse_roundingmode() ); |
| 9560 | t0 = newTemp(Ity_F64); |
| 9561 | t1 = newTemp(Ity_F64); |
| 9562 | assign( t0, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9563 | unop(Iop_V128to64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9564 | assign( t1, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9565 | unop(Iop_V128HIto64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9566 | |
| 9567 | # define CVT(_t) binop( Iop_F64toF32, \ |
| 9568 | mkexpr(rmode), \ |
| 9569 | mkexpr(_t) ) |
| 9570 | |
| 9571 | putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); |
| 9572 | putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); |
| 9573 | putXMMRegLane32F( gregOfRM(modrm), 1, CVT(t1) ); |
| 9574 | putXMMRegLane32F( gregOfRM(modrm), 0, CVT(t0) ); |
| 9575 | |
| 9576 | # undef CVT |
| 9577 | |
| 9578 | goto decode_success; |
| 9579 | } |
| 9580 | |
| 9581 | /* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in |
| 9582 | xmm(G) */ |
| 9583 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x2A) { |
| 9584 | IRTemp arg64 = newTemp(Ity_I64); |
| 9585 | |
| 9586 | modrm = getIByte(delta+2); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9587 | if (epartIsReg(modrm)) { |
sewardj | 30a20e9 | 2010-02-21 20:40:53 +0000 | [diff] [blame] | 9588 | /* Only switch to MMX mode if the source is a MMX register. |
| 9589 | This is inconsistent with all other instructions which |
| 9590 | convert between XMM and (M64 or MMX), which always switch |
| 9591 | to MMX mode even if 64-bit operand is M64 and not MMX. At |
| 9592 | least, that's what the Intel docs seem to me to say. |
| 9593 | Fixes #210264. */ |
| 9594 | do_MMX_preamble(); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9595 | assign( arg64, getMMXReg(eregOfRM(modrm)) ); |
| 9596 | delta += 2+1; |
| 9597 | DIP("cvtpi2pd %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 9598 | nameXMMReg(gregOfRM(modrm))); |
| 9599 | } else { |
| 9600 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9601 | assign( arg64, loadLE(Ity_I64, mkexpr(addr)) ); |
| 9602 | delta += 2+alen; |
| 9603 | DIP("cvtpi2pd %s,%s\n", dis_buf, |
| 9604 | nameXMMReg(gregOfRM(modrm)) ); |
| 9605 | } |
| 9606 | |
| 9607 | putXMMRegLane64F( |
| 9608 | gregOfRM(modrm), 0, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9609 | unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) ) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9610 | ); |
| 9611 | |
| 9612 | putXMMRegLane64F( |
| 9613 | gregOfRM(modrm), 1, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9614 | unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) ) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9615 | ); |
| 9616 | |
| 9617 | goto decode_success; |
| 9618 | } |
| 9619 | |
| 9620 | /* 66 0F 5B = CVTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in |
| 9621 | xmm(G) */ |
| 9622 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5B) { |
| 9623 | IRTemp argV = newTemp(Ity_V128); |
| 9624 | IRTemp rmode = newTemp(Ity_I32); |
| 9625 | |
| 9626 | modrm = getIByte(delta+2); |
| 9627 | if (epartIsReg(modrm)) { |
| 9628 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9629 | delta += 2+1; |
| 9630 | DIP("cvtps2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9631 | nameXMMReg(gregOfRM(modrm))); |
| 9632 | } else { |
| 9633 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9634 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9635 | delta += 2+alen; |
| 9636 | DIP("cvtps2dq %s,%s\n", dis_buf, |
| 9637 | nameXMMReg(gregOfRM(modrm)) ); |
| 9638 | } |
| 9639 | |
| 9640 | assign( rmode, get_sse_roundingmode() ); |
| 9641 | breakup128to32s( argV, &t3, &t2, &t1, &t0 ); |
| 9642 | |
| 9643 | /* This is less than ideal. If it turns out to be a performance |
| 9644 | bottleneck it can be improved. */ |
| 9645 | # define CVT(_t) \ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9646 | binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9647 | mkexpr(rmode), \ |
| 9648 | unop( Iop_F32toF64, \ |
| 9649 | unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) |
| 9650 | |
| 9651 | putXMMRegLane32( gregOfRM(modrm), 3, CVT(t3) ); |
| 9652 | putXMMRegLane32( gregOfRM(modrm), 2, CVT(t2) ); |
| 9653 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 9654 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 9655 | |
| 9656 | # undef CVT |
| 9657 | |
| 9658 | goto decode_success; |
| 9659 | } |
| 9660 | |
| 9661 | /* 0F 5A = CVTPS2PD -- convert 2 x F32 in low half mem/xmm to 2 x |
| 9662 | F64 in xmm(G). */ |
| 9663 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5A) { |
| 9664 | IRTemp f32lo = newTemp(Ity_F32); |
| 9665 | IRTemp f32hi = newTemp(Ity_F32); |
| 9666 | |
| 9667 | modrm = getIByte(delta+2); |
| 9668 | if (epartIsReg(modrm)) { |
| 9669 | assign( f32lo, getXMMRegLane32F(eregOfRM(modrm), 0) ); |
| 9670 | assign( f32hi, getXMMRegLane32F(eregOfRM(modrm), 1) ); |
| 9671 | delta += 2+1; |
| 9672 | DIP("cvtps2pd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9673 | nameXMMReg(gregOfRM(modrm))); |
| 9674 | } else { |
| 9675 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9676 | assign( f32lo, loadLE(Ity_F32, mkexpr(addr)) ); |
| 9677 | assign( f32hi, loadLE(Ity_F32, |
| 9678 | binop(Iop_Add32,mkexpr(addr),mkU32(4))) ); |
| 9679 | delta += 2+alen; |
| 9680 | DIP("cvtps2pd %s,%s\n", dis_buf, |
| 9681 | nameXMMReg(gregOfRM(modrm)) ); |
| 9682 | } |
| 9683 | |
| 9684 | putXMMRegLane64F( gregOfRM(modrm), 1, |
| 9685 | unop(Iop_F32toF64, mkexpr(f32hi)) ); |
| 9686 | putXMMRegLane64F( gregOfRM(modrm), 0, |
| 9687 | unop(Iop_F32toF64, mkexpr(f32lo)) ); |
| 9688 | |
| 9689 | goto decode_success; |
| 9690 | } |
| 9691 | |
| 9692 | /* F2 0F 2D = CVTSD2SI -- convert F64 in mem/low half xmm to |
| 9693 | I32 in ireg, according to prevailing SSE rounding mode */ |
| 9694 | /* F2 0F 2C = CVTTSD2SI -- convert F64 in mem/low half xmm to |
sewardj | 0b21044 | 2005-02-23 13:28:27 +0000 | [diff] [blame] | 9695 | I32 in ireg, rounding towards zero */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9696 | if (insn[0] == 0xF2 && insn[1] == 0x0F |
| 9697 | && (insn[2] == 0x2D || insn[2] == 0x2C)) { |
| 9698 | IRTemp rmode = newTemp(Ity_I32); |
| 9699 | IRTemp f64lo = newTemp(Ity_F64); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 9700 | Bool r2zero = toBool(insn[2] == 0x2C); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9701 | vassert(sz == 4); |
| 9702 | |
| 9703 | modrm = getIByte(delta+3); |
| 9704 | if (epartIsReg(modrm)) { |
| 9705 | delta += 3+1; |
| 9706 | assign(f64lo, getXMMRegLane64F(eregOfRM(modrm), 0)); |
| 9707 | DIP("cvt%ssd2si %s,%s\n", r2zero ? "t" : "", |
| 9708 | nameXMMReg(eregOfRM(modrm)), |
| 9709 | nameIReg(4, gregOfRM(modrm))); |
| 9710 | } else { |
| 9711 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9712 | assign(f64lo, loadLE(Ity_F64, mkexpr(addr))); |
| 9713 | delta += 3+alen; |
| 9714 | DIP("cvt%ssd2si %s,%s\n", r2zero ? "t" : "", |
| 9715 | dis_buf, |
| 9716 | nameIReg(4, gregOfRM(modrm))); |
| 9717 | } |
| 9718 | |
| 9719 | if (r2zero) { |
| 9720 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
| 9721 | } else { |
| 9722 | assign( rmode, get_sse_roundingmode() ); |
| 9723 | } |
| 9724 | |
| 9725 | putIReg(4, gregOfRM(modrm), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9726 | binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo)) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9727 | |
| 9728 | goto decode_success; |
| 9729 | } |
| 9730 | |
| 9731 | /* F2 0F 5A = CVTSD2SS -- convert F64 in mem/low half xmm to F32 in |
| 9732 | low 1/4 xmm(G), according to prevailing SSE rounding mode */ |
| 9733 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5A) { |
| 9734 | IRTemp rmode = newTemp(Ity_I32); |
| 9735 | IRTemp f64lo = newTemp(Ity_F64); |
| 9736 | vassert(sz == 4); |
| 9737 | |
| 9738 | modrm = getIByte(delta+3); |
| 9739 | if (epartIsReg(modrm)) { |
| 9740 | delta += 3+1; |
| 9741 | assign(f64lo, getXMMRegLane64F(eregOfRM(modrm), 0)); |
| 9742 | DIP("cvtsd2ss %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9743 | nameXMMReg(gregOfRM(modrm))); |
| 9744 | } else { |
| 9745 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9746 | assign(f64lo, loadLE(Ity_F64, mkexpr(addr))); |
| 9747 | delta += 3+alen; |
| 9748 | DIP("cvtsd2ss %s,%s\n", dis_buf, |
| 9749 | nameXMMReg(gregOfRM(modrm))); |
| 9750 | } |
| 9751 | |
| 9752 | assign( rmode, get_sse_roundingmode() ); |
| 9753 | putXMMRegLane32F( |
| 9754 | gregOfRM(modrm), 0, |
| 9755 | binop( Iop_F64toF32, mkexpr(rmode), mkexpr(f64lo) ) |
| 9756 | ); |
| 9757 | |
| 9758 | goto decode_success; |
| 9759 | } |
| 9760 | |
| 9761 | /* F2 0F 2A = CVTSI2SD -- convert I32 in mem/ireg to F64 in low |
| 9762 | half xmm */ |
| 9763 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x2A) { |
| 9764 | IRTemp arg32 = newTemp(Ity_I32); |
| 9765 | vassert(sz == 4); |
| 9766 | |
| 9767 | modrm = getIByte(delta+3); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9768 | if (epartIsReg(modrm)) { |
| 9769 | assign( arg32, getIReg(4, eregOfRM(modrm)) ); |
| 9770 | delta += 3+1; |
| 9771 | DIP("cvtsi2sd %s,%s\n", nameIReg(4, eregOfRM(modrm)), |
| 9772 | nameXMMReg(gregOfRM(modrm))); |
| 9773 | } else { |
| 9774 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9775 | assign( arg32, loadLE(Ity_I32, mkexpr(addr)) ); |
| 9776 | delta += 3+alen; |
| 9777 | DIP("cvtsi2sd %s,%s\n", dis_buf, |
| 9778 | nameXMMReg(gregOfRM(modrm)) ); |
| 9779 | } |
| 9780 | |
| 9781 | putXMMRegLane64F( |
| 9782 | gregOfRM(modrm), 0, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9783 | unop(Iop_I32StoF64, mkexpr(arg32)) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9784 | |
| 9785 | goto decode_success; |
| 9786 | } |
| 9787 | |
| 9788 | /* F3 0F 5A = CVTSS2SD -- convert F32 in mem/low 1/4 xmm to F64 in |
| 9789 | low half xmm(G) */ |
| 9790 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5A) { |
| 9791 | IRTemp f32lo = newTemp(Ity_F32); |
| 9792 | vassert(sz == 4); |
| 9793 | |
| 9794 | modrm = getIByte(delta+3); |
| 9795 | if (epartIsReg(modrm)) { |
| 9796 | delta += 3+1; |
| 9797 | assign(f32lo, getXMMRegLane32F(eregOfRM(modrm), 0)); |
| 9798 | DIP("cvtss2sd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9799 | nameXMMReg(gregOfRM(modrm))); |
| 9800 | } else { |
| 9801 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9802 | assign(f32lo, loadLE(Ity_F32, mkexpr(addr))); |
| 9803 | delta += 3+alen; |
| 9804 | DIP("cvtss2sd %s,%s\n", dis_buf, |
| 9805 | nameXMMReg(gregOfRM(modrm))); |
| 9806 | } |
| 9807 | |
| 9808 | putXMMRegLane64F( gregOfRM(modrm), 0, |
| 9809 | unop( Iop_F32toF64, mkexpr(f32lo) ) ); |
| 9810 | |
| 9811 | goto decode_success; |
| 9812 | } |
| 9813 | |
| 9814 | /* 66 0F E6 = CVTTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in |
| 9815 | lo half xmm(G), and zero upper half, rounding towards zero */ |
| 9816 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE6) { |
| 9817 | IRTemp argV = newTemp(Ity_V128); |
| 9818 | IRTemp rmode = newTemp(Ity_I32); |
| 9819 | |
| 9820 | modrm = getIByte(delta+2); |
| 9821 | if (epartIsReg(modrm)) { |
| 9822 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9823 | delta += 2+1; |
| 9824 | DIP("cvttpd2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9825 | nameXMMReg(gregOfRM(modrm))); |
| 9826 | } else { |
| 9827 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9828 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9829 | delta += 2+alen; |
| 9830 | DIP("cvttpd2dq %s,%s\n", dis_buf, |
| 9831 | nameXMMReg(gregOfRM(modrm)) ); |
| 9832 | } |
| 9833 | |
| 9834 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
| 9835 | |
| 9836 | t0 = newTemp(Ity_F64); |
| 9837 | t1 = newTemp(Ity_F64); |
| 9838 | assign( t0, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9839 | unop(Iop_V128to64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9840 | assign( t1, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9841 | unop(Iop_V128HIto64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9842 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9843 | # define CVT(_t) binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9844 | mkexpr(rmode), \ |
| 9845 | mkexpr(_t) ) |
| 9846 | |
| 9847 | putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); |
| 9848 | putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); |
| 9849 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 9850 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 9851 | |
| 9852 | # undef CVT |
| 9853 | |
| 9854 | goto decode_success; |
| 9855 | } |
| 9856 | |
| 9857 | /* F3 0F 5B = CVTTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in |
| 9858 | xmm(G), rounding towards zero */ |
| 9859 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5B) { |
| 9860 | IRTemp argV = newTemp(Ity_V128); |
| 9861 | IRTemp rmode = newTemp(Ity_I32); |
| 9862 | vassert(sz == 4); |
| 9863 | |
| 9864 | modrm = getIByte(delta+3); |
| 9865 | if (epartIsReg(modrm)) { |
| 9866 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9867 | delta += 3+1; |
| 9868 | DIP("cvttps2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9869 | nameXMMReg(gregOfRM(modrm))); |
| 9870 | } else { |
| 9871 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9872 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9873 | delta += 3+alen; |
| 9874 | DIP("cvttps2dq %s,%s\n", dis_buf, |
| 9875 | nameXMMReg(gregOfRM(modrm)) ); |
| 9876 | } |
| 9877 | |
| 9878 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
| 9879 | breakup128to32s( argV, &t3, &t2, &t1, &t0 ); |
| 9880 | |
| 9881 | /* This is less than ideal. If it turns out to be a performance |
| 9882 | bottleneck it can be improved. */ |
| 9883 | # define CVT(_t) \ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9884 | binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9885 | mkexpr(rmode), \ |
| 9886 | unop( Iop_F32toF64, \ |
| 9887 | unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) |
| 9888 | |
| 9889 | putXMMRegLane32( gregOfRM(modrm), 3, CVT(t3) ); |
| 9890 | putXMMRegLane32( gregOfRM(modrm), 2, CVT(t2) ); |
| 9891 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 9892 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 9893 | |
| 9894 | # undef CVT |
| 9895 | |
| 9896 | goto decode_success; |
| 9897 | } |
| 9898 | |
| 9899 | /* 66 0F 5E = DIVPD -- div 64Fx2 from R/M to R */ |
| 9900 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5E) { |
| 9901 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "divpd", Iop_Div64Fx2 ); |
| 9902 | goto decode_success; |
| 9903 | } |
| 9904 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 9905 | /* F2 0F 5E = DIVSD -- div 64F0x2 from R/M to R */ |
| 9906 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5E) { |
| 9907 | vassert(sz == 4); |
| 9908 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "divsd", Iop_Div64F0x2 ); |
| 9909 | goto decode_success; |
| 9910 | } |
| 9911 | |
| 9912 | /* 0F AE /5 = LFENCE -- flush pending operations to memory */ |
| 9913 | /* 0F AE /6 = MFENCE -- flush pending operations to memory */ |
| 9914 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 9915 | && epartIsReg(insn[2]) |
| 9916 | && (gregOfRM(insn[2]) == 5 || gregOfRM(insn[2]) == 6)) { |
| 9917 | vassert(sz == 4); |
| 9918 | delta += 3; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 9919 | /* Insert a memory fence. It's sometimes important that these |
| 9920 | are carried through to the generated code. */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 9921 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 9922 | DIP("%sfence\n", gregOfRM(insn[2])==5 ? "l" : "m"); |
| 9923 | goto decode_success; |
| 9924 | } |
| 9925 | |
| 9926 | /* 66 0F 5F = MAXPD -- max 64Fx2 from R/M to R */ |
| 9927 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5F) { |
| 9928 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "maxpd", Iop_Max64Fx2 ); |
| 9929 | goto decode_success; |
| 9930 | } |
| 9931 | |
| 9932 | /* F2 0F 5F = MAXSD -- max 64F0x2 from R/M to R */ |
| 9933 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5F) { |
| 9934 | vassert(sz == 4); |
| 9935 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "maxsd", Iop_Max64F0x2 ); |
| 9936 | goto decode_success; |
| 9937 | } |
| 9938 | |
| 9939 | /* 66 0F 5D = MINPD -- min 64Fx2 from R/M to R */ |
| 9940 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5D) { |
| 9941 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "minpd", Iop_Min64Fx2 ); |
| 9942 | goto decode_success; |
| 9943 | } |
| 9944 | |
| 9945 | /* F2 0F 5D = MINSD -- min 64F0x2 from R/M to R */ |
| 9946 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5D) { |
| 9947 | vassert(sz == 4); |
| 9948 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "minsd", Iop_Min64F0x2 ); |
| 9949 | goto decode_success; |
| 9950 | } |
| 9951 | |
| 9952 | /* 66 0F 28 = MOVAPD -- move from E (mem or xmm) to G (xmm). */ |
| 9953 | /* 66 0F 10 = MOVUPD -- move from E (mem or xmm) to G (xmm). */ |
| 9954 | /* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */ |
| 9955 | if (sz == 2 && insn[0] == 0x0F |
| 9956 | && (insn[1] == 0x28 || insn[1] == 0x10 || insn[1] == 0x6F)) { |
| 9957 | HChar* wot = insn[1]==0x28 ? "apd" : |
| 9958 | insn[1]==0x10 ? "upd" : "dqa"; |
| 9959 | modrm = getIByte(delta+2); |
| 9960 | if (epartIsReg(modrm)) { |
| 9961 | putXMMReg( gregOfRM(modrm), |
| 9962 | getXMMReg( eregOfRM(modrm) )); |
| 9963 | DIP("mov%s %s,%s\n", wot, nameXMMReg(eregOfRM(modrm)), |
| 9964 | nameXMMReg(gregOfRM(modrm))); |
| 9965 | delta += 2+1; |
| 9966 | } else { |
| 9967 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 9968 | if (insn[1] == 0x28/*movapd*/ || insn[1] == 0x6F/*movdqa*/) |
| 9969 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 9970 | putXMMReg( gregOfRM(modrm), |
| 9971 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 9972 | DIP("mov%s %s,%s\n", wot, dis_buf, |
| 9973 | nameXMMReg(gregOfRM(modrm))); |
| 9974 | delta += 2+alen; |
| 9975 | } |
| 9976 | goto decode_success; |
| 9977 | } |
| 9978 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 9979 | /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */ |
sewardj | 1c31877 | 2005-03-19 14:27:04 +0000 | [diff] [blame] | 9980 | /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */ |
| 9981 | if (sz == 2 && insn[0] == 0x0F |
| 9982 | && (insn[1] == 0x29 || insn[1] == 0x11)) { |
| 9983 | HChar* wot = insn[1]==0x29 ? "apd" : "upd"; |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 9984 | modrm = getIByte(delta+2); |
| 9985 | if (epartIsReg(modrm)) { |
| 9986 | /* fall through; awaiting test case */ |
| 9987 | } else { |
| 9988 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 9989 | if (insn[1] == 0x29/*movapd*/) |
| 9990 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 9991 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
sewardj | 1c31877 | 2005-03-19 14:27:04 +0000 | [diff] [blame] | 9992 | DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRM(modrm)), |
| 9993 | dis_buf ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 9994 | delta += 2+alen; |
| 9995 | goto decode_success; |
| 9996 | } |
| 9997 | } |
| 9998 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 9999 | /* 66 0F 6E = MOVD from r/m32 to xmm, zeroing high 3/4 of xmm. */ |
| 10000 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6E) { |
| 10001 | modrm = getIByte(delta+2); |
| 10002 | if (epartIsReg(modrm)) { |
| 10003 | delta += 2+1; |
| 10004 | putXMMReg( |
| 10005 | gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10006 | unop( Iop_32UtoV128, getIReg(4, eregOfRM(modrm)) ) |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10007 | ); |
| 10008 | DIP("movd %s, %s\n", |
| 10009 | nameIReg(4,eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm))); |
| 10010 | } else { |
| 10011 | addr = disAMode( &alen, sorb, delta+2, dis_buf ); |
| 10012 | delta += 2+alen; |
| 10013 | putXMMReg( |
| 10014 | gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10015 | unop( Iop_32UtoV128,loadLE(Ity_I32, mkexpr(addr)) ) |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10016 | ); |
| 10017 | DIP("movd %s, %s\n", dis_buf, nameXMMReg(gregOfRM(modrm))); |
| 10018 | } |
| 10019 | goto decode_success; |
| 10020 | } |
| 10021 | |
| 10022 | /* 66 0F 7E = MOVD from xmm low 1/4 to r/m32. */ |
| 10023 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x7E) { |
| 10024 | modrm = getIByte(delta+2); |
| 10025 | if (epartIsReg(modrm)) { |
| 10026 | delta += 2+1; |
| 10027 | putIReg( 4, eregOfRM(modrm), |
| 10028 | getXMMRegLane32(gregOfRM(modrm), 0) ); |
| 10029 | DIP("movd %s, %s\n", |
| 10030 | nameXMMReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm))); |
| 10031 | } else { |
| 10032 | addr = disAMode( &alen, sorb, delta+2, dis_buf ); |
| 10033 | delta += 2+alen; |
| 10034 | storeLE( mkexpr(addr), |
| 10035 | getXMMRegLane32(gregOfRM(modrm), 0) ); |
| 10036 | DIP("movd %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); |
| 10037 | } |
| 10038 | goto decode_success; |
| 10039 | } |
| 10040 | |
| 10041 | /* 66 0F 7F = MOVDQA -- move from G (xmm) to E (mem or xmm). */ |
| 10042 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x7F) { |
| 10043 | modrm = getIByte(delta+2); |
| 10044 | if (epartIsReg(modrm)) { |
| 10045 | delta += 2+1; |
| 10046 | putXMMReg( eregOfRM(modrm), |
| 10047 | getXMMReg(gregOfRM(modrm)) ); |
| 10048 | DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)), |
| 10049 | nameXMMReg(eregOfRM(modrm))); |
| 10050 | } else { |
| 10051 | addr = disAMode( &alen, sorb, delta+2, dis_buf ); |
| 10052 | delta += 2+alen; |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 10053 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10054 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 10055 | DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); |
| 10056 | } |
| 10057 | goto decode_success; |
| 10058 | } |
| 10059 | |
| 10060 | /* F3 0F 6F = MOVDQU -- move from E (mem or xmm) to G (xmm). */ |
| 10061 | /* Unfortunately can't simply use the MOVDQA case since the |
| 10062 | prefix lengths are different (66 vs F3) */ |
| 10063 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x6F) { |
| 10064 | vassert(sz == 4); |
| 10065 | modrm = getIByte(delta+3); |
| 10066 | if (epartIsReg(modrm)) { |
| 10067 | putXMMReg( gregOfRM(modrm), |
| 10068 | getXMMReg( eregOfRM(modrm) )); |
| 10069 | DIP("movdqu %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10070 | nameXMMReg(gregOfRM(modrm))); |
| 10071 | delta += 3+1; |
| 10072 | } else { |
| 10073 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10074 | putXMMReg( gregOfRM(modrm), |
| 10075 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 10076 | DIP("movdqu %s,%s\n", dis_buf, |
| 10077 | nameXMMReg(gregOfRM(modrm))); |
| 10078 | delta += 3+alen; |
| 10079 | } |
| 10080 | goto decode_success; |
| 10081 | } |
| 10082 | |
| 10083 | /* F3 0F 7F = MOVDQU -- move from G (xmm) to E (mem or xmm). */ |
| 10084 | /* Unfortunately can't simply use the MOVDQA case since the |
| 10085 | prefix lengths are different (66 vs F3) */ |
| 10086 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x7F) { |
| 10087 | vassert(sz == 4); |
| 10088 | modrm = getIByte(delta+3); |
| 10089 | if (epartIsReg(modrm)) { |
| 10090 | delta += 3+1; |
| 10091 | putXMMReg( eregOfRM(modrm), |
| 10092 | getXMMReg(gregOfRM(modrm)) ); |
| 10093 | DIP("movdqu %s, %s\n", nameXMMReg(gregOfRM(modrm)), |
| 10094 | nameXMMReg(eregOfRM(modrm))); |
| 10095 | } else { |
| 10096 | addr = disAMode( &alen, sorb, delta+3, dis_buf ); |
| 10097 | delta += 3+alen; |
| 10098 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 10099 | DIP("movdqu %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); |
| 10100 | } |
| 10101 | goto decode_success; |
| 10102 | } |
| 10103 | |
| 10104 | /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */ |
| 10105 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xD6) { |
| 10106 | vassert(sz == 4); |
| 10107 | modrm = getIByte(delta+3); |
| 10108 | if (epartIsReg(modrm)) { |
| 10109 | do_MMX_preamble(); |
| 10110 | putMMXReg( gregOfRM(modrm), |
| 10111 | getXMMRegLane64( eregOfRM(modrm), 0 )); |
| 10112 | DIP("movdq2q %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10113 | nameMMXReg(gregOfRM(modrm))); |
| 10114 | delta += 3+1; |
| 10115 | goto decode_success; |
| 10116 | } else { |
| 10117 | /* fall through, apparently no mem case for this insn */ |
| 10118 | } |
| 10119 | } |
| 10120 | |
| 10121 | /* 66 0F 16 = MOVHPD -- move from mem to high half of XMM. */ |
| 10122 | /* These seems identical to MOVHPS. This instruction encoding is |
| 10123 | completely crazy. */ |
| 10124 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x16) { |
| 10125 | modrm = getIByte(delta+2); |
| 10126 | if (epartIsReg(modrm)) { |
| 10127 | /* fall through; apparently reg-reg is not possible */ |
| 10128 | } else { |
| 10129 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10130 | delta += 2+alen; |
| 10131 | putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, |
| 10132 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 10133 | DIP("movhpd %s,%s\n", dis_buf, |
| 10134 | nameXMMReg( gregOfRM(modrm) )); |
| 10135 | goto decode_success; |
| 10136 | } |
| 10137 | } |
| 10138 | |
| 10139 | /* 66 0F 17 = MOVHPD -- move from high half of XMM to mem. */ |
| 10140 | /* Again, this seems identical to MOVHPS. */ |
| 10141 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x17) { |
| 10142 | if (!epartIsReg(insn[2])) { |
| 10143 | delta += 2; |
| 10144 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 10145 | delta += alen; |
| 10146 | storeLE( mkexpr(addr), |
| 10147 | getXMMRegLane64( gregOfRM(insn[2]), |
| 10148 | 1/*upper lane*/ ) ); |
| 10149 | DIP("movhpd %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 10150 | dis_buf); |
| 10151 | goto decode_success; |
| 10152 | } |
| 10153 | /* else fall through */ |
| 10154 | } |
| 10155 | |
| 10156 | /* 66 0F 12 = MOVLPD -- move from mem to low half of XMM. */ |
| 10157 | /* Identical to MOVLPS ? */ |
| 10158 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x12) { |
| 10159 | modrm = getIByte(delta+2); |
| 10160 | if (epartIsReg(modrm)) { |
| 10161 | /* fall through; apparently reg-reg is not possible */ |
| 10162 | } else { |
| 10163 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10164 | delta += 2+alen; |
| 10165 | putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/, |
| 10166 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 10167 | DIP("movlpd %s, %s\n", |
| 10168 | dis_buf, nameXMMReg( gregOfRM(modrm) )); |
| 10169 | goto decode_success; |
| 10170 | } |
| 10171 | } |
| 10172 | |
| 10173 | /* 66 0F 13 = MOVLPD -- move from low half of XMM to mem. */ |
| 10174 | /* Identical to MOVLPS ? */ |
| 10175 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x13) { |
| 10176 | if (!epartIsReg(insn[2])) { |
| 10177 | delta += 2; |
| 10178 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 10179 | delta += alen; |
| 10180 | storeLE( mkexpr(addr), |
| 10181 | getXMMRegLane64( gregOfRM(insn[2]), |
| 10182 | 0/*lower lane*/ ) ); |
| 10183 | DIP("movlpd %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 10184 | dis_buf); |
| 10185 | goto decode_success; |
| 10186 | } |
| 10187 | /* else fall through */ |
| 10188 | } |
| 10189 | |
| 10190 | /* 66 0F 50 = MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(E) to |
| 10191 | 2 lowest bits of ireg(G) */ |
| 10192 | if (insn[0] == 0x0F && insn[1] == 0x50) { |
| 10193 | modrm = getIByte(delta+2); |
| 10194 | if (sz == 2 && epartIsReg(modrm)) { |
| 10195 | Int src; |
| 10196 | t0 = newTemp(Ity_I32); |
| 10197 | t1 = newTemp(Ity_I32); |
| 10198 | delta += 2+1; |
| 10199 | src = eregOfRM(modrm); |
| 10200 | assign( t0, binop( Iop_And32, |
| 10201 | binop(Iop_Shr32, getXMMRegLane32(src,1), mkU8(31)), |
| 10202 | mkU32(1) )); |
| 10203 | assign( t1, binop( Iop_And32, |
| 10204 | binop(Iop_Shr32, getXMMRegLane32(src,3), mkU8(30)), |
| 10205 | mkU32(2) )); |
| 10206 | putIReg(4, gregOfRM(modrm), |
| 10207 | binop(Iop_Or32, mkexpr(t0), mkexpr(t1)) |
| 10208 | ); |
| 10209 | DIP("movmskpd %s,%s\n", nameXMMReg(src), |
| 10210 | nameIReg(4, gregOfRM(modrm))); |
| 10211 | goto decode_success; |
| 10212 | } |
| 10213 | /* else fall through */ |
| 10214 | } |
| 10215 | |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 10216 | /* 66 0F F7 = MASKMOVDQU -- store selected bytes of double quadword */ |
| 10217 | if (insn[0] == 0x0F && insn[1] == 0xF7) { |
| 10218 | modrm = getIByte(delta+2); |
| 10219 | if (sz == 2 && epartIsReg(modrm)) { |
| 10220 | IRTemp regD = newTemp(Ity_V128); |
| 10221 | IRTemp mask = newTemp(Ity_V128); |
| 10222 | IRTemp olddata = newTemp(Ity_V128); |
| 10223 | IRTemp newdata = newTemp(Ity_V128); |
| 10224 | addr = newTemp(Ity_I32); |
| 10225 | |
| 10226 | assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) )); |
| 10227 | assign( regD, getXMMReg( gregOfRM(modrm) )); |
| 10228 | |
| 10229 | /* Unfortunately can't do the obvious thing with SarN8x16 |
| 10230 | here since that can't be re-emitted as SSE2 code - no such |
| 10231 | insn. */ |
| 10232 | assign( |
| 10233 | mask, |
| 10234 | binop(Iop_64HLtoV128, |
| 10235 | binop(Iop_SarN8x8, |
| 10236 | getXMMRegLane64( eregOfRM(modrm), 1 ), |
| 10237 | mkU8(7) ), |
| 10238 | binop(Iop_SarN8x8, |
| 10239 | getXMMRegLane64( eregOfRM(modrm), 0 ), |
| 10240 | mkU8(7) ) )); |
| 10241 | assign( olddata, loadLE( Ity_V128, mkexpr(addr) )); |
| 10242 | assign( newdata, |
| 10243 | binop(Iop_OrV128, |
| 10244 | binop(Iop_AndV128, |
| 10245 | mkexpr(regD), |
| 10246 | mkexpr(mask) ), |
| 10247 | binop(Iop_AndV128, |
| 10248 | mkexpr(olddata), |
| 10249 | unop(Iop_NotV128, mkexpr(mask)))) ); |
| 10250 | storeLE( mkexpr(addr), mkexpr(newdata) ); |
| 10251 | |
| 10252 | delta += 2+1; |
| 10253 | DIP("maskmovdqu %s,%s\n", nameXMMReg( eregOfRM(modrm) ), |
| 10254 | nameXMMReg( gregOfRM(modrm) ) ); |
| 10255 | goto decode_success; |
| 10256 | } |
| 10257 | /* else fall through */ |
| 10258 | } |
| 10259 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10260 | /* 66 0F E7 = MOVNTDQ -- for us, just a plain SSE store. */ |
| 10261 | if (insn[0] == 0x0F && insn[1] == 0xE7) { |
| 10262 | modrm = getIByte(delta+2); |
| 10263 | if (sz == 2 && !epartIsReg(modrm)) { |
| 10264 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 10265 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10266 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 10267 | DIP("movntdq %s,%s\n", dis_buf, |
| 10268 | nameXMMReg(gregOfRM(modrm))); |
| 10269 | delta += 2+alen; |
| 10270 | goto decode_success; |
| 10271 | } |
| 10272 | /* else fall through */ |
| 10273 | } |
| 10274 | |
| 10275 | /* 0F C3 = MOVNTI -- for us, just a plain ireg store. */ |
| 10276 | if (insn[0] == 0x0F && insn[1] == 0xC3) { |
| 10277 | vassert(sz == 4); |
| 10278 | modrm = getIByte(delta+2); |
| 10279 | if (!epartIsReg(modrm)) { |
| 10280 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10281 | storeLE( mkexpr(addr), getIReg(4, gregOfRM(modrm)) ); |
| 10282 | DIP("movnti %s,%s\n", dis_buf, |
| 10283 | nameIReg(4, gregOfRM(modrm))); |
| 10284 | delta += 2+alen; |
| 10285 | goto decode_success; |
| 10286 | } |
| 10287 | /* else fall through */ |
| 10288 | } |
| 10289 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10290 | /* 66 0F D6 = MOVQ -- move 64 bits from G (lo half xmm) to E (mem |
| 10291 | or lo half xmm). */ |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 10292 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD6) { |
| 10293 | modrm = getIByte(delta+2); |
| 10294 | if (epartIsReg(modrm)) { |
| 10295 | /* fall through, awaiting test case */ |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10296 | /* dst: lo half copied, hi half zeroed */ |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 10297 | } else { |
| 10298 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10299 | storeLE( mkexpr(addr), |
| 10300 | getXMMRegLane64( gregOfRM(modrm), 0 )); |
| 10301 | DIP("movq %s,%s\n", nameXMMReg(gregOfRM(modrm)), dis_buf ); |
| 10302 | delta += 2+alen; |
| 10303 | goto decode_success; |
| 10304 | } |
| 10305 | } |
| 10306 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10307 | /* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero |
| 10308 | hi half). */ |
| 10309 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xD6) { |
| 10310 | vassert(sz == 4); |
| 10311 | modrm = getIByte(delta+3); |
| 10312 | if (epartIsReg(modrm)) { |
| 10313 | do_MMX_preamble(); |
| 10314 | putXMMReg( gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10315 | unop(Iop_64UtoV128, getMMXReg( eregOfRM(modrm) )) ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10316 | DIP("movq2dq %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 10317 | nameXMMReg(gregOfRM(modrm))); |
| 10318 | delta += 3+1; |
| 10319 | goto decode_success; |
| 10320 | } else { |
| 10321 | /* fall through, apparently no mem case for this insn */ |
| 10322 | } |
| 10323 | } |
| 10324 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10325 | /* F3 0F 7E = MOVQ -- move 64 bits from E (mem or lo half xmm) to |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10326 | G (lo half xmm). Upper half of G is zeroed out. */ |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10327 | /* F2 0F 10 = MOVSD -- move 64 bits from E (mem or lo half xmm) to |
| 10328 | G (lo half xmm). If E is mem, upper half of G is zeroed out. |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10329 | If E is reg, upper half of G is unchanged. */ |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10330 | if ((insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x10) |
| 10331 | || (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x7E)) { |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10332 | vassert(sz == 4); |
| 10333 | modrm = getIByte(delta+3); |
| 10334 | if (epartIsReg(modrm)) { |
| 10335 | putXMMRegLane64( gregOfRM(modrm), 0, |
| 10336 | getXMMRegLane64( eregOfRM(modrm), 0 )); |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10337 | if (insn[0] == 0xF3/*MOVQ*/) { |
| 10338 | /* zero bits 127:64 */ |
| 10339 | putXMMRegLane64( gregOfRM(modrm), 1, mkU64(0) ); |
| 10340 | } |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10341 | DIP("movsd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10342 | nameXMMReg(gregOfRM(modrm))); |
| 10343 | delta += 3+1; |
| 10344 | } else { |
| 10345 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
sewardj | ad50db0 | 2005-04-06 01:45:44 +0000 | [diff] [blame] | 10346 | /* zero bits 127:64 */ |
sewardj | 5bf1fd4 | 2005-04-06 01:11:08 +0000 | [diff] [blame] | 10347 | putXMMRegLane64( gregOfRM(modrm), 1, mkU64(0) ); |
sewardj | ad50db0 | 2005-04-06 01:45:44 +0000 | [diff] [blame] | 10348 | /* write bits 63:0 */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10349 | putXMMRegLane64( gregOfRM(modrm), 0, |
| 10350 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 10351 | DIP("movsd %s,%s\n", dis_buf, |
| 10352 | nameXMMReg(gregOfRM(modrm))); |
| 10353 | delta += 3+alen; |
| 10354 | } |
| 10355 | goto decode_success; |
| 10356 | } |
| 10357 | |
| 10358 | /* F2 0F 11 = MOVSD -- move 64 bits from G (lo half xmm) to E (mem |
| 10359 | or lo half xmm). */ |
| 10360 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x11) { |
| 10361 | vassert(sz == 4); |
| 10362 | modrm = getIByte(delta+3); |
| 10363 | if (epartIsReg(modrm)) { |
sewardj | b7ba04f | 2008-11-17 20:25:37 +0000 | [diff] [blame] | 10364 | putXMMRegLane64( eregOfRM(modrm), 0, |
| 10365 | getXMMRegLane64( gregOfRM(modrm), 0 )); |
| 10366 | DIP("movsd %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
| 10367 | nameXMMReg(eregOfRM(modrm))); |
| 10368 | delta += 3+1; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10369 | } else { |
| 10370 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10371 | storeLE( mkexpr(addr), |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 10372 | getXMMRegLane64(gregOfRM(modrm), 0) ); |
| 10373 | DIP("movsd %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10374 | dis_buf); |
| 10375 | delta += 3+alen; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10376 | } |
sewardj | b7ba04f | 2008-11-17 20:25:37 +0000 | [diff] [blame] | 10377 | goto decode_success; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10378 | } |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10379 | |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10380 | /* 66 0F 59 = MULPD -- mul 64Fx2 from R/M to R */ |
| 10381 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x59) { |
| 10382 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "mulpd", Iop_Mul64Fx2 ); |
| 10383 | goto decode_success; |
| 10384 | } |
| 10385 | |
| 10386 | /* F2 0F 59 = MULSD -- mul 64F0x2 from R/M to R */ |
| 10387 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x59) { |
| 10388 | vassert(sz == 4); |
| 10389 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "mulsd", Iop_Mul64F0x2 ); |
| 10390 | goto decode_success; |
| 10391 | } |
| 10392 | |
| 10393 | /* 66 0F 56 = ORPD -- G = G and E */ |
| 10394 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x56) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10395 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "orpd", Iop_OrV128 ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10396 | goto decode_success; |
| 10397 | } |
| 10398 | |
| 10399 | /* 66 0F C6 /r ib = SHUFPD -- shuffle packed F64s */ |
| 10400 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC6) { |
| 10401 | Int select; |
| 10402 | IRTemp sV = newTemp(Ity_V128); |
| 10403 | IRTemp dV = newTemp(Ity_V128); |
| 10404 | IRTemp s1 = newTemp(Ity_I64); |
| 10405 | IRTemp s0 = newTemp(Ity_I64); |
| 10406 | IRTemp d1 = newTemp(Ity_I64); |
| 10407 | IRTemp d0 = newTemp(Ity_I64); |
| 10408 | |
| 10409 | modrm = insn[2]; |
| 10410 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 10411 | |
| 10412 | if (epartIsReg(modrm)) { |
| 10413 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 10414 | select = (Int)insn[3]; |
| 10415 | delta += 2+2; |
| 10416 | DIP("shufpd $%d,%s,%s\n", select, |
| 10417 | nameXMMReg(eregOfRM(modrm)), |
| 10418 | nameXMMReg(gregOfRM(modrm))); |
| 10419 | } else { |
| 10420 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10421 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10422 | select = (Int)insn[2+alen]; |
| 10423 | delta += 3+alen; |
| 10424 | DIP("shufpd $%d,%s,%s\n", select, |
| 10425 | dis_buf, |
| 10426 | nameXMMReg(gregOfRM(modrm))); |
| 10427 | } |
| 10428 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10429 | assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 10430 | assign( d0, unop(Iop_V128to64, mkexpr(dV)) ); |
| 10431 | assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 10432 | assign( s0, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10433 | |
| 10434 | # define SELD(n) mkexpr((n)==0 ? d0 : d1) |
| 10435 | # define SELS(n) mkexpr((n)==0 ? s0 : s1) |
| 10436 | |
| 10437 | putXMMReg( |
| 10438 | gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10439 | binop(Iop_64HLtoV128, SELS((select>>1)&1), SELD((select>>0)&1) ) |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10440 | ); |
| 10441 | |
| 10442 | # undef SELD |
| 10443 | # undef SELS |
| 10444 | |
| 10445 | goto decode_success; |
| 10446 | } |
| 10447 | |
| 10448 | /* 66 0F 51 = SQRTPD -- approx sqrt 64Fx2 from R/M to R */ |
| 10449 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x51) { |
| 10450 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
| 10451 | "sqrtpd", Iop_Sqrt64Fx2 ); |
| 10452 | goto decode_success; |
| 10453 | } |
| 10454 | |
| 10455 | /* F2 0F 51 = SQRTSD -- approx sqrt 64F0x2 from R/M to R */ |
| 10456 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x51) { |
| 10457 | vassert(sz == 4); |
| 10458 | delta = dis_SSE_E_to_G_unary_lo64( sorb, delta+3, |
| 10459 | "sqrtsd", Iop_Sqrt64F0x2 ); |
| 10460 | goto decode_success; |
| 10461 | } |
| 10462 | |
| 10463 | /* 66 0F 5C = SUBPD -- sub 64Fx2 from R/M to R */ |
| 10464 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5C) { |
| 10465 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "subpd", Iop_Sub64Fx2 ); |
| 10466 | goto decode_success; |
| 10467 | } |
| 10468 | |
| 10469 | /* F2 0F 5C = SUBSD -- sub 64F0x2 from R/M to R */ |
| 10470 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5C) { |
| 10471 | vassert(sz == 4); |
| 10472 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "subsd", Iop_Sub64F0x2 ); |
| 10473 | goto decode_success; |
| 10474 | } |
| 10475 | |
| 10476 | /* 66 0F 15 = UNPCKHPD -- unpack and interleave high part F64s */ |
| 10477 | /* 66 0F 14 = UNPCKLPD -- unpack and interleave low part F64s */ |
| 10478 | /* These just appear to be special cases of SHUFPS */ |
| 10479 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) { |
| 10480 | IRTemp s1 = newTemp(Ity_I64); |
| 10481 | IRTemp s0 = newTemp(Ity_I64); |
| 10482 | IRTemp d1 = newTemp(Ity_I64); |
| 10483 | IRTemp d0 = newTemp(Ity_I64); |
| 10484 | IRTemp sV = newTemp(Ity_V128); |
| 10485 | IRTemp dV = newTemp(Ity_V128); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 10486 | Bool hi = toBool(insn[1] == 0x15); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10487 | |
| 10488 | modrm = insn[2]; |
| 10489 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 10490 | |
| 10491 | if (epartIsReg(modrm)) { |
| 10492 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 10493 | delta += 2+1; |
| 10494 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 10495 | nameXMMReg(eregOfRM(modrm)), |
| 10496 | nameXMMReg(gregOfRM(modrm))); |
| 10497 | } else { |
| 10498 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10499 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10500 | delta += 2+alen; |
| 10501 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 10502 | dis_buf, |
| 10503 | nameXMMReg(gregOfRM(modrm))); |
| 10504 | } |
| 10505 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10506 | assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 10507 | assign( d0, unop(Iop_V128to64, mkexpr(dV)) ); |
| 10508 | assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 10509 | assign( s0, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10510 | |
| 10511 | if (hi) { |
| 10512 | putXMMReg( gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10513 | binop(Iop_64HLtoV128, mkexpr(s1), mkexpr(d1)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10514 | } else { |
| 10515 | putXMMReg( gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10516 | binop(Iop_64HLtoV128, mkexpr(s0), mkexpr(d0)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10517 | } |
| 10518 | |
| 10519 | goto decode_success; |
| 10520 | } |
| 10521 | |
| 10522 | /* 66 0F 57 = XORPD -- G = G and E */ |
| 10523 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x57) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10524 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "xorpd", Iop_XorV128 ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10525 | goto decode_success; |
| 10526 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 10527 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10528 | /* 66 0F 6B = PACKSSDW */ |
| 10529 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6B) { |
| 10530 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 10531 | "packssdw", |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 10532 | Iop_QNarrowBin32Sto16Sx8, True ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10533 | goto decode_success; |
| 10534 | } |
| 10535 | |
| 10536 | /* 66 0F 63 = PACKSSWB */ |
| 10537 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x63) { |
| 10538 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 10539 | "packsswb", |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 10540 | Iop_QNarrowBin16Sto8Sx16, True ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10541 | goto decode_success; |
| 10542 | } |
| 10543 | |
| 10544 | /* 66 0F 67 = PACKUSWB */ |
| 10545 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x67) { |
| 10546 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 10547 | "packuswb", |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 10548 | Iop_QNarrowBin16Sto8Ux16, True ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10549 | goto decode_success; |
| 10550 | } |
| 10551 | |
| 10552 | /* 66 0F FC = PADDB */ |
| 10553 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFC) { |
| 10554 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10555 | "paddb", Iop_Add8x16, False ); |
| 10556 | goto decode_success; |
| 10557 | } |
| 10558 | |
| 10559 | /* 66 0F FE = PADDD */ |
| 10560 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFE) { |
| 10561 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10562 | "paddd", Iop_Add32x4, False ); |
| 10563 | goto decode_success; |
| 10564 | } |
| 10565 | |
| 10566 | /* ***--- this is an MMX class insn introduced in SSE2 ---*** */ |
| 10567 | /* 0F D4 = PADDQ -- add 64x1 */ |
| 10568 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xD4) { |
| 10569 | do_MMX_preamble(); |
| 10570 | delta = dis_MMXop_regmem_to_reg ( |
| 10571 | sorb, delta+2, insn[1], "paddq", False ); |
| 10572 | goto decode_success; |
| 10573 | } |
| 10574 | |
| 10575 | /* 66 0F D4 = PADDQ */ |
| 10576 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD4) { |
| 10577 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10578 | "paddq", Iop_Add64x2, False ); |
| 10579 | goto decode_success; |
| 10580 | } |
| 10581 | |
| 10582 | /* 66 0F FD = PADDW */ |
| 10583 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFD) { |
| 10584 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10585 | "paddw", Iop_Add16x8, False ); |
| 10586 | goto decode_success; |
| 10587 | } |
| 10588 | |
| 10589 | /* 66 0F EC = PADDSB */ |
| 10590 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEC) { |
| 10591 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10592 | "paddsb", Iop_QAdd8Sx16, False ); |
| 10593 | goto decode_success; |
| 10594 | } |
| 10595 | |
| 10596 | /* 66 0F ED = PADDSW */ |
| 10597 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xED) { |
| 10598 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10599 | "paddsw", Iop_QAdd16Sx8, False ); |
| 10600 | goto decode_success; |
| 10601 | } |
| 10602 | |
| 10603 | /* 66 0F DC = PADDUSB */ |
| 10604 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDC) { |
| 10605 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10606 | "paddusb", Iop_QAdd8Ux16, False ); |
| 10607 | goto decode_success; |
| 10608 | } |
| 10609 | |
| 10610 | /* 66 0F DD = PADDUSW */ |
| 10611 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDD) { |
| 10612 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10613 | "paddusw", Iop_QAdd16Ux8, False ); |
| 10614 | goto decode_success; |
| 10615 | } |
| 10616 | |
| 10617 | /* 66 0F DB = PAND */ |
| 10618 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDB) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10619 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "pand", Iop_AndV128 ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10620 | goto decode_success; |
| 10621 | } |
| 10622 | |
| 10623 | /* 66 0F DF = PANDN */ |
| 10624 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDF) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10625 | delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "pandn", Iop_AndV128 ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10626 | goto decode_success; |
| 10627 | } |
| 10628 | |
| 10629 | /* 66 0F E0 = PAVGB */ |
| 10630 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE0) { |
| 10631 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10632 | "pavgb", Iop_Avg8Ux16, False ); |
| 10633 | goto decode_success; |
| 10634 | } |
| 10635 | |
| 10636 | /* 66 0F E3 = PAVGW */ |
| 10637 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE3) { |
| 10638 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10639 | "pavgw", Iop_Avg16Ux8, False ); |
| 10640 | goto decode_success; |
| 10641 | } |
| 10642 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10643 | /* 66 0F 74 = PCMPEQB */ |
| 10644 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x74) { |
| 10645 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10646 | "pcmpeqb", Iop_CmpEQ8x16, False ); |
| 10647 | goto decode_success; |
| 10648 | } |
| 10649 | |
| 10650 | /* 66 0F 76 = PCMPEQD */ |
| 10651 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x76) { |
| 10652 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10653 | "pcmpeqd", Iop_CmpEQ32x4, False ); |
| 10654 | goto decode_success; |
| 10655 | } |
| 10656 | |
| 10657 | /* 66 0F 75 = PCMPEQW */ |
| 10658 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x75) { |
| 10659 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10660 | "pcmpeqw", Iop_CmpEQ16x8, False ); |
| 10661 | goto decode_success; |
| 10662 | } |
| 10663 | |
| 10664 | /* 66 0F 64 = PCMPGTB */ |
| 10665 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x64) { |
| 10666 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10667 | "pcmpgtb", Iop_CmpGT8Sx16, False ); |
| 10668 | goto decode_success; |
| 10669 | } |
| 10670 | |
| 10671 | /* 66 0F 66 = PCMPGTD */ |
| 10672 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x66) { |
| 10673 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10674 | "pcmpgtd", Iop_CmpGT32Sx4, False ); |
| 10675 | goto decode_success; |
| 10676 | } |
| 10677 | |
| 10678 | /* 66 0F 65 = PCMPGTW */ |
| 10679 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x65) { |
| 10680 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10681 | "pcmpgtw", Iop_CmpGT16Sx8, False ); |
| 10682 | goto decode_success; |
| 10683 | } |
| 10684 | |
| 10685 | /* 66 0F C5 = PEXTRW -- extract 16-bit field from xmm(E) and put |
| 10686 | zero-extend of it in ireg(G). */ |
| 10687 | if (insn[0] == 0x0F && insn[1] == 0xC5) { |
| 10688 | modrm = insn[2]; |
| 10689 | if (sz == 2 && epartIsReg(modrm)) { |
| 10690 | t5 = newTemp(Ity_V128); |
| 10691 | t4 = newTemp(Ity_I16); |
| 10692 | assign(t5, getXMMReg(eregOfRM(modrm))); |
| 10693 | breakup128to32s( t5, &t3, &t2, &t1, &t0 ); |
| 10694 | switch (insn[3] & 7) { |
| 10695 | case 0: assign(t4, unop(Iop_32to16, mkexpr(t0))); break; |
| 10696 | case 1: assign(t4, unop(Iop_32HIto16, mkexpr(t0))); break; |
| 10697 | case 2: assign(t4, unop(Iop_32to16, mkexpr(t1))); break; |
| 10698 | case 3: assign(t4, unop(Iop_32HIto16, mkexpr(t1))); break; |
| 10699 | case 4: assign(t4, unop(Iop_32to16, mkexpr(t2))); break; |
| 10700 | case 5: assign(t4, unop(Iop_32HIto16, mkexpr(t2))); break; |
| 10701 | case 6: assign(t4, unop(Iop_32to16, mkexpr(t3))); break; |
| 10702 | case 7: assign(t4, unop(Iop_32HIto16, mkexpr(t3))); break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 10703 | default: vassert(0); /*NOTREACHED*/ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10704 | } |
| 10705 | putIReg(4, gregOfRM(modrm), unop(Iop_16Uto32, mkexpr(t4))); |
| 10706 | DIP("pextrw $%d,%s,%s\n", |
| 10707 | (Int)insn[3], nameXMMReg(eregOfRM(modrm)), |
| 10708 | nameIReg(4,gregOfRM(modrm))); |
| 10709 | delta += 4; |
| 10710 | goto decode_success; |
| 10711 | } |
| 10712 | /* else fall through */ |
| 10713 | } |
| 10714 | |
| 10715 | /* 66 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and |
| 10716 | put it into the specified lane of xmm(G). */ |
| 10717 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC4) { |
| 10718 | Int lane; |
| 10719 | t4 = newTemp(Ity_I16); |
| 10720 | modrm = insn[2]; |
| 10721 | |
| 10722 | if (epartIsReg(modrm)) { |
| 10723 | assign(t4, getIReg(2, eregOfRM(modrm))); |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 10724 | delta += 3+1; |
| 10725 | lane = insn[3+1-1]; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10726 | DIP("pinsrw $%d,%s,%s\n", (Int)lane, |
| 10727 | nameIReg(2,eregOfRM(modrm)), |
| 10728 | nameXMMReg(gregOfRM(modrm))); |
| 10729 | } else { |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 10730 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10731 | delta += 3+alen; |
| 10732 | lane = insn[3+alen-1]; |
| 10733 | assign(t4, loadLE(Ity_I16, mkexpr(addr))); |
| 10734 | DIP("pinsrw $%d,%s,%s\n", (Int)lane, |
| 10735 | dis_buf, |
| 10736 | nameXMMReg(gregOfRM(modrm))); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10737 | } |
| 10738 | |
| 10739 | putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) ); |
| 10740 | goto decode_success; |
| 10741 | } |
| 10742 | |
sewardj | b8a3dea | 2005-10-04 20:00:49 +0000 | [diff] [blame] | 10743 | /* 66 0F F5 = PMADDWD -- Multiply and add packed integers from |
| 10744 | E(xmm or mem) to G(xmm) */ |
| 10745 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF5) { |
| 10746 | IRTemp s1V = newTemp(Ity_V128); |
| 10747 | IRTemp s2V = newTemp(Ity_V128); |
| 10748 | IRTemp dV = newTemp(Ity_V128); |
| 10749 | IRTemp s1Hi = newTemp(Ity_I64); |
| 10750 | IRTemp s1Lo = newTemp(Ity_I64); |
| 10751 | IRTemp s2Hi = newTemp(Ity_I64); |
| 10752 | IRTemp s2Lo = newTemp(Ity_I64); |
| 10753 | IRTemp dHi = newTemp(Ity_I64); |
| 10754 | IRTemp dLo = newTemp(Ity_I64); |
| 10755 | modrm = insn[2]; |
| 10756 | if (epartIsReg(modrm)) { |
| 10757 | assign( s1V, getXMMReg(eregOfRM(modrm)) ); |
| 10758 | delta += 2+1; |
| 10759 | DIP("pmaddwd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10760 | nameXMMReg(gregOfRM(modrm))); |
| 10761 | } else { |
| 10762 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10763 | assign( s1V, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10764 | delta += 2+alen; |
| 10765 | DIP("pmaddwd %s,%s\n", dis_buf, |
| 10766 | nameXMMReg(gregOfRM(modrm))); |
| 10767 | } |
| 10768 | assign( s2V, getXMMReg(gregOfRM(modrm)) ); |
| 10769 | assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) ); |
| 10770 | assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) ); |
| 10771 | assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) ); |
| 10772 | assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) ); |
| 10773 | assign( dHi, mkIRExprCCall( |
| 10774 | Ity_I64, 0/*regparms*/, |
| 10775 | "x86g_calculate_mmx_pmaddwd", |
| 10776 | &x86g_calculate_mmx_pmaddwd, |
| 10777 | mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi)) |
| 10778 | )); |
| 10779 | assign( dLo, mkIRExprCCall( |
| 10780 | Ity_I64, 0/*regparms*/, |
| 10781 | "x86g_calculate_mmx_pmaddwd", |
| 10782 | &x86g_calculate_mmx_pmaddwd, |
| 10783 | mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo)) |
| 10784 | )); |
| 10785 | assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ; |
| 10786 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 10787 | goto decode_success; |
| 10788 | } |
| 10789 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10790 | /* 66 0F EE = PMAXSW -- 16x8 signed max */ |
| 10791 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEE) { |
| 10792 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10793 | "pmaxsw", Iop_Max16Sx8, False ); |
| 10794 | goto decode_success; |
| 10795 | } |
| 10796 | |
| 10797 | /* 66 0F DE = PMAXUB -- 8x16 unsigned max */ |
| 10798 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDE) { |
| 10799 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10800 | "pmaxub", Iop_Max8Ux16, False ); |
| 10801 | goto decode_success; |
| 10802 | } |
| 10803 | |
| 10804 | /* 66 0F EA = PMINSW -- 16x8 signed min */ |
| 10805 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEA) { |
| 10806 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10807 | "pminsw", Iop_Min16Sx8, False ); |
| 10808 | goto decode_success; |
| 10809 | } |
| 10810 | |
| 10811 | /* 66 0F DA = PMINUB -- 8x16 unsigned min */ |
| 10812 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDA) { |
| 10813 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10814 | "pminub", Iop_Min8Ux16, False ); |
| 10815 | goto decode_success; |
| 10816 | } |
| 10817 | |
| 10818 | /* 66 0F D7 = PMOVMSKB -- extract sign bits from each of 16 lanes in |
| 10819 | xmm(G), turn them into a byte, and put zero-extend of it in |
| 10820 | ireg(G). Doing this directly is just too cumbersome; give up |
| 10821 | therefore and call a helper. */ |
| 10822 | /* UInt x86g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo ); */ |
| 10823 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD7) { |
| 10824 | modrm = insn[2]; |
| 10825 | if (epartIsReg(modrm)) { |
| 10826 | t0 = newTemp(Ity_I64); |
| 10827 | t1 = newTemp(Ity_I64); |
| 10828 | assign(t0, getXMMRegLane64(eregOfRM(modrm), 0)); |
| 10829 | assign(t1, getXMMRegLane64(eregOfRM(modrm), 1)); |
| 10830 | t5 = newTemp(Ity_I32); |
| 10831 | assign(t5, mkIRExprCCall( |
| 10832 | Ity_I32, 0/*regparms*/, |
| 10833 | "x86g_calculate_sse_pmovmskb", |
| 10834 | &x86g_calculate_sse_pmovmskb, |
sewardj | 28e5c83 | 2004-12-16 11:39:04 +0000 | [diff] [blame] | 10835 | mkIRExprVec_2( mkexpr(t1), mkexpr(t0) ))); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10836 | putIReg(4, gregOfRM(modrm), mkexpr(t5)); |
| 10837 | DIP("pmovmskb %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10838 | nameIReg(4,gregOfRM(modrm))); |
| 10839 | delta += 3; |
| 10840 | goto decode_success; |
| 10841 | } |
| 10842 | /* else fall through */ |
| 10843 | } |
| 10844 | |
| 10845 | /* 66 0F E4 = PMULHUW -- 16x8 hi-half of unsigned widening multiply */ |
| 10846 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE4) { |
| 10847 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10848 | "pmulhuw", Iop_MulHi16Ux8, False ); |
| 10849 | goto decode_success; |
| 10850 | } |
| 10851 | |
| 10852 | /* 66 0F E5 = PMULHW -- 16x8 hi-half of signed widening multiply */ |
| 10853 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE5) { |
| 10854 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10855 | "pmulhw", Iop_MulHi16Sx8, False ); |
| 10856 | goto decode_success; |
| 10857 | } |
| 10858 | |
| 10859 | /* 66 0F D5 = PMULHL -- 16x8 multiply */ |
| 10860 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD5) { |
| 10861 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10862 | "pmullw", Iop_Mul16x8, False ); |
| 10863 | goto decode_success; |
| 10864 | } |
| 10865 | |
| 10866 | /* ***--- this is an MMX class insn introduced in SSE2 ---*** */ |
| 10867 | /* 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x |
| 10868 | 0 to form 64-bit result */ |
| 10869 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xF4) { |
| 10870 | IRTemp sV = newTemp(Ity_I64); |
| 10871 | IRTemp dV = newTemp(Ity_I64); |
| 10872 | t1 = newTemp(Ity_I32); |
| 10873 | t0 = newTemp(Ity_I32); |
| 10874 | modrm = insn[2]; |
| 10875 | |
| 10876 | do_MMX_preamble(); |
| 10877 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 10878 | |
| 10879 | if (epartIsReg(modrm)) { |
| 10880 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 10881 | delta += 2+1; |
| 10882 | DIP("pmuludq %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 10883 | nameMMXReg(gregOfRM(modrm))); |
| 10884 | } else { |
| 10885 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10886 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 10887 | delta += 2+alen; |
| 10888 | DIP("pmuludq %s,%s\n", dis_buf, |
| 10889 | nameMMXReg(gregOfRM(modrm))); |
| 10890 | } |
| 10891 | |
| 10892 | assign( t0, unop(Iop_64to32, mkexpr(dV)) ); |
| 10893 | assign( t1, unop(Iop_64to32, mkexpr(sV)) ); |
| 10894 | putMMXReg( gregOfRM(modrm), |
| 10895 | binop( Iop_MullU32, mkexpr(t0), mkexpr(t1) ) ); |
| 10896 | goto decode_success; |
| 10897 | } |
| 10898 | |
| 10899 | /* 66 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x |
| 10900 | 0 to form lower 64-bit half and lanes 2 x 2 to form upper 64-bit |
| 10901 | half */ |
| 10902 | /* This is a really poor translation -- could be improved if |
| 10903 | performance critical */ |
| 10904 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF4) { |
| 10905 | IRTemp sV, dV; |
| 10906 | IRTemp s3, s2, s1, s0, d3, d2, d1, d0; |
| 10907 | sV = newTemp(Ity_V128); |
| 10908 | dV = newTemp(Ity_V128); |
| 10909 | s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; |
| 10910 | t1 = newTemp(Ity_I64); |
| 10911 | t0 = newTemp(Ity_I64); |
| 10912 | modrm = insn[2]; |
| 10913 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 10914 | |
| 10915 | if (epartIsReg(modrm)) { |
| 10916 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 10917 | delta += 2+1; |
| 10918 | DIP("pmuludq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10919 | nameXMMReg(gregOfRM(modrm))); |
| 10920 | } else { |
| 10921 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10922 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10923 | delta += 2+alen; |
| 10924 | DIP("pmuludq %s,%s\n", dis_buf, |
| 10925 | nameXMMReg(gregOfRM(modrm))); |
| 10926 | } |
| 10927 | |
| 10928 | breakup128to32s( dV, &d3, &d2, &d1, &d0 ); |
| 10929 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 10930 | |
| 10931 | assign( t0, binop( Iop_MullU32, mkexpr(d0), mkexpr(s0)) ); |
| 10932 | putXMMRegLane64( gregOfRM(modrm), 0, mkexpr(t0) ); |
| 10933 | assign( t1, binop( Iop_MullU32, mkexpr(d2), mkexpr(s2)) ); |
| 10934 | putXMMRegLane64( gregOfRM(modrm), 1, mkexpr(t1) ); |
| 10935 | goto decode_success; |
| 10936 | } |
| 10937 | |
| 10938 | /* 66 0F EB = POR */ |
| 10939 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEB) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10940 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "por", Iop_OrV128 ); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10941 | goto decode_success; |
| 10942 | } |
| 10943 | |
sewardj | 7b5b998 | 2005-10-04 11:43:37 +0000 | [diff] [blame] | 10944 | /* 66 0F F6 = PSADBW -- 2 x (8x8 -> 48 zeroes ++ u16) Sum Abs Diffs |
| 10945 | from E(xmm or mem) to G(xmm) */ |
| 10946 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF6) { |
| 10947 | IRTemp s1V = newTemp(Ity_V128); |
| 10948 | IRTemp s2V = newTemp(Ity_V128); |
| 10949 | IRTemp dV = newTemp(Ity_V128); |
| 10950 | IRTemp s1Hi = newTemp(Ity_I64); |
| 10951 | IRTemp s1Lo = newTemp(Ity_I64); |
| 10952 | IRTemp s2Hi = newTemp(Ity_I64); |
| 10953 | IRTemp s2Lo = newTemp(Ity_I64); |
| 10954 | IRTemp dHi = newTemp(Ity_I64); |
| 10955 | IRTemp dLo = newTemp(Ity_I64); |
| 10956 | modrm = insn[2]; |
| 10957 | if (epartIsReg(modrm)) { |
| 10958 | assign( s1V, getXMMReg(eregOfRM(modrm)) ); |
| 10959 | delta += 2+1; |
| 10960 | DIP("psadbw %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10961 | nameXMMReg(gregOfRM(modrm))); |
| 10962 | } else { |
| 10963 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10964 | assign( s1V, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10965 | delta += 2+alen; |
| 10966 | DIP("psadbw %s,%s\n", dis_buf, |
| 10967 | nameXMMReg(gregOfRM(modrm))); |
| 10968 | } |
| 10969 | assign( s2V, getXMMReg(gregOfRM(modrm)) ); |
| 10970 | assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) ); |
| 10971 | assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) ); |
| 10972 | assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) ); |
| 10973 | assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) ); |
| 10974 | assign( dHi, mkIRExprCCall( |
| 10975 | Ity_I64, 0/*regparms*/, |
| 10976 | "x86g_calculate_mmx_psadbw", |
| 10977 | &x86g_calculate_mmx_psadbw, |
| 10978 | mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi)) |
| 10979 | )); |
| 10980 | assign( dLo, mkIRExprCCall( |
| 10981 | Ity_I64, 0/*regparms*/, |
| 10982 | "x86g_calculate_mmx_psadbw", |
| 10983 | &x86g_calculate_mmx_psadbw, |
| 10984 | mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo)) |
| 10985 | )); |
| 10986 | assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ; |
| 10987 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 10988 | goto decode_success; |
| 10989 | } |
| 10990 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 10991 | /* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */ |
| 10992 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x70) { |
| 10993 | Int order; |
| 10994 | IRTemp sV, dV, s3, s2, s1, s0; |
| 10995 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 10996 | sV = newTemp(Ity_V128); |
| 10997 | dV = newTemp(Ity_V128); |
| 10998 | modrm = insn[2]; |
| 10999 | if (epartIsReg(modrm)) { |
| 11000 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11001 | order = (Int)insn[3]; |
| 11002 | delta += 2+2; |
| 11003 | DIP("pshufd $%d,%s,%s\n", order, |
| 11004 | nameXMMReg(eregOfRM(modrm)), |
| 11005 | nameXMMReg(gregOfRM(modrm))); |
| 11006 | } else { |
| 11007 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11008 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11009 | order = (Int)insn[2+alen]; |
| 11010 | delta += 3+alen; |
| 11011 | DIP("pshufd $%d,%s,%s\n", order, |
| 11012 | dis_buf, |
| 11013 | nameXMMReg(gregOfRM(modrm))); |
| 11014 | } |
| 11015 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 11016 | |
| 11017 | # define SEL(n) \ |
| 11018 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 11019 | assign(dV, |
| 11020 | mk128from32s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 11021 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
| 11022 | ); |
| 11023 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11024 | # undef SEL |
| 11025 | goto decode_success; |
| 11026 | } |
| 11027 | |
| 11028 | /* F3 0F 70 = PSHUFHW -- rearrange upper half 4x16 from E(xmm or |
| 11029 | mem) to G(xmm), and copy lower half */ |
| 11030 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x70) { |
| 11031 | Int order; |
| 11032 | IRTemp sVhi, dVhi, sV, dV, s3, s2, s1, s0; |
| 11033 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11034 | sV = newTemp(Ity_V128); |
| 11035 | dV = newTemp(Ity_V128); |
| 11036 | sVhi = newTemp(Ity_I64); |
| 11037 | dVhi = newTemp(Ity_I64); |
| 11038 | modrm = insn[3]; |
| 11039 | if (epartIsReg(modrm)) { |
| 11040 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11041 | order = (Int)insn[4]; |
| 11042 | delta += 4+1; |
| 11043 | DIP("pshufhw $%d,%s,%s\n", order, |
| 11044 | nameXMMReg(eregOfRM(modrm)), |
| 11045 | nameXMMReg(gregOfRM(modrm))); |
| 11046 | } else { |
| 11047 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11048 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11049 | order = (Int)insn[3+alen]; |
| 11050 | delta += 4+alen; |
| 11051 | DIP("pshufhw $%d,%s,%s\n", order, |
| 11052 | dis_buf, |
| 11053 | nameXMMReg(gregOfRM(modrm))); |
| 11054 | } |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11055 | assign( sVhi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11056 | breakup64to16s( sVhi, &s3, &s2, &s1, &s0 ); |
| 11057 | |
| 11058 | # define SEL(n) \ |
| 11059 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 11060 | assign(dVhi, |
| 11061 | mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 11062 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
| 11063 | ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11064 | assign(dV, binop( Iop_64HLtoV128, |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11065 | mkexpr(dVhi), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11066 | unop(Iop_V128to64, mkexpr(sV))) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11067 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11068 | # undef SEL |
| 11069 | goto decode_success; |
| 11070 | } |
| 11071 | |
| 11072 | /* F2 0F 70 = PSHUFLW -- rearrange lower half 4x16 from E(xmm or |
| 11073 | mem) to G(xmm), and copy upper half */ |
| 11074 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x70) { |
| 11075 | Int order; |
| 11076 | IRTemp sVlo, dVlo, sV, dV, s3, s2, s1, s0; |
| 11077 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11078 | sV = newTemp(Ity_V128); |
| 11079 | dV = newTemp(Ity_V128); |
| 11080 | sVlo = newTemp(Ity_I64); |
| 11081 | dVlo = newTemp(Ity_I64); |
| 11082 | modrm = insn[3]; |
| 11083 | if (epartIsReg(modrm)) { |
| 11084 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11085 | order = (Int)insn[4]; |
| 11086 | delta += 4+1; |
| 11087 | DIP("pshuflw $%d,%s,%s\n", order, |
| 11088 | nameXMMReg(eregOfRM(modrm)), |
| 11089 | nameXMMReg(gregOfRM(modrm))); |
| 11090 | } else { |
| 11091 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11092 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11093 | order = (Int)insn[3+alen]; |
| 11094 | delta += 4+alen; |
| 11095 | DIP("pshuflw $%d,%s,%s\n", order, |
| 11096 | dis_buf, |
| 11097 | nameXMMReg(gregOfRM(modrm))); |
| 11098 | } |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11099 | assign( sVlo, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11100 | breakup64to16s( sVlo, &s3, &s2, &s1, &s0 ); |
| 11101 | |
| 11102 | # define SEL(n) \ |
| 11103 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 11104 | assign(dVlo, |
| 11105 | mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 11106 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
| 11107 | ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11108 | assign(dV, binop( Iop_64HLtoV128, |
| 11109 | unop(Iop_V128HIto64, mkexpr(sV)), |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11110 | mkexpr(dVlo) ) ); |
| 11111 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11112 | # undef SEL |
| 11113 | goto decode_success; |
| 11114 | } |
| 11115 | |
| 11116 | /* 66 0F 72 /6 ib = PSLLD by immediate */ |
| 11117 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x72 |
| 11118 | && epartIsReg(insn[2]) |
| 11119 | && gregOfRM(insn[2]) == 6) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11120 | delta = dis_SSE_shiftE_imm( delta+2, "pslld", Iop_ShlN32x4 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11121 | goto decode_success; |
| 11122 | } |
| 11123 | |
| 11124 | /* 66 0F F2 = PSLLD by E */ |
| 11125 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF2) { |
| 11126 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "pslld", Iop_ShlN32x4 ); |
| 11127 | goto decode_success; |
| 11128 | } |
| 11129 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11130 | /* 66 0F 73 /7 ib = PSLLDQ by immediate */ |
| 11131 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11132 | && epartIsReg(insn[2]) |
| 11133 | && gregOfRM(insn[2]) == 7) { |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11134 | IRTemp sV, dV, hi64, lo64, hi64r, lo64r; |
| 11135 | Int imm = (Int)insn[3]; |
| 11136 | Int reg = eregOfRM(insn[2]); |
| 11137 | DIP("pslldq $%d,%s\n", imm, nameXMMReg(reg)); |
| 11138 | vassert(imm >= 0 && imm <= 255); |
| 11139 | delta += 4; |
| 11140 | |
| 11141 | sV = newTemp(Ity_V128); |
| 11142 | dV = newTemp(Ity_V128); |
| 11143 | hi64 = newTemp(Ity_I64); |
| 11144 | lo64 = newTemp(Ity_I64); |
| 11145 | hi64r = newTemp(Ity_I64); |
| 11146 | lo64r = newTemp(Ity_I64); |
| 11147 | |
| 11148 | if (imm >= 16) { |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11149 | putXMMReg(reg, mkV128(0x0000)); |
| 11150 | goto decode_success; |
| 11151 | } |
| 11152 | |
| 11153 | assign( sV, getXMMReg(reg) ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11154 | assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 11155 | assign( lo64, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11156 | |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 11157 | if (imm == 0) { |
| 11158 | assign( lo64r, mkexpr(lo64) ); |
| 11159 | assign( hi64r, mkexpr(hi64) ); |
| 11160 | } |
| 11161 | else |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11162 | if (imm == 8) { |
| 11163 | assign( lo64r, mkU64(0) ); |
| 11164 | assign( hi64r, mkexpr(lo64) ); |
| 11165 | } |
sewardj | c02043c | 2005-01-11 15:03:53 +0000 | [diff] [blame] | 11166 | else |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11167 | if (imm > 8) { |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11168 | assign( lo64r, mkU64(0) ); |
| 11169 | assign( hi64r, binop( Iop_Shl64, |
| 11170 | mkexpr(lo64), |
| 11171 | mkU8( 8*(imm-8) ) )); |
| 11172 | } else { |
| 11173 | assign( lo64r, binop( Iop_Shl64, |
| 11174 | mkexpr(lo64), |
| 11175 | mkU8(8 * imm) )); |
| 11176 | assign( hi64r, |
| 11177 | binop( Iop_Or64, |
| 11178 | binop(Iop_Shl64, mkexpr(hi64), |
| 11179 | mkU8(8 * imm)), |
| 11180 | binop(Iop_Shr64, mkexpr(lo64), |
| 11181 | mkU8(8 * (8 - imm)) ) |
| 11182 | ) |
| 11183 | ); |
| 11184 | } |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11185 | assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) ); |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11186 | putXMMReg(reg, mkexpr(dV)); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11187 | goto decode_success; |
| 11188 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11189 | |
| 11190 | /* 66 0F 73 /6 ib = PSLLQ by immediate */ |
| 11191 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11192 | && epartIsReg(insn[2]) |
| 11193 | && gregOfRM(insn[2]) == 6) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11194 | delta = dis_SSE_shiftE_imm( delta+2, "psllq", Iop_ShlN64x2 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11195 | goto decode_success; |
| 11196 | } |
| 11197 | |
| 11198 | /* 66 0F F3 = PSLLQ by E */ |
| 11199 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF3) { |
| 11200 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psllq", Iop_ShlN64x2 ); |
| 11201 | goto decode_success; |
| 11202 | } |
| 11203 | |
| 11204 | /* 66 0F 71 /6 ib = PSLLW by immediate */ |
| 11205 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x71 |
| 11206 | && epartIsReg(insn[2]) |
| 11207 | && gregOfRM(insn[2]) == 6) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11208 | delta = dis_SSE_shiftE_imm( delta+2, "psllw", Iop_ShlN16x8 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11209 | goto decode_success; |
| 11210 | } |
| 11211 | |
| 11212 | /* 66 0F F1 = PSLLW by E */ |
| 11213 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF1) { |
| 11214 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psllw", Iop_ShlN16x8 ); |
| 11215 | goto decode_success; |
| 11216 | } |
| 11217 | |
| 11218 | /* 66 0F 72 /4 ib = PSRAD by immediate */ |
| 11219 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x72 |
| 11220 | && epartIsReg(insn[2]) |
| 11221 | && gregOfRM(insn[2]) == 4) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11222 | delta = dis_SSE_shiftE_imm( delta+2, "psrad", Iop_SarN32x4 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11223 | goto decode_success; |
| 11224 | } |
| 11225 | |
| 11226 | /* 66 0F E2 = PSRAD by E */ |
| 11227 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE2) { |
| 11228 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrad", Iop_SarN32x4 ); |
| 11229 | goto decode_success; |
| 11230 | } |
| 11231 | |
| 11232 | /* 66 0F 71 /4 ib = PSRAW by immediate */ |
| 11233 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x71 |
| 11234 | && epartIsReg(insn[2]) |
| 11235 | && gregOfRM(insn[2]) == 4) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11236 | delta = dis_SSE_shiftE_imm( delta+2, "psraw", Iop_SarN16x8 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11237 | goto decode_success; |
| 11238 | } |
| 11239 | |
| 11240 | /* 66 0F E1 = PSRAW by E */ |
| 11241 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE1) { |
| 11242 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psraw", Iop_SarN16x8 ); |
| 11243 | goto decode_success; |
| 11244 | } |
| 11245 | |
| 11246 | /* 66 0F 72 /2 ib = PSRLD by immediate */ |
| 11247 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x72 |
| 11248 | && epartIsReg(insn[2]) |
| 11249 | && gregOfRM(insn[2]) == 2) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11250 | delta = dis_SSE_shiftE_imm( delta+2, "psrld", Iop_ShrN32x4 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11251 | goto decode_success; |
| 11252 | } |
| 11253 | |
| 11254 | /* 66 0F D2 = PSRLD by E */ |
| 11255 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD2) { |
| 11256 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrld", Iop_ShrN32x4 ); |
| 11257 | goto decode_success; |
| 11258 | } |
| 11259 | |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11260 | /* 66 0F 73 /3 ib = PSRLDQ by immediate */ |
| 11261 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11262 | && epartIsReg(insn[2]) |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11263 | && gregOfRM(insn[2]) == 3) { |
| 11264 | IRTemp sV, dV, hi64, lo64, hi64r, lo64r; |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11265 | Int imm = (Int)insn[3]; |
| 11266 | Int reg = eregOfRM(insn[2]); |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11267 | DIP("psrldq $%d,%s\n", imm, nameXMMReg(reg)); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11268 | vassert(imm >= 0 && imm <= 255); |
| 11269 | delta += 4; |
| 11270 | |
| 11271 | sV = newTemp(Ity_V128); |
| 11272 | dV = newTemp(Ity_V128); |
| 11273 | hi64 = newTemp(Ity_I64); |
| 11274 | lo64 = newTemp(Ity_I64); |
| 11275 | hi64r = newTemp(Ity_I64); |
| 11276 | lo64r = newTemp(Ity_I64); |
| 11277 | |
| 11278 | if (imm >= 16) { |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11279 | putXMMReg(reg, mkV128(0x0000)); |
| 11280 | goto decode_success; |
| 11281 | } |
| 11282 | |
| 11283 | assign( sV, getXMMReg(reg) ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11284 | assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 11285 | assign( lo64, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11286 | |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 11287 | if (imm == 0) { |
| 11288 | assign( lo64r, mkexpr(lo64) ); |
| 11289 | assign( hi64r, mkexpr(hi64) ); |
| 11290 | } |
| 11291 | else |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11292 | if (imm == 8) { |
| 11293 | assign( hi64r, mkU64(0) ); |
| 11294 | assign( lo64r, mkexpr(hi64) ); |
| 11295 | } |
| 11296 | else |
| 11297 | if (imm > 8) { |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11298 | assign( hi64r, mkU64(0) ); |
| 11299 | assign( lo64r, binop( Iop_Shr64, |
| 11300 | mkexpr(hi64), |
| 11301 | mkU8( 8*(imm-8) ) )); |
| 11302 | } else { |
| 11303 | assign( hi64r, binop( Iop_Shr64, |
| 11304 | mkexpr(hi64), |
| 11305 | mkU8(8 * imm) )); |
| 11306 | assign( lo64r, |
| 11307 | binop( Iop_Or64, |
| 11308 | binop(Iop_Shr64, mkexpr(lo64), |
| 11309 | mkU8(8 * imm)), |
| 11310 | binop(Iop_Shl64, mkexpr(hi64), |
| 11311 | mkU8(8 * (8 - imm)) ) |
| 11312 | ) |
| 11313 | ); |
| 11314 | } |
| 11315 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11316 | assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11317 | putXMMReg(reg, mkexpr(dV)); |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11318 | goto decode_success; |
| 11319 | } |
| 11320 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11321 | /* 66 0F 73 /2 ib = PSRLQ by immediate */ |
| 11322 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11323 | && epartIsReg(insn[2]) |
| 11324 | && gregOfRM(insn[2]) == 2) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11325 | delta = dis_SSE_shiftE_imm( delta+2, "psrlq", Iop_ShrN64x2 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11326 | goto decode_success; |
| 11327 | } |
| 11328 | |
| 11329 | /* 66 0F D3 = PSRLQ by E */ |
| 11330 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD3) { |
| 11331 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrlq", Iop_ShrN64x2 ); |
| 11332 | goto decode_success; |
| 11333 | } |
| 11334 | |
| 11335 | /* 66 0F 71 /2 ib = PSRLW by immediate */ |
| 11336 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x71 |
| 11337 | && epartIsReg(insn[2]) |
| 11338 | && gregOfRM(insn[2]) == 2) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11339 | delta = dis_SSE_shiftE_imm( delta+2, "psrlw", Iop_ShrN16x8 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11340 | goto decode_success; |
| 11341 | } |
| 11342 | |
| 11343 | /* 66 0F D1 = PSRLW by E */ |
| 11344 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD1) { |
| 11345 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrlw", Iop_ShrN16x8 ); |
| 11346 | goto decode_success; |
| 11347 | } |
| 11348 | |
| 11349 | /* 66 0F F8 = PSUBB */ |
| 11350 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF8) { |
| 11351 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11352 | "psubb", Iop_Sub8x16, False ); |
| 11353 | goto decode_success; |
| 11354 | } |
| 11355 | |
| 11356 | /* 66 0F FA = PSUBD */ |
| 11357 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFA) { |
| 11358 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11359 | "psubd", Iop_Sub32x4, False ); |
| 11360 | goto decode_success; |
| 11361 | } |
| 11362 | |
| 11363 | /* ***--- this is an MMX class insn introduced in SSE2 ---*** */ |
| 11364 | /* 0F FB = PSUBQ -- sub 64x1 */ |
| 11365 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xFB) { |
| 11366 | do_MMX_preamble(); |
| 11367 | delta = dis_MMXop_regmem_to_reg ( |
| 11368 | sorb, delta+2, insn[1], "psubq", False ); |
| 11369 | goto decode_success; |
| 11370 | } |
| 11371 | |
| 11372 | /* 66 0F FB = PSUBQ */ |
| 11373 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFB) { |
| 11374 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11375 | "psubq", Iop_Sub64x2, False ); |
| 11376 | goto decode_success; |
| 11377 | } |
| 11378 | |
| 11379 | /* 66 0F F9 = PSUBW */ |
| 11380 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF9) { |
| 11381 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11382 | "psubw", Iop_Sub16x8, False ); |
| 11383 | goto decode_success; |
| 11384 | } |
| 11385 | |
| 11386 | /* 66 0F E8 = PSUBSB */ |
| 11387 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE8) { |
| 11388 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11389 | "psubsb", Iop_QSub8Sx16, False ); |
| 11390 | goto decode_success; |
| 11391 | } |
| 11392 | |
| 11393 | /* 66 0F E9 = PSUBSW */ |
| 11394 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE9) { |
| 11395 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11396 | "psubsw", Iop_QSub16Sx8, False ); |
| 11397 | goto decode_success; |
| 11398 | } |
| 11399 | |
| 11400 | /* 66 0F D8 = PSUBSB */ |
| 11401 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD8) { |
| 11402 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11403 | "psubusb", Iop_QSub8Ux16, False ); |
| 11404 | goto decode_success; |
| 11405 | } |
| 11406 | |
| 11407 | /* 66 0F D9 = PSUBSW */ |
| 11408 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD9) { |
| 11409 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11410 | "psubusw", Iop_QSub16Ux8, False ); |
| 11411 | goto decode_success; |
| 11412 | } |
| 11413 | |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 11414 | /* 66 0F 68 = PUNPCKHBW */ |
| 11415 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x68) { |
| 11416 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11417 | "punpckhbw", |
| 11418 | Iop_InterleaveHI8x16, True ); |
| 11419 | goto decode_success; |
| 11420 | } |
| 11421 | |
| 11422 | /* 66 0F 6A = PUNPCKHDQ */ |
| 11423 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6A) { |
| 11424 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11425 | "punpckhdq", |
| 11426 | Iop_InterleaveHI32x4, True ); |
| 11427 | goto decode_success; |
| 11428 | } |
| 11429 | |
| 11430 | /* 66 0F 6D = PUNPCKHQDQ */ |
| 11431 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6D) { |
| 11432 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11433 | "punpckhqdq", |
| 11434 | Iop_InterleaveHI64x2, True ); |
| 11435 | goto decode_success; |
| 11436 | } |
| 11437 | |
| 11438 | /* 66 0F 69 = PUNPCKHWD */ |
| 11439 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x69) { |
| 11440 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11441 | "punpckhwd", |
| 11442 | Iop_InterleaveHI16x8, True ); |
| 11443 | goto decode_success; |
| 11444 | } |
| 11445 | |
| 11446 | /* 66 0F 60 = PUNPCKLBW */ |
| 11447 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x60) { |
| 11448 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11449 | "punpcklbw", |
| 11450 | Iop_InterleaveLO8x16, True ); |
| 11451 | goto decode_success; |
| 11452 | } |
| 11453 | |
| 11454 | /* 66 0F 62 = PUNPCKLDQ */ |
| 11455 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x62) { |
| 11456 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11457 | "punpckldq", |
| 11458 | Iop_InterleaveLO32x4, True ); |
| 11459 | goto decode_success; |
| 11460 | } |
| 11461 | |
| 11462 | /* 66 0F 6C = PUNPCKLQDQ */ |
| 11463 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6C) { |
| 11464 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11465 | "punpcklqdq", |
| 11466 | Iop_InterleaveLO64x2, True ); |
| 11467 | goto decode_success; |
| 11468 | } |
| 11469 | |
| 11470 | /* 66 0F 61 = PUNPCKLWD */ |
| 11471 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x61) { |
| 11472 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11473 | "punpcklwd", |
| 11474 | Iop_InterleaveLO16x8, True ); |
| 11475 | goto decode_success; |
| 11476 | } |
| 11477 | |
| 11478 | /* 66 0F EF = PXOR */ |
| 11479 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEF) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11480 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "pxor", Iop_XorV128 ); |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 11481 | goto decode_success; |
| 11482 | } |
| 11483 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11484 | //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */ |
| 11485 | //-- if (insn[0] == 0x0F && insn[1] == 0xAE |
| 11486 | //-- && (!epartIsReg(insn[2])) |
| 11487 | //-- && (gregOfRM(insn[2]) == 1 || gregOfRM(insn[2]) == 0) ) { |
| 11488 | //-- Bool store = gregOfRM(insn[2]) == 0; |
| 11489 | //-- vg_assert(sz == 4); |
| 11490 | //-- pair = disAMode ( cb, sorb, eip+2, dis_buf ); |
| 11491 | //-- t1 = LOW24(pair); |
| 11492 | //-- eip += 2+HI8(pair); |
| 11493 | //-- uInstr3(cb, store ? SSE2a_MemWr : SSE2a_MemRd, 512, |
| 11494 | //-- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1], |
| 11495 | //-- Lit16, (UShort)insn[2], |
| 11496 | //-- TempReg, t1 ); |
| 11497 | //-- DIP("fx%s %s\n", store ? "save" : "rstor", dis_buf ); |
| 11498 | //-- goto decode_success; |
| 11499 | //-- } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11500 | |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 11501 | /* 0F AE /7 = CLFLUSH -- flush cache line */ |
| 11502 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE |
| 11503 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 7) { |
| 11504 | |
| 11505 | /* This is something of a hack. We need to know the size of the |
| 11506 | cache line containing addr. Since we don't (easily), assume |
| 11507 | 256 on the basis that no real cache would have a line that |
| 11508 | big. It's safe to invalidate more stuff than we need, just |
| 11509 | inefficient. */ |
| 11510 | UInt lineszB = 256; |
| 11511 | |
| 11512 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11513 | delta += 2+alen; |
| 11514 | |
| 11515 | /* Round addr down to the start of the containing block. */ |
| 11516 | stmt( IRStmt_Put( |
| 11517 | OFFB_TISTART, |
| 11518 | binop( Iop_And32, |
| 11519 | mkexpr(addr), |
| 11520 | mkU32( ~(lineszB-1) ))) ); |
| 11521 | |
| 11522 | stmt( IRStmt_Put(OFFB_TILEN, mkU32(lineszB) ) ); |
| 11523 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 11524 | irsb->jumpkind = Ijk_TInval; |
| 11525 | irsb->next = mkU32(guest_EIP_bbstart+delta); |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 11526 | dres.whatNext = Dis_StopHere; |
| 11527 | |
| 11528 | DIP("clflush %s\n", dis_buf); |
| 11529 | goto decode_success; |
| 11530 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11531 | |
| 11532 | /* ---------------------------------------------------- */ |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11533 | /* --- end of the SSE2 decoder. --- */ |
| 11534 | /* ---------------------------------------------------- */ |
| 11535 | |
| 11536 | /* ---------------------------------------------------- */ |
| 11537 | /* --- start of the SSE3 decoder. --- */ |
| 11538 | /* ---------------------------------------------------- */ |
| 11539 | |
| 11540 | /* Skip parts of the decoder which don't apply given the stated |
| 11541 | guest subarchitecture. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 11542 | /* if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE3)) */ |
| 11543 | /* In fact this is highly bogus; we accept SSE3 insns even on a |
| 11544 | SSE2-only guest since they turn into IR which can be re-emitted |
| 11545 | successfully on an SSE2 host. */ |
| 11546 | if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2)) |
| 11547 | goto after_sse_decoders; /* no SSE3 capabilities */ |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11548 | |
| 11549 | insn = (UChar*)&guest_code[delta]; |
| 11550 | |
| 11551 | /* F3 0F 12 = MOVSLDUP -- move from E (mem or xmm) to G (xmm), |
| 11552 | duplicating some lanes (2:2:0:0). */ |
| 11553 | /* F3 0F 16 = MOVSHDUP -- move from E (mem or xmm) to G (xmm), |
| 11554 | duplicating some lanes (3:3:1:1). */ |
| 11555 | if (sz == 4 && insn[0] == 0xF3 && insn[1] == 0x0F |
| 11556 | && (insn[2] == 0x12 || insn[2] == 0x16)) { |
| 11557 | IRTemp s3, s2, s1, s0; |
| 11558 | IRTemp sV = newTemp(Ity_V128); |
| 11559 | Bool isH = insn[2] == 0x16; |
| 11560 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11561 | |
| 11562 | modrm = insn[3]; |
| 11563 | if (epartIsReg(modrm)) { |
| 11564 | assign( sV, getXMMReg( eregOfRM(modrm)) ); |
| 11565 | DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l', |
| 11566 | nameXMMReg(eregOfRM(modrm)), |
| 11567 | nameXMMReg(gregOfRM(modrm))); |
| 11568 | delta += 3+1; |
| 11569 | } else { |
| 11570 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 11571 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11572 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11573 | DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l', |
| 11574 | dis_buf, |
| 11575 | nameXMMReg(gregOfRM(modrm))); |
| 11576 | delta += 3+alen; |
| 11577 | } |
| 11578 | |
| 11579 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 11580 | putXMMReg( gregOfRM(modrm), |
| 11581 | isH ? mk128from32s( s3, s3, s1, s1 ) |
| 11582 | : mk128from32s( s2, s2, s0, s0 ) ); |
| 11583 | goto decode_success; |
| 11584 | } |
| 11585 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11586 | /* F2 0F 12 = MOVDDUP -- move from E (mem or xmm) to G (xmm), |
| 11587 | duplicating some lanes (0:1:0:1). */ |
| 11588 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x12) { |
| 11589 | IRTemp sV = newTemp(Ity_V128); |
| 11590 | IRTemp d0 = newTemp(Ity_I64); |
| 11591 | |
| 11592 | modrm = insn[3]; |
| 11593 | if (epartIsReg(modrm)) { |
| 11594 | assign( sV, getXMMReg( eregOfRM(modrm)) ); |
| 11595 | DIP("movddup %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11596 | nameXMMReg(gregOfRM(modrm))); |
| 11597 | delta += 3+1; |
| 11598 | assign ( d0, unop(Iop_V128to64, mkexpr(sV)) ); |
| 11599 | } else { |
| 11600 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11601 | assign( d0, loadLE(Ity_I64, mkexpr(addr)) ); |
| 11602 | DIP("movddup %s,%s\n", dis_buf, |
| 11603 | nameXMMReg(gregOfRM(modrm))); |
| 11604 | delta += 3+alen; |
| 11605 | } |
| 11606 | |
| 11607 | putXMMReg( gregOfRM(modrm), binop(Iop_64HLtoV128,mkexpr(d0),mkexpr(d0)) ); |
| 11608 | goto decode_success; |
| 11609 | } |
| 11610 | |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11611 | /* F2 0F D0 = ADDSUBPS -- 32x4 +/-/+/- from E (mem or xmm) to G (xmm). */ |
| 11612 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xD0) { |
| 11613 | IRTemp a3, a2, a1, a0, s3, s2, s1, s0; |
| 11614 | IRTemp eV = newTemp(Ity_V128); |
| 11615 | IRTemp gV = newTemp(Ity_V128); |
| 11616 | IRTemp addV = newTemp(Ity_V128); |
| 11617 | IRTemp subV = newTemp(Ity_V128); |
| 11618 | a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11619 | |
| 11620 | modrm = insn[3]; |
| 11621 | if (epartIsReg(modrm)) { |
| 11622 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11623 | DIP("addsubps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11624 | nameXMMReg(gregOfRM(modrm))); |
| 11625 | delta += 3+1; |
| 11626 | } else { |
| 11627 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11628 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11629 | DIP("addsubps %s,%s\n", dis_buf, |
| 11630 | nameXMMReg(gregOfRM(modrm))); |
| 11631 | delta += 3+alen; |
| 11632 | } |
| 11633 | |
| 11634 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11635 | |
| 11636 | assign( addV, binop(Iop_Add32Fx4, mkexpr(gV), mkexpr(eV)) ); |
| 11637 | assign( subV, binop(Iop_Sub32Fx4, mkexpr(gV), mkexpr(eV)) ); |
| 11638 | |
| 11639 | breakup128to32s( addV, &a3, &a2, &a1, &a0 ); |
| 11640 | breakup128to32s( subV, &s3, &s2, &s1, &s0 ); |
| 11641 | |
| 11642 | putXMMReg( gregOfRM(modrm), mk128from32s( a3, s2, a1, s0 )); |
| 11643 | goto decode_success; |
| 11644 | } |
| 11645 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11646 | /* 66 0F D0 = ADDSUBPD -- 64x4 +/- from E (mem or xmm) to G (xmm). */ |
| 11647 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD0) { |
| 11648 | IRTemp eV = newTemp(Ity_V128); |
| 11649 | IRTemp gV = newTemp(Ity_V128); |
| 11650 | IRTemp addV = newTemp(Ity_V128); |
| 11651 | IRTemp subV = newTemp(Ity_V128); |
| 11652 | IRTemp a1 = newTemp(Ity_I64); |
| 11653 | IRTemp s0 = newTemp(Ity_I64); |
| 11654 | |
| 11655 | modrm = insn[2]; |
| 11656 | if (epartIsReg(modrm)) { |
| 11657 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11658 | DIP("addsubpd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11659 | nameXMMReg(gregOfRM(modrm))); |
| 11660 | delta += 2+1; |
| 11661 | } else { |
| 11662 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11663 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11664 | DIP("addsubpd %s,%s\n", dis_buf, |
| 11665 | nameXMMReg(gregOfRM(modrm))); |
| 11666 | delta += 2+alen; |
| 11667 | } |
| 11668 | |
| 11669 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11670 | |
| 11671 | assign( addV, binop(Iop_Add64Fx2, mkexpr(gV), mkexpr(eV)) ); |
| 11672 | assign( subV, binop(Iop_Sub64Fx2, mkexpr(gV), mkexpr(eV)) ); |
| 11673 | |
| 11674 | assign( a1, unop(Iop_V128HIto64, mkexpr(addV) )); |
| 11675 | assign( s0, unop(Iop_V128to64, mkexpr(subV) )); |
| 11676 | |
| 11677 | putXMMReg( gregOfRM(modrm), |
| 11678 | binop(Iop_64HLtoV128, mkexpr(a1), mkexpr(s0)) ); |
| 11679 | goto decode_success; |
| 11680 | } |
| 11681 | |
| 11682 | /* F2 0F 7D = HSUBPS -- 32x4 sub across from E (mem or xmm) to G (xmm). */ |
| 11683 | /* F2 0F 7C = HADDPS -- 32x4 add across from E (mem or xmm) to G (xmm). */ |
| 11684 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F |
| 11685 | && (insn[2] == 0x7C || insn[2] == 0x7D)) { |
| 11686 | IRTemp e3, e2, e1, e0, g3, g2, g1, g0; |
| 11687 | IRTemp eV = newTemp(Ity_V128); |
| 11688 | IRTemp gV = newTemp(Ity_V128); |
| 11689 | IRTemp leftV = newTemp(Ity_V128); |
| 11690 | IRTemp rightV = newTemp(Ity_V128); |
| 11691 | Bool isAdd = insn[2] == 0x7C; |
| 11692 | HChar* str = isAdd ? "add" : "sub"; |
| 11693 | e3 = e2 = e1 = e0 = g3 = g2 = g1 = g0 = IRTemp_INVALID; |
| 11694 | |
| 11695 | modrm = insn[3]; |
| 11696 | if (epartIsReg(modrm)) { |
| 11697 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11698 | DIP("h%sps %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 11699 | nameXMMReg(gregOfRM(modrm))); |
| 11700 | delta += 3+1; |
| 11701 | } else { |
| 11702 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11703 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11704 | DIP("h%sps %s,%s\n", str, dis_buf, |
| 11705 | nameXMMReg(gregOfRM(modrm))); |
| 11706 | delta += 3+alen; |
| 11707 | } |
| 11708 | |
| 11709 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11710 | |
| 11711 | breakup128to32s( eV, &e3, &e2, &e1, &e0 ); |
| 11712 | breakup128to32s( gV, &g3, &g2, &g1, &g0 ); |
| 11713 | |
| 11714 | assign( leftV, mk128from32s( e2, e0, g2, g0 ) ); |
| 11715 | assign( rightV, mk128from32s( e3, e1, g3, g1 ) ); |
| 11716 | |
| 11717 | putXMMReg( gregOfRM(modrm), |
| 11718 | binop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, |
| 11719 | mkexpr(leftV), mkexpr(rightV) ) ); |
| 11720 | goto decode_success; |
| 11721 | } |
| 11722 | |
| 11723 | /* 66 0F 7D = HSUBPD -- 64x2 sub across from E (mem or xmm) to G (xmm). */ |
| 11724 | /* 66 0F 7C = HADDPD -- 64x2 add across from E (mem or xmm) to G (xmm). */ |
| 11725 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x7C || insn[1] == 0x7D)) { |
| 11726 | IRTemp e1 = newTemp(Ity_I64); |
| 11727 | IRTemp e0 = newTemp(Ity_I64); |
| 11728 | IRTemp g1 = newTemp(Ity_I64); |
| 11729 | IRTemp g0 = newTemp(Ity_I64); |
| 11730 | IRTemp eV = newTemp(Ity_V128); |
| 11731 | IRTemp gV = newTemp(Ity_V128); |
| 11732 | IRTemp leftV = newTemp(Ity_V128); |
| 11733 | IRTemp rightV = newTemp(Ity_V128); |
| 11734 | Bool isAdd = insn[1] == 0x7C; |
| 11735 | HChar* str = isAdd ? "add" : "sub"; |
| 11736 | |
| 11737 | modrm = insn[2]; |
| 11738 | if (epartIsReg(modrm)) { |
| 11739 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11740 | DIP("h%spd %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 11741 | nameXMMReg(gregOfRM(modrm))); |
| 11742 | delta += 2+1; |
| 11743 | } else { |
| 11744 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11745 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11746 | DIP("h%spd %s,%s\n", str, dis_buf, |
| 11747 | nameXMMReg(gregOfRM(modrm))); |
| 11748 | delta += 2+alen; |
| 11749 | } |
| 11750 | |
| 11751 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11752 | |
| 11753 | assign( e1, unop(Iop_V128HIto64, mkexpr(eV) )); |
| 11754 | assign( e0, unop(Iop_V128to64, mkexpr(eV) )); |
| 11755 | assign( g1, unop(Iop_V128HIto64, mkexpr(gV) )); |
| 11756 | assign( g0, unop(Iop_V128to64, mkexpr(gV) )); |
| 11757 | |
| 11758 | assign( leftV, binop(Iop_64HLtoV128, mkexpr(e0),mkexpr(g0)) ); |
| 11759 | assign( rightV, binop(Iop_64HLtoV128, mkexpr(e1),mkexpr(g1)) ); |
| 11760 | |
| 11761 | putXMMReg( gregOfRM(modrm), |
| 11762 | binop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, |
| 11763 | mkexpr(leftV), mkexpr(rightV) ) ); |
| 11764 | goto decode_success; |
| 11765 | } |
| 11766 | |
| 11767 | /* F2 0F F0 = LDDQU -- move from E (mem or xmm) to G (xmm). */ |
| 11768 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xF0) { |
| 11769 | modrm = getIByte(delta+3); |
| 11770 | if (epartIsReg(modrm)) { |
| 11771 | goto decode_failure; |
| 11772 | } else { |
| 11773 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11774 | putXMMReg( gregOfRM(modrm), |
| 11775 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 11776 | DIP("lddqu %s,%s\n", dis_buf, |
| 11777 | nameXMMReg(gregOfRM(modrm))); |
| 11778 | delta += 3+alen; |
| 11779 | } |
| 11780 | goto decode_success; |
| 11781 | } |
| 11782 | |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11783 | /* ---------------------------------------------------- */ |
| 11784 | /* --- end of the SSE3 decoder. --- */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11785 | /* ---------------------------------------------------- */ |
| 11786 | |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 11787 | /* ---------------------------------------------------- */ |
| 11788 | /* --- start of the SSSE3 decoder. --- */ |
| 11789 | /* ---------------------------------------------------- */ |
| 11790 | |
| 11791 | /* 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and |
| 11792 | Unsigned Bytes (MMX) */ |
| 11793 | if (sz == 4 |
| 11794 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) { |
| 11795 | IRTemp sV = newTemp(Ity_I64); |
| 11796 | IRTemp dV = newTemp(Ity_I64); |
| 11797 | IRTemp sVoddsSX = newTemp(Ity_I64); |
| 11798 | IRTemp sVevensSX = newTemp(Ity_I64); |
| 11799 | IRTemp dVoddsZX = newTemp(Ity_I64); |
| 11800 | IRTemp dVevensZX = newTemp(Ity_I64); |
| 11801 | |
| 11802 | modrm = insn[3]; |
| 11803 | do_MMX_preamble(); |
| 11804 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 11805 | |
| 11806 | if (epartIsReg(modrm)) { |
| 11807 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 11808 | delta += 3+1; |
| 11809 | DIP("pmaddubsw %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 11810 | nameMMXReg(gregOfRM(modrm))); |
| 11811 | } else { |
| 11812 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11813 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 11814 | delta += 3+alen; |
| 11815 | DIP("pmaddubsw %s,%s\n", dis_buf, |
| 11816 | nameMMXReg(gregOfRM(modrm))); |
| 11817 | } |
| 11818 | |
| 11819 | /* compute dV unsigned x sV signed */ |
| 11820 | assign( sVoddsSX, |
| 11821 | binop(Iop_SarN16x4, mkexpr(sV), mkU8(8)) ); |
| 11822 | assign( sVevensSX, |
| 11823 | binop(Iop_SarN16x4, |
| 11824 | binop(Iop_ShlN16x4, mkexpr(sV), mkU8(8)), |
| 11825 | mkU8(8)) ); |
| 11826 | assign( dVoddsZX, |
| 11827 | binop(Iop_ShrN16x4, mkexpr(dV), mkU8(8)) ); |
| 11828 | assign( dVevensZX, |
| 11829 | binop(Iop_ShrN16x4, |
| 11830 | binop(Iop_ShlN16x4, mkexpr(dV), mkU8(8)), |
| 11831 | mkU8(8)) ); |
| 11832 | |
| 11833 | putMMXReg( |
| 11834 | gregOfRM(modrm), |
| 11835 | binop(Iop_QAdd16Sx4, |
| 11836 | binop(Iop_Mul16x4, mkexpr(sVoddsSX), mkexpr(dVoddsZX)), |
| 11837 | binop(Iop_Mul16x4, mkexpr(sVevensSX), mkexpr(dVevensZX)) |
| 11838 | ) |
| 11839 | ); |
| 11840 | goto decode_success; |
| 11841 | } |
| 11842 | |
| 11843 | /* 66 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and |
| 11844 | Unsigned Bytes (XMM) */ |
| 11845 | if (sz == 2 |
| 11846 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) { |
| 11847 | IRTemp sV = newTemp(Ity_V128); |
| 11848 | IRTemp dV = newTemp(Ity_V128); |
| 11849 | IRTemp sVoddsSX = newTemp(Ity_V128); |
| 11850 | IRTemp sVevensSX = newTemp(Ity_V128); |
| 11851 | IRTemp dVoddsZX = newTemp(Ity_V128); |
| 11852 | IRTemp dVevensZX = newTemp(Ity_V128); |
| 11853 | |
| 11854 | modrm = insn[3]; |
| 11855 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 11856 | |
| 11857 | if (epartIsReg(modrm)) { |
| 11858 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11859 | delta += 3+1; |
| 11860 | DIP("pmaddubsw %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11861 | nameXMMReg(gregOfRM(modrm))); |
| 11862 | } else { |
| 11863 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11864 | gen_SEGV_if_not_16_aligned( addr ); |
| 11865 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11866 | delta += 3+alen; |
| 11867 | DIP("pmaddubsw %s,%s\n", dis_buf, |
| 11868 | nameXMMReg(gregOfRM(modrm))); |
| 11869 | } |
| 11870 | |
| 11871 | /* compute dV unsigned x sV signed */ |
| 11872 | assign( sVoddsSX, |
| 11873 | binop(Iop_SarN16x8, mkexpr(sV), mkU8(8)) ); |
| 11874 | assign( sVevensSX, |
| 11875 | binop(Iop_SarN16x8, |
| 11876 | binop(Iop_ShlN16x8, mkexpr(sV), mkU8(8)), |
| 11877 | mkU8(8)) ); |
| 11878 | assign( dVoddsZX, |
| 11879 | binop(Iop_ShrN16x8, mkexpr(dV), mkU8(8)) ); |
| 11880 | assign( dVevensZX, |
| 11881 | binop(Iop_ShrN16x8, |
| 11882 | binop(Iop_ShlN16x8, mkexpr(dV), mkU8(8)), |
| 11883 | mkU8(8)) ); |
| 11884 | |
| 11885 | putXMMReg( |
| 11886 | gregOfRM(modrm), |
| 11887 | binop(Iop_QAdd16Sx8, |
| 11888 | binop(Iop_Mul16x8, mkexpr(sVoddsSX), mkexpr(dVoddsZX)), |
| 11889 | binop(Iop_Mul16x8, mkexpr(sVevensSX), mkexpr(dVevensZX)) |
| 11890 | ) |
| 11891 | ); |
| 11892 | goto decode_success; |
| 11893 | } |
| 11894 | |
| 11895 | /* ***--- these are MMX class insns introduced in SSSE3 ---*** */ |
| 11896 | /* 0F 38 03 = PHADDSW -- 16x4 signed qadd across from E (mem or |
| 11897 | mmx) and G to G (mmx). */ |
| 11898 | /* 0F 38 07 = PHSUBSW -- 16x4 signed qsub across from E (mem or |
| 11899 | mmx) and G to G (mmx). */ |
| 11900 | /* 0F 38 01 = PHADDW -- 16x4 add across from E (mem or mmx) and G |
| 11901 | to G (mmx). */ |
| 11902 | /* 0F 38 05 = PHSUBW -- 16x4 sub across from E (mem or mmx) and G |
| 11903 | to G (mmx). */ |
| 11904 | /* 0F 38 02 = PHADDD -- 32x2 add across from E (mem or mmx) and G |
| 11905 | to G (mmx). */ |
| 11906 | /* 0F 38 06 = PHSUBD -- 32x2 sub across from E (mem or mmx) and G |
| 11907 | to G (mmx). */ |
| 11908 | |
| 11909 | if (sz == 4 |
| 11910 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 11911 | && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01 |
| 11912 | || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) { |
| 11913 | HChar* str = "???"; |
| 11914 | IROp opV64 = Iop_INVALID; |
| 11915 | IROp opCatO = Iop_CatOddLanes16x4; |
| 11916 | IROp opCatE = Iop_CatEvenLanes16x4; |
| 11917 | IRTemp sV = newTemp(Ity_I64); |
| 11918 | IRTemp dV = newTemp(Ity_I64); |
| 11919 | |
| 11920 | modrm = insn[3]; |
| 11921 | |
| 11922 | switch (insn[2]) { |
| 11923 | case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break; |
| 11924 | case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break; |
| 11925 | case 0x01: opV64 = Iop_Add16x4; str = "addw"; break; |
| 11926 | case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break; |
| 11927 | case 0x02: opV64 = Iop_Add32x2; str = "addd"; break; |
| 11928 | case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break; |
| 11929 | default: vassert(0); |
| 11930 | } |
| 11931 | if (insn[2] == 0x02 || insn[2] == 0x06) { |
| 11932 | opCatO = Iop_InterleaveHI32x2; |
| 11933 | opCatE = Iop_InterleaveLO32x2; |
| 11934 | } |
| 11935 | |
| 11936 | do_MMX_preamble(); |
| 11937 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 11938 | |
| 11939 | if (epartIsReg(modrm)) { |
| 11940 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 11941 | delta += 3+1; |
| 11942 | DIP("ph%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)), |
| 11943 | nameMMXReg(gregOfRM(modrm))); |
| 11944 | } else { |
| 11945 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11946 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 11947 | delta += 3+alen; |
| 11948 | DIP("ph%s %s,%s\n", str, dis_buf, |
| 11949 | nameMMXReg(gregOfRM(modrm))); |
| 11950 | } |
| 11951 | |
| 11952 | putMMXReg( |
| 11953 | gregOfRM(modrm), |
| 11954 | binop(opV64, |
| 11955 | binop(opCatE,mkexpr(sV),mkexpr(dV)), |
| 11956 | binop(opCatO,mkexpr(sV),mkexpr(dV)) |
| 11957 | ) |
| 11958 | ); |
| 11959 | goto decode_success; |
| 11960 | } |
| 11961 | |
| 11962 | /* 66 0F 38 03 = PHADDSW -- 16x8 signed qadd across from E (mem or |
| 11963 | xmm) and G to G (xmm). */ |
| 11964 | /* 66 0F 38 07 = PHSUBSW -- 16x8 signed qsub across from E (mem or |
| 11965 | xmm) and G to G (xmm). */ |
| 11966 | /* 66 0F 38 01 = PHADDW -- 16x8 add across from E (mem or xmm) and |
| 11967 | G to G (xmm). */ |
| 11968 | /* 66 0F 38 05 = PHSUBW -- 16x8 sub across from E (mem or xmm) and |
| 11969 | G to G (xmm). */ |
| 11970 | /* 66 0F 38 02 = PHADDD -- 32x4 add across from E (mem or xmm) and |
| 11971 | G to G (xmm). */ |
| 11972 | /* 66 0F 38 06 = PHSUBD -- 32x4 sub across from E (mem or xmm) and |
| 11973 | G to G (xmm). */ |
| 11974 | |
| 11975 | if (sz == 2 |
| 11976 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 11977 | && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01 |
| 11978 | || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) { |
| 11979 | HChar* str = "???"; |
| 11980 | IROp opV64 = Iop_INVALID; |
| 11981 | IROp opCatO = Iop_CatOddLanes16x4; |
| 11982 | IROp opCatE = Iop_CatEvenLanes16x4; |
| 11983 | IRTemp sV = newTemp(Ity_V128); |
| 11984 | IRTemp dV = newTemp(Ity_V128); |
| 11985 | IRTemp sHi = newTemp(Ity_I64); |
| 11986 | IRTemp sLo = newTemp(Ity_I64); |
| 11987 | IRTemp dHi = newTemp(Ity_I64); |
| 11988 | IRTemp dLo = newTemp(Ity_I64); |
| 11989 | |
| 11990 | modrm = insn[3]; |
| 11991 | |
| 11992 | switch (insn[2]) { |
| 11993 | case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break; |
| 11994 | case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break; |
| 11995 | case 0x01: opV64 = Iop_Add16x4; str = "addw"; break; |
| 11996 | case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break; |
| 11997 | case 0x02: opV64 = Iop_Add32x2; str = "addd"; break; |
| 11998 | case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break; |
| 11999 | default: vassert(0); |
| 12000 | } |
| 12001 | if (insn[2] == 0x02 || insn[2] == 0x06) { |
| 12002 | opCatO = Iop_InterleaveHI32x2; |
| 12003 | opCatE = Iop_InterleaveLO32x2; |
| 12004 | } |
| 12005 | |
| 12006 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12007 | |
| 12008 | if (epartIsReg(modrm)) { |
| 12009 | assign( sV, getXMMReg( eregOfRM(modrm)) ); |
| 12010 | DIP("ph%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 12011 | nameXMMReg(gregOfRM(modrm))); |
| 12012 | delta += 3+1; |
| 12013 | } else { |
| 12014 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12015 | gen_SEGV_if_not_16_aligned( addr ); |
| 12016 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12017 | DIP("ph%s %s,%s\n", str, dis_buf, |
| 12018 | nameXMMReg(gregOfRM(modrm))); |
| 12019 | delta += 3+alen; |
| 12020 | } |
| 12021 | |
| 12022 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12023 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12024 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12025 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12026 | |
| 12027 | /* This isn't a particularly efficient way to compute the |
| 12028 | result, but at least it avoids a proliferation of IROps, |
| 12029 | hence avoids complication all the backends. */ |
| 12030 | putXMMReg( |
| 12031 | gregOfRM(modrm), |
| 12032 | binop(Iop_64HLtoV128, |
| 12033 | binop(opV64, |
| 12034 | binop(opCatE,mkexpr(sHi),mkexpr(sLo)), |
| 12035 | binop(opCatO,mkexpr(sHi),mkexpr(sLo)) |
| 12036 | ), |
| 12037 | binop(opV64, |
| 12038 | binop(opCatE,mkexpr(dHi),mkexpr(dLo)), |
| 12039 | binop(opCatO,mkexpr(dHi),mkexpr(dLo)) |
| 12040 | ) |
| 12041 | ) |
| 12042 | ); |
| 12043 | goto decode_success; |
| 12044 | } |
| 12045 | |
| 12046 | /* 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and Scale |
| 12047 | (MMX) */ |
| 12048 | if (sz == 4 |
| 12049 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) { |
| 12050 | IRTemp sV = newTemp(Ity_I64); |
| 12051 | IRTemp dV = newTemp(Ity_I64); |
| 12052 | |
| 12053 | modrm = insn[3]; |
| 12054 | do_MMX_preamble(); |
| 12055 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12056 | |
| 12057 | if (epartIsReg(modrm)) { |
| 12058 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12059 | delta += 3+1; |
| 12060 | DIP("pmulhrsw %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 12061 | nameMMXReg(gregOfRM(modrm))); |
| 12062 | } else { |
| 12063 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12064 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12065 | delta += 3+alen; |
| 12066 | DIP("pmulhrsw %s,%s\n", dis_buf, |
| 12067 | nameMMXReg(gregOfRM(modrm))); |
| 12068 | } |
| 12069 | |
| 12070 | putMMXReg( |
| 12071 | gregOfRM(modrm), |
| 12072 | dis_PMULHRSW_helper( mkexpr(sV), mkexpr(dV) ) |
| 12073 | ); |
| 12074 | goto decode_success; |
| 12075 | } |
| 12076 | |
| 12077 | /* 66 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and |
| 12078 | Scale (XMM) */ |
| 12079 | if (sz == 2 |
| 12080 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) { |
| 12081 | IRTemp sV = newTemp(Ity_V128); |
| 12082 | IRTemp dV = newTemp(Ity_V128); |
| 12083 | IRTemp sHi = newTemp(Ity_I64); |
| 12084 | IRTemp sLo = newTemp(Ity_I64); |
| 12085 | IRTemp dHi = newTemp(Ity_I64); |
| 12086 | IRTemp dLo = newTemp(Ity_I64); |
| 12087 | |
| 12088 | modrm = insn[3]; |
| 12089 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12090 | |
| 12091 | if (epartIsReg(modrm)) { |
| 12092 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12093 | delta += 3+1; |
| 12094 | DIP("pmulhrsw %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 12095 | nameXMMReg(gregOfRM(modrm))); |
| 12096 | } else { |
| 12097 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12098 | gen_SEGV_if_not_16_aligned( addr ); |
| 12099 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12100 | delta += 3+alen; |
| 12101 | DIP("pmulhrsw %s,%s\n", dis_buf, |
| 12102 | nameXMMReg(gregOfRM(modrm))); |
| 12103 | } |
| 12104 | |
| 12105 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12106 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12107 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12108 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12109 | |
| 12110 | putXMMReg( |
| 12111 | gregOfRM(modrm), |
| 12112 | binop(Iop_64HLtoV128, |
| 12113 | dis_PMULHRSW_helper( mkexpr(sHi), mkexpr(dHi) ), |
| 12114 | dis_PMULHRSW_helper( mkexpr(sLo), mkexpr(dLo) ) |
| 12115 | ) |
| 12116 | ); |
| 12117 | goto decode_success; |
| 12118 | } |
| 12119 | |
| 12120 | /* 0F 38 08 = PSIGNB -- Packed Sign 8x8 (MMX) */ |
| 12121 | /* 0F 38 09 = PSIGNW -- Packed Sign 16x4 (MMX) */ |
| 12122 | /* 0F 38 09 = PSIGND -- Packed Sign 32x2 (MMX) */ |
| 12123 | if (sz == 4 |
| 12124 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12125 | && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) { |
| 12126 | IRTemp sV = newTemp(Ity_I64); |
| 12127 | IRTemp dV = newTemp(Ity_I64); |
| 12128 | HChar* str = "???"; |
| 12129 | Int laneszB = 0; |
| 12130 | |
| 12131 | switch (insn[2]) { |
| 12132 | case 0x08: laneszB = 1; str = "b"; break; |
| 12133 | case 0x09: laneszB = 2; str = "w"; break; |
| 12134 | case 0x0A: laneszB = 4; str = "d"; break; |
| 12135 | default: vassert(0); |
| 12136 | } |
| 12137 | |
| 12138 | modrm = insn[3]; |
| 12139 | do_MMX_preamble(); |
| 12140 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12141 | |
| 12142 | if (epartIsReg(modrm)) { |
| 12143 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12144 | delta += 3+1; |
| 12145 | DIP("psign%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)), |
| 12146 | nameMMXReg(gregOfRM(modrm))); |
| 12147 | } else { |
| 12148 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12149 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12150 | delta += 3+alen; |
| 12151 | DIP("psign%s %s,%s\n", str, dis_buf, |
| 12152 | nameMMXReg(gregOfRM(modrm))); |
| 12153 | } |
| 12154 | |
| 12155 | putMMXReg( |
| 12156 | gregOfRM(modrm), |
| 12157 | dis_PSIGN_helper( mkexpr(sV), mkexpr(dV), laneszB ) |
| 12158 | ); |
| 12159 | goto decode_success; |
| 12160 | } |
| 12161 | |
| 12162 | /* 66 0F 38 08 = PSIGNB -- Packed Sign 8x16 (XMM) */ |
| 12163 | /* 66 0F 38 09 = PSIGNW -- Packed Sign 16x8 (XMM) */ |
| 12164 | /* 66 0F 38 09 = PSIGND -- Packed Sign 32x4 (XMM) */ |
| 12165 | if (sz == 2 |
| 12166 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12167 | && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) { |
| 12168 | IRTemp sV = newTemp(Ity_V128); |
| 12169 | IRTemp dV = newTemp(Ity_V128); |
| 12170 | IRTemp sHi = newTemp(Ity_I64); |
| 12171 | IRTemp sLo = newTemp(Ity_I64); |
| 12172 | IRTemp dHi = newTemp(Ity_I64); |
| 12173 | IRTemp dLo = newTemp(Ity_I64); |
| 12174 | HChar* str = "???"; |
| 12175 | Int laneszB = 0; |
| 12176 | |
| 12177 | switch (insn[2]) { |
| 12178 | case 0x08: laneszB = 1; str = "b"; break; |
| 12179 | case 0x09: laneszB = 2; str = "w"; break; |
| 12180 | case 0x0A: laneszB = 4; str = "d"; break; |
| 12181 | default: vassert(0); |
| 12182 | } |
| 12183 | |
| 12184 | modrm = insn[3]; |
| 12185 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12186 | |
| 12187 | if (epartIsReg(modrm)) { |
| 12188 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12189 | delta += 3+1; |
| 12190 | DIP("psign%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 12191 | nameXMMReg(gregOfRM(modrm))); |
| 12192 | } else { |
| 12193 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12194 | gen_SEGV_if_not_16_aligned( addr ); |
| 12195 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12196 | delta += 3+alen; |
| 12197 | DIP("psign%s %s,%s\n", str, dis_buf, |
| 12198 | nameXMMReg(gregOfRM(modrm))); |
| 12199 | } |
| 12200 | |
| 12201 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12202 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12203 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12204 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12205 | |
| 12206 | putXMMReg( |
| 12207 | gregOfRM(modrm), |
| 12208 | binop(Iop_64HLtoV128, |
| 12209 | dis_PSIGN_helper( mkexpr(sHi), mkexpr(dHi), laneszB ), |
| 12210 | dis_PSIGN_helper( mkexpr(sLo), mkexpr(dLo), laneszB ) |
| 12211 | ) |
| 12212 | ); |
| 12213 | goto decode_success; |
| 12214 | } |
| 12215 | |
| 12216 | /* 0F 38 1C = PABSB -- Packed Absolute Value 8x8 (MMX) */ |
| 12217 | /* 0F 38 1D = PABSW -- Packed Absolute Value 16x4 (MMX) */ |
| 12218 | /* 0F 38 1E = PABSD -- Packed Absolute Value 32x2 (MMX) */ |
| 12219 | if (sz == 4 |
| 12220 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12221 | && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) { |
| 12222 | IRTemp sV = newTemp(Ity_I64); |
| 12223 | HChar* str = "???"; |
| 12224 | Int laneszB = 0; |
| 12225 | |
| 12226 | switch (insn[2]) { |
| 12227 | case 0x1C: laneszB = 1; str = "b"; break; |
| 12228 | case 0x1D: laneszB = 2; str = "w"; break; |
| 12229 | case 0x1E: laneszB = 4; str = "d"; break; |
| 12230 | default: vassert(0); |
| 12231 | } |
| 12232 | |
| 12233 | modrm = insn[3]; |
| 12234 | do_MMX_preamble(); |
| 12235 | |
| 12236 | if (epartIsReg(modrm)) { |
| 12237 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12238 | delta += 3+1; |
| 12239 | DIP("pabs%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)), |
| 12240 | nameMMXReg(gregOfRM(modrm))); |
| 12241 | } else { |
| 12242 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12243 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12244 | delta += 3+alen; |
| 12245 | DIP("pabs%s %s,%s\n", str, dis_buf, |
| 12246 | nameMMXReg(gregOfRM(modrm))); |
| 12247 | } |
| 12248 | |
| 12249 | putMMXReg( |
| 12250 | gregOfRM(modrm), |
| 12251 | dis_PABS_helper( mkexpr(sV), laneszB ) |
| 12252 | ); |
| 12253 | goto decode_success; |
| 12254 | } |
| 12255 | |
| 12256 | /* 66 0F 38 1C = PABSB -- Packed Absolute Value 8x16 (XMM) */ |
| 12257 | /* 66 0F 38 1D = PABSW -- Packed Absolute Value 16x8 (XMM) */ |
| 12258 | /* 66 0F 38 1E = PABSD -- Packed Absolute Value 32x4 (XMM) */ |
| 12259 | if (sz == 2 |
| 12260 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12261 | && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) { |
| 12262 | IRTemp sV = newTemp(Ity_V128); |
| 12263 | IRTemp sHi = newTemp(Ity_I64); |
| 12264 | IRTemp sLo = newTemp(Ity_I64); |
| 12265 | HChar* str = "???"; |
| 12266 | Int laneszB = 0; |
| 12267 | |
| 12268 | switch (insn[2]) { |
| 12269 | case 0x1C: laneszB = 1; str = "b"; break; |
| 12270 | case 0x1D: laneszB = 2; str = "w"; break; |
| 12271 | case 0x1E: laneszB = 4; str = "d"; break; |
| 12272 | default: vassert(0); |
| 12273 | } |
| 12274 | |
| 12275 | modrm = insn[3]; |
| 12276 | |
| 12277 | if (epartIsReg(modrm)) { |
| 12278 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12279 | delta += 3+1; |
| 12280 | DIP("pabs%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 12281 | nameXMMReg(gregOfRM(modrm))); |
| 12282 | } else { |
| 12283 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12284 | gen_SEGV_if_not_16_aligned( addr ); |
| 12285 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12286 | delta += 3+alen; |
| 12287 | DIP("pabs%s %s,%s\n", str, dis_buf, |
| 12288 | nameXMMReg(gregOfRM(modrm))); |
| 12289 | } |
| 12290 | |
| 12291 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12292 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12293 | |
| 12294 | putXMMReg( |
| 12295 | gregOfRM(modrm), |
| 12296 | binop(Iop_64HLtoV128, |
| 12297 | dis_PABS_helper( mkexpr(sHi), laneszB ), |
| 12298 | dis_PABS_helper( mkexpr(sLo), laneszB ) |
| 12299 | ) |
| 12300 | ); |
| 12301 | goto decode_success; |
| 12302 | } |
| 12303 | |
| 12304 | /* 0F 3A 0F = PALIGNR -- Packed Align Right (MMX) */ |
| 12305 | if (sz == 4 |
| 12306 | && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) { |
| 12307 | IRTemp sV = newTemp(Ity_I64); |
| 12308 | IRTemp dV = newTemp(Ity_I64); |
| 12309 | IRTemp res = newTemp(Ity_I64); |
| 12310 | |
| 12311 | modrm = insn[3]; |
| 12312 | do_MMX_preamble(); |
| 12313 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12314 | |
| 12315 | if (epartIsReg(modrm)) { |
| 12316 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12317 | d32 = (UInt)insn[3+1]; |
| 12318 | delta += 3+1+1; |
| 12319 | DIP("palignr $%d,%s,%s\n", (Int)d32, |
| 12320 | nameMMXReg(eregOfRM(modrm)), |
| 12321 | nameMMXReg(gregOfRM(modrm))); |
| 12322 | } else { |
| 12323 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12324 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12325 | d32 = (UInt)insn[3+alen]; |
| 12326 | delta += 3+alen+1; |
| 12327 | DIP("palignr $%d%s,%s\n", (Int)d32, |
| 12328 | dis_buf, |
| 12329 | nameMMXReg(gregOfRM(modrm))); |
| 12330 | } |
| 12331 | |
| 12332 | if (d32 == 0) { |
| 12333 | assign( res, mkexpr(sV) ); |
| 12334 | } |
| 12335 | else if (d32 >= 1 && d32 <= 7) { |
| 12336 | assign(res, |
| 12337 | binop(Iop_Or64, |
| 12338 | binop(Iop_Shr64, mkexpr(sV), mkU8(8*d32)), |
| 12339 | binop(Iop_Shl64, mkexpr(dV), mkU8(8*(8-d32)) |
| 12340 | ))); |
| 12341 | } |
| 12342 | else if (d32 == 8) { |
| 12343 | assign( res, mkexpr(dV) ); |
| 12344 | } |
| 12345 | else if (d32 >= 9 && d32 <= 15) { |
| 12346 | assign( res, binop(Iop_Shr64, mkexpr(dV), mkU8(8*(d32-8))) ); |
| 12347 | } |
| 12348 | else if (d32 >= 16 && d32 <= 255) { |
| 12349 | assign( res, mkU64(0) ); |
| 12350 | } |
| 12351 | else |
| 12352 | vassert(0); |
| 12353 | |
| 12354 | putMMXReg( gregOfRM(modrm), mkexpr(res) ); |
| 12355 | goto decode_success; |
| 12356 | } |
| 12357 | |
| 12358 | /* 66 0F 3A 0F = PALIGNR -- Packed Align Right (XMM) */ |
| 12359 | if (sz == 2 |
| 12360 | && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) { |
| 12361 | IRTemp sV = newTemp(Ity_V128); |
| 12362 | IRTemp dV = newTemp(Ity_V128); |
| 12363 | IRTemp sHi = newTemp(Ity_I64); |
| 12364 | IRTemp sLo = newTemp(Ity_I64); |
| 12365 | IRTemp dHi = newTemp(Ity_I64); |
| 12366 | IRTemp dLo = newTemp(Ity_I64); |
| 12367 | IRTemp rHi = newTemp(Ity_I64); |
| 12368 | IRTemp rLo = newTemp(Ity_I64); |
| 12369 | |
| 12370 | modrm = insn[3]; |
| 12371 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12372 | |
| 12373 | if (epartIsReg(modrm)) { |
| 12374 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12375 | d32 = (UInt)insn[3+1]; |
| 12376 | delta += 3+1+1; |
| 12377 | DIP("palignr $%d,%s,%s\n", (Int)d32, |
| 12378 | nameXMMReg(eregOfRM(modrm)), |
| 12379 | nameXMMReg(gregOfRM(modrm))); |
| 12380 | } else { |
| 12381 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12382 | gen_SEGV_if_not_16_aligned( addr ); |
| 12383 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12384 | d32 = (UInt)insn[3+alen]; |
| 12385 | delta += 3+alen+1; |
| 12386 | DIP("palignr $%d,%s,%s\n", (Int)d32, |
| 12387 | dis_buf, |
| 12388 | nameXMMReg(gregOfRM(modrm))); |
| 12389 | } |
| 12390 | |
| 12391 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12392 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12393 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12394 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12395 | |
| 12396 | if (d32 == 0) { |
| 12397 | assign( rHi, mkexpr(sHi) ); |
| 12398 | assign( rLo, mkexpr(sLo) ); |
| 12399 | } |
| 12400 | else if (d32 >= 1 && d32 <= 7) { |
| 12401 | assign( rHi, dis_PALIGNR_XMM_helper(dLo, sHi, d32) ); |
| 12402 | assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, d32) ); |
| 12403 | } |
| 12404 | else if (d32 == 8) { |
| 12405 | assign( rHi, mkexpr(dLo) ); |
| 12406 | assign( rLo, mkexpr(sHi) ); |
| 12407 | } |
| 12408 | else if (d32 >= 9 && d32 <= 15) { |
| 12409 | assign( rHi, dis_PALIGNR_XMM_helper(dHi, dLo, d32-8) ); |
| 12410 | assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, d32-8) ); |
| 12411 | } |
| 12412 | else if (d32 == 16) { |
| 12413 | assign( rHi, mkexpr(dHi) ); |
| 12414 | assign( rLo, mkexpr(dLo) ); |
| 12415 | } |
| 12416 | else if (d32 >= 17 && d32 <= 23) { |
| 12417 | assign( rHi, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d32-16))) ); |
| 12418 | assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, d32-16) ); |
| 12419 | } |
| 12420 | else if (d32 == 24) { |
| 12421 | assign( rHi, mkU64(0) ); |
| 12422 | assign( rLo, mkexpr(dHi) ); |
| 12423 | } |
| 12424 | else if (d32 >= 25 && d32 <= 31) { |
| 12425 | assign( rHi, mkU64(0) ); |
| 12426 | assign( rLo, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d32-24))) ); |
| 12427 | } |
| 12428 | else if (d32 >= 32 && d32 <= 255) { |
| 12429 | assign( rHi, mkU64(0) ); |
| 12430 | assign( rLo, mkU64(0) ); |
| 12431 | } |
| 12432 | else |
| 12433 | vassert(0); |
| 12434 | |
| 12435 | putXMMReg( |
| 12436 | gregOfRM(modrm), |
| 12437 | binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo)) |
| 12438 | ); |
| 12439 | goto decode_success; |
| 12440 | } |
| 12441 | |
| 12442 | /* 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x8 (MMX) */ |
| 12443 | if (sz == 4 |
| 12444 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) { |
| 12445 | IRTemp sV = newTemp(Ity_I64); |
| 12446 | IRTemp dV = newTemp(Ity_I64); |
| 12447 | |
| 12448 | modrm = insn[3]; |
| 12449 | do_MMX_preamble(); |
| 12450 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12451 | |
| 12452 | if (epartIsReg(modrm)) { |
| 12453 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12454 | delta += 3+1; |
| 12455 | DIP("pshufb %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 12456 | nameMMXReg(gregOfRM(modrm))); |
| 12457 | } else { |
| 12458 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12459 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12460 | delta += 3+alen; |
| 12461 | DIP("pshufb %s,%s\n", dis_buf, |
| 12462 | nameMMXReg(gregOfRM(modrm))); |
| 12463 | } |
| 12464 | |
| 12465 | putMMXReg( |
| 12466 | gregOfRM(modrm), |
| 12467 | binop( |
| 12468 | Iop_And64, |
| 12469 | /* permute the lanes */ |
| 12470 | binop( |
| 12471 | Iop_Perm8x8, |
| 12472 | mkexpr(dV), |
| 12473 | binop(Iop_And64, mkexpr(sV), mkU64(0x0707070707070707ULL)) |
| 12474 | ), |
| 12475 | /* mask off lanes which have (index & 0x80) == 0x80 */ |
| 12476 | unop(Iop_Not64, binop(Iop_SarN8x8, mkexpr(sV), mkU8(7))) |
| 12477 | ) |
| 12478 | ); |
| 12479 | goto decode_success; |
| 12480 | } |
| 12481 | |
| 12482 | /* 66 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x16 (XMM) */ |
| 12483 | if (sz == 2 |
| 12484 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) { |
| 12485 | IRTemp sV = newTemp(Ity_V128); |
| 12486 | IRTemp dV = newTemp(Ity_V128); |
| 12487 | IRTemp sHi = newTemp(Ity_I64); |
| 12488 | IRTemp sLo = newTemp(Ity_I64); |
| 12489 | IRTemp dHi = newTemp(Ity_I64); |
| 12490 | IRTemp dLo = newTemp(Ity_I64); |
| 12491 | IRTemp rHi = newTemp(Ity_I64); |
| 12492 | IRTemp rLo = newTemp(Ity_I64); |
| 12493 | IRTemp sevens = newTemp(Ity_I64); |
| 12494 | IRTemp mask0x80hi = newTemp(Ity_I64); |
| 12495 | IRTemp mask0x80lo = newTemp(Ity_I64); |
| 12496 | IRTemp maskBit3hi = newTemp(Ity_I64); |
| 12497 | IRTemp maskBit3lo = newTemp(Ity_I64); |
| 12498 | IRTemp sAnd7hi = newTemp(Ity_I64); |
| 12499 | IRTemp sAnd7lo = newTemp(Ity_I64); |
| 12500 | IRTemp permdHi = newTemp(Ity_I64); |
| 12501 | IRTemp permdLo = newTemp(Ity_I64); |
| 12502 | |
| 12503 | modrm = insn[3]; |
| 12504 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12505 | |
| 12506 | if (epartIsReg(modrm)) { |
| 12507 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12508 | delta += 3+1; |
| 12509 | DIP("pshufb %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 12510 | nameXMMReg(gregOfRM(modrm))); |
| 12511 | } else { |
| 12512 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12513 | gen_SEGV_if_not_16_aligned( addr ); |
| 12514 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12515 | delta += 3+alen; |
| 12516 | DIP("pshufb %s,%s\n", dis_buf, |
| 12517 | nameXMMReg(gregOfRM(modrm))); |
| 12518 | } |
| 12519 | |
| 12520 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12521 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12522 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12523 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12524 | |
| 12525 | assign( sevens, mkU64(0x0707070707070707ULL) ); |
| 12526 | |
| 12527 | /* |
| 12528 | mask0x80hi = Not(SarN8x8(sHi,7)) |
| 12529 | maskBit3hi = SarN8x8(ShlN8x8(sHi,4),7) |
| 12530 | sAnd7hi = And(sHi,sevens) |
| 12531 | permdHi = Or( And(Perm8x8(dHi,sAnd7hi),maskBit3hi), |
| 12532 | And(Perm8x8(dLo,sAnd7hi),Not(maskBit3hi)) ) |
| 12533 | rHi = And(permdHi,mask0x80hi) |
| 12534 | */ |
| 12535 | assign( |
| 12536 | mask0x80hi, |
| 12537 | unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sHi),mkU8(7)))); |
| 12538 | |
| 12539 | assign( |
| 12540 | maskBit3hi, |
| 12541 | binop(Iop_SarN8x8, |
| 12542 | binop(Iop_ShlN8x8,mkexpr(sHi),mkU8(4)), |
| 12543 | mkU8(7))); |
| 12544 | |
| 12545 | assign(sAnd7hi, binop(Iop_And64,mkexpr(sHi),mkexpr(sevens))); |
| 12546 | |
| 12547 | assign( |
| 12548 | permdHi, |
| 12549 | binop( |
| 12550 | Iop_Or64, |
| 12551 | binop(Iop_And64, |
| 12552 | binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7hi)), |
| 12553 | mkexpr(maskBit3hi)), |
| 12554 | binop(Iop_And64, |
| 12555 | binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7hi)), |
| 12556 | unop(Iop_Not64,mkexpr(maskBit3hi))) )); |
| 12557 | |
| 12558 | assign(rHi, binop(Iop_And64,mkexpr(permdHi),mkexpr(mask0x80hi)) ); |
| 12559 | |
| 12560 | /* And the same for the lower half of the result. What fun. */ |
| 12561 | |
| 12562 | assign( |
| 12563 | mask0x80lo, |
| 12564 | unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sLo),mkU8(7)))); |
| 12565 | |
| 12566 | assign( |
| 12567 | maskBit3lo, |
| 12568 | binop(Iop_SarN8x8, |
| 12569 | binop(Iop_ShlN8x8,mkexpr(sLo),mkU8(4)), |
| 12570 | mkU8(7))); |
| 12571 | |
| 12572 | assign(sAnd7lo, binop(Iop_And64,mkexpr(sLo),mkexpr(sevens))); |
| 12573 | |
| 12574 | assign( |
| 12575 | permdLo, |
| 12576 | binop( |
| 12577 | Iop_Or64, |
| 12578 | binop(Iop_And64, |
| 12579 | binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7lo)), |
| 12580 | mkexpr(maskBit3lo)), |
| 12581 | binop(Iop_And64, |
| 12582 | binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7lo)), |
| 12583 | unop(Iop_Not64,mkexpr(maskBit3lo))) )); |
| 12584 | |
| 12585 | assign(rLo, binop(Iop_And64,mkexpr(permdLo),mkexpr(mask0x80lo)) ); |
| 12586 | |
| 12587 | putXMMReg( |
| 12588 | gregOfRM(modrm), |
| 12589 | binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo)) |
| 12590 | ); |
| 12591 | goto decode_success; |
| 12592 | } |
| 12593 | |
| 12594 | /* ---------------------------------------------------- */ |
| 12595 | /* --- end of the SSSE3 decoder. --- */ |
| 12596 | /* ---------------------------------------------------- */ |
| 12597 | |
sewardj | b727161 | 2010-07-23 21:23:25 +0000 | [diff] [blame] | 12598 | /* ---------------------------------------------------- */ |
| 12599 | /* --- start of the SSE4 decoder --- */ |
| 12600 | /* ---------------------------------------------------- */ |
| 12601 | |
| 12602 | /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1 |
| 12603 | (Partial implementation only -- only deal with cases where |
| 12604 | the rounding mode is specified directly by the immediate byte.) |
| 12605 | 66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1 |
| 12606 | (Limitations ditto) |
| 12607 | */ |
| 12608 | if (sz == 2 |
| 12609 | && insn[0] == 0x0F && insn[1] == 0x3A |
| 12610 | && (/*insn[2] == 0x0B || */insn[2] == 0x0A)) { |
| 12611 | |
| 12612 | Bool isD = insn[2] == 0x0B; |
| 12613 | IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32); |
| 12614 | IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32); |
| 12615 | Int imm = 0; |
| 12616 | |
| 12617 | modrm = insn[3]; |
| 12618 | |
| 12619 | if (epartIsReg(modrm)) { |
| 12620 | assign( src, |
| 12621 | isD ? getXMMRegLane64F( eregOfRM(modrm), 0 ) |
| 12622 | : getXMMRegLane32F( eregOfRM(modrm), 0 ) ); |
| 12623 | imm = insn[3+1]; |
| 12624 | if (imm & ~3) goto decode_failure; |
| 12625 | delta += 3+1+1; |
| 12626 | DIP( "rounds%c $%d,%s,%s\n", |
| 12627 | isD ? 'd' : 's', |
| 12628 | imm, nameXMMReg( eregOfRM(modrm) ), |
| 12629 | nameXMMReg( gregOfRM(modrm) ) ); |
| 12630 | } else { |
| 12631 | addr = disAMode( &alen, sorb, delta+3, dis_buf ); |
| 12632 | assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) )); |
| 12633 | imm = insn[3+alen]; |
| 12634 | if (imm & ~3) goto decode_failure; |
| 12635 | delta += 3+alen+1; |
| 12636 | DIP( "roundsd $%d,%s,%s\n", |
| 12637 | imm, dis_buf, nameXMMReg( gregOfRM(modrm) ) ); |
| 12638 | } |
| 12639 | |
| 12640 | /* (imm & 3) contains an Intel-encoded rounding mode. Because |
| 12641 | that encoding is the same as the encoding for IRRoundingMode, |
| 12642 | we can use that value directly in the IR as a rounding |
| 12643 | mode. */ |
| 12644 | assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, |
| 12645 | mkU32(imm & 3), mkexpr(src)) ); |
| 12646 | |
| 12647 | if (isD) |
| 12648 | putXMMRegLane64F( gregOfRM(modrm), 0, mkexpr(res) ); |
| 12649 | else |
| 12650 | putXMMRegLane32F( gregOfRM(modrm), 0, mkexpr(res) ); |
| 12651 | |
| 12652 | goto decode_success; |
| 12653 | } |
| 12654 | |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 12655 | /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, |
| 12656 | which we can only decode if we're sure this is an AMD cpu that |
| 12657 | supports LZCNT, since otherwise it's BSR, which behaves |
| 12658 | differently. */ |
| 12659 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD |
| 12660 | && 0 != (archinfo->hwcaps & VEX_HWCAPS_X86_LZCNT)) { |
sewardj | 9a660ea | 2010-07-29 11:34:38 +0000 | [diff] [blame] | 12661 | vassert(sz == 2 || sz == 4); |
| 12662 | /*IRType*/ ty = szToITy(sz); |
| 12663 | IRTemp src = newTemp(ty); |
| 12664 | modrm = insn[3]; |
| 12665 | if (epartIsReg(modrm)) { |
| 12666 | assign(src, getIReg(sz, eregOfRM(modrm))); |
| 12667 | delta += 3+1; |
| 12668 | DIP("lzcnt%c %s, %s\n", nameISize(sz), |
| 12669 | nameIReg(sz, eregOfRM(modrm)), |
| 12670 | nameIReg(sz, gregOfRM(modrm))); |
| 12671 | } else { |
| 12672 | addr = disAMode( &alen, sorb, delta+3, dis_buf ); |
| 12673 | assign(src, loadLE(ty, mkexpr(addr))); |
| 12674 | delta += 3+alen; |
| 12675 | DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf, |
| 12676 | nameIReg(sz, gregOfRM(modrm))); |
| 12677 | } |
| 12678 | |
| 12679 | IRTemp res = gen_LZCNT(ty, src); |
| 12680 | putIReg(sz, gregOfRM(modrm), mkexpr(res)); |
| 12681 | |
| 12682 | // Update flags. This is pretty lame .. perhaps can do better |
| 12683 | // if this turns out to be performance critical. |
| 12684 | // O S A P are cleared. Z is set if RESULT == 0. |
| 12685 | // C is set if SRC is zero. |
| 12686 | IRTemp src32 = newTemp(Ity_I32); |
| 12687 | IRTemp res32 = newTemp(Ity_I32); |
| 12688 | assign(src32, widenUto32(mkexpr(src))); |
| 12689 | assign(res32, widenUto32(mkexpr(res))); |
| 12690 | |
| 12691 | IRTemp oszacp = newTemp(Ity_I32); |
| 12692 | assign( |
| 12693 | oszacp, |
| 12694 | binop(Iop_Or32, |
| 12695 | binop(Iop_Shl32, |
| 12696 | unop(Iop_1Uto32, |
| 12697 | binop(Iop_CmpEQ32, mkexpr(res32), mkU32(0))), |
| 12698 | mkU8(X86G_CC_SHIFT_Z)), |
| 12699 | binop(Iop_Shl32, |
| 12700 | unop(Iop_1Uto32, |
| 12701 | binop(Iop_CmpEQ32, mkexpr(src32), mkU32(0))), |
| 12702 | mkU8(X86G_CC_SHIFT_C)) |
| 12703 | ) |
| 12704 | ); |
| 12705 | |
| 12706 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 12707 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 12708 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 12709 | stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) )); |
| 12710 | |
| 12711 | goto decode_success; |
| 12712 | } |
| 12713 | |
sewardj | b727161 | 2010-07-23 21:23:25 +0000 | [diff] [blame] | 12714 | /* ---------------------------------------------------- */ |
| 12715 | /* --- end of the SSE4 decoder --- */ |
| 12716 | /* ---------------------------------------------------- */ |
| 12717 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 12718 | after_sse_decoders: |
| 12719 | |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 12720 | /* ---------------------------------------------------- */ |
| 12721 | /* --- deal with misc 0x67 pfxs (addr size override) -- */ |
| 12722 | /* ---------------------------------------------------- */ |
| 12723 | |
| 12724 | /* 67 E3 = JCXZ (for JECXZ see below) */ |
| 12725 | if (insn[0] == 0x67 && insn[1] == 0xE3 && sz == 4) { |
| 12726 | delta += 2; |
| 12727 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
| 12728 | delta ++; |
| 12729 | stmt( IRStmt_Exit( |
| 12730 | binop(Iop_CmpEQ16, getIReg(2,R_ECX), mkU16(0)), |
| 12731 | Ijk_Boring, |
| 12732 | IRConst_U32(d32) |
| 12733 | )); |
| 12734 | DIP("jcxz 0x%x\n", d32); |
| 12735 | goto decode_success; |
| 12736 | } |
| 12737 | |
| 12738 | /* ---------------------------------------------------- */ |
| 12739 | /* --- start of the baseline insn decoder -- */ |
| 12740 | /* ---------------------------------------------------- */ |
| 12741 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 12742 | /* Get the primary opcode. */ |
| 12743 | opc = getIByte(delta); delta++; |
| 12744 | |
| 12745 | /* We get here if the current insn isn't SSE, or this CPU doesn't |
| 12746 | support SSE. */ |
| 12747 | |
| 12748 | switch (opc) { |
| 12749 | |
| 12750 | /* ------------------------ Control flow --------------- */ |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 12751 | |
| 12752 | case 0xC2: /* RET imm16 */ |
| 12753 | d32 = getUDisp16(delta); |
| 12754 | delta += 2; |
| 12755 | dis_ret(d32); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12756 | dres.whatNext = Dis_StopHere; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 12757 | DIP("ret %d\n", (Int)d32); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 12758 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 12759 | case 0xC3: /* RET */ |
| 12760 | dis_ret(0); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12761 | dres.whatNext = Dis_StopHere; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 12762 | DIP("ret\n"); |
| 12763 | break; |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 12764 | |
| 12765 | case 0xCF: /* IRET */ |
| 12766 | /* Note, this is an extremely kludgey and limited implementation |
| 12767 | of iret. All it really does is: |
| 12768 | popl %EIP; popl %CS; popl %EFLAGS. |
| 12769 | %CS is set but ignored (as it is in (eg) popw %cs)". */ |
| 12770 | t1 = newTemp(Ity_I32); /* ESP */ |
| 12771 | t2 = newTemp(Ity_I32); /* new EIP */ |
| 12772 | t3 = newTemp(Ity_I32); /* new CS */ |
| 12773 | t4 = newTemp(Ity_I32); /* new EFLAGS */ |
| 12774 | assign(t1, getIReg(4,R_ESP)); |
| 12775 | assign(t2, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t1),mkU32(0) ))); |
| 12776 | assign(t3, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t1),mkU32(4) ))); |
| 12777 | assign(t4, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t1),mkU32(8) ))); |
| 12778 | /* Get stuff off stack */ |
| 12779 | putIReg(4, R_ESP,binop(Iop_Add32, mkexpr(t1), mkU32(12))); |
| 12780 | /* set %CS (which is ignored anyway) */ |
| 12781 | putSReg( R_CS, unop(Iop_32to16, mkexpr(t3)) ); |
| 12782 | /* set %EFLAGS */ |
| 12783 | set_EFLAGS_from_value( t4, False/*!emit_AC_emwarn*/, 0/*unused*/ ); |
| 12784 | /* goto new EIP value */ |
| 12785 | jmp_treg(Ijk_Ret,t2); |
| 12786 | dres.whatNext = Dis_StopHere; |
| 12787 | DIP("iret (very kludgey)\n"); |
| 12788 | break; |
| 12789 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 12790 | case 0xE8: /* CALL J4 */ |
| 12791 | d32 = getUDisp32(delta); delta += 4; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12792 | d32 += (guest_EIP_bbstart+delta); |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 12793 | /* (guest_eip_bbstart+delta) == return-to addr, d32 == call-to addr */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12794 | if (d32 == guest_EIP_bbstart+delta && getIByte(delta) >= 0x58 |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 12795 | && getIByte(delta) <= 0x5F) { |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 12796 | /* Specially treat the position-independent-code idiom |
| 12797 | call X |
| 12798 | X: popl %reg |
| 12799 | as |
| 12800 | movl %eip, %reg. |
| 12801 | since this generates better code, but for no other reason. */ |
| 12802 | Int archReg = getIByte(delta) - 0x58; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 12803 | /* vex_printf("-- fPIC thingy\n"); */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12804 | putIReg(4, archReg, mkU32(guest_EIP_bbstart+delta)); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 12805 | delta++; /* Step over the POP */ |
| 12806 | DIP("call 0x%x ; popl %s\n",d32,nameIReg(4,archReg)); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 12807 | } else { |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 12808 | /* The normal sequence for a call. */ |
| 12809 | t1 = newTemp(Ity_I32); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 12810 | assign(t1, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 12811 | putIReg(4, R_ESP, mkexpr(t1)); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12812 | storeLE( mkexpr(t1), mkU32(guest_EIP_bbstart+delta)); |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 12813 | if (resteerOkFn( callback_opaque, (Addr64)(Addr32)d32 )) { |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 12814 | /* follow into the call target. */ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 12815 | dres.whatNext = Dis_ResteerU; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12816 | dres.continueAt = (Addr64)(Addr32)d32; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 12817 | } else { |
| 12818 | jmp_lit(Ijk_Call,d32); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 12819 | dres.whatNext = Dis_StopHere; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 12820 | } |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 12821 | DIP("call 0x%x\n",d32); |
| 12822 | } |
| 12823 | break; |
| 12824 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 12825 | //-- case 0xC8: /* ENTER */ |
| 12826 | //-- d32 = getUDisp16(eip); eip += 2; |
| 12827 | //-- abyte = getIByte(delta); delta++; |
| 12828 | //-- |
| 12829 | //-- vg_assert(sz == 4); |
| 12830 | //-- vg_assert(abyte == 0); |
| 12831 | //-- |
| 12832 | //-- t1 = newTemp(cb); t2 = newTemp(cb); |
| 12833 | //-- uInstr2(cb, GET, sz, ArchReg, R_EBP, TempReg, t1); |
| 12834 | //-- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2); |
| 12835 | //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); |
| 12836 | //-- uLiteral(cb, sz); |
| 12837 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); |
| 12838 | //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2); |
| 12839 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP); |
| 12840 | //-- if (d32) { |
| 12841 | //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 12842 | //-- uLiteral(cb, d32); |
| 12843 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 12844 | //-- } |
| 12845 | //-- DIP("enter 0x%x, 0x%x", d32, abyte); |
| 12846 | //-- break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 12847 | |
| 12848 | case 0xC9: /* LEAVE */ |
| 12849 | vassert(sz == 4); |
| 12850 | t1 = newTemp(Ity_I32); t2 = newTemp(Ity_I32); |
| 12851 | assign(t1, getIReg(4,R_EBP)); |
| 12852 | /* First PUT ESP looks redundant, but need it because ESP must |
| 12853 | always be up-to-date for Memcheck to work... */ |
| 12854 | putIReg(4, R_ESP, mkexpr(t1)); |
| 12855 | assign(t2, loadLE(Ity_I32,mkexpr(t1))); |
| 12856 | putIReg(4, R_EBP, mkexpr(t2)); |
| 12857 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t1), mkU32(4)) ); |
| 12858 | DIP("leave\n"); |
| 12859 | break; |
| 12860 | |
sewardj | 8edc36b | 2007-11-23 02:46:29 +0000 | [diff] [blame] | 12861 | /* ---------------- Misc weird-ass insns --------------- */ |
| 12862 | |
| 12863 | case 0x27: /* DAA */ |
| 12864 | case 0x2F: /* DAS */ |
| 12865 | case 0x37: /* AAA */ |
| 12866 | case 0x3F: /* AAS */ |
| 12867 | /* An ugly implementation for some ugly instructions. Oh |
| 12868 | well. */ |
| 12869 | if (sz != 4) goto decode_failure; |
| 12870 | t1 = newTemp(Ity_I32); |
| 12871 | t2 = newTemp(Ity_I32); |
| 12872 | /* Make up a 32-bit value (t1), with the old value of AX in the |
| 12873 | bottom 16 bits, and the old OSZACP bitmask in the upper 16 |
| 12874 | bits. */ |
| 12875 | assign(t1, |
| 12876 | binop(Iop_16HLto32, |
| 12877 | unop(Iop_32to16, |
| 12878 | mk_x86g_calculate_eflags_all()), |
| 12879 | getIReg(2, R_EAX) |
| 12880 | )); |
| 12881 | /* Call the helper fn, to get a new AX and OSZACP value, and |
| 12882 | poke both back into the guest state. Also pass the helper |
| 12883 | the actual opcode so it knows which of the 4 instructions it |
| 12884 | is doing the computation for. */ |
| 12885 | vassert(opc == 0x27 || opc == 0x2F || opc == 0x37 || opc == 0x3F); |
| 12886 | assign(t2, |
| 12887 | mkIRExprCCall( |
| 12888 | Ity_I32, 0/*regparm*/, "x86g_calculate_daa_das_aaa_aas", |
| 12889 | &x86g_calculate_daa_das_aaa_aas, |
| 12890 | mkIRExprVec_2( mkexpr(t1), mkU32( opc & 0xFF) ) |
| 12891 | )); |
| 12892 | putIReg(2, R_EAX, unop(Iop_32to16, mkexpr(t2) )); |
| 12893 | |
| 12894 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 12895 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 12896 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
| 12897 | binop(Iop_And32, |
| 12898 | binop(Iop_Shr32, mkexpr(t2), mkU8(16)), |
| 12899 | mkU32( X86G_CC_MASK_C | X86G_CC_MASK_P |
| 12900 | | X86G_CC_MASK_A | X86G_CC_MASK_Z |
| 12901 | | X86G_CC_MASK_S| X86G_CC_MASK_O ) |
| 12902 | ) |
| 12903 | ) |
| 12904 | ); |
| 12905 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 12906 | elimination of previous stores to this field work better. */ |
| 12907 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 12908 | switch (opc) { |
| 12909 | case 0x27: DIP("daa\n"); break; |
| 12910 | case 0x2F: DIP("das\n"); break; |
| 12911 | case 0x37: DIP("aaa\n"); break; |
| 12912 | case 0x3F: DIP("aas\n"); break; |
| 12913 | default: vassert(0); |
| 12914 | } |
| 12915 | break; |
| 12916 | |
sewardj | 321bbbf | 2011-01-17 12:32:25 +0000 | [diff] [blame] | 12917 | case 0xD4: /* AAM */ |
| 12918 | case 0xD5: /* AAD */ |
| 12919 | d32 = getIByte(delta); delta++; |
| 12920 | if (sz != 4 || d32 != 10) goto decode_failure; |
| 12921 | t1 = newTemp(Ity_I32); |
| 12922 | t2 = newTemp(Ity_I32); |
| 12923 | /* Make up a 32-bit value (t1), with the old value of AX in the |
| 12924 | bottom 16 bits, and the old OSZACP bitmask in the upper 16 |
| 12925 | bits. */ |
| 12926 | assign(t1, |
| 12927 | binop(Iop_16HLto32, |
| 12928 | unop(Iop_32to16, |
| 12929 | mk_x86g_calculate_eflags_all()), |
| 12930 | getIReg(2, R_EAX) |
| 12931 | )); |
| 12932 | /* Call the helper fn, to get a new AX and OSZACP value, and |
| 12933 | poke both back into the guest state. Also pass the helper |
| 12934 | the actual opcode so it knows which of the 2 instructions it |
| 12935 | is doing the computation for. */ |
| 12936 | assign(t2, |
| 12937 | mkIRExprCCall( |
| 12938 | Ity_I32, 0/*regparm*/, "x86g_calculate_aad_aam", |
| 12939 | &x86g_calculate_aad_aam, |
| 12940 | mkIRExprVec_2( mkexpr(t1), mkU32( opc & 0xFF) ) |
| 12941 | )); |
| 12942 | putIReg(2, R_EAX, unop(Iop_32to16, mkexpr(t2) )); |
| 12943 | |
| 12944 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 12945 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 12946 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
| 12947 | binop(Iop_And32, |
| 12948 | binop(Iop_Shr32, mkexpr(t2), mkU8(16)), |
| 12949 | mkU32( X86G_CC_MASK_C | X86G_CC_MASK_P |
| 12950 | | X86G_CC_MASK_A | X86G_CC_MASK_Z |
| 12951 | | X86G_CC_MASK_S| X86G_CC_MASK_O ) |
| 12952 | ) |
| 12953 | ) |
| 12954 | ); |
| 12955 | /* Set NDEP even though it isn't used. This makes |
| 12956 | redundant-PUT elimination of previous stores to this field |
| 12957 | work better. */ |
| 12958 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 12959 | |
| 12960 | DIP(opc == 0xD4 ? "aam\n" : "aad\n"); |
| 12961 | break; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 12962 | |
| 12963 | /* ------------------------ CWD/CDQ -------------------- */ |
| 12964 | |
| 12965 | case 0x98: /* CBW */ |
| 12966 | if (sz == 4) { |
| 12967 | putIReg(4, R_EAX, unop(Iop_16Sto32, getIReg(2, R_EAX))); |
| 12968 | DIP("cwde\n"); |
| 12969 | } else { |
sewardj | 4734104 | 2004-09-19 11:55:46 +0000 | [diff] [blame] | 12970 | vassert(sz == 2); |
| 12971 | putIReg(2, R_EAX, unop(Iop_8Sto16, getIReg(1, R_EAX))); |
| 12972 | DIP("cbw\n"); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 12973 | } |
| 12974 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 12975 | |
| 12976 | case 0x99: /* CWD/CDQ */ |
| 12977 | ty = szToITy(sz); |
| 12978 | putIReg(sz, R_EDX, |
| 12979 | binop(mkSizedOp(ty,Iop_Sar8), |
| 12980 | getIReg(sz, R_EAX), |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 12981 | mkU8(sz == 2 ? 15 : 31)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 12982 | DIP(sz == 2 ? "cwdq\n" : "cdqq\n"); |
| 12983 | break; |
| 12984 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 12985 | /* ------------------------ FPU ops -------------------- */ |
| 12986 | |
| 12987 | case 0x9E: /* SAHF */ |
| 12988 | codegen_SAHF(); |
| 12989 | DIP("sahf\n"); |
| 12990 | break; |
| 12991 | |
sewardj | 8dfdc8a | 2005-10-03 11:39:02 +0000 | [diff] [blame] | 12992 | case 0x9F: /* LAHF */ |
| 12993 | codegen_LAHF(); |
| 12994 | DIP("lahf\n"); |
| 12995 | break; |
| 12996 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 12997 | case 0x9B: /* FWAIT */ |
| 12998 | /* ignore? */ |
| 12999 | DIP("fwait\n"); |
| 13000 | break; |
| 13001 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 13002 | case 0xD8: |
| 13003 | case 0xD9: |
| 13004 | case 0xDA: |
| 13005 | case 0xDB: |
| 13006 | case 0xDC: |
| 13007 | case 0xDD: |
| 13008 | case 0xDE: |
| 13009 | case 0xDF: { |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 13010 | Int delta0 = delta; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 13011 | Bool decode_OK = False; |
| 13012 | delta = dis_FPU ( &decode_OK, sorb, delta ); |
| 13013 | if (!decode_OK) { |
| 13014 | delta = delta0; |
| 13015 | goto decode_failure; |
| 13016 | } |
| 13017 | break; |
| 13018 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13019 | |
| 13020 | /* ------------------------ INC & DEC ------------------ */ |
| 13021 | |
| 13022 | case 0x40: /* INC eAX */ |
| 13023 | case 0x41: /* INC eCX */ |
| 13024 | case 0x42: /* INC eDX */ |
| 13025 | case 0x43: /* INC eBX */ |
| 13026 | case 0x44: /* INC eSP */ |
| 13027 | case 0x45: /* INC eBP */ |
| 13028 | case 0x46: /* INC eSI */ |
| 13029 | case 0x47: /* INC eDI */ |
| 13030 | vassert(sz == 2 || sz == 4); |
| 13031 | ty = szToITy(sz); |
| 13032 | t1 = newTemp(ty); |
| 13033 | assign( t1, binop(mkSizedOp(ty,Iop_Add8), |
| 13034 | getIReg(sz, (UInt)(opc - 0x40)), |
| 13035 | mkU(ty,1)) ); |
| 13036 | setFlags_INC_DEC( True, t1, ty ); |
| 13037 | putIReg(sz, (UInt)(opc - 0x40), mkexpr(t1)); |
| 13038 | DIP("inc%c %s\n", nameISize(sz), nameIReg(sz,opc-0x40)); |
| 13039 | break; |
| 13040 | |
| 13041 | case 0x48: /* DEC eAX */ |
| 13042 | case 0x49: /* DEC eCX */ |
| 13043 | case 0x4A: /* DEC eDX */ |
| 13044 | case 0x4B: /* DEC eBX */ |
| 13045 | case 0x4C: /* DEC eSP */ |
| 13046 | case 0x4D: /* DEC eBP */ |
| 13047 | case 0x4E: /* DEC eSI */ |
| 13048 | case 0x4F: /* DEC eDI */ |
| 13049 | vassert(sz == 2 || sz == 4); |
| 13050 | ty = szToITy(sz); |
| 13051 | t1 = newTemp(ty); |
| 13052 | assign( t1, binop(mkSizedOp(ty,Iop_Sub8), |
| 13053 | getIReg(sz, (UInt)(opc - 0x48)), |
| 13054 | mkU(ty,1)) ); |
| 13055 | setFlags_INC_DEC( False, t1, ty ); |
| 13056 | putIReg(sz, (UInt)(opc - 0x48), mkexpr(t1)); |
| 13057 | DIP("dec%c %s\n", nameISize(sz), nameIReg(sz,opc-0x48)); |
| 13058 | break; |
| 13059 | |
| 13060 | /* ------------------------ INT ------------------------ */ |
| 13061 | |
sewardj | 322bfa0 | 2007-02-28 23:31:42 +0000 | [diff] [blame] | 13062 | case 0xCC: /* INT 3 */ |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 13063 | jmp_lit(Ijk_SigTRAP,((Addr32)guest_EIP_bbstart)+delta); |
sewardj | 322bfa0 | 2007-02-28 23:31:42 +0000 | [diff] [blame] | 13064 | dres.whatNext = Dis_StopHere; |
| 13065 | DIP("int $0x3\n"); |
| 13066 | break; |
| 13067 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13068 | case 0xCD: /* INT imm8 */ |
| 13069 | d32 = getIByte(delta); delta++; |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 13070 | |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13071 | /* For any of the cases where we emit a jump (that is, for all |
| 13072 | currently handled cases), it's important that all ArchRegs |
| 13073 | carry their up-to-date value at this point. So we declare an |
| 13074 | end-of-block here, which forces any TempRegs caching ArchRegs |
| 13075 | to be flushed. */ |
| 13076 | |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 13077 | /* Handle int $0x40 .. $0x43 by synthesising a segfault and a |
| 13078 | restart of this instruction (hence the "-2" two lines below, |
| 13079 | to get the restart EIP to be this instruction. This is |
| 13080 | probably Linux-specific and it would be more correct to only |
| 13081 | do this if the VexAbiInfo says that is what we should do. */ |
| 13082 | if (d32 >= 0x40 && d32 <= 0x43) { |
| 13083 | jmp_lit(Ijk_SigSEGV,((Addr32)guest_EIP_bbstart)+delta-2); |
| 13084 | dres.whatNext = Dis_StopHere; |
| 13085 | DIP("int $0x%x\n", (Int)d32); |
| 13086 | break; |
| 13087 | } |
| 13088 | |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13089 | /* Handle int $0x80 (linux syscalls), int $0x81 and $0x82 |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 13090 | (darwin syscalls). As part of this, note where we are, so we |
| 13091 | can back up the guest to this point if the syscall needs to |
| 13092 | be restarted. */ |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13093 | if (d32 == 0x80) { |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 13094 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
| 13095 | mkU32(guest_EIP_curr_instr) ) ); |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13096 | jmp_lit(Ijk_Sys_int128,((Addr32)guest_EIP_bbstart)+delta); |
| 13097 | dres.whatNext = Dis_StopHere; |
| 13098 | DIP("int $0x80\n"); |
| 13099 | break; |
| 13100 | } |
| 13101 | if (d32 == 0x81) { |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 13102 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
| 13103 | mkU32(guest_EIP_curr_instr) ) ); |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13104 | jmp_lit(Ijk_Sys_int129,((Addr32)guest_EIP_bbstart)+delta); |
| 13105 | dres.whatNext = Dis_StopHere; |
| 13106 | DIP("int $0x81\n"); |
| 13107 | break; |
| 13108 | } |
| 13109 | if (d32 == 0x82) { |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 13110 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
| 13111 | mkU32(guest_EIP_curr_instr) ) ); |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13112 | jmp_lit(Ijk_Sys_int130,((Addr32)guest_EIP_bbstart)+delta); |
| 13113 | dres.whatNext = Dis_StopHere; |
| 13114 | DIP("int $0x82\n"); |
| 13115 | break; |
| 13116 | } |
| 13117 | |
| 13118 | /* none of the above */ |
| 13119 | goto decode_failure; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13120 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13121 | /* ------------------------ Jcond, byte offset --------- */ |
| 13122 | |
| 13123 | case 0xEB: /* Jb (jump, byte offset) */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13124 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13125 | delta++; |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 13126 | if (resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13127 | dres.whatNext = Dis_ResteerU; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13128 | dres.continueAt = (Addr64)(Addr32)d32; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13129 | } else { |
| 13130 | jmp_lit(Ijk_Boring,d32); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13131 | dres.whatNext = Dis_StopHere; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13132 | } |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13133 | DIP("jmp-8 0x%x\n", d32); |
| 13134 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13135 | |
| 13136 | case 0xE9: /* Jv (jump, 16/32 offset) */ |
| 13137 | vassert(sz == 4); /* JRS added 2004 July 11 */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13138 | d32 = (((Addr32)guest_EIP_bbstart)+delta+sz) + getSDisp(sz,delta); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13139 | delta += sz; |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 13140 | if (resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13141 | dres.whatNext = Dis_ResteerU; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13142 | dres.continueAt = (Addr64)(Addr32)d32; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13143 | } else { |
| 13144 | jmp_lit(Ijk_Boring,d32); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13145 | dres.whatNext = Dis_StopHere; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13146 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13147 | DIP("jmp 0x%x\n", d32); |
| 13148 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13149 | |
| 13150 | case 0x70: |
| 13151 | case 0x71: |
| 13152 | case 0x72: /* JBb/JNAEb (jump below) */ |
| 13153 | case 0x73: /* JNBb/JAEb (jump not below) */ |
| 13154 | case 0x74: /* JZb/JEb (jump zero) */ |
| 13155 | case 0x75: /* JNZb/JNEb (jump not zero) */ |
| 13156 | case 0x76: /* JBEb/JNAb (jump below or equal) */ |
| 13157 | case 0x77: /* JNBEb/JAb (jump not below or equal) */ |
| 13158 | case 0x78: /* JSb (jump negative) */ |
| 13159 | case 0x79: /* JSb (jump not negative) */ |
| 13160 | case 0x7A: /* JP (jump parity even) */ |
| 13161 | case 0x7B: /* JNP/JPO (jump parity odd) */ |
| 13162 | case 0x7C: /* JLb/JNGEb (jump less) */ |
| 13163 | case 0x7D: /* JGEb/JNLb (jump greater or equal) */ |
| 13164 | case 0x7E: /* JLEb/JNGb (jump less or equal) */ |
| 13165 | case 0x7F: /* JGb/JNLEb (jump greater) */ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13166 | { Int jmpDelta; |
| 13167 | HChar* comment = ""; |
| 13168 | jmpDelta = (Int)getSDisp8(delta); |
| 13169 | vassert(-128 <= jmpDelta && jmpDelta < 128); |
| 13170 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + jmpDelta; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13171 | delta++; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13172 | if (resteerCisOk |
| 13173 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 13174 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13175 | && jmpDelta < 0 |
| 13176 | && resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { |
| 13177 | /* Speculation: assume this backward branch is taken. So we |
| 13178 | need to emit a side-exit to the insn following this one, |
| 13179 | on the negation of the condition, and continue at the |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 13180 | branch target address (d32). If we wind up back at the |
| 13181 | first instruction of the trace, just stop; it's better to |
| 13182 | let the IR loop unroller handle that case. */ |
sewardj | dbf550c | 2005-01-24 11:54:11 +0000 | [diff] [blame] | 13183 | stmt( IRStmt_Exit( |
| 13184 | mk_x86g_calculate_condition((X86Condcode)(1 ^ (opc - 0x70))), |
| 13185 | Ijk_Boring, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13186 | IRConst_U32(guest_EIP_bbstart+delta) ) ); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13187 | dres.whatNext = Dis_ResteerC; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13188 | dres.continueAt = (Addr64)(Addr32)d32; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13189 | comment = "(assumed taken)"; |
| 13190 | } |
| 13191 | else |
| 13192 | if (resteerCisOk |
| 13193 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 13194 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13195 | && jmpDelta >= 0 |
| 13196 | && resteerOkFn( callback_opaque, |
| 13197 | (Addr64)(Addr32)(guest_EIP_bbstart+delta)) ) { |
| 13198 | /* Speculation: assume this forward branch is not taken. So |
| 13199 | we need to emit a side-exit to d32 (the dest) and continue |
| 13200 | disassembling at the insn immediately following this |
| 13201 | one. */ |
| 13202 | stmt( IRStmt_Exit( |
| 13203 | mk_x86g_calculate_condition((X86Condcode)(opc - 0x70)), |
| 13204 | Ijk_Boring, |
| 13205 | IRConst_U32(d32) ) ); |
| 13206 | dres.whatNext = Dis_ResteerC; |
| 13207 | dres.continueAt = (Addr64)(Addr32)(guest_EIP_bbstart+delta); |
| 13208 | comment = "(assumed not taken)"; |
| 13209 | } |
| 13210 | else { |
| 13211 | /* Conservative default translation - end the block at this |
| 13212 | point. */ |
| 13213 | jcc_01( (X86Condcode)(opc - 0x70), |
| 13214 | (Addr32)(guest_EIP_bbstart+delta), d32); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13215 | dres.whatNext = Dis_StopHere; |
sewardj | dbf550c | 2005-01-24 11:54:11 +0000 | [diff] [blame] | 13216 | } |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13217 | DIP("j%s-8 0x%x %s\n", name_X86Condcode(opc - 0x70), d32, comment); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13218 | break; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13219 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13220 | |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13221 | case 0xE3: /* JECXZ (for JCXZ see above) */ |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 13222 | if (sz != 4) goto decode_failure; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13223 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13224 | delta ++; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 13225 | stmt( IRStmt_Exit( |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13226 | binop(Iop_CmpEQ32, getIReg(4,R_ECX), mkU32(0)), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 13227 | Ijk_Boring, |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13228 | IRConst_U32(d32) |
| 13229 | )); |
| 13230 | DIP("jecxz 0x%x\n", d32); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 13231 | break; |
| 13232 | |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 13233 | case 0xE0: /* LOOPNE disp8: decrement count, jump if count != 0 && ZF==0 */ |
| 13234 | case 0xE1: /* LOOPE disp8: decrement count, jump if count != 0 && ZF==1 */ |
| 13235 | case 0xE2: /* LOOP disp8: decrement count, jump if count != 0 */ |
| 13236 | { /* Again, the docs say this uses ECX/CX as a count depending on |
| 13237 | the address size override, not the operand one. Since we |
| 13238 | don't handle address size overrides, I guess that means |
| 13239 | ECX. */ |
| 13240 | IRExpr* zbit = NULL; |
| 13241 | IRExpr* count = NULL; |
| 13242 | IRExpr* cond = NULL; |
| 13243 | HChar* xtra = NULL; |
| 13244 | |
| 13245 | if (sz != 4) goto decode_failure; |
| 13246 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
| 13247 | delta++; |
| 13248 | putIReg(4, R_ECX, binop(Iop_Sub32, getIReg(4,R_ECX), mkU32(1))); |
| 13249 | |
| 13250 | count = getIReg(4,R_ECX); |
| 13251 | cond = binop(Iop_CmpNE32, count, mkU32(0)); |
| 13252 | switch (opc) { |
| 13253 | case 0xE2: |
| 13254 | xtra = ""; |
| 13255 | break; |
| 13256 | case 0xE1: |
| 13257 | xtra = "e"; |
| 13258 | zbit = mk_x86g_calculate_condition( X86CondZ ); |
| 13259 | cond = mkAnd1(cond, zbit); |
| 13260 | break; |
| 13261 | case 0xE0: |
| 13262 | xtra = "ne"; |
| 13263 | zbit = mk_x86g_calculate_condition( X86CondNZ ); |
| 13264 | cond = mkAnd1(cond, zbit); |
| 13265 | break; |
| 13266 | default: |
| 13267 | vassert(0); |
| 13268 | } |
| 13269 | stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U32(d32)) ); |
| 13270 | |
| 13271 | DIP("loop%s 0x%x\n", xtra, d32); |
| 13272 | break; |
| 13273 | } |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13274 | |
| 13275 | /* ------------------------ IMUL ----------------------- */ |
| 13276 | |
| 13277 | case 0x69: /* IMUL Iv, Ev, Gv */ |
| 13278 | delta = dis_imul_I_E_G ( sorb, sz, delta, sz ); |
| 13279 | break; |
| 13280 | case 0x6B: /* IMUL Ib, Ev, Gv */ |
| 13281 | delta = dis_imul_I_E_G ( sorb, sz, delta, 1 ); |
| 13282 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13283 | |
| 13284 | /* ------------------------ MOV ------------------------ */ |
| 13285 | |
| 13286 | case 0x88: /* MOV Gb,Eb */ |
| 13287 | delta = dis_mov_G_E(sorb, 1, delta); |
| 13288 | break; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 13289 | |
| 13290 | case 0x89: /* MOV Gv,Ev */ |
| 13291 | delta = dis_mov_G_E(sorb, sz, delta); |
| 13292 | break; |
| 13293 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13294 | case 0x8A: /* MOV Eb,Gb */ |
| 13295 | delta = dis_mov_E_G(sorb, 1, delta); |
| 13296 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13297 | |
| 13298 | case 0x8B: /* MOV Ev,Gv */ |
| 13299 | delta = dis_mov_E_G(sorb, sz, delta); |
| 13300 | break; |
| 13301 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13302 | case 0x8D: /* LEA M,Gv */ |
sewardj | e9460bd | 2005-01-28 13:45:42 +0000 | [diff] [blame] | 13303 | if (sz != 4) |
| 13304 | goto decode_failure; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13305 | modrm = getIByte(delta); |
| 13306 | if (epartIsReg(modrm)) |
sewardj | e9460bd | 2005-01-28 13:45:42 +0000 | [diff] [blame] | 13307 | goto decode_failure; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13308 | /* NOTE! this is the one place where a segment override prefix |
| 13309 | has no effect on the address calculation. Therefore we pass |
| 13310 | zero instead of sorb here. */ |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13311 | addr = disAMode ( &alen, /*sorb*/ 0, delta, dis_buf ); |
| 13312 | delta += alen; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13313 | putIReg(sz, gregOfRM(modrm), mkexpr(addr)); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13314 | DIP("lea%c %s, %s\n", nameISize(sz), dis_buf, |
| 13315 | nameIReg(sz,gregOfRM(modrm))); |
| 13316 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13317 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 13318 | case 0x8C: /* MOV Sw,Ew -- MOV from a SEGMENT REGISTER */ |
| 13319 | delta = dis_mov_Sw_Ew(sorb, sz, delta); |
| 13320 | break; |
| 13321 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 13322 | case 0x8E: /* MOV Ew,Sw -- MOV to a SEGMENT REGISTER */ |
| 13323 | delta = dis_mov_Ew_Sw(sorb, delta); |
| 13324 | break; |
| 13325 | |
sewardj | 4385281 | 2004-10-16 23:10:08 +0000 | [diff] [blame] | 13326 | case 0xA0: /* MOV Ob,AL */ |
| 13327 | sz = 1; |
| 13328 | /* Fall through ... */ |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 13329 | case 0xA1: /* MOV Ov,eAX */ |
| 13330 | d32 = getUDisp32(delta); delta += 4; |
| 13331 | ty = szToITy(sz); |
| 13332 | addr = newTemp(Ity_I32); |
| 13333 | assign( addr, handleSegOverride(sorb, mkU32(d32)) ); |
| 13334 | putIReg(sz, R_EAX, loadLE(ty, mkexpr(addr))); |
| 13335 | DIP("mov%c %s0x%x, %s\n", nameISize(sz), sorbTxt(sorb), |
| 13336 | d32, nameIReg(sz,R_EAX)); |
| 13337 | break; |
| 13338 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13339 | case 0xA2: /* MOV Ob,AL */ |
| 13340 | sz = 1; |
| 13341 | /* Fall through ... */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 13342 | case 0xA3: /* MOV eAX,Ov */ |
| 13343 | d32 = getUDisp32(delta); delta += 4; |
| 13344 | ty = szToITy(sz); |
| 13345 | addr = newTemp(Ity_I32); |
| 13346 | assign( addr, handleSegOverride(sorb, mkU32(d32)) ); |
| 13347 | storeLE( mkexpr(addr), getIReg(sz,R_EAX) ); |
| 13348 | DIP("mov%c %s, %s0x%x\n", nameISize(sz), nameIReg(sz,R_EAX), |
| 13349 | sorbTxt(sorb), d32); |
| 13350 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13351 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13352 | case 0xB0: /* MOV imm,AL */ |
| 13353 | case 0xB1: /* MOV imm,CL */ |
| 13354 | case 0xB2: /* MOV imm,DL */ |
| 13355 | case 0xB3: /* MOV imm,BL */ |
| 13356 | case 0xB4: /* MOV imm,AH */ |
| 13357 | case 0xB5: /* MOV imm,CH */ |
| 13358 | case 0xB6: /* MOV imm,DH */ |
| 13359 | case 0xB7: /* MOV imm,BH */ |
| 13360 | d32 = getIByte(delta); delta += 1; |
| 13361 | putIReg(1, opc-0xB0, mkU8(d32)); |
| 13362 | DIP("movb $0x%x,%s\n", d32, nameIReg(1,opc-0xB0)); |
| 13363 | break; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 13364 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13365 | case 0xB8: /* MOV imm,eAX */ |
| 13366 | case 0xB9: /* MOV imm,eCX */ |
| 13367 | case 0xBA: /* MOV imm,eDX */ |
| 13368 | case 0xBB: /* MOV imm,eBX */ |
| 13369 | case 0xBC: /* MOV imm,eSP */ |
| 13370 | case 0xBD: /* MOV imm,eBP */ |
| 13371 | case 0xBE: /* MOV imm,eSI */ |
| 13372 | case 0xBF: /* MOV imm,eDI */ |
| 13373 | d32 = getUDisp(sz,delta); delta += sz; |
| 13374 | putIReg(sz, opc-0xB8, mkU(szToITy(sz), d32)); |
| 13375 | DIP("mov%c $0x%x,%s\n", nameISize(sz), d32, nameIReg(sz,opc-0xB8)); |
| 13376 | break; |
| 13377 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13378 | case 0xC6: /* MOV Ib,Eb */ |
| 13379 | sz = 1; |
| 13380 | goto do_Mov_I_E; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13381 | case 0xC7: /* MOV Iv,Ev */ |
| 13382 | goto do_Mov_I_E; |
| 13383 | |
| 13384 | do_Mov_I_E: |
| 13385 | modrm = getIByte(delta); |
| 13386 | if (epartIsReg(modrm)) { |
| 13387 | delta++; /* mod/rm byte */ |
| 13388 | d32 = getUDisp(sz,delta); delta += sz; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 13389 | putIReg(sz, eregOfRM(modrm), mkU(szToITy(sz), d32)); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13390 | DIP("mov%c $0x%x, %s\n", nameISize(sz), d32, |
| 13391 | nameIReg(sz,eregOfRM(modrm))); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13392 | } else { |
| 13393 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 13394 | delta += alen; |
| 13395 | d32 = getUDisp(sz,delta); delta += sz; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 13396 | storeLE(mkexpr(addr), mkU(szToITy(sz), d32)); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13397 | DIP("mov%c $0x%x, %s\n", nameISize(sz), d32, dis_buf); |
| 13398 | } |
| 13399 | break; |
| 13400 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13401 | /* ------------------------ opl imm, A ----------------- */ |
| 13402 | |
| 13403 | case 0x04: /* ADD Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13404 | delta = dis_op_imm_A( 1, False, Iop_Add8, True, delta, "add" ); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13405 | break; |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13406 | case 0x05: /* ADD Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13407 | delta = dis_op_imm_A( sz, False, Iop_Add8, True, delta, "add" ); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13408 | break; |
| 13409 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13410 | case 0x0C: /* OR Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13411 | delta = dis_op_imm_A( 1, False, Iop_Or8, True, delta, "or" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13412 | break; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13413 | case 0x0D: /* OR Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13414 | delta = dis_op_imm_A( sz, False, Iop_Or8, True, delta, "or" ); |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13415 | break; |
| 13416 | |
sewardj | eca2036 | 2005-08-24 09:22:39 +0000 | [diff] [blame] | 13417 | case 0x14: /* ADC Ib, AL */ |
| 13418 | delta = dis_op_imm_A( 1, True, Iop_Add8, True, delta, "adc" ); |
| 13419 | break; |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13420 | case 0x15: /* ADC Iv, eAX */ |
sewardj | eca2036 | 2005-08-24 09:22:39 +0000 | [diff] [blame] | 13421 | delta = dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" ); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13422 | break; |
| 13423 | |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 13424 | case 0x1C: /* SBB Ib, AL */ |
| 13425 | delta = dis_op_imm_A( 1, True, Iop_Sub8, True, delta, "sbb" ); |
| 13426 | break; |
| 13427 | case 0x1D: /* SBB Iv, eAX */ |
| 13428 | delta = dis_op_imm_A( sz, True, Iop_Sub8, True, delta, "sbb" ); |
| 13429 | break; |
| 13430 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13431 | case 0x24: /* AND Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13432 | delta = dis_op_imm_A( 1, False, Iop_And8, True, delta, "and" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13433 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13434 | case 0x25: /* AND Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13435 | delta = dis_op_imm_A( sz, False, Iop_And8, True, delta, "and" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13436 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13437 | |
| 13438 | case 0x2C: /* SUB Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13439 | delta = dis_op_imm_A( 1, False, Iop_Sub8, True, delta, "sub" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13440 | break; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 13441 | case 0x2D: /* SUB Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13442 | delta = dis_op_imm_A( sz, False, Iop_Sub8, True, delta, "sub" ); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 13443 | break; |
| 13444 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13445 | case 0x34: /* XOR Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13446 | delta = dis_op_imm_A( 1, False, Iop_Xor8, True, delta, "xor" ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13447 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13448 | case 0x35: /* XOR Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13449 | delta = dis_op_imm_A( sz, False, Iop_Xor8, True, delta, "xor" ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13450 | break; |
| 13451 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13452 | case 0x3C: /* CMP Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13453 | delta = dis_op_imm_A( 1, False, Iop_Sub8, False, delta, "cmp" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13454 | break; |
| 13455 | case 0x3D: /* CMP Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13456 | delta = dis_op_imm_A( sz, False, Iop_Sub8, False, delta, "cmp" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13457 | break; |
| 13458 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13459 | case 0xA8: /* TEST Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13460 | delta = dis_op_imm_A( 1, False, Iop_And8, False, delta, "test" ); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13461 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13462 | case 0xA9: /* TEST Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13463 | delta = dis_op_imm_A( sz, False, Iop_And8, False, delta, "test" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13464 | break; |
| 13465 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13466 | /* ------------------------ opl Ev, Gv ----------------- */ |
| 13467 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 13468 | case 0x02: /* ADD Eb,Gb */ |
| 13469 | delta = dis_op2_E_G ( sorb, False, Iop_Add8, True, 1, delta, "add" ); |
| 13470 | break; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13471 | case 0x03: /* ADD Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13472 | delta = dis_op2_E_G ( sorb, False, Iop_Add8, True, sz, delta, "add" ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13473 | break; |
| 13474 | |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 13475 | case 0x0A: /* OR Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13476 | delta = dis_op2_E_G ( sorb, False, Iop_Or8, True, 1, delta, "or" ); |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 13477 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13478 | case 0x0B: /* OR Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13479 | delta = dis_op2_E_G ( sorb, False, Iop_Or8, True, sz, delta, "or" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13480 | break; |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 13481 | |
| 13482 | case 0x12: /* ADC Eb,Gb */ |
| 13483 | delta = dis_op2_E_G ( sorb, True, Iop_Add8, True, 1, delta, "adc" ); |
| 13484 | break; |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 13485 | case 0x13: /* ADC Ev,Gv */ |
| 13486 | delta = dis_op2_E_G ( sorb, True, Iop_Add8, True, sz, delta, "adc" ); |
| 13487 | break; |
| 13488 | |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 13489 | case 0x1A: /* SBB Eb,Gb */ |
| 13490 | delta = dis_op2_E_G ( sorb, True, Iop_Sub8, True, 1, delta, "sbb" ); |
| 13491 | break; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13492 | case 0x1B: /* SBB Ev,Gv */ |
| 13493 | delta = dis_op2_E_G ( sorb, True, Iop_Sub8, True, sz, delta, "sbb" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13494 | break; |
| 13495 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13496 | case 0x22: /* AND Eb,Gb */ |
| 13497 | delta = dis_op2_E_G ( sorb, False, Iop_And8, True, 1, delta, "and" ); |
| 13498 | break; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13499 | case 0x23: /* AND Ev,Gv */ |
| 13500 | delta = dis_op2_E_G ( sorb, False, Iop_And8, True, sz, delta, "and" ); |
| 13501 | break; |
| 13502 | |
| 13503 | case 0x2A: /* SUB Eb,Gb */ |
| 13504 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, True, 1, delta, "sub" ); |
| 13505 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13506 | case 0x2B: /* SUB Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13507 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, True, sz, delta, "sub" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13508 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13509 | |
| 13510 | case 0x32: /* XOR Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13511 | delta = dis_op2_E_G ( sorb, False, Iop_Xor8, True, 1, delta, "xor" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13512 | break; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13513 | case 0x33: /* XOR Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13514 | delta = dis_op2_E_G ( sorb, False, Iop_Xor8, True, sz, delta, "xor" ); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13515 | break; |
| 13516 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13517 | case 0x3A: /* CMP Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13518 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, False, 1, delta, "cmp" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13519 | break; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13520 | case 0x3B: /* CMP Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13521 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, False, sz, delta, "cmp" ); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13522 | break; |
| 13523 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13524 | case 0x84: /* TEST Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13525 | delta = dis_op2_E_G ( sorb, False, Iop_And8, False, 1, delta, "test" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13526 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13527 | case 0x85: /* TEST Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13528 | delta = dis_op2_E_G ( sorb, False, Iop_And8, False, sz, delta, "test" ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13529 | break; |
| 13530 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13531 | /* ------------------------ opl Gv, Ev ----------------- */ |
| 13532 | |
| 13533 | case 0x00: /* ADD Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13534 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13535 | Iop_Add8, True, 1, delta, "add" ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13536 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13537 | case 0x01: /* ADD Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13538 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13539 | Iop_Add8, True, sz, delta, "add" ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13540 | break; |
| 13541 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13542 | case 0x08: /* OR Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13543 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13544 | Iop_Or8, True, 1, delta, "or" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13545 | break; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13546 | case 0x09: /* OR Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13547 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13548 | Iop_Or8, True, sz, delta, "or" ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13549 | break; |
| 13550 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13551 | case 0x10: /* ADC Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13552 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13553 | Iop_Add8, True, 1, delta, "adc" ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13554 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13555 | case 0x11: /* ADC Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13556 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13557 | Iop_Add8, True, sz, delta, "adc" ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13558 | break; |
| 13559 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13560 | case 0x18: /* SBB Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13561 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13562 | Iop_Sub8, True, 1, delta, "sbb" ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13563 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13564 | case 0x19: /* SBB Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13565 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13566 | Iop_Sub8, True, sz, delta, "sbb" ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13567 | break; |
| 13568 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13569 | case 0x20: /* AND Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13570 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13571 | Iop_And8, True, 1, delta, "and" ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13572 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13573 | case 0x21: /* AND Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13574 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13575 | Iop_And8, True, sz, delta, "and" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13576 | break; |
| 13577 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13578 | case 0x28: /* SUB Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13579 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13580 | Iop_Sub8, True, 1, delta, "sub" ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13581 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13582 | case 0x29: /* SUB Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13583 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13584 | Iop_Sub8, True, sz, delta, "sub" ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13585 | break; |
| 13586 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13587 | case 0x30: /* XOR Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13588 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13589 | Iop_Xor8, True, 1, delta, "xor" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13590 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13591 | case 0x31: /* XOR Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13592 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13593 | Iop_Xor8, True, sz, delta, "xor" ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13594 | break; |
| 13595 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13596 | case 0x38: /* CMP Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13597 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13598 | Iop_Sub8, False, 1, delta, "cmp" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13599 | break; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13600 | case 0x39: /* CMP Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13601 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13602 | Iop_Sub8, False, sz, delta, "cmp" ); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13603 | break; |
| 13604 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13605 | /* ------------------------ POP ------------------------ */ |
| 13606 | |
| 13607 | case 0x58: /* POP eAX */ |
| 13608 | case 0x59: /* POP eCX */ |
| 13609 | case 0x5A: /* POP eDX */ |
| 13610 | case 0x5B: /* POP eBX */ |
| 13611 | case 0x5D: /* POP eBP */ |
| 13612 | case 0x5E: /* POP eSI */ |
| 13613 | case 0x5F: /* POP eDI */ |
| 13614 | case 0x5C: /* POP eSP */ |
| 13615 | vassert(sz == 2 || sz == 4); |
| 13616 | t1 = newTemp(szToITy(sz)); t2 = newTemp(Ity_I32); |
| 13617 | assign(t2, getIReg(4, R_ESP)); |
| 13618 | assign(t1, loadLE(szToITy(sz),mkexpr(t2))); |
| 13619 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t2), mkU32(sz))); |
| 13620 | putIReg(sz, opc-0x58, mkexpr(t1)); |
| 13621 | DIP("pop%c %s\n", nameISize(sz), nameIReg(sz,opc-0x58)); |
| 13622 | break; |
| 13623 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13624 | case 0x9D: /* POPF */ |
| 13625 | vassert(sz == 2 || sz == 4); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13626 | t1 = newTemp(Ity_I32); t2 = newTemp(Ity_I32); |
| 13627 | assign(t2, getIReg(4, R_ESP)); |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 13628 | assign(t1, widenUto32(loadLE(szToITy(sz),mkexpr(t2)))); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13629 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t2), mkU32(sz))); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13630 | |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 13631 | /* Generate IR to set %EFLAGS{O,S,Z,A,C,P,D,ID,AC} from the |
| 13632 | value in t1. */ |
| 13633 | set_EFLAGS_from_value( t1, True/*emit_AC_emwarn*/, |
| 13634 | ((Addr32)guest_EIP_bbstart)+delta ); |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 13635 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13636 | DIP("popf%c\n", nameISize(sz)); |
| 13637 | break; |
| 13638 | |
sewardj | bbdc622 | 2004-12-15 18:43:39 +0000 | [diff] [blame] | 13639 | case 0x61: /* POPA */ |
| 13640 | /* This is almost certainly wrong for sz==2. So ... */ |
| 13641 | if (sz != 4) goto decode_failure; |
| 13642 | |
| 13643 | /* t5 is the old %ESP value. */ |
| 13644 | t5 = newTemp(Ity_I32); |
| 13645 | assign( t5, getIReg(4, R_ESP) ); |
| 13646 | |
| 13647 | /* Reload all the registers, except %esp. */ |
| 13648 | putIReg(4,R_EAX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(28)) )); |
| 13649 | putIReg(4,R_ECX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(24)) )); |
| 13650 | putIReg(4,R_EDX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(20)) )); |
| 13651 | putIReg(4,R_EBX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(16)) )); |
| 13652 | /* ignore saved %ESP */ |
| 13653 | putIReg(4,R_EBP, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 8)) )); |
| 13654 | putIReg(4,R_ESI, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 4)) )); |
| 13655 | putIReg(4,R_EDI, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 0)) )); |
| 13656 | |
| 13657 | /* and move %ESP back up */ |
| 13658 | putIReg( 4, R_ESP, binop(Iop_Add32, mkexpr(t5), mkU32(8*4)) ); |
| 13659 | |
sewardj | a3d1a66 | 2005-03-29 21:33:11 +0000 | [diff] [blame] | 13660 | DIP("popa%c\n", nameISize(sz)); |
sewardj | bbdc622 | 2004-12-15 18:43:39 +0000 | [diff] [blame] | 13661 | break; |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13662 | |
| 13663 | case 0x8F: /* POPL/POPW m32 */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13664 | { Int len; |
| 13665 | UChar rm = getIByte(delta); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13666 | |
| 13667 | /* make sure this instruction is correct POP */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13668 | if (epartIsReg(rm) || gregOfRM(rm) != 0) |
| 13669 | goto decode_failure; |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13670 | /* and has correct size */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13671 | if (sz != 4 && sz != 2) |
| 13672 | goto decode_failure; |
| 13673 | ty = szToITy(sz); |
| 13674 | |
| 13675 | t1 = newTemp(Ity_I32); /* stack address */ |
| 13676 | t3 = newTemp(ty); /* data */ |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13677 | /* set t1 to ESP: t1 = ESP */ |
| 13678 | assign( t1, getIReg(4, R_ESP) ); |
| 13679 | /* load M[ESP] to virtual register t3: t3 = M[t1] */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13680 | assign( t3, loadLE(ty, mkexpr(t1)) ); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13681 | |
| 13682 | /* increase ESP; must be done before the STORE. Intel manual says: |
| 13683 | If the ESP register is used as a base register for addressing |
| 13684 | a destination operand in memory, the POP instruction computes |
| 13685 | the effective address of the operand after it increments the |
| 13686 | ESP register. |
| 13687 | */ |
| 13688 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t1), mkU32(sz)) ); |
| 13689 | |
| 13690 | /* resolve MODR/M */ |
| 13691 | addr = disAMode ( &len, sorb, delta, dis_buf); |
| 13692 | storeLE( mkexpr(addr), mkexpr(t3) ); |
| 13693 | |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13694 | DIP("pop%c %s\n", sz==2 ? 'w' : 'l', dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13695 | |
| 13696 | delta += len; |
| 13697 | break; |
| 13698 | } |
| 13699 | |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 13700 | case 0x1F: /* POP %DS */ |
| 13701 | dis_pop_segreg( R_DS, sz ); break; |
| 13702 | case 0x07: /* POP %ES */ |
| 13703 | dis_pop_segreg( R_ES, sz ); break; |
| 13704 | case 0x17: /* POP %SS */ |
| 13705 | dis_pop_segreg( R_SS, sz ); break; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13706 | |
| 13707 | /* ------------------------ PUSH ----------------------- */ |
| 13708 | |
| 13709 | case 0x50: /* PUSH eAX */ |
| 13710 | case 0x51: /* PUSH eCX */ |
| 13711 | case 0x52: /* PUSH eDX */ |
| 13712 | case 0x53: /* PUSH eBX */ |
| 13713 | case 0x55: /* PUSH eBP */ |
| 13714 | case 0x56: /* PUSH eSI */ |
| 13715 | case 0x57: /* PUSH eDI */ |
| 13716 | case 0x54: /* PUSH eSP */ |
| 13717 | /* This is the Right Way, in that the value to be pushed is |
| 13718 | established before %esp is changed, so that pushl %esp |
| 13719 | correctly pushes the old value. */ |
| 13720 | vassert(sz == 2 || sz == 4); |
| 13721 | ty = sz==2 ? Ity_I16 : Ity_I32; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 13722 | t1 = newTemp(ty); t2 = newTemp(Ity_I32); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 13723 | assign(t1, getIReg(sz, opc-0x50)); |
| 13724 | assign(t2, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz))); |
| 13725 | putIReg(4, R_ESP, mkexpr(t2) ); |
| 13726 | storeLE(mkexpr(t2),mkexpr(t1)); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13727 | DIP("push%c %s\n", nameISize(sz), nameIReg(sz,opc-0x50)); |
| 13728 | break; |
| 13729 | |
| 13730 | |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 13731 | case 0x68: /* PUSH Iv */ |
| 13732 | d32 = getUDisp(sz,delta); delta += sz; |
| 13733 | goto do_push_I; |
sewardj | 741153c | 2004-07-25 23:39:13 +0000 | [diff] [blame] | 13734 | case 0x6A: /* PUSH Ib, sign-extended to sz */ |
| 13735 | d32 = getSDisp8(delta); delta += 1; |
| 13736 | goto do_push_I; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 13737 | do_push_I: |
| 13738 | ty = szToITy(sz); |
| 13739 | t1 = newTemp(Ity_I32); t2 = newTemp(ty); |
| 13740 | assign( t1, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 13741 | putIReg(4, R_ESP, mkexpr(t1) ); |
sewardj | c4255a0 | 2006-08-28 18:04:33 +0000 | [diff] [blame] | 13742 | /* stop mkU16 asserting if d32 is a negative 16-bit number |
| 13743 | (bug #132813) */ |
| 13744 | if (ty == Ity_I16) |
| 13745 | d32 &= 0xFFFF; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 13746 | storeLE( mkexpr(t1), mkU(ty,d32) ); |
| 13747 | DIP("push%c $0x%x\n", nameISize(sz), d32); |
| 13748 | break; |
| 13749 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13750 | case 0x9C: /* PUSHF */ { |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13751 | vassert(sz == 2 || sz == 4); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13752 | |
| 13753 | t1 = newTemp(Ity_I32); |
| 13754 | assign( t1, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 13755 | putIReg(4, R_ESP, mkexpr(t1) ); |
| 13756 | |
sewardj | bc21094 | 2005-07-21 10:07:13 +0000 | [diff] [blame] | 13757 | /* Calculate OSZACP, and patch in fixed fields as per |
| 13758 | Intel docs. |
| 13759 | - bit 1 is always 1 |
| 13760 | - bit 9 is Interrupt Enable (should always be 1 in user mode?) |
| 13761 | */ |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13762 | t2 = newTemp(Ity_I32); |
sewardj | bc21094 | 2005-07-21 10:07:13 +0000 | [diff] [blame] | 13763 | assign( t2, binop(Iop_Or32, |
| 13764 | mk_x86g_calculate_eflags_all(), |
| 13765 | mkU32( (1<<1)|(1<<9) ) )); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13766 | |
sewardj | f9c74fe | 2004-12-16 02:54:54 +0000 | [diff] [blame] | 13767 | /* Patch in the D flag. This can simply be a copy of bit 10 of |
| 13768 | baseBlock[OFFB_DFLAG]. */ |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13769 | t3 = newTemp(Ity_I32); |
| 13770 | assign( t3, binop(Iop_Or32, |
| 13771 | mkexpr(t2), |
| 13772 | binop(Iop_And32, |
sewardj | f9c74fe | 2004-12-16 02:54:54 +0000 | [diff] [blame] | 13773 | IRExpr_Get(OFFB_DFLAG,Ity_I32), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 13774 | mkU32(1<<10))) |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13775 | ); |
sewardj | 006a6a2 | 2004-10-26 00:50:52 +0000 | [diff] [blame] | 13776 | |
| 13777 | /* And patch in the ID flag. */ |
| 13778 | t4 = newTemp(Ity_I32); |
| 13779 | assign( t4, binop(Iop_Or32, |
| 13780 | mkexpr(t3), |
| 13781 | binop(Iop_And32, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 13782 | binop(Iop_Shl32, IRExpr_Get(OFFB_IDFLAG,Ity_I32), |
sewardj | 006a6a2 | 2004-10-26 00:50:52 +0000 | [diff] [blame] | 13783 | mkU8(21)), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 13784 | mkU32(1<<21))) |
sewardj | 006a6a2 | 2004-10-26 00:50:52 +0000 | [diff] [blame] | 13785 | ); |
| 13786 | |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 13787 | /* And patch in the AC flag. */ |
| 13788 | t5 = newTemp(Ity_I32); |
| 13789 | assign( t5, binop(Iop_Or32, |
| 13790 | mkexpr(t4), |
| 13791 | binop(Iop_And32, |
| 13792 | binop(Iop_Shl32, IRExpr_Get(OFFB_ACFLAG,Ity_I32), |
| 13793 | mkU8(18)), |
| 13794 | mkU32(1<<18))) |
| 13795 | ); |
| 13796 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13797 | /* if sz==2, the stored value needs to be narrowed. */ |
| 13798 | if (sz == 2) |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 13799 | storeLE( mkexpr(t1), unop(Iop_32to16,mkexpr(t5)) ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13800 | else |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 13801 | storeLE( mkexpr(t1), mkexpr(t5) ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13802 | |
| 13803 | DIP("pushf%c\n", nameISize(sz)); |
| 13804 | break; |
| 13805 | } |
| 13806 | |
sewardj | bbdc622 | 2004-12-15 18:43:39 +0000 | [diff] [blame] | 13807 | case 0x60: /* PUSHA */ |
| 13808 | /* This is almost certainly wrong for sz==2. So ... */ |
| 13809 | if (sz != 4) goto decode_failure; |
| 13810 | |
| 13811 | /* This is the Right Way, in that the value to be pushed is |
| 13812 | established before %esp is changed, so that pusha |
| 13813 | correctly pushes the old %esp value. New value of %esp is |
| 13814 | pushed at start. */ |
| 13815 | /* t0 is the %ESP value we're going to push. */ |
| 13816 | t0 = newTemp(Ity_I32); |
| 13817 | assign( t0, getIReg(4, R_ESP) ); |
| 13818 | |
| 13819 | /* t5 will be the new %ESP value. */ |
| 13820 | t5 = newTemp(Ity_I32); |
| 13821 | assign( t5, binop(Iop_Sub32, mkexpr(t0), mkU32(8*4)) ); |
| 13822 | |
| 13823 | /* Update guest state before prodding memory. */ |
| 13824 | putIReg(4, R_ESP, mkexpr(t5)); |
| 13825 | |
| 13826 | /* Dump all the registers. */ |
| 13827 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(28)), getIReg(4,R_EAX) ); |
| 13828 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(24)), getIReg(4,R_ECX) ); |
| 13829 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(20)), getIReg(4,R_EDX) ); |
| 13830 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(16)), getIReg(4,R_EBX) ); |
| 13831 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(12)), mkexpr(t0) /*esp*/); |
| 13832 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 8)), getIReg(4,R_EBP) ); |
| 13833 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 4)), getIReg(4,R_ESI) ); |
| 13834 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 0)), getIReg(4,R_EDI) ); |
| 13835 | |
| 13836 | DIP("pusha%c\n", nameISize(sz)); |
| 13837 | break; |
| 13838 | |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 13839 | case 0x0E: /* PUSH %CS */ |
| 13840 | dis_push_segreg( R_CS, sz ); break; |
| 13841 | case 0x1E: /* PUSH %DS */ |
| 13842 | dis_push_segreg( R_DS, sz ); break; |
| 13843 | case 0x06: /* PUSH %ES */ |
| 13844 | dis_push_segreg( R_ES, sz ); break; |
| 13845 | case 0x16: /* PUSH %SS */ |
| 13846 | dis_push_segreg( R_SS, sz ); break; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 13847 | |
| 13848 | /* ------------------------ SCAS et al ----------------- */ |
| 13849 | |
| 13850 | case 0xA4: /* MOVS, no REP prefix */ |
| 13851 | case 0xA5: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13852 | if (sorb != 0) |
| 13853 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 13854 | dis_string_op( dis_MOVS, ( opc == 0xA4 ? 1 : sz ), "movs", sorb ); |
| 13855 | break; |
| 13856 | |
sewardj | 8d4d223 | 2005-01-20 10:47:46 +0000 | [diff] [blame] | 13857 | case 0xA6: /* CMPSb, no REP prefix */ |
sewardj | 33b5354 | 2005-03-11 14:00:27 +0000 | [diff] [blame] | 13858 | case 0xA7: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13859 | if (sorb != 0) |
| 13860 | goto decode_failure; /* else dis_string_op asserts */ |
| 13861 | dis_string_op( dis_CMPS, ( opc == 0xA6 ? 1 : sz ), "cmps", sorb ); |
| 13862 | break; |
sewardj | 33b5354 | 2005-03-11 14:00:27 +0000 | [diff] [blame] | 13863 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 13864 | case 0xAA: /* STOS, no REP prefix */ |
sewardj | 4734104 | 2004-09-19 11:55:46 +0000 | [diff] [blame] | 13865 | case 0xAB: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13866 | if (sorb != 0) |
| 13867 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 13868 | dis_string_op( dis_STOS, ( opc == 0xAA ? 1 : sz ), "stos", sorb ); |
| 13869 | break; |
sewardj | 33b5354 | 2005-03-11 14:00:27 +0000 | [diff] [blame] | 13870 | |
sewardj | 10ca4eb | 2005-05-30 11:19:54 +0000 | [diff] [blame] | 13871 | case 0xAC: /* LODS, no REP prefix */ |
| 13872 | case 0xAD: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13873 | if (sorb != 0) |
| 13874 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 10ca4eb | 2005-05-30 11:19:54 +0000 | [diff] [blame] | 13875 | dis_string_op( dis_LODS, ( opc == 0xAC ? 1 : sz ), "lods", sorb ); |
| 13876 | break; |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 13877 | |
| 13878 | case 0xAE: /* SCAS, no REP prefix */ |
| 13879 | case 0xAF: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13880 | if (sorb != 0) |
| 13881 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 13882 | dis_string_op( dis_SCAS, ( opc == 0xAE ? 1 : sz ), "scas", sorb ); |
| 13883 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13884 | |
| 13885 | |
| 13886 | case 0xFC: /* CLD */ |
sewardj | eeb9ef8 | 2004-07-15 12:39:03 +0000 | [diff] [blame] | 13887 | stmt( IRStmt_Put( OFFB_DFLAG, mkU32(1)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13888 | DIP("cld\n"); |
| 13889 | break; |
| 13890 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13891 | case 0xFD: /* STD */ |
| 13892 | stmt( IRStmt_Put( OFFB_DFLAG, mkU32(0xFFFFFFFF)) ); |
| 13893 | DIP("std\n"); |
| 13894 | break; |
| 13895 | |
sewardj | bc21094 | 2005-07-21 10:07:13 +0000 | [diff] [blame] | 13896 | case 0xF8: /* CLC */ |
| 13897 | case 0xF9: /* STC */ |
| 13898 | case 0xF5: /* CMC */ |
| 13899 | t0 = newTemp(Ity_I32); |
| 13900 | t1 = newTemp(Ity_I32); |
| 13901 | assign( t0, mk_x86g_calculate_eflags_all() ); |
| 13902 | switch (opc) { |
| 13903 | case 0xF8: |
| 13904 | assign( t1, binop(Iop_And32, mkexpr(t0), |
| 13905 | mkU32(~X86G_CC_MASK_C))); |
| 13906 | DIP("clc\n"); |
| 13907 | break; |
| 13908 | case 0xF9: |
| 13909 | assign( t1, binop(Iop_Or32, mkexpr(t0), |
| 13910 | mkU32(X86G_CC_MASK_C))); |
| 13911 | DIP("stc\n"); |
| 13912 | break; |
| 13913 | case 0xF5: |
| 13914 | assign( t1, binop(Iop_Xor32, mkexpr(t0), |
| 13915 | mkU32(X86G_CC_MASK_C))); |
| 13916 | DIP("cmc\n"); |
| 13917 | break; |
| 13918 | default: |
| 13919 | vpanic("disInstr(x86)(clc/stc/cmc)"); |
| 13920 | } |
| 13921 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 13922 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 13923 | stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t1) )); |
| 13924 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 13925 | elimination of previous stores to this field work better. */ |
| 13926 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 13927 | break; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13928 | |
sewardj | a384eb9 | 2007-11-16 02:30:38 +0000 | [diff] [blame] | 13929 | case 0xD6: /* SALC */ |
| 13930 | t0 = newTemp(Ity_I32); |
| 13931 | t1 = newTemp(Ity_I32); |
| 13932 | assign( t0, binop(Iop_And32, |
| 13933 | mk_x86g_calculate_eflags_c(), |
| 13934 | mkU32(1)) ); |
| 13935 | assign( t1, binop(Iop_Sar32, |
| 13936 | binop(Iop_Shl32, mkexpr(t0), mkU8(31)), |
| 13937 | mkU8(31)) ); |
| 13938 | putIReg(1, R_EAX, unop(Iop_32to8, mkexpr(t1)) ); |
| 13939 | DIP("salc\n"); |
| 13940 | break; |
| 13941 | |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13942 | /* REPNE prefix insn */ |
| 13943 | case 0xF2: { |
sewardj | 068baa2 | 2008-05-11 10:11:58 +0000 | [diff] [blame] | 13944 | Addr32 eip_orig = guest_EIP_bbstart + delta_start; |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13945 | if (sorb != 0) goto decode_failure; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13946 | abyte = getIByte(delta); delta++; |
| 13947 | |
| 13948 | if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13949 | dres.whatNext = Dis_StopHere; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13950 | |
| 13951 | switch (abyte) { |
| 13952 | /* According to the Intel manual, "repne movs" should never occur, but |
| 13953 | * in practice it has happened, so allow for it here... */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13954 | case 0xA4: sz = 1; /* REPNE MOVS<sz> */ |
sewardj | cea9662 | 2006-11-14 15:33:05 +0000 | [diff] [blame] | 13955 | case 0xA5: |
| 13956 | dis_REP_op ( X86CondNZ, dis_MOVS, sz, eip_orig, |
| 13957 | guest_EIP_bbstart+delta, "repne movs" ); |
| 13958 | break; |
sewardj | 842dfb4 | 2008-05-09 08:53:50 +0000 | [diff] [blame] | 13959 | |
| 13960 | case 0xA6: sz = 1; /* REPNE CMP<sz> */ |
| 13961 | case 0xA7: |
| 13962 | dis_REP_op ( X86CondNZ, dis_CMPS, sz, eip_orig, |
| 13963 | guest_EIP_bbstart+delta, "repne cmps" ); |
| 13964 | break; |
| 13965 | |
sewardj | b69a6fa | 2006-11-14 15:13:55 +0000 | [diff] [blame] | 13966 | case 0xAA: sz = 1; /* REPNE STOS<sz> */ |
| 13967 | case 0xAB: |
| 13968 | dis_REP_op ( X86CondNZ, dis_STOS, sz, eip_orig, |
| 13969 | guest_EIP_bbstart+delta, "repne stos" ); |
| 13970 | break; |
| 13971 | |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13972 | case 0xAE: sz = 1; /* REPNE SCAS<sz> */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 13973 | case 0xAF: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 13974 | dis_REP_op ( X86CondNZ, dis_SCAS, sz, eip_orig, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13975 | guest_EIP_bbstart+delta, "repne scas" ); |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13976 | break; |
| 13977 | |
| 13978 | default: |
| 13979 | goto decode_failure; |
| 13980 | } |
| 13981 | break; |
| 13982 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13983 | |
| 13984 | /* REP/REPE prefix insn (for SCAS and CMPS, 0xF3 means REPE, |
| 13985 | for the rest, it means REP) */ |
| 13986 | case 0xF3: { |
sewardj | 068baa2 | 2008-05-11 10:11:58 +0000 | [diff] [blame] | 13987 | Addr32 eip_orig = guest_EIP_bbstart + delta_start; |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 13988 | if (sorb != 0) goto decode_failure; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13989 | abyte = getIByte(delta); delta++; |
| 13990 | |
| 13991 | if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13992 | dres.whatNext = Dis_StopHere; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13993 | |
| 13994 | switch (abyte) { |
| 13995 | case 0xA4: sz = 1; /* REP MOVS<sz> */ |
| 13996 | case 0xA5: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 13997 | dis_REP_op ( X86CondAlways, dis_MOVS, sz, eip_orig, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13998 | guest_EIP_bbstart+delta, "rep movs" ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13999 | break; |
| 14000 | |
| 14001 | case 0xA6: sz = 1; /* REPE CMP<sz> */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14002 | case 0xA7: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14003 | dis_REP_op ( X86CondZ, dis_CMPS, sz, eip_orig, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 14004 | guest_EIP_bbstart+delta, "repe cmps" ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14005 | break; |
| 14006 | |
| 14007 | case 0xAA: sz = 1; /* REP STOS<sz> */ |
| 14008 | case 0xAB: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14009 | dis_REP_op ( X86CondAlways, dis_STOS, sz, eip_orig, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 14010 | guest_EIP_bbstart+delta, "rep stos" ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14011 | break; |
sewardj | 576f323 | 2006-04-12 17:30:46 +0000 | [diff] [blame] | 14012 | |
sewardj | dfb038d | 2007-11-25 01:34:03 +0000 | [diff] [blame] | 14013 | case 0xAC: sz = 1; /* REP LODS<sz> */ |
| 14014 | case 0xAD: |
| 14015 | dis_REP_op ( X86CondAlways, dis_LODS, sz, eip_orig, |
| 14016 | guest_EIP_bbstart+delta, "rep lods" ); |
| 14017 | break; |
| 14018 | |
sewardj | 576f323 | 2006-04-12 17:30:46 +0000 | [diff] [blame] | 14019 | case 0xAE: sz = 1; /* REPE SCAS<sz> */ |
| 14020 | case 0xAF: |
| 14021 | dis_REP_op ( X86CondZ, dis_SCAS, sz, eip_orig, |
| 14022 | guest_EIP_bbstart+delta, "repe scas" ); |
| 14023 | break; |
sewardj | 43b8df1 | 2004-11-26 12:18:51 +0000 | [diff] [blame] | 14024 | |
| 14025 | case 0x90: /* REP NOP (PAUSE) */ |
| 14026 | /* a hint to the P4 re spin-wait loop */ |
| 14027 | DIP("rep nop (P4 pause)\n"); |
sewardj | 7ec59f6 | 2005-03-12 16:47:18 +0000 | [diff] [blame] | 14028 | /* "observe" the hint. The Vex client needs to be careful not |
| 14029 | to cause very long delays as a result, though. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 14030 | jmp_lit(Ijk_Yield, ((Addr32)guest_EIP_bbstart)+delta); |
| 14031 | dres.whatNext = Dis_StopHere; |
sewardj | 43b8df1 | 2004-11-26 12:18:51 +0000 | [diff] [blame] | 14032 | break; |
| 14033 | |
sewardj | 7d3d347 | 2005-08-12 23:51:31 +0000 | [diff] [blame] | 14034 | case 0xC3: /* REP RET -- same as normal ret? */ |
| 14035 | dis_ret(0); |
| 14036 | dres.whatNext = Dis_StopHere; |
| 14037 | DIP("rep ret\n"); |
| 14038 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14039 | |
| 14040 | default: |
| 14041 | goto decode_failure; |
| 14042 | } |
| 14043 | break; |
| 14044 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14045 | |
| 14046 | /* ------------------------ XCHG ----------------------- */ |
| 14047 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 14048 | /* XCHG reg,mem automatically asserts LOCK# even without a LOCK |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 14049 | prefix; hence it must be translated with an IRCAS (at least, the |
| 14050 | memory variant). */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14051 | case 0x86: /* XCHG Gb,Eb */ |
| 14052 | sz = 1; |
| 14053 | /* Fall through ... */ |
| 14054 | case 0x87: /* XCHG Gv,Ev */ |
| 14055 | modrm = getIByte(delta); |
| 14056 | ty = szToITy(sz); |
| 14057 | t1 = newTemp(ty); t2 = newTemp(ty); |
| 14058 | if (epartIsReg(modrm)) { |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14059 | assign(t1, getIReg(sz, eregOfRM(modrm))); |
| 14060 | assign(t2, getIReg(sz, gregOfRM(modrm))); |
| 14061 | putIReg(sz, gregOfRM(modrm), mkexpr(t1)); |
| 14062 | putIReg(sz, eregOfRM(modrm), mkexpr(t2)); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14063 | delta++; |
| 14064 | DIP("xchg%c %s, %s\n", |
| 14065 | nameISize(sz), nameIReg(sz,gregOfRM(modrm)), |
| 14066 | nameIReg(sz,eregOfRM(modrm))); |
| 14067 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14068 | *expect_CAS = True; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 14069 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14070 | assign( t1, loadLE(ty,mkexpr(addr)) ); |
| 14071 | assign( t2, getIReg(sz,gregOfRM(modrm)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14072 | casLE( mkexpr(addr), |
| 14073 | mkexpr(t1), mkexpr(t2), guest_EIP_curr_instr ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14074 | putIReg( sz, gregOfRM(modrm), mkexpr(t1) ); |
| 14075 | delta += alen; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14076 | DIP("xchg%c %s, %s\n", nameISize(sz), |
| 14077 | nameIReg(sz,gregOfRM(modrm)), dis_buf); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14078 | } |
| 14079 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14080 | |
| 14081 | case 0x90: /* XCHG eAX,eAX */ |
| 14082 | DIP("nop\n"); |
| 14083 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14084 | case 0x91: /* XCHG eAX,eCX */ |
| 14085 | case 0x92: /* XCHG eAX,eDX */ |
| 14086 | case 0x93: /* XCHG eAX,eBX */ |
| 14087 | case 0x94: /* XCHG eAX,eSP */ |
| 14088 | case 0x95: /* XCHG eAX,eBP */ |
| 14089 | case 0x96: /* XCHG eAX,eSI */ |
| 14090 | case 0x97: /* XCHG eAX,eDI */ |
| 14091 | codegen_xchg_eAX_Reg ( sz, opc - 0x90 ); |
| 14092 | break; |
| 14093 | |
sewardj | 048de4d | 2006-11-12 22:25:21 +0000 | [diff] [blame] | 14094 | /* ------------------------ XLAT ----------------------- */ |
| 14095 | |
| 14096 | case 0xD7: /* XLAT */ |
| 14097 | if (sz != 4) goto decode_failure; /* sz == 2 is also allowed (0x66) */ |
| 14098 | putIReg( |
| 14099 | 1, |
| 14100 | R_EAX/*AL*/, |
| 14101 | loadLE(Ity_I8, |
| 14102 | handleSegOverride( |
| 14103 | sorb, |
| 14104 | binop(Iop_Add32, |
| 14105 | getIReg(4, R_EBX), |
| 14106 | unop(Iop_8Uto32, getIReg(1, R_EAX/*AL*/)))))); |
| 14107 | |
| 14108 | DIP("xlat%c [ebx]\n", nameISize(sz)); |
| 14109 | break; |
sewardj | d14c570 | 2005-10-29 19:19:51 +0000 | [diff] [blame] | 14110 | |
| 14111 | /* ------------------------ IN / OUT ----------------------- */ |
| 14112 | |
| 14113 | case 0xE4: /* IN imm8, AL */ |
| 14114 | sz = 1; |
| 14115 | t1 = newTemp(Ity_I32); |
| 14116 | abyte = getIByte(delta); delta++; |
| 14117 | assign(t1, mkU32( abyte & 0xFF )); |
| 14118 | DIP("in%c $%d,%s\n", nameISize(sz), (Int)abyte, nameIReg(sz,R_EAX)); |
| 14119 | goto do_IN; |
| 14120 | case 0xE5: /* IN imm8, eAX */ |
| 14121 | vassert(sz == 2 || sz == 4); |
| 14122 | t1 = newTemp(Ity_I32); |
| 14123 | abyte = getIByte(delta); delta++; |
| 14124 | assign(t1, mkU32( abyte & 0xFF )); |
| 14125 | DIP("in%c $%d,%s\n", nameISize(sz), (Int)abyte, nameIReg(sz,R_EAX)); |
| 14126 | goto do_IN; |
| 14127 | case 0xEC: /* IN %DX, AL */ |
| 14128 | sz = 1; |
| 14129 | t1 = newTemp(Ity_I32); |
| 14130 | assign(t1, unop(Iop_16Uto32, getIReg(2, R_EDX))); |
| 14131 | DIP("in%c %s,%s\n", nameISize(sz), nameIReg(2,R_EDX), |
| 14132 | nameIReg(sz,R_EAX)); |
| 14133 | goto do_IN; |
| 14134 | case 0xED: /* IN %DX, eAX */ |
| 14135 | vassert(sz == 2 || sz == 4); |
| 14136 | t1 = newTemp(Ity_I32); |
| 14137 | assign(t1, unop(Iop_16Uto32, getIReg(2, R_EDX))); |
| 14138 | DIP("in%c %s,%s\n", nameISize(sz), nameIReg(2,R_EDX), |
| 14139 | nameIReg(sz,R_EAX)); |
| 14140 | goto do_IN; |
| 14141 | do_IN: { |
| 14142 | /* At this point, sz indicates the width, and t1 is a 32-bit |
| 14143 | value giving port number. */ |
| 14144 | IRDirty* d; |
| 14145 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 14146 | ty = szToITy(sz); |
| 14147 | t2 = newTemp(Ity_I32); |
| 14148 | d = unsafeIRDirty_1_N( |
| 14149 | t2, |
| 14150 | 0/*regparms*/, |
| 14151 | "x86g_dirtyhelper_IN", |
| 14152 | &x86g_dirtyhelper_IN, |
| 14153 | mkIRExprVec_2( mkexpr(t1), mkU32(sz) ) |
| 14154 | ); |
| 14155 | /* do the call, dumping the result in t2. */ |
| 14156 | stmt( IRStmt_Dirty(d) ); |
| 14157 | putIReg(sz, R_EAX, narrowTo( ty, mkexpr(t2) ) ); |
| 14158 | break; |
| 14159 | } |
| 14160 | |
| 14161 | case 0xE6: /* OUT AL, imm8 */ |
| 14162 | sz = 1; |
| 14163 | t1 = newTemp(Ity_I32); |
| 14164 | abyte = getIByte(delta); delta++; |
| 14165 | assign( t1, mkU32( abyte & 0xFF ) ); |
| 14166 | DIP("out%c %s,$%d\n", nameISize(sz), nameIReg(sz,R_EAX), (Int)abyte); |
| 14167 | goto do_OUT; |
| 14168 | case 0xE7: /* OUT eAX, imm8 */ |
| 14169 | vassert(sz == 2 || sz == 4); |
| 14170 | t1 = newTemp(Ity_I32); |
| 14171 | abyte = getIByte(delta); delta++; |
| 14172 | assign( t1, mkU32( abyte & 0xFF ) ); |
| 14173 | DIP("out%c %s,$%d\n", nameISize(sz), nameIReg(sz,R_EAX), (Int)abyte); |
| 14174 | goto do_OUT; |
| 14175 | case 0xEE: /* OUT AL, %DX */ |
| 14176 | sz = 1; |
| 14177 | t1 = newTemp(Ity_I32); |
| 14178 | assign( t1, unop(Iop_16Uto32, getIReg(2, R_EDX)) ); |
| 14179 | DIP("out%c %s,%s\n", nameISize(sz), nameIReg(sz,R_EAX), |
| 14180 | nameIReg(2,R_EDX)); |
| 14181 | goto do_OUT; |
| 14182 | case 0xEF: /* OUT eAX, %DX */ |
| 14183 | vassert(sz == 2 || sz == 4); |
| 14184 | t1 = newTemp(Ity_I32); |
| 14185 | assign( t1, unop(Iop_16Uto32, getIReg(2, R_EDX)) ); |
| 14186 | DIP("out%c %s,%s\n", nameISize(sz), nameIReg(sz,R_EAX), |
| 14187 | nameIReg(2,R_EDX)); |
| 14188 | goto do_OUT; |
| 14189 | do_OUT: { |
| 14190 | /* At this point, sz indicates the width, and t1 is a 32-bit |
| 14191 | value giving port number. */ |
| 14192 | IRDirty* d; |
| 14193 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 14194 | ty = szToITy(sz); |
| 14195 | d = unsafeIRDirty_0_N( |
| 14196 | 0/*regparms*/, |
| 14197 | "x86g_dirtyhelper_OUT", |
| 14198 | &x86g_dirtyhelper_OUT, |
| 14199 | mkIRExprVec_3( mkexpr(t1), |
| 14200 | widenUto32( getIReg(sz, R_EAX) ), |
| 14201 | mkU32(sz) ) |
| 14202 | ); |
| 14203 | stmt( IRStmt_Dirty(d) ); |
| 14204 | break; |
| 14205 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14206 | |
| 14207 | /* ------------------------ (Grp1 extensions) ---------- */ |
| 14208 | |
sewardj | 792d771 | 2008-10-31 21:27:38 +0000 | [diff] [blame] | 14209 | case 0x82: /* Grp1 Ib,Eb too. Apparently this is the same as |
| 14210 | case 0x80, but only in 32-bit mode. */ |
| 14211 | /* fallthru */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14212 | case 0x80: /* Grp1 Ib,Eb */ |
| 14213 | modrm = getIByte(delta); |
| 14214 | am_sz = lengthAMode(delta); |
| 14215 | sz = 1; |
| 14216 | d_sz = 1; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14217 | d32 = getUChar(delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14218 | delta = dis_Grp1 ( sorb, pfx_lock, delta, modrm, am_sz, d_sz, sz, d32 ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14219 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 14220 | |
| 14221 | case 0x81: /* Grp1 Iv,Ev */ |
| 14222 | modrm = getIByte(delta); |
| 14223 | am_sz = lengthAMode(delta); |
| 14224 | d_sz = sz; |
| 14225 | d32 = getUDisp(d_sz, delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14226 | delta = dis_Grp1 ( sorb, pfx_lock, delta, modrm, am_sz, d_sz, sz, d32 ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 14227 | break; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 14228 | |
| 14229 | case 0x83: /* Grp1 Ib,Ev */ |
| 14230 | modrm = getIByte(delta); |
| 14231 | am_sz = lengthAMode(delta); |
| 14232 | d_sz = 1; |
| 14233 | d32 = getSDisp8(delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14234 | delta = dis_Grp1 ( sorb, pfx_lock, delta, modrm, am_sz, d_sz, sz, d32 ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 14235 | break; |
| 14236 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14237 | /* ------------------------ (Grp2 extensions) ---------- */ |
| 14238 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14239 | case 0xC0: { /* Grp2 Ib,Eb */ |
| 14240 | Bool decode_OK = True; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14241 | modrm = getIByte(delta); |
| 14242 | am_sz = lengthAMode(delta); |
| 14243 | d_sz = 1; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14244 | d32 = getUChar(delta + am_sz); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14245 | sz = 1; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 14246 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14247 | mkU8(d32 & 0xFF), NULL, &decode_OK ); |
| 14248 | if (!decode_OK) |
| 14249 | goto decode_failure; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14250 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14251 | } |
| 14252 | case 0xC1: { /* Grp2 Ib,Ev */ |
| 14253 | Bool decode_OK = True; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14254 | modrm = getIByte(delta); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 14255 | am_sz = lengthAMode(delta); |
| 14256 | d_sz = 1; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14257 | d32 = getUChar(delta + am_sz); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 14258 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14259 | mkU8(d32 & 0xFF), NULL, &decode_OK ); |
| 14260 | if (!decode_OK) |
| 14261 | goto decode_failure; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 14262 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14263 | } |
| 14264 | case 0xD0: { /* Grp2 1,Eb */ |
| 14265 | Bool decode_OK = True; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14266 | modrm = getIByte(delta); |
| 14267 | am_sz = lengthAMode(delta); |
| 14268 | d_sz = 0; |
| 14269 | d32 = 1; |
| 14270 | sz = 1; |
| 14271 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14272 | mkU8(d32), NULL, &decode_OK ); |
| 14273 | if (!decode_OK) |
| 14274 | goto decode_failure; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14275 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14276 | } |
| 14277 | case 0xD1: { /* Grp2 1,Ev */ |
| 14278 | Bool decode_OK = True; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14279 | modrm = getUChar(delta); |
| 14280 | am_sz = lengthAMode(delta); |
| 14281 | d_sz = 0; |
| 14282 | d32 = 1; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 14283 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14284 | mkU8(d32), NULL, &decode_OK ); |
| 14285 | if (!decode_OK) |
| 14286 | goto decode_failure; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14287 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14288 | } |
| 14289 | case 0xD2: { /* Grp2 CL,Eb */ |
| 14290 | Bool decode_OK = True; |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 14291 | modrm = getUChar(delta); |
| 14292 | am_sz = lengthAMode(delta); |
| 14293 | d_sz = 0; |
| 14294 | sz = 1; |
| 14295 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14296 | getIReg(1,R_ECX), "%cl", &decode_OK ); |
| 14297 | if (!decode_OK) |
| 14298 | goto decode_failure; |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 14299 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14300 | } |
| 14301 | case 0xD3: { /* Grp2 CL,Ev */ |
| 14302 | Bool decode_OK = True; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14303 | modrm = getIByte(delta); |
| 14304 | am_sz = lengthAMode(delta); |
| 14305 | d_sz = 0; |
| 14306 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14307 | getIReg(1,R_ECX), "%cl", &decode_OK ); |
| 14308 | if (!decode_OK) |
| 14309 | goto decode_failure; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14310 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14311 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14312 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14313 | /* ------------------------ (Grp3 extensions) ---------- */ |
| 14314 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14315 | case 0xF6: { /* Grp3 Eb */ |
| 14316 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14317 | delta = dis_Grp3 ( sorb, pfx_lock, 1, delta, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14318 | if (!decode_OK) |
| 14319 | goto decode_failure; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14320 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14321 | } |
| 14322 | case 0xF7: { /* Grp3 Ev */ |
| 14323 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14324 | delta = dis_Grp3 ( sorb, pfx_lock, sz, delta, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14325 | if (!decode_OK) |
| 14326 | goto decode_failure; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14327 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14328 | } |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14329 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14330 | /* ------------------------ (Grp4 extensions) ---------- */ |
| 14331 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14332 | case 0xFE: { /* Grp4 Eb */ |
| 14333 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14334 | delta = dis_Grp4 ( sorb, pfx_lock, delta, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14335 | if (!decode_OK) |
| 14336 | goto decode_failure; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14337 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14338 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14339 | |
| 14340 | /* ------------------------ (Grp5 extensions) ---------- */ |
| 14341 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14342 | case 0xFF: { /* Grp5 Ev */ |
| 14343 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14344 | delta = dis_Grp5 ( sorb, pfx_lock, sz, delta, &dres, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14345 | if (!decode_OK) |
| 14346 | goto decode_failure; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14347 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14348 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14349 | |
| 14350 | /* ------------------------ Escapes to 2-byte opcodes -- */ |
| 14351 | |
| 14352 | case 0x0F: { |
| 14353 | opc = getIByte(delta); delta++; |
| 14354 | switch (opc) { |
| 14355 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 14356 | /* =-=-=-=-=-=-=-=-=- Grp8 =-=-=-=-=-=-=-=-=-=-=-= */ |
| 14357 | |
| 14358 | case 0xBA: { /* Grp8 Ib,Ev */ |
| 14359 | Bool decode_OK = False; |
| 14360 | modrm = getUChar(delta); |
| 14361 | am_sz = lengthAMode(delta); |
| 14362 | d32 = getSDisp8(delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14363 | delta = dis_Grp8_Imm ( sorb, pfx_lock, delta, modrm, |
| 14364 | am_sz, sz, d32, &decode_OK ); |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 14365 | if (!decode_OK) |
| 14366 | goto decode_failure; |
| 14367 | break; |
| 14368 | } |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 14369 | |
| 14370 | /* =-=-=-=-=-=-=-=-=- BSF/BSR -=-=-=-=-=-=-=-=-=-= */ |
| 14371 | |
| 14372 | case 0xBC: /* BSF Gv,Ev */ |
| 14373 | delta = dis_bs_E_G ( sorb, sz, delta, True ); |
| 14374 | break; |
| 14375 | case 0xBD: /* BSR Gv,Ev */ |
| 14376 | delta = dis_bs_E_G ( sorb, sz, delta, False ); |
| 14377 | break; |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14378 | |
| 14379 | /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */ |
| 14380 | |
| 14381 | case 0xC8: /* BSWAP %eax */ |
| 14382 | case 0xC9: |
| 14383 | case 0xCA: |
sewardj | b4666cf | 2004-10-23 00:21:50 +0000 | [diff] [blame] | 14384 | case 0xCB: |
| 14385 | case 0xCC: |
| 14386 | case 0xCD: |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14387 | case 0xCE: |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14388 | case 0xCF: /* BSWAP %edi */ |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14389 | /* AFAICS from the Intel docs, this only exists at size 4. */ |
| 14390 | vassert(sz == 4); |
| 14391 | t1 = newTemp(Ity_I32); |
| 14392 | t2 = newTemp(Ity_I32); |
| 14393 | assign( t1, getIReg(4, opc-0xC8) ); |
| 14394 | |
| 14395 | assign( t2, |
| 14396 | binop(Iop_Or32, |
| 14397 | binop(Iop_Shl32, mkexpr(t1), mkU8(24)), |
| 14398 | binop(Iop_Or32, |
| 14399 | binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)), |
| 14400 | mkU32(0x00FF0000)), |
| 14401 | binop(Iop_Or32, |
| 14402 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)), |
| 14403 | mkU32(0x0000FF00)), |
| 14404 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)), |
| 14405 | mkU32(0x000000FF) ) |
| 14406 | ))) |
| 14407 | ); |
| 14408 | |
| 14409 | putIReg(4, opc-0xC8, mkexpr(t2)); |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14410 | DIP("bswapl %s\n", nameIReg(4, opc-0xC8)); |
| 14411 | break; |
| 14412 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14413 | /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */ |
| 14414 | |
| 14415 | case 0xA3: /* BT Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14416 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpNone ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14417 | break; |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 14418 | case 0xB3: /* BTR Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14419 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpReset ); |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 14420 | break; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14421 | case 0xAB: /* BTS Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14422 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpSet ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14423 | break; |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 14424 | case 0xBB: /* BTC Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14425 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpComp ); |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 14426 | break; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14427 | |
| 14428 | /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */ |
| 14429 | |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14430 | case 0x40: |
| 14431 | case 0x41: |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14432 | case 0x42: /* CMOVBb/CMOVNAEb (cmov below) */ |
| 14433 | case 0x43: /* CMOVNBb/CMOVAEb (cmov not below) */ |
| 14434 | case 0x44: /* CMOVZb/CMOVEb (cmov zero) */ |
| 14435 | case 0x45: /* CMOVNZb/CMOVNEb (cmov not zero) */ |
| 14436 | case 0x46: /* CMOVBEb/CMOVNAb (cmov below or equal) */ |
| 14437 | case 0x47: /* CMOVNBEb/CMOVAb (cmov not below or equal) */ |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 14438 | case 0x48: /* CMOVSb (cmov negative) */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14439 | case 0x49: /* CMOVSb (cmov not negative) */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14440 | case 0x4A: /* CMOVP (cmov parity even) */ |
| 14441 | case 0x4B: /* CMOVNP (cmov parity odd) */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14442 | case 0x4C: /* CMOVLb/CMOVNGEb (cmov less) */ |
| 14443 | case 0x4D: /* CMOVGEb/CMOVNLb (cmov greater or equal) */ |
| 14444 | case 0x4E: /* CMOVLEb/CMOVNGb (cmov less or equal) */ |
| 14445 | case 0x4F: /* CMOVGb/CMOVNLEb (cmov greater) */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14446 | delta = dis_cmov_E_G(sorb, sz, (X86Condcode)(opc - 0x40), delta); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14447 | break; |
| 14448 | |
| 14449 | /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */ |
| 14450 | |
sewardj | c744e87 | 2004-08-26 11:24:39 +0000 | [diff] [blame] | 14451 | case 0xB0: /* CMPXCHG Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14452 | delta = dis_cmpxchg_G_E ( sorb, pfx_lock, 1, delta ); |
sewardj | c744e87 | 2004-08-26 11:24:39 +0000 | [diff] [blame] | 14453 | break; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14454 | case 0xB1: /* CMPXCHG Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14455 | delta = dis_cmpxchg_G_E ( sorb, pfx_lock, sz, delta ); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14456 | break; |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14457 | |
| 14458 | case 0xC7: { /* CMPXCHG8B Gv (0F C7 /1) */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14459 | IRTemp expdHi = newTemp(Ity_I32); |
| 14460 | IRTemp expdLo = newTemp(Ity_I32); |
| 14461 | IRTemp dataHi = newTemp(Ity_I32); |
| 14462 | IRTemp dataLo = newTemp(Ity_I32); |
| 14463 | IRTemp oldHi = newTemp(Ity_I32); |
| 14464 | IRTemp oldLo = newTemp(Ity_I32); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14465 | IRTemp flags_old = newTemp(Ity_I32); |
| 14466 | IRTemp flags_new = newTemp(Ity_I32); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14467 | IRTemp success = newTemp(Ity_I1); |
| 14468 | |
| 14469 | /* Translate this using a DCAS, even if there is no LOCK |
| 14470 | prefix. Life is too short to bother with generating two |
| 14471 | different translations for the with/without-LOCK-prefix |
| 14472 | cases. */ |
| 14473 | *expect_CAS = True; |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14474 | |
| 14475 | /* Decode, and generate address. */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14476 | if (sz != 4) goto decode_failure; |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14477 | modrm = getIByte(delta); |
| 14478 | if (epartIsReg(modrm)) goto decode_failure; |
| 14479 | if (gregOfRM(modrm) != 1) goto decode_failure; |
| 14480 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 14481 | delta += alen; |
| 14482 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14483 | /* Get the expected and new values. */ |
| 14484 | assign( expdHi, getIReg(4,R_EDX) ); |
| 14485 | assign( expdLo, getIReg(4,R_EAX) ); |
| 14486 | assign( dataHi, getIReg(4,R_ECX) ); |
| 14487 | assign( dataLo, getIReg(4,R_EBX) ); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14488 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14489 | /* Do the DCAS */ |
| 14490 | stmt( IRStmt_CAS( |
| 14491 | mkIRCAS( oldHi, oldLo, |
| 14492 | Iend_LE, mkexpr(addr), |
| 14493 | mkexpr(expdHi), mkexpr(expdLo), |
| 14494 | mkexpr(dataHi), mkexpr(dataLo) |
| 14495 | ))); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14496 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14497 | /* success when oldHi:oldLo == expdHi:expdLo */ |
| 14498 | assign( success, |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 14499 | binop(Iop_CasCmpEQ32, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14500 | binop(Iop_Or32, |
| 14501 | binop(Iop_Xor32, mkexpr(oldHi), mkexpr(expdHi)), |
| 14502 | binop(Iop_Xor32, mkexpr(oldLo), mkexpr(expdLo)) |
| 14503 | ), |
| 14504 | mkU32(0) |
| 14505 | )); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14506 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14507 | /* If the DCAS is successful, that is to say oldHi:oldLo == |
| 14508 | expdHi:expdLo, then put expdHi:expdLo back in EDX:EAX, |
| 14509 | which is where they came from originally. Both the actual |
| 14510 | contents of these two regs, and any shadow values, are |
| 14511 | unchanged. If the DCAS fails then we're putting into |
| 14512 | EDX:EAX the value seen in memory. */ |
| 14513 | putIReg(4, R_EDX, |
| 14514 | IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(success)), |
| 14515 | mkexpr(oldHi), |
| 14516 | mkexpr(expdHi) |
| 14517 | )); |
| 14518 | putIReg(4, R_EAX, |
| 14519 | IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(success)), |
| 14520 | mkexpr(oldLo), |
| 14521 | mkexpr(expdLo) |
| 14522 | )); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14523 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14524 | /* Copy the success bit into the Z flag and leave the others |
| 14525 | unchanged */ |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14526 | assign( flags_old, widenUto32(mk_x86g_calculate_eflags_all())); |
| 14527 | assign( |
| 14528 | flags_new, |
| 14529 | binop(Iop_Or32, |
| 14530 | binop(Iop_And32, mkexpr(flags_old), |
| 14531 | mkU32(~X86G_CC_MASK_Z)), |
| 14532 | binop(Iop_Shl32, |
| 14533 | binop(Iop_And32, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14534 | unop(Iop_1Uto32, mkexpr(success)), mkU32(1)), |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14535 | mkU8(X86G_CC_SHIFT_Z)) )); |
| 14536 | |
| 14537 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 14538 | stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(flags_new) )); |
| 14539 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 14540 | /* Set NDEP even though it isn't used. This makes |
| 14541 | redundant-PUT elimination of previous stores to this field |
| 14542 | work better. */ |
| 14543 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 14544 | |
| 14545 | /* Sheesh. Aren't you glad it was me and not you that had to |
| 14546 | write and validate all this grunge? */ |
| 14547 | |
| 14548 | DIP("cmpxchg8b %s\n", dis_buf); |
| 14549 | break; |
| 14550 | } |
| 14551 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 14552 | /* =-=-=-=-=-=-=-=-=- CPUID -=-=-=-=-=-=-=-=-=-=-= */ |
| 14553 | |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14554 | case 0xA2: { /* CPUID */ |
| 14555 | /* Uses dirty helper: |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14556 | void dirtyhelper_CPUID_sse[012] ( VexGuestX86State* ) |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14557 | declared to mod eax, wr ebx, ecx, edx |
| 14558 | */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14559 | IRDirty* d = NULL; |
| 14560 | HChar* fName = NULL; |
| 14561 | void* fAddr = NULL; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 14562 | if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2) { |
| 14563 | fName = "x86g_dirtyhelper_CPUID_sse2"; |
| 14564 | fAddr = &x86g_dirtyhelper_CPUID_sse2; |
| 14565 | } |
| 14566 | else |
| 14567 | if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE1) { |
| 14568 | fName = "x86g_dirtyhelper_CPUID_sse1"; |
| 14569 | fAddr = &x86g_dirtyhelper_CPUID_sse1; |
| 14570 | } |
| 14571 | else |
| 14572 | if (archinfo->hwcaps == 0/*no SSE*/) { |
| 14573 | fName = "x86g_dirtyhelper_CPUID_sse0"; |
| 14574 | fAddr = &x86g_dirtyhelper_CPUID_sse0; |
| 14575 | } else |
| 14576 | vpanic("disInstr(x86)(cpuid)"); |
| 14577 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14578 | vassert(fName); vassert(fAddr); |
| 14579 | d = unsafeIRDirty_0_N ( 0/*regparms*/, |
| 14580 | fName, fAddr, mkIRExprVec_0() ); |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14581 | /* declare guest state effects */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 14582 | d->needsBBP = True; |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14583 | d->nFxState = 4; |
| 14584 | d->fxState[0].fx = Ifx_Modify; |
| 14585 | d->fxState[0].offset = OFFB_EAX; |
| 14586 | d->fxState[0].size = 4; |
| 14587 | d->fxState[1].fx = Ifx_Write; |
| 14588 | d->fxState[1].offset = OFFB_EBX; |
| 14589 | d->fxState[1].size = 4; |
sewardj | 32bfd3e | 2008-02-10 13:29:19 +0000 | [diff] [blame] | 14590 | d->fxState[2].fx = Ifx_Modify; |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14591 | d->fxState[2].offset = OFFB_ECX; |
| 14592 | d->fxState[2].size = 4; |
| 14593 | d->fxState[3].fx = Ifx_Write; |
| 14594 | d->fxState[3].offset = OFFB_EDX; |
| 14595 | d->fxState[3].size = 4; |
| 14596 | /* execute the dirty call, side-effecting guest state */ |
| 14597 | stmt( IRStmt_Dirty(d) ); |
sewardj | 55860d8 | 2005-01-08 18:25:05 +0000 | [diff] [blame] | 14598 | /* CPUID is a serialising insn. So, just in case someone is |
| 14599 | using it as a memory fence ... */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 14600 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | 517a7d6 | 2004-10-25 09:52:18 +0000 | [diff] [blame] | 14601 | DIP("cpuid\n"); |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 14602 | break; |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14603 | } |
| 14604 | |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14605 | //-- if (!VG_(cpu_has_feature)(VG_X86_FEAT_CPUID)) |
| 14606 | //-- goto decode_failure; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 14607 | //-- |
| 14608 | //-- t1 = newTemp(cb); |
| 14609 | //-- t2 = newTemp(cb); |
| 14610 | //-- t3 = newTemp(cb); |
| 14611 | //-- t4 = newTemp(cb); |
| 14612 | //-- uInstr0(cb, CALLM_S, 0); |
| 14613 | //-- |
| 14614 | //-- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t1); |
| 14615 | //-- uInstr1(cb, PUSH, 4, TempReg, t1); |
| 14616 | //-- |
| 14617 | //-- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2); |
| 14618 | //-- uLiteral(cb, 0); |
| 14619 | //-- uInstr1(cb, PUSH, 4, TempReg, t2); |
| 14620 | //-- |
| 14621 | //-- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t3); |
| 14622 | //-- uLiteral(cb, 0); |
| 14623 | //-- uInstr1(cb, PUSH, 4, TempReg, t3); |
| 14624 | //-- |
| 14625 | //-- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t4); |
| 14626 | //-- uLiteral(cb, 0); |
| 14627 | //-- uInstr1(cb, PUSH, 4, TempReg, t4); |
| 14628 | //-- |
| 14629 | //-- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_CPUID)); |
| 14630 | //-- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty); |
| 14631 | //-- |
| 14632 | //-- uInstr1(cb, POP, 4, TempReg, t4); |
| 14633 | //-- uInstr2(cb, PUT, 4, TempReg, t4, ArchReg, R_EDX); |
| 14634 | //-- |
| 14635 | //-- uInstr1(cb, POP, 4, TempReg, t3); |
| 14636 | //-- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ECX); |
| 14637 | //-- |
| 14638 | //-- uInstr1(cb, POP, 4, TempReg, t2); |
| 14639 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBX); |
| 14640 | //-- |
| 14641 | //-- uInstr1(cb, POP, 4, TempReg, t1); |
| 14642 | //-- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_EAX); |
| 14643 | //-- |
| 14644 | //-- uInstr0(cb, CALLM_E, 0); |
| 14645 | //-- DIP("cpuid\n"); |
| 14646 | //-- break; |
| 14647 | //-- |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14648 | /* =-=-=-=-=-=-=-=-=- MOVZX, MOVSX =-=-=-=-=-=-=-= */ |
| 14649 | |
| 14650 | case 0xB6: /* MOVZXb Eb,Gv */ |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14651 | if (sz != 2 && sz != 4) |
| 14652 | goto decode_failure; |
| 14653 | delta = dis_movx_E_G ( sorb, delta, 1, sz, False ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14654 | break; |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14655 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14656 | case 0xB7: /* MOVZXw Ew,Gv */ |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14657 | if (sz != 4) |
| 14658 | goto decode_failure; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14659 | delta = dis_movx_E_G ( sorb, delta, 2, 4, False ); |
| 14660 | break; |
| 14661 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14662 | case 0xBE: /* MOVSXb Eb,Gv */ |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14663 | if (sz != 2 && sz != 4) |
| 14664 | goto decode_failure; |
| 14665 | delta = dis_movx_E_G ( sorb, delta, 1, sz, True ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14666 | break; |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14667 | |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 14668 | case 0xBF: /* MOVSXw Ew,Gv */ |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 14669 | if (sz != 4 && /* accept movsww, sigh, see #250799 */sz != 2) |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14670 | goto decode_failure; |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 14671 | delta = dis_movx_E_G ( sorb, delta, 2, sz, True ); |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 14672 | break; |
| 14673 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 14674 | //-- /* =-=-=-=-=-=-=-=-=-=-= MOVNTI -=-=-=-=-=-=-=-=-= */ |
| 14675 | //-- |
| 14676 | //-- case 0xC3: /* MOVNTI Gv,Ev */ |
| 14677 | //-- vg_assert(sz == 4); |
| 14678 | //-- modrm = getUChar(eip); |
| 14679 | //-- vg_assert(!epartIsReg(modrm)); |
| 14680 | //-- t1 = newTemp(cb); |
| 14681 | //-- uInstr2(cb, GET, 4, ArchReg, gregOfRM(modrm), TempReg, t1); |
| 14682 | //-- pair = disAMode ( cb, sorb, eip, dis_buf ); |
| 14683 | //-- t2 = LOW24(pair); |
| 14684 | //-- eip += HI8(pair); |
| 14685 | //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2); |
| 14686 | //-- DIP("movnti %s,%s\n", nameIReg(4,gregOfRM(modrm)), dis_buf); |
| 14687 | //-- break; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 14688 | |
| 14689 | /* =-=-=-=-=-=-=-=-=- MUL/IMUL =-=-=-=-=-=-=-=-=-= */ |
| 14690 | |
| 14691 | case 0xAF: /* IMUL Ev, Gv */ |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 14692 | delta = dis_mul_E_G ( sorb, sz, delta ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 14693 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14694 | |
sewardj | ec387ca | 2006-08-01 18:36:25 +0000 | [diff] [blame] | 14695 | /* =-=-=-=-=-=-=-=-=- NOPs =-=-=-=-=-=-=-=-=-=-=-= */ |
| 14696 | |
| 14697 | case 0x1F: |
| 14698 | modrm = getUChar(delta); |
| 14699 | if (epartIsReg(modrm)) goto decode_failure; |
| 14700 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 14701 | delta += alen; |
| 14702 | DIP("nop%c %s\n", nameISize(sz), dis_buf); |
| 14703 | break; |
| 14704 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14705 | /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */ |
| 14706 | case 0x80: |
| 14707 | case 0x81: |
| 14708 | case 0x82: /* JBb/JNAEb (jump below) */ |
| 14709 | case 0x83: /* JNBb/JAEb (jump not below) */ |
| 14710 | case 0x84: /* JZb/JEb (jump zero) */ |
| 14711 | case 0x85: /* JNZb/JNEb (jump not zero) */ |
| 14712 | case 0x86: /* JBEb/JNAb (jump below or equal) */ |
| 14713 | case 0x87: /* JNBEb/JAb (jump not below or equal) */ |
| 14714 | case 0x88: /* JSb (jump negative) */ |
| 14715 | case 0x89: /* JSb (jump not negative) */ |
| 14716 | case 0x8A: /* JP (jump parity even) */ |
| 14717 | case 0x8B: /* JNP/JPO (jump parity odd) */ |
| 14718 | case 0x8C: /* JLb/JNGEb (jump less) */ |
| 14719 | case 0x8D: /* JGEb/JNLb (jump greater or equal) */ |
| 14720 | case 0x8E: /* JLEb/JNGb (jump less or equal) */ |
| 14721 | case 0x8F: /* JGb/JNLEb (jump greater) */ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14722 | { Int jmpDelta; |
| 14723 | HChar* comment = ""; |
| 14724 | jmpDelta = (Int)getUDisp32(delta); |
| 14725 | d32 = (((Addr32)guest_EIP_bbstart)+delta+4) + jmpDelta; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14726 | delta += 4; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14727 | if (resteerCisOk |
| 14728 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 14729 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14730 | && jmpDelta < 0 |
| 14731 | && resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { |
| 14732 | /* Speculation: assume this backward branch is taken. So |
| 14733 | we need to emit a side-exit to the insn following this |
| 14734 | one, on the negation of the condition, and continue at |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 14735 | the branch target address (d32). If we wind up back at |
| 14736 | the first instruction of the trace, just stop; it's |
| 14737 | better to let the IR loop unroller handle that case.*/ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14738 | stmt( IRStmt_Exit( |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 14739 | mk_x86g_calculate_condition((X86Condcode) |
| 14740 | (1 ^ (opc - 0x80))), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14741 | Ijk_Boring, |
| 14742 | IRConst_U32(guest_EIP_bbstart+delta) ) ); |
| 14743 | dres.whatNext = Dis_ResteerC; |
| 14744 | dres.continueAt = (Addr64)(Addr32)d32; |
| 14745 | comment = "(assumed taken)"; |
| 14746 | } |
| 14747 | else |
| 14748 | if (resteerCisOk |
| 14749 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 14750 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14751 | && jmpDelta >= 0 |
| 14752 | && resteerOkFn( callback_opaque, |
| 14753 | (Addr64)(Addr32)(guest_EIP_bbstart+delta)) ) { |
| 14754 | /* Speculation: assume this forward branch is not taken. |
| 14755 | So we need to emit a side-exit to d32 (the dest) and |
| 14756 | continue disassembling at the insn immediately |
| 14757 | following this one. */ |
| 14758 | stmt( IRStmt_Exit( |
| 14759 | mk_x86g_calculate_condition((X86Condcode)(opc - 0x80)), |
| 14760 | Ijk_Boring, |
| 14761 | IRConst_U32(d32) ) ); |
| 14762 | dres.whatNext = Dis_ResteerC; |
| 14763 | dres.continueAt = (Addr64)(Addr32)(guest_EIP_bbstart+delta); |
| 14764 | comment = "(assumed not taken)"; |
| 14765 | } |
| 14766 | else { |
| 14767 | /* Conservative default translation - end the block at |
| 14768 | this point. */ |
| 14769 | jcc_01( (X86Condcode)(opc - 0x80), |
| 14770 | (Addr32)(guest_EIP_bbstart+delta), d32); |
| 14771 | dres.whatNext = Dis_StopHere; |
| 14772 | } |
| 14773 | DIP("j%s-32 0x%x %s\n", name_X86Condcode(opc - 0x80), d32, comment); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14774 | break; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 14775 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14776 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 14777 | /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */ |
sewardj | 4ed6429 | 2005-08-23 19:24:29 +0000 | [diff] [blame] | 14778 | case 0x31: { /* RDTSC */ |
| 14779 | IRTemp val = newTemp(Ity_I64); |
| 14780 | IRExpr** args = mkIRExprVec_0(); |
| 14781 | IRDirty* d = unsafeIRDirty_1_N ( |
| 14782 | val, |
| 14783 | 0/*regparms*/, |
| 14784 | "x86g_dirtyhelper_RDTSC", |
| 14785 | &x86g_dirtyhelper_RDTSC, |
| 14786 | args |
| 14787 | ); |
sewardj | a5cbbdc | 2005-08-23 23:17:38 +0000 | [diff] [blame] | 14788 | /* execute the dirty call, dumping the result in val. */ |
| 14789 | stmt( IRStmt_Dirty(d) ); |
| 14790 | putIReg(4, R_EDX, unop(Iop_64HIto32, mkexpr(val))); |
| 14791 | putIReg(4, R_EAX, unop(Iop_64to32, mkexpr(val))); |
| 14792 | DIP("rdtsc\n"); |
| 14793 | break; |
sewardj | 4ed6429 | 2005-08-23 19:24:29 +0000 | [diff] [blame] | 14794 | } |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 14795 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 14796 | /* =-=-=-=-=-=-=-=-=- PUSH/POP Sreg =-=-=-=-=-=-=-=-=-= */ |
| 14797 | |
| 14798 | case 0xA1: /* POP %FS */ |
| 14799 | dis_pop_segreg( R_FS, sz ); break; |
| 14800 | case 0xA9: /* POP %GS */ |
| 14801 | dis_pop_segreg( R_GS, sz ); break; |
| 14802 | |
| 14803 | case 0xA0: /* PUSH %FS */ |
| 14804 | dis_push_segreg( R_FS, sz ); break; |
| 14805 | case 0xA8: /* PUSH %GS */ |
| 14806 | dis_push_segreg( R_GS, sz ); break; |
| 14807 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 14808 | /* =-=-=-=-=-=-=-=-=- SETcc Eb =-=-=-=-=-=-=-=-=-= */ |
| 14809 | case 0x90: |
| 14810 | case 0x91: |
| 14811 | case 0x92: /* set-Bb/set-NAEb (jump below) */ |
| 14812 | case 0x93: /* set-NBb/set-AEb (jump not below) */ |
| 14813 | case 0x94: /* set-Zb/set-Eb (jump zero) */ |
| 14814 | case 0x95: /* set-NZb/set-NEb (jump not zero) */ |
| 14815 | case 0x96: /* set-BEb/set-NAb (jump below or equal) */ |
| 14816 | case 0x97: /* set-NBEb/set-Ab (jump not below or equal) */ |
| 14817 | case 0x98: /* set-Sb (jump negative) */ |
| 14818 | case 0x99: /* set-Sb (jump not negative) */ |
| 14819 | case 0x9A: /* set-P (jump parity even) */ |
| 14820 | case 0x9B: /* set-NP (jump parity odd) */ |
| 14821 | case 0x9C: /* set-Lb/set-NGEb (jump less) */ |
| 14822 | case 0x9D: /* set-GEb/set-NLb (jump greater or equal) */ |
| 14823 | case 0x9E: /* set-LEb/set-NGb (jump less or equal) */ |
| 14824 | case 0x9F: /* set-Gb/set-NLEb (jump greater) */ |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14825 | t1 = newTemp(Ity_I8); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14826 | assign( t1, unop(Iop_1Uto8,mk_x86g_calculate_condition(opc-0x90)) ); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 14827 | modrm = getIByte(delta); |
| 14828 | if (epartIsReg(modrm)) { |
| 14829 | delta++; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14830 | putIReg(1, eregOfRM(modrm), mkexpr(t1)); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14831 | DIP("set%s %s\n", name_X86Condcode(opc-0x90), |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 14832 | nameIReg(1,eregOfRM(modrm))); |
| 14833 | } else { |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 14834 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 14835 | delta += alen; |
| 14836 | storeLE( mkexpr(addr), mkexpr(t1) ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14837 | DIP("set%s %s\n", name_X86Condcode(opc-0x90), dis_buf); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 14838 | } |
| 14839 | break; |
| 14840 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14841 | /* =-=-=-=-=-=-=-=-=- SHLD/SHRD -=-=-=-=-=-=-=-=-= */ |
| 14842 | |
| 14843 | case 0xA4: /* SHLDv imm8,Gv,Ev */ |
| 14844 | modrm = getIByte(delta); |
| 14845 | d32 = delta + lengthAMode(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 14846 | vex_sprintf(dis_buf, "$%d", getIByte(d32)); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14847 | delta = dis_SHLRD_Gv_Ev ( |
| 14848 | sorb, delta, modrm, sz, |
| 14849 | mkU8(getIByte(d32)), True, /* literal */ |
| 14850 | dis_buf, True ); |
| 14851 | break; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 14852 | case 0xA5: /* SHLDv %cl,Gv,Ev */ |
| 14853 | modrm = getIByte(delta); |
| 14854 | delta = dis_SHLRD_Gv_Ev ( |
| 14855 | sorb, delta, modrm, sz, |
| 14856 | getIReg(1,R_ECX), False, /* not literal */ |
| 14857 | "%cl", True ); |
| 14858 | break; |
| 14859 | |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 14860 | case 0xAC: /* SHRDv imm8,Gv,Ev */ |
| 14861 | modrm = getIByte(delta); |
| 14862 | d32 = delta + lengthAMode(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 14863 | vex_sprintf(dis_buf, "$%d", getIByte(d32)); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 14864 | delta = dis_SHLRD_Gv_Ev ( |
| 14865 | sorb, delta, modrm, sz, |
| 14866 | mkU8(getIByte(d32)), True, /* literal */ |
| 14867 | dis_buf, False ); |
| 14868 | break; |
sewardj | a511afc | 2004-07-29 22:26:03 +0000 | [diff] [blame] | 14869 | case 0xAD: /* SHRDv %cl,Gv,Ev */ |
| 14870 | modrm = getIByte(delta); |
| 14871 | delta = dis_SHLRD_Gv_Ev ( |
| 14872 | sorb, delta, modrm, sz, |
| 14873 | getIReg(1,R_ECX), False, /* not literal */ |
| 14874 | "%cl", False ); |
| 14875 | break; |
| 14876 | |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 14877 | /* =-=-=-=-=-=-=-=-=- SYSENTER -=-=-=-=-=-=-=-=-=-= */ |
| 14878 | |
| 14879 | case 0x34: |
| 14880 | /* Simple implementation needing a long explaination. |
| 14881 | |
| 14882 | sysenter is a kind of syscall entry. The key thing here |
| 14883 | is that the return address is not known -- that is |
| 14884 | something that is beyond Vex's knowledge. So this IR |
| 14885 | forces a return to the scheduler, which can do what it |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 14886 | likes to simulate the systenter, but it MUST set this |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 14887 | thread's guest_EIP field with the continuation address |
| 14888 | before resuming execution. If that doesn't happen, the |
| 14889 | thread will jump to address zero, which is probably |
| 14890 | fatal. |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 14891 | */ |
| 14892 | |
| 14893 | /* Note where we are, so we can back up the guest to this |
| 14894 | point if the syscall needs to be restarted. */ |
| 14895 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
| 14896 | mkU32(guest_EIP_curr_instr) ) ); |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 14897 | jmp_lit(Ijk_Sys_sysenter, 0/*bogus next EIP value*/); |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 14898 | dres.whatNext = Dis_StopHere; |
| 14899 | DIP("sysenter"); |
| 14900 | break; |
| 14901 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14902 | /* =-=-=-=-=-=-=-=-=- XADD -=-=-=-=-=-=-=-=-=-= */ |
| 14903 | |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 14904 | case 0xC0: { /* XADD Gb,Eb */ |
| 14905 | Bool decodeOK; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14906 | delta = dis_xadd_G_E ( sorb, pfx_lock, 1, delta, &decodeOK ); |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 14907 | if (!decodeOK) goto decode_failure; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 14908 | break; |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 14909 | } |
| 14910 | case 0xC1: { /* XADD Gv,Ev */ |
| 14911 | Bool decodeOK; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14912 | delta = dis_xadd_G_E ( sorb, pfx_lock, sz, delta, &decodeOK ); |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 14913 | if (!decodeOK) goto decode_failure; |
| 14914 | break; |
| 14915 | } |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 14916 | |
sewardj | f13f37b | 2004-12-08 17:01:23 +0000 | [diff] [blame] | 14917 | /* =-=-=-=-=-=-=-=-=- MMXery =-=-=-=-=-=-=-=-=-=-= */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14918 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 14919 | case 0x71: |
| 14920 | case 0x72: |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14921 | case 0x73: /* PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */ |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 14922 | |
| 14923 | case 0x6E: /* MOVD (src)ireg-or-mem, (dst)mmxreg */ |
| 14924 | case 0x7E: /* MOVD (src)mmxreg, (dst)ireg-or-mem */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14925 | case 0x7F: /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */ |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 14926 | case 0x6F: /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14927 | |
| 14928 | case 0xFC: |
| 14929 | case 0xFD: |
| 14930 | case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14931 | |
| 14932 | case 0xEC: |
| 14933 | case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14934 | |
| 14935 | case 0xDC: |
| 14936 | case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14937 | |
| 14938 | case 0xF8: |
| 14939 | case 0xF9: |
| 14940 | case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14941 | |
| 14942 | case 0xE8: |
| 14943 | case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14944 | |
| 14945 | case 0xD8: |
| 14946 | case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14947 | |
| 14948 | case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14949 | case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14950 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 14951 | case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14952 | |
| 14953 | case 0x74: |
| 14954 | case 0x75: |
| 14955 | case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14956 | |
| 14957 | case 0x64: |
| 14958 | case 0x65: |
| 14959 | case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14960 | |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 14961 | case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14962 | case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14963 | case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14964 | |
| 14965 | case 0x68: |
| 14966 | case 0x69: |
| 14967 | case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14968 | |
| 14969 | case 0x60: |
| 14970 | case 0x61: |
| 14971 | case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14972 | |
| 14973 | case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14974 | case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14975 | case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14976 | case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14977 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14978 | case 0xF1: /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 14979 | case 0xF2: |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14980 | case 0xF3: |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 14981 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14982 | case 0xD1: /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 14983 | case 0xD2: |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14984 | case 0xD3: |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 14985 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14986 | case 0xE1: /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 14987 | case 0xE2: |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14988 | { |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 14989 | Int delta0 = delta-1; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14990 | Bool decode_OK = False; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 14991 | |
| 14992 | /* If sz==2 this is SSE, and we assume sse idec has |
| 14993 | already spotted those cases by now. */ |
| 14994 | if (sz != 4) |
| 14995 | goto decode_failure; |
| 14996 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 14997 | delta = dis_MMX ( &decode_OK, sorb, sz, delta-1 ); |
| 14998 | if (!decode_OK) { |
| 14999 | delta = delta0; |
| 15000 | goto decode_failure; |
| 15001 | } |
| 15002 | break; |
| 15003 | } |
| 15004 | |
tom | e3aa016 | 2011-08-11 14:43:12 +0000 | [diff] [blame] | 15005 | case 0x0E: /* FEMMS */ |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15006 | case 0x77: /* EMMS */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15007 | if (sz != 4) |
| 15008 | goto decode_failure; |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 15009 | do_EMMS_preamble(); |
tom | e3aa016 | 2011-08-11 14:43:12 +0000 | [diff] [blame] | 15010 | DIP("{f}emms\n"); |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15011 | break; |
| 15012 | |
sewardj | b9dc243 | 2010-06-07 16:22:22 +0000 | [diff] [blame] | 15013 | /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */ |
| 15014 | case 0x01: /* 0F 01 /0 -- SGDT */ |
| 15015 | /* 0F 01 /1 -- SIDT */ |
| 15016 | { |
| 15017 | /* This is really revolting, but ... since each processor |
| 15018 | (core) only has one IDT and one GDT, just let the guest |
| 15019 | see it (pass-through semantics). I can't see any way to |
| 15020 | construct a faked-up value, so don't bother to try. */ |
| 15021 | modrm = getUChar(delta); |
| 15022 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 15023 | delta += alen; |
| 15024 | if (epartIsReg(modrm)) goto decode_failure; |
| 15025 | if (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1) |
| 15026 | goto decode_failure; |
| 15027 | switch (gregOfRM(modrm)) { |
| 15028 | case 0: DIP("sgdt %s\n", dis_buf); break; |
| 15029 | case 1: DIP("sidt %s\n", dis_buf); break; |
| 15030 | default: vassert(0); /*NOTREACHED*/ |
| 15031 | } |
| 15032 | |
| 15033 | IRDirty* d = unsafeIRDirty_0_N ( |
| 15034 | 0/*regparms*/, |
| 15035 | "x86g_dirtyhelper_SxDT", |
| 15036 | &x86g_dirtyhelper_SxDT, |
| 15037 | mkIRExprVec_2( mkexpr(addr), |
| 15038 | mkU32(gregOfRM(modrm)) ) |
| 15039 | ); |
| 15040 | /* declare we're writing memory */ |
| 15041 | d->mFx = Ifx_Write; |
| 15042 | d->mAddr = mkexpr(addr); |
| 15043 | d->mSize = 6; |
| 15044 | stmt( IRStmt_Dirty(d) ); |
| 15045 | break; |
| 15046 | } |
| 15047 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15048 | /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */ |
| 15049 | |
| 15050 | default: |
| 15051 | goto decode_failure; |
| 15052 | } /* switch (opc) for the 2-byte opcodes */ |
| 15053 | goto decode_success; |
| 15054 | } /* case 0x0F: of primary opcode */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15055 | |
| 15056 | /* ------------------------ ??? ------------------------ */ |
| 15057 | |
| 15058 | default: |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15059 | decode_failure: |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15060 | /* All decode failures end up here. */ |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 15061 | vex_printf("vex x86->IR: unhandled instruction bytes: " |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15062 | "0x%x 0x%x 0x%x 0x%x\n", |
| 15063 | (Int)getIByte(delta_start+0), |
| 15064 | (Int)getIByte(delta_start+1), |
| 15065 | (Int)getIByte(delta_start+2), |
| 15066 | (Int)getIByte(delta_start+3) ); |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 15067 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 15068 | /* Tell the dispatcher that this insn cannot be decoded, and so has |
| 15069 | not been executed, and (is currently) the next to be executed. |
| 15070 | EIP should be up-to-date since it made so at the start of each |
| 15071 | insn, but nevertheless be paranoid and update it again right |
| 15072 | now. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15073 | stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_curr_instr) ) ); |
| 15074 | jmp_lit(Ijk_NoDecode, guest_EIP_curr_instr); |
| 15075 | dres.whatNext = Dis_StopHere; |
| 15076 | dres.len = 0; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15077 | /* We also need to say that a CAS is not expected now, regardless |
| 15078 | of what it might have been set to at the start of the function, |
| 15079 | since the IR that we've emitted just above (to synthesis a |
| 15080 | SIGILL) does not involve any CAS, and presumably no other IR has |
| 15081 | been emitted for this (non-decoded) insn. */ |
| 15082 | *expect_CAS = False; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15083 | return dres; |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 15084 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15085 | } /* switch (opc) for the main (primary) opcode switch. */ |
| 15086 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15087 | decode_success: |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15088 | /* All decode successes end up here. */ |
| 15089 | DIP("\n"); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15090 | dres.len = delta - delta_start; |
| 15091 | return dres; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15092 | } |
| 15093 | |
| 15094 | #undef DIP |
| 15095 | #undef DIS |
| 15096 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15097 | |
| 15098 | /*------------------------------------------------------------*/ |
| 15099 | /*--- Top-level fn ---*/ |
| 15100 | /*------------------------------------------------------------*/ |
| 15101 | |
| 15102 | /* Disassemble a single instruction into IR. The instruction |
| 15103 | is located in host memory at &guest_code[delta]. */ |
| 15104 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15105 | DisResult disInstr_X86 ( IRSB* irsb_IN, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15106 | Bool put_IP, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 15107 | Bool (*resteerOkFn) ( void*, Addr64 ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15108 | Bool resteerCisOk, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 15109 | void* callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15110 | UChar* guest_code_IN, |
| 15111 | Long delta, |
| 15112 | Addr64 guest_IP, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 15113 | VexArch guest_arch, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15114 | VexArchInfo* archinfo, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15115 | VexAbiInfo* abiinfo, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15116 | Bool host_bigendian_IN ) |
| 15117 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15118 | Int i, x1, x2; |
| 15119 | Bool expect_CAS, has_CAS; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15120 | DisResult dres; |
| 15121 | |
| 15122 | /* Set globals (see top of this file) */ |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 15123 | vassert(guest_arch == VexArchX86); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15124 | guest_code = guest_code_IN; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15125 | irsb = irsb_IN; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15126 | host_is_bigendian = host_bigendian_IN; |
| 15127 | guest_EIP_curr_instr = (Addr32)guest_IP; |
| 15128 | guest_EIP_bbstart = (Addr32)toUInt(guest_IP - delta); |
| 15129 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15130 | x1 = irsb_IN->stmts_used; |
| 15131 | expect_CAS = False; |
| 15132 | dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn, |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15133 | resteerCisOk, |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 15134 | callback_opaque, |
| 15135 | delta, archinfo, abiinfo ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15136 | x2 = irsb_IN->stmts_used; |
| 15137 | vassert(x2 >= x1); |
| 15138 | |
| 15139 | /* See comment at the top of disInstr_X86_WRK for meaning of |
| 15140 | expect_CAS. Here, we (sanity-)check for the presence/absence of |
| 15141 | IRCAS as directed by the returned expect_CAS value. */ |
| 15142 | has_CAS = False; |
| 15143 | for (i = x1; i < x2; i++) { |
| 15144 | if (irsb_IN->stmts[i]->tag == Ist_CAS) |
| 15145 | has_CAS = True; |
| 15146 | } |
| 15147 | |
| 15148 | if (expect_CAS != has_CAS) { |
| 15149 | /* inconsistency detected. re-disassemble the instruction so as |
| 15150 | to generate a useful error message; then assert. */ |
| 15151 | vex_traceflags |= VEX_TRACE_FE; |
| 15152 | dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn, |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15153 | resteerCisOk, |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 15154 | callback_opaque, |
| 15155 | delta, archinfo, abiinfo ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15156 | for (i = x1; i < x2; i++) { |
| 15157 | vex_printf("\t\t"); |
| 15158 | ppIRStmt(irsb_IN->stmts[i]); |
| 15159 | vex_printf("\n"); |
| 15160 | } |
| 15161 | /* Failure of this assertion is serious and denotes a bug in |
| 15162 | disInstr. */ |
| 15163 | vpanic("disInstr_X86: inconsistency in LOCK prefix handling"); |
| 15164 | } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15165 | |
| 15166 | return dres; |
| 15167 | } |
| 15168 | |
| 15169 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15170 | /*--------------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 15171 | /*--- end guest_x86_toIR.c ---*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15172 | /*--------------------------------------------------------------------*/ |