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Chia-I Wue54854a2014-08-05 10:23:50 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef DEV_H
26#define DEV_H
27
Chia-I Wue09b5362014-08-07 09:25:14 +080028#include "intel.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080029#include "gpu.h"
Chia-I Wua2161db2014-08-15 16:34:34 +080030#include "obj.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080031
Chia-I Wue54854a2014-08-05 10:23:50 +080032struct intel_queue;
33struct intel_winsys;
34
35struct intel_dev_dbg_msg_filter {
36 XGL_INT msg_code;
37 XGL_DBG_MSG_FILTER filter;
38 bool triggered;
39
40 struct intel_dev_dbg_msg_filter *next;
41};
42
43struct intel_dev_dbg {
44 struct intel_base_dbg base;
45
Chia-I Wu069f30f2014-08-21 13:45:20 +080046 XGL_VALIDATION_LEVEL validation_level;
47 bool disable_pipeline_loads;
48 bool force_object_memory_reqs;
49 bool force_large_image_alignment;
50
Chia-I Wue54854a2014-08-05 10:23:50 +080051 struct intel_dev_dbg_msg_filter *filters;
52};
53
54struct intel_dev {
55 struct intel_base base;
56
57 struct intel_gpu *gpu;
58 struct intel_winsys *winsys;
Chia-I Wu0b784442014-08-25 22:54:16 +080059 struct intel_bo *cmd_scratch_bo;
60
Chia-I Wue54854a2014-08-05 10:23:50 +080061 struct intel_queue *queues[INTEL_GPU_ENGINE_COUNT];
62};
63
Chia-I Wue54854a2014-08-05 10:23:50 +080064static inline struct intel_dev *intel_dev(XGL_DEVICE dev)
65{
66 return (struct intel_dev *) dev;
67}
68
69static inline struct intel_dev_dbg *intel_dev_dbg(struct intel_dev *dev)
70{
71 return (struct intel_dev_dbg *) dev->base.dbg;
72}
73
Chia-I Wue54854a2014-08-05 10:23:50 +080074XGL_RESULT intel_dev_create(struct intel_gpu *gpu,
75 const XGL_DEVICE_CREATE_INFO *info,
76 struct intel_dev **dev_ret);
77void intel_dev_destroy(struct intel_dev *dev);
78
79void intel_dev_get_heap_props(const struct intel_dev *dev,
80 XGL_MEMORY_HEAP_PROPERTIES *props);
81
82XGL_RESULT intel_dev_add_msg_filter(struct intel_dev *dev,
83 XGL_INT msg_code,
84 XGL_DBG_MSG_FILTER filter);
85
86void intel_dev_remove_msg_filter(struct intel_dev *dev,
87 XGL_INT msg_code);
88
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080089void intel_dev_log(struct intel_dev *dev,
90 XGL_DBG_MSG_TYPE msg_type,
91 XGL_VALIDATION_LEVEL validation_level,
Chia-I Wuaabb3602014-08-19 14:18:23 +080092 struct intel_base *src_object,
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080093 XGL_SIZE location,
94 XGL_INT msg_code,
95 const char *format, ...);
96
Chia-I Wua207aba2014-08-05 15:13:37 +080097XGL_RESULT XGLAPI intelCreateDevice(
98 XGL_PHYSICAL_GPU gpu,
99 const XGL_DEVICE_CREATE_INFO* pCreateInfo,
100 XGL_DEVICE* pDevice);
101
102XGL_RESULT XGLAPI intelDestroyDevice(
103 XGL_DEVICE device);
104
105XGL_RESULT XGLAPI intelGetMemoryHeapCount(
106 XGL_DEVICE device,
107 XGL_UINT* pCount);
108
109XGL_RESULT XGLAPI intelGetMemoryHeapInfo(
110 XGL_DEVICE device,
111 XGL_UINT heapId,
112 XGL_MEMORY_HEAP_INFO_TYPE infoType,
113 XGL_SIZE* pDataSize,
114 XGL_VOID* pData);
115
Chia-I Wu49dbee82014-08-06 12:48:47 +0800116XGL_RESULT XGLAPI intelGetDeviceQueue(
117 XGL_DEVICE device,
118 XGL_QUEUE_TYPE queueType,
119 XGL_UINT queueIndex,
120 XGL_QUEUE* pQueue);
121
Chia-I Wu49dbee82014-08-06 12:48:47 +0800122XGL_RESULT XGLAPI intelDeviceWaitIdle(
123 XGL_DEVICE device);
124
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800125XGL_RESULT XGLAPI intelDbgSetValidationLevel(
126 XGL_DEVICE device,
127 XGL_VALIDATION_LEVEL validationLevel);
128
129XGL_RESULT XGLAPI intelDbgSetMessageFilter(
130 XGL_DEVICE device,
131 XGL_INT msgCode,
132 XGL_DBG_MSG_FILTER filter);
133
134XGL_RESULT XGLAPI intelDbgSetDeviceOption(
135 XGL_DEVICE device,
136 XGL_DBG_DEVICE_OPTION dbgOption,
137 XGL_SIZE dataSize,
138 const XGL_VOID* pData);
139
Chia-I Wue54854a2014-08-05 10:23:50 +0800140#endif /* DEV_H */