blob: 74e187553e5ca36fd300f6e7e208b79b2ef56bcb [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
40
Chia-I Wu958d1b72014-08-21 11:28:11 +080041struct intel_cmd_reloc;
42
Chia-I Wub2755562014-08-20 13:38:52 +080043/*
44 * States bounded to the command buffer. We want to write states directly to
45 * the command buffer when possible, and reduce this struct.
46 */
47struct intel_cmd_bind {
48 struct {
49 const struct intel_pipeline *graphics;
50 const struct intel_pipeline *compute;
51 const struct intel_pipeline_delta *graphics_delta;
52 const struct intel_pipeline_delta *compute_delta;
53 } pipeline;
54
55 struct {
56 const struct intel_viewport_state *viewport;
57 const struct intel_raster_state *raster;
58 const struct intel_msaa_state *msaa;
59 const struct intel_blend_state *blend;
60 const struct intel_ds_state *ds;
61 } state;
62
63 struct {
64 const struct intel_dset *graphics;
65 XGL_UINT graphics_offset;
66 const struct intel_dset *compute;
67 XGL_UINT compute_offset;
68 } dset;
69
70 struct {
71 struct intel_mem_view graphics;
72 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +080073 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +080074
75 struct {
76 const struct intel_mem *mem;
77 XGL_GPU_SIZE offset;
78 XGL_INDEX_TYPE type;
79 } index;
80
81 struct {
82 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
83 XGL_UINT rt_count;
84
85 const struct intel_ds_view *ds;
86 } att;
87};
Chia-I Wu09142132014-08-11 15:42:55 +080088
Chia-I Wue24c3292014-08-21 14:05:23 +080089struct intel_cmd_writer {
90 struct intel_bo *bo;
91 void *ptr_opaque;
92
93 /* in DWords */
94 XGL_UINT size;
95 XGL_UINT used;
96};
97
Chia-I Wu730e5362014-08-19 12:15:09 +080098struct intel_cmd {
99 struct intel_obj obj;
100
101 struct intel_dev *dev;
Chia-I Wu63883292014-08-25 13:50:26 +0800102 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800103
Chia-I Wu343b1372014-08-20 16:39:20 +0800104 struct intel_cmd_reloc *relocs;
105 XGL_UINT reloc_count;
106
Chia-I Wu730e5362014-08-19 12:15:09 +0800107 XGL_FLAGS flags;
108
Chia-I Wue24c3292014-08-21 14:05:23 +0800109 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800110 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800111 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800112
Chia-I Wu343b1372014-08-20 16:39:20 +0800113 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800114 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800115
116 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800117};
118
119static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
120{
121 return (struct intel_cmd *) cmd;
122}
123
124static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
125{
126 return (struct intel_cmd *) obj;
127}
128
129XGL_RESULT intel_cmd_create(struct intel_dev *dev,
130 const XGL_CMD_BUFFER_CREATE_INFO *info,
131 struct intel_cmd **cmd_ret);
132void intel_cmd_destroy(struct intel_cmd *cmd);
133
134XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
135XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
136
Chia-I Wue24c3292014-08-21 14:05:23 +0800137static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
138 XGL_GPU_SIZE *used)
139{
140 const struct intel_cmd_writer *writer = &cmd->batch;
141
142 if (used)
143 *used = sizeof(uint32_t) * writer->used;
144
145 return writer->bo;
146}
147
Chia-I Wu09142132014-08-11 15:42:55 +0800148XGL_RESULT XGLAPI intelCreateCommandBuffer(
149 XGL_DEVICE device,
150 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
151 XGL_CMD_BUFFER* pCmdBuffer);
152
153XGL_RESULT XGLAPI intelBeginCommandBuffer(
154 XGL_CMD_BUFFER cmdBuffer,
155 XGL_FLAGS flags);
156
157XGL_RESULT XGLAPI intelEndCommandBuffer(
158 XGL_CMD_BUFFER cmdBuffer);
159
160XGL_RESULT XGLAPI intelResetCommandBuffer(
161 XGL_CMD_BUFFER cmdBuffer);
162
163XGL_VOID XGLAPI intelCmdBindPipeline(
164 XGL_CMD_BUFFER cmdBuffer,
165 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
166 XGL_PIPELINE pipeline);
167
168XGL_VOID XGLAPI intelCmdBindPipelineDelta(
169 XGL_CMD_BUFFER cmdBuffer,
170 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
171 XGL_PIPELINE_DELTA delta);
172
173XGL_VOID XGLAPI intelCmdBindStateObject(
174 XGL_CMD_BUFFER cmdBuffer,
175 XGL_STATE_BIND_POINT stateBindPoint,
176 XGL_STATE_OBJECT state);
177
178XGL_VOID XGLAPI intelCmdBindDescriptorSet(
179 XGL_CMD_BUFFER cmdBuffer,
180 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
181 XGL_UINT index,
182 XGL_DESCRIPTOR_SET descriptorSet,
183 XGL_UINT slotOffset);
184
185XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
186 XGL_CMD_BUFFER cmdBuffer,
187 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
188 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
189
190XGL_VOID XGLAPI intelCmdBindIndexData(
191 XGL_CMD_BUFFER cmdBuffer,
192 XGL_GPU_MEMORY mem,
193 XGL_GPU_SIZE offset,
194 XGL_INDEX_TYPE indexType);
195
196XGL_VOID XGLAPI intelCmdBindAttachments(
197 XGL_CMD_BUFFER cmdBuffer,
198 XGL_UINT colorAttachmentCount,
199 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
200 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
201
202XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
203 XGL_CMD_BUFFER cmdBuffer,
204 XGL_UINT transitionCount,
205 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
206
207XGL_VOID XGLAPI intelCmdPrepareImages(
208 XGL_CMD_BUFFER cmdBuffer,
209 XGL_UINT transitionCount,
210 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
211
212XGL_VOID XGLAPI intelCmdDraw(
213 XGL_CMD_BUFFER cmdBuffer,
214 XGL_UINT firstVertex,
215 XGL_UINT vertexCount,
216 XGL_UINT firstInstance,
217 XGL_UINT instanceCount);
218
219XGL_VOID XGLAPI intelCmdDrawIndexed(
220 XGL_CMD_BUFFER cmdBuffer,
221 XGL_UINT firstIndex,
222 XGL_UINT indexCount,
223 XGL_INT vertexOffset,
224 XGL_UINT firstInstance,
225 XGL_UINT instanceCount);
226
227XGL_VOID XGLAPI intelCmdDrawIndirect(
228 XGL_CMD_BUFFER cmdBuffer,
229 XGL_GPU_MEMORY mem,
230 XGL_GPU_SIZE offset,
231 XGL_UINT32 count,
232 XGL_UINT32 stride);
233
234XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
235 XGL_CMD_BUFFER cmdBuffer,
236 XGL_GPU_MEMORY mem,
237 XGL_GPU_SIZE offset,
238 XGL_UINT32 count,
239 XGL_UINT32 stride);
240
241XGL_VOID XGLAPI intelCmdDispatch(
242 XGL_CMD_BUFFER cmdBuffer,
243 XGL_UINT x,
244 XGL_UINT y,
245 XGL_UINT z);
246
247XGL_VOID XGLAPI intelCmdDispatchIndirect(
248 XGL_CMD_BUFFER cmdBuffer,
249 XGL_GPU_MEMORY mem,
250 XGL_GPU_SIZE offset);
251
252XGL_VOID XGLAPI intelCmdCopyMemory(
253 XGL_CMD_BUFFER cmdBuffer,
254 XGL_GPU_MEMORY srcMem,
255 XGL_GPU_MEMORY destMem,
256 XGL_UINT regionCount,
257 const XGL_MEMORY_COPY* pRegions);
258
259XGL_VOID XGLAPI intelCmdCopyImage(
260 XGL_CMD_BUFFER cmdBuffer,
261 XGL_IMAGE srcImage,
262 XGL_IMAGE destImage,
263 XGL_UINT regionCount,
264 const XGL_IMAGE_COPY* pRegions);
265
266XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
267 XGL_CMD_BUFFER cmdBuffer,
268 XGL_GPU_MEMORY srcMem,
269 XGL_IMAGE destImage,
270 XGL_UINT regionCount,
271 const XGL_MEMORY_IMAGE_COPY* pRegions);
272
273XGL_VOID XGLAPI intelCmdCopyImageToMemory(
274 XGL_CMD_BUFFER cmdBuffer,
275 XGL_IMAGE srcImage,
276 XGL_GPU_MEMORY destMem,
277 XGL_UINT regionCount,
278 const XGL_MEMORY_IMAGE_COPY* pRegions);
279
280XGL_VOID XGLAPI intelCmdCloneImageData(
281 XGL_CMD_BUFFER cmdBuffer,
282 XGL_IMAGE srcImage,
283 XGL_IMAGE_STATE srcImageState,
284 XGL_IMAGE destImage,
285 XGL_IMAGE_STATE destImageState);
286
287XGL_VOID XGLAPI intelCmdUpdateMemory(
288 XGL_CMD_BUFFER cmdBuffer,
289 XGL_GPU_MEMORY destMem,
290 XGL_GPU_SIZE destOffset,
291 XGL_GPU_SIZE dataSize,
292 const XGL_UINT32* pData);
293
294XGL_VOID XGLAPI intelCmdFillMemory(
295 XGL_CMD_BUFFER cmdBuffer,
296 XGL_GPU_MEMORY destMem,
297 XGL_GPU_SIZE destOffset,
298 XGL_GPU_SIZE fillSize,
299 XGL_UINT32 data);
300
301XGL_VOID XGLAPI intelCmdClearColorImage(
302 XGL_CMD_BUFFER cmdBuffer,
303 XGL_IMAGE image,
304 const XGL_FLOAT color[4],
305 XGL_UINT rangeCount,
306 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
307
308XGL_VOID XGLAPI intelCmdClearColorImageRaw(
309 XGL_CMD_BUFFER cmdBuffer,
310 XGL_IMAGE image,
311 const XGL_UINT32 color[4],
312 XGL_UINT rangeCount,
313 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
314
315XGL_VOID XGLAPI intelCmdClearDepthStencil(
316 XGL_CMD_BUFFER cmdBuffer,
317 XGL_IMAGE image,
318 XGL_FLOAT depth,
319 XGL_UINT32 stencil,
320 XGL_UINT rangeCount,
321 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
322
323XGL_VOID XGLAPI intelCmdResolveImage(
324 XGL_CMD_BUFFER cmdBuffer,
325 XGL_IMAGE srcImage,
326 XGL_IMAGE destImage,
327 XGL_UINT rectCount,
328 const XGL_IMAGE_RESOLVE* pRects);
329
330XGL_VOID XGLAPI intelCmdSetEvent(
331 XGL_CMD_BUFFER cmdBuffer,
332 XGL_EVENT event);
333
334XGL_VOID XGLAPI intelCmdResetEvent(
335 XGL_CMD_BUFFER cmdBuffer,
336 XGL_EVENT event);
337
338XGL_VOID XGLAPI intelCmdMemoryAtomic(
339 XGL_CMD_BUFFER cmdBuffer,
340 XGL_GPU_MEMORY destMem,
341 XGL_GPU_SIZE destOffset,
342 XGL_UINT64 srcData,
343 XGL_ATOMIC_OP atomicOp);
344
345XGL_VOID XGLAPI intelCmdBeginQuery(
346 XGL_CMD_BUFFER cmdBuffer,
347 XGL_QUERY_POOL queryPool,
348 XGL_UINT slot,
349 XGL_FLAGS flags);
350
351XGL_VOID XGLAPI intelCmdEndQuery(
352 XGL_CMD_BUFFER cmdBuffer,
353 XGL_QUERY_POOL queryPool,
354 XGL_UINT slot);
355
356XGL_VOID XGLAPI intelCmdResetQueryPool(
357 XGL_CMD_BUFFER cmdBuffer,
358 XGL_QUERY_POOL queryPool,
359 XGL_UINT startQuery,
360 XGL_UINT queryCount);
361
362XGL_VOID XGLAPI intelCmdWriteTimestamp(
363 XGL_CMD_BUFFER cmdBuffer,
364 XGL_TIMESTAMP_TYPE timestampType,
365 XGL_GPU_MEMORY destMem,
366 XGL_GPU_SIZE destOffset);
367
368XGL_VOID XGLAPI intelCmdInitAtomicCounters(
369 XGL_CMD_BUFFER cmdBuffer,
370 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
371 XGL_UINT startCounter,
372 XGL_UINT counterCount,
373 const XGL_UINT32* pData);
374
375XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
376 XGL_CMD_BUFFER cmdBuffer,
377 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
378 XGL_UINT startCounter,
379 XGL_UINT counterCount,
380 XGL_GPU_MEMORY srcMem,
381 XGL_GPU_SIZE srcOffset);
382
383XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
384 XGL_CMD_BUFFER cmdBuffer,
385 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
386 XGL_UINT startCounter,
387 XGL_UINT counterCount,
388 XGL_GPU_MEMORY destMem,
389 XGL_GPU_SIZE destOffset);
390
391XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
392 XGL_CMD_BUFFER cmdBuffer,
393 const XGL_CHAR* pMarker);
394
395XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
396 XGL_CMD_BUFFER cmdBuffer);
397
398#endif /* CMD_H */