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Chia-I Wub2755562014-08-20 13:38:52 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu9f039862014-08-20 15:39:56 +080025#include "genhw/genhw.h"
Chia-I Wub2755562014-08-20 13:38:52 +080026#include "dset.h"
Chia-I Wu7fae4e32014-08-21 11:39:44 +080027#include "img.h"
Chia-I Wub2755562014-08-20 13:38:52 +080028#include "mem.h"
Chia-I Wu018a3962014-08-21 10:37:52 +080029#include "pipeline.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "state.h"
31#include "view.h"
32#include "cmd_priv.h"
33
Chia-I Wu59c097e2014-08-21 10:51:07 +080034static void gen6_3DPRIMITIVE(struct intel_cmd *cmd,
Chia-I Wu254db422014-08-21 11:54:29 +080035 int prim_type, bool indexed,
Chia-I Wu59c097e2014-08-21 10:51:07 +080036 uint32_t vertex_count,
37 uint32_t vertex_start,
38 uint32_t instance_count,
39 uint32_t instance_start,
40 uint32_t vertex_base)
41{
42 const uint8_t cmd_len = 6;
43 uint32_t dw0;
44
45 CMD_ASSERT(cmd, 6, 6);
46
Chia-I Wub0b9f692014-08-21 11:33:29 +080047 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) |
Chia-I Wu254db422014-08-21 11:54:29 +080048 prim_type << GEN6_3DPRIM_DW0_TYPE__SHIFT |
Chia-I Wu59c097e2014-08-21 10:51:07 +080049 (cmd_len - 2);
50
51 if (indexed)
52 dw0 |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
53
Chia-I Wue24c3292014-08-21 14:05:23 +080054 cmd_batch_reserve(cmd, cmd_len);
55 cmd_batch_write(cmd, dw0);
56 cmd_batch_write(cmd, vertex_count);
57 cmd_batch_write(cmd, vertex_start);
58 cmd_batch_write(cmd, instance_count);
59 cmd_batch_write(cmd, instance_start);
60 cmd_batch_write(cmd, vertex_base);
Chia-I Wu59c097e2014-08-21 10:51:07 +080061}
62
63static void gen7_3DPRIMITIVE(struct intel_cmd *cmd,
Chia-I Wu254db422014-08-21 11:54:29 +080064 int prim_type, bool indexed,
Chia-I Wu59c097e2014-08-21 10:51:07 +080065 uint32_t vertex_count,
66 uint32_t vertex_start,
67 uint32_t instance_count,
68 uint32_t instance_start,
69 uint32_t vertex_base)
70{
71 const uint8_t cmd_len = 7;
72 uint32_t dw0, dw1;
73
74 CMD_ASSERT(cmd, 7, 7.5);
75
Chia-I Wub0b9f692014-08-21 11:33:29 +080076 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) | (cmd_len - 2);
Chia-I Wu254db422014-08-21 11:54:29 +080077 dw1 = prim_type << GEN7_3DPRIM_DW1_TYPE__SHIFT;
Chia-I Wu59c097e2014-08-21 10:51:07 +080078
79 if (indexed)
80 dw1 |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
81
Chia-I Wue24c3292014-08-21 14:05:23 +080082 cmd_batch_reserve(cmd, cmd_len);
83 cmd_batch_write(cmd, dw0);
84 cmd_batch_write(cmd, dw1);
85 cmd_batch_write(cmd, vertex_count);
86 cmd_batch_write(cmd, vertex_start);
87 cmd_batch_write(cmd, instance_count);
88 cmd_batch_write(cmd, instance_start);
89 cmd_batch_write(cmd, vertex_base);
Chia-I Wu59c097e2014-08-21 10:51:07 +080090}
91
Chia-I Wu254db422014-08-21 11:54:29 +080092static bool gen6_can_primitive_restart(const struct intel_cmd *cmd)
93{
94 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
95 bool supported;
96
97 CMD_ASSERT(cmd, 6, 7.5);
98
99 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
100 return (p->prim_type != GEN6_3DPRIM_RECTLIST);
101
102 switch (p->prim_type) {
103 case GEN6_3DPRIM_POINTLIST:
104 case GEN6_3DPRIM_LINELIST:
105 case GEN6_3DPRIM_LINESTRIP:
106 case GEN6_3DPRIM_TRILIST:
107 case GEN6_3DPRIM_TRISTRIP:
108 supported = true;
109 break;
110 default:
111 supported = false;
112 break;
113 }
114
115 if (!supported)
116 return false;
117
118 switch (cmd->bind.index.type) {
119 case XGL_INDEX_8:
120 supported = (p->primitive_restart_index != 0xffu);
121 break;
122 case XGL_INDEX_16:
123 supported = (p->primitive_restart_index != 0xffffu);
124 break;
125 case XGL_INDEX_32:
126 supported = (p->primitive_restart_index != 0xffffffffu);
127 break;
128 default:
129 supported = false;
130 break;
131 }
132
133 return supported;
134}
135
Chia-I Wu59c097e2014-08-21 10:51:07 +0800136static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
Chia-I Wu958d1b72014-08-21 11:28:11 +0800137 const struct intel_mem *mem,
Chia-I Wu59c097e2014-08-21 10:51:07 +0800138 XGL_GPU_SIZE offset,
139 XGL_INDEX_TYPE type,
140 bool enable_cut_index)
141{
142 const uint8_t cmd_len = 3;
143 uint32_t dw0, end_offset;
144 unsigned offset_align;
145
146 CMD_ASSERT(cmd, 6, 7.5);
147
Chia-I Wub0b9f692014-08-21 11:33:29 +0800148 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800149
150 /* the bit is moved to 3DSTATE_VF */
151 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
152 assert(!enable_cut_index);
153 if (enable_cut_index)
154 dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
155
156 switch (type) {
157 case XGL_INDEX_8:
158 dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
159 offset_align = 1;
160 break;
161 case XGL_INDEX_16:
162 dw0 |= GEN6_IB_DW0_FORMAT_WORD;
163 offset_align = 2;
164 break;
165 case XGL_INDEX_32:
166 dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
167 offset_align = 4;
168 break;
169 default:
170 cmd->result = XGL_ERROR_INVALID_VALUE;
171 return;
172 break;
173 }
174
175 if (offset % offset_align) {
176 cmd->result = XGL_ERROR_INVALID_VALUE;
177 return;
178 }
179
180 /* aligned and inclusive */
181 end_offset = mem->size - (mem->size % offset_align) - 1;
182
Chia-I Wue24c3292014-08-21 14:05:23 +0800183 cmd_batch_reserve(cmd, cmd_len);
184 cmd_batch_write(cmd, dw0);
185 cmd_batch_reloc(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0);
186 cmd_batch_reloc(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800187}
188
Chia-I Wu254db422014-08-21 11:54:29 +0800189static inline void
190gen75_3DSTATE_VF(struct intel_cmd *cmd,
191 bool enable_cut_index,
192 uint32_t cut_index)
193{
194 const uint8_t cmd_len = 2;
195 uint32_t dw0;
196
197 CMD_ASSERT(cmd, 7.5, 7.5);
198
199 dw0 = GEN_RENDER_CMD(3D, GEN75, 3DSTATE_VF) | (cmd_len - 2);
200 if (enable_cut_index)
201 dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE;
202
Chia-I Wue24c3292014-08-21 14:05:23 +0800203 cmd_batch_reserve(cmd, cmd_len);
204 cmd_batch_write(cmd, dw0);
205 cmd_batch_write(cmd, cut_index);
Chia-I Wu254db422014-08-21 11:54:29 +0800206}
207
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800208static void gen6_3DSTATE_DEPTH_BUFFER(struct intel_cmd *cmd,
209 const struct intel_ds_view *view)
210{
211 const uint8_t cmd_len = 7;
212 uint32_t dw0;
213
214 CMD_ASSERT(cmd, 6, 7.5);
215
216 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
217 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_DEPTH_BUFFER) :
218 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_DEPTH_BUFFER);
219 dw0 |= (cmd_len - 2);
220
Chia-I Wue24c3292014-08-21 14:05:23 +0800221 cmd_batch_reserve(cmd, cmd_len);
222 cmd_batch_write(cmd, dw0);
223 cmd_batch_write(cmd, view->cmd[0]);
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600224 if (view->img) {
225 cmd_batch_reloc(cmd, view->cmd[1], view->img->obj.mem,
226 INTEL_DOMAIN_RENDER,
227 INTEL_DOMAIN_RENDER);
228 } else {
229 cmd_batch_write(cmd, 0);
230 }
Chia-I Wue24c3292014-08-21 14:05:23 +0800231 cmd_batch_write(cmd, view->cmd[2]);
232 cmd_batch_write(cmd, view->cmd[3]);
233 cmd_batch_write(cmd, view->cmd[4]);
234 cmd_batch_write(cmd, view->cmd[5]);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800235}
236
237static void gen6_3DSTATE_STENCIL_BUFFER(struct intel_cmd *cmd,
238 const struct intel_ds_view *view)
239{
240 const uint8_t cmd_len = 3;
241 uint32_t dw0;
242
243 CMD_ASSERT(cmd, 6, 7.5);
244
245 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
246 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_STENCIL_BUFFER) :
247 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_STENCIL_BUFFER);
248 dw0 |= (cmd_len - 2);
249
Chia-I Wue24c3292014-08-21 14:05:23 +0800250 cmd_batch_reserve(cmd, cmd_len);
251 cmd_batch_write(cmd, dw0);
252 cmd_batch_write(cmd, view->cmd[6]);
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600253 if (view->img) {
254 cmd_batch_reloc(cmd, view->cmd[7], view->img->obj.mem,
255 INTEL_DOMAIN_RENDER,
256 INTEL_DOMAIN_RENDER);
257 } else {
258 cmd_batch_write(cmd, 0);
259 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800260}
261
262static void gen6_3DSTATE_HIER_DEPTH_BUFFER(struct intel_cmd *cmd,
263 const struct intel_ds_view *view)
264{
265 const uint8_t cmd_len = 3;
266 uint32_t dw0;
267
268 CMD_ASSERT(cmd, 6, 7.5);
269
270 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
271 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_HIER_DEPTH_BUFFER) :
272 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_HIER_DEPTH_BUFFER);
273 dw0 |= (cmd_len - 2);
274
Chia-I Wue24c3292014-08-21 14:05:23 +0800275 cmd_batch_reserve(cmd, cmd_len);
276 cmd_batch_write(cmd, dw0);
277 cmd_batch_write(cmd, view->cmd[8]);
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600278 if (view->img) {
279 cmd_batch_reloc(cmd, view->cmd[9], view->img->obj.mem,
280 INTEL_DOMAIN_RENDER,
281 INTEL_DOMAIN_RENDER);
282 } else {
283 cmd_batch_write(cmd, 0);
284 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800285}
286
Chia-I Wu302742d2014-08-22 10:28:29 +0800287static void gen6_3DSTATE_CC_STATE_POINTERS(struct intel_cmd *cmd,
288 XGL_UINT blend_pos,
289 XGL_UINT ds_pos,
290 XGL_UINT cc_pos)
291{
292 const uint8_t cmd_len = 4;
293 uint32_t dw0;
294
295 CMD_ASSERT(cmd, 6, 6);
296
297 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_CC_STATE_POINTERS) |
298 (cmd_len - 2);
299
300 cmd_batch_reserve(cmd, cmd_len);
301 cmd_batch_write(cmd, dw0);
302 cmd_batch_write(cmd, (blend_pos << 2) | 1);
303 cmd_batch_write(cmd, (ds_pos << 2) | 1);
304 cmd_batch_write(cmd, (cc_pos << 2) | 1);
305}
306
Chia-I Wu1744cca2014-08-22 11:10:17 +0800307static void gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct intel_cmd *cmd,
308 XGL_UINT clip_pos,
309 XGL_UINT sf_pos,
310 XGL_UINT cc_pos)
311{
312 const uint8_t cmd_len = 4;
313 uint32_t dw0;
314
315 CMD_ASSERT(cmd, 6, 6);
316
317 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_VIEWPORT_STATE_POINTERS) |
318 GEN6_PTR_VP_DW0_CLIP_CHANGED |
319 GEN6_PTR_VP_DW0_SF_CHANGED |
320 GEN6_PTR_VP_DW0_CC_CHANGED |
321 (cmd_len - 2);
322
323 cmd_batch_reserve(cmd, cmd_len);
324 cmd_batch_write(cmd, dw0);
325 cmd_batch_write(cmd, clip_pos << 2);
326 cmd_batch_write(cmd, sf_pos << 2);
327 cmd_batch_write(cmd, cc_pos << 2);
328}
329
330static void gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct intel_cmd *cmd,
331 XGL_UINT scissor_pos)
332{
333 const uint8_t cmd_len = 2;
334 uint32_t dw0;
335
336 CMD_ASSERT(cmd, 6, 6);
337
338 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_SCISSOR_STATE_POINTERS) |
339 (cmd_len - 2);
340
341 cmd_batch_reserve(cmd, cmd_len);
342 cmd_batch_write(cmd, dw0);
343 cmd_batch_write(cmd, scissor_pos << 2);
344}
345
Chia-I Wu302742d2014-08-22 10:28:29 +0800346static void gen7_3dstate_pointer(struct intel_cmd *cmd,
347 int subop, XGL_UINT pos)
348{
349 const uint8_t cmd_len = 2;
350 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
351 GEN6_RENDER_SUBTYPE_3D |
352 subop | (cmd_len - 2);
353
354 cmd_batch_reserve(cmd, cmd_len);
355 cmd_batch_write(cmd, dw0);
356 cmd_batch_write(cmd, pos << 2);
357}
358
359static XGL_UINT gen6_BLEND_STATE(struct intel_cmd *cmd,
360 const struct intel_blend_state *state)
361{
362 const uint8_t cmd_align = GEN6_ALIGNMENT_BLEND_STATE;
363 const uint8_t cmd_len = XGL_MAX_COLOR_ATTACHMENTS * 2;
364
365 CMD_ASSERT(cmd, 6, 7.5);
366 STATIC_ASSERT(ARRAY_SIZE(state->cmd) >= cmd_len);
367
368 return cmd_state_copy(cmd, state->cmd, cmd_len, cmd_align);
369}
370
371static XGL_UINT gen6_DEPTH_STENCIL_STATE(struct intel_cmd *cmd,
372 const struct intel_ds_state *state)
373{
374 const uint8_t cmd_align = GEN6_ALIGNMENT_DEPTH_STENCIL_STATE;
375 const uint8_t cmd_len = 3;
376
377 CMD_ASSERT(cmd, 6, 7.5);
378 STATIC_ASSERT(ARRAY_SIZE(state->cmd) >= cmd_len);
379
380 return cmd_state_copy(cmd, state->cmd, cmd_len, cmd_align);
381}
382
383static XGL_UINT gen6_COLOR_CALC_STATE(struct intel_cmd *cmd,
384 uint32_t stencil_ref,
385 const uint32_t blend_color[4])
386{
387 const uint8_t cmd_align = GEN6_ALIGNMENT_COLOR_CALC_STATE;
388 const uint8_t cmd_len = 6;
389 XGL_UINT pos;
390 uint32_t *dw;
391
392 CMD_ASSERT(cmd, 6, 7.5);
393
394 dw = cmd_state_reserve(cmd, cmd_len, cmd_align, &pos);
395 dw[0] = stencil_ref;
396 dw[1] = 0;
397 dw[2] = blend_color[0];
398 dw[3] = blend_color[1];
399 dw[4] = blend_color[2];
400 dw[5] = blend_color[3];
401 cmd_state_advance(cmd, cmd_len);
402
403 return pos;
404}
405
406static void gen6_cc_states(struct intel_cmd *cmd)
407{
408 const struct intel_blend_state *blend = cmd->bind.state.blend;
409 const struct intel_ds_state *ds = cmd->bind.state.ds;
410 XGL_UINT blend_pos, ds_pos, cc_pos;
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800411 uint32_t stencil_ref;
412 uint32_t blend_color[4];
Chia-I Wu302742d2014-08-22 10:28:29 +0800413
414 CMD_ASSERT(cmd, 6, 6);
415
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800416 if (blend) {
417 blend_pos = gen6_BLEND_STATE(cmd, blend);
418 memcpy(blend_color, blend->cmd_blend_color, sizeof(blend_color));
419 } else {
420 blend_pos = 0;
421 memset(blend_color, 0, sizeof(blend_color));
422 }
423
424 if (ds) {
425 ds_pos = gen6_DEPTH_STENCIL_STATE(cmd, ds);
426 stencil_ref = ds->cmd_stencil_ref;
427 } else {
428 ds_pos = 0;
429 stencil_ref = 0;
430 }
431
432 cc_pos = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color);
Chia-I Wu302742d2014-08-22 10:28:29 +0800433
434 gen6_3DSTATE_CC_STATE_POINTERS(cmd, blend_pos, ds_pos, cc_pos);
435}
436
Chia-I Wu1744cca2014-08-22 11:10:17 +0800437static void gen6_viewport_states(struct intel_cmd *cmd)
438{
439 const struct intel_viewport_state *viewport = cmd->bind.state.viewport;
440 XGL_UINT pos;
441
442 if (!viewport)
443 return;
444
445 pos = cmd_state_copy(cmd, viewport->cmd, viewport->cmd_len,
446 viewport->cmd_align);
447
448 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(cmd,
449 pos + viewport->cmd_clip_offset,
450 pos,
451 pos + viewport->cmd_cc_offset);
452
453 pos = (viewport->scissor_enable) ?
454 pos + viewport->cmd_scissor_rect_offset : 0;
455
456 gen6_3DSTATE_SCISSOR_STATE_POINTERS(cmd, pos);
457}
458
Chia-I Wu302742d2014-08-22 10:28:29 +0800459static void gen7_cc_states(struct intel_cmd *cmd)
460{
461 const struct intel_blend_state *blend = cmd->bind.state.blend;
462 const struct intel_ds_state *ds = cmd->bind.state.ds;
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800463 uint32_t stencil_ref;
464 uint32_t blend_color[4];
Chia-I Wu302742d2014-08-22 10:28:29 +0800465 XGL_UINT pos;
466
467 CMD_ASSERT(cmd, 7, 7.5);
468
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800469 if (!blend && !ds)
470 return;
Chia-I Wu302742d2014-08-22 10:28:29 +0800471
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800472 if (blend) {
473 pos = gen6_BLEND_STATE(cmd, blend);
474 gen7_3dstate_pointer(cmd,
475 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS, pos);
Chia-I Wu302742d2014-08-22 10:28:29 +0800476
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800477 memcpy(blend_color, blend->cmd_blend_color, sizeof(blend_color));
478 } else {
479 memset(blend_color, 0, sizeof(blend_color));
480 }
481
482 if (ds) {
483 pos = gen6_DEPTH_STENCIL_STATE(cmd, ds);
484 gen7_3dstate_pointer(cmd,
485 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, pos);
486 } else {
487 stencil_ref = 0;
488 }
489
490 pos = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color);
Chia-I Wu302742d2014-08-22 10:28:29 +0800491 gen7_3dstate_pointer(cmd,
492 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, pos);
493}
494
Chia-I Wu1744cca2014-08-22 11:10:17 +0800495static void gen7_viewport_states(struct intel_cmd *cmd)
496{
497 const struct intel_viewport_state *viewport = cmd->bind.state.viewport;
498 XGL_UINT pos;
499
500 if (!viewport)
501 return;
502
503 pos = cmd_state_copy(cmd, viewport->cmd, viewport->cmd_len,
504 viewport->cmd_align);
505
506 gen7_3dstate_pointer(cmd,
507 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, pos);
508 gen7_3dstate_pointer(cmd,
509 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
510 pos + viewport->cmd_cc_offset);
511 if (viewport->scissor_enable) {
512 gen7_3dstate_pointer(cmd,
513 GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS,
514 pos + viewport->cmd_scissor_rect_offset);
515 }
516}
517
Chia-I Wu52500102014-08-22 00:46:04 +0800518static void emit_bounded_states(struct intel_cmd *cmd)
519{
520 const struct intel_msaa_state *msaa = cmd->bind.state.msaa;
521
522 /* TODO more states */
523
Chia-I Wu1744cca2014-08-22 11:10:17 +0800524 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu302742d2014-08-22 10:28:29 +0800525 gen7_cc_states(cmd);
Chia-I Wu1744cca2014-08-22 11:10:17 +0800526 gen7_viewport_states(cmd);
527 } else {
Chia-I Wu302742d2014-08-22 10:28:29 +0800528 gen6_cc_states(cmd);
Chia-I Wu1744cca2014-08-22 11:10:17 +0800529 gen6_viewport_states(cmd);
530 }
Chia-I Wu302742d2014-08-22 10:28:29 +0800531
Chia-I Wu52500102014-08-22 00:46:04 +0800532 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
533 cmd_batch_reserve(cmd, msaa->cmd_len);
534 cmd_batch_write_n(cmd, msaa->cmd, msaa->cmd_len);
535}
536
Chia-I Wub2755562014-08-20 13:38:52 +0800537XGL_VOID XGLAPI intelCmdBindPipeline(
538 XGL_CMD_BUFFER cmdBuffer,
539 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
540 XGL_PIPELINE pipeline)
541{
542 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
543
544 switch (pipelineBindPoint) {
545 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu018a3962014-08-21 10:37:52 +0800546 cmd->bind.pipeline.compute = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800547 break;
548 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu018a3962014-08-21 10:37:52 +0800549 cmd->bind.pipeline.graphics = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800550 break;
551 default:
552 break;
553 }
554}
555
556XGL_VOID XGLAPI intelCmdBindPipelineDelta(
557 XGL_CMD_BUFFER cmdBuffer,
558 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
559 XGL_PIPELINE_DELTA delta)
560{
561 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
562
563 switch (pipelineBindPoint) {
564 case XGL_PIPELINE_BIND_POINT_COMPUTE:
565 cmd->bind.pipeline.compute_delta = delta;
566 break;
567 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
568 cmd->bind.pipeline.graphics_delta = delta;
569 break;
570 default:
571 break;
572 }
573}
574
575XGL_VOID XGLAPI intelCmdBindStateObject(
576 XGL_CMD_BUFFER cmdBuffer,
577 XGL_STATE_BIND_POINT stateBindPoint,
578 XGL_STATE_OBJECT state)
579{
580 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
581
582 switch (stateBindPoint) {
583 case XGL_STATE_BIND_VIEWPORT:
584 cmd->bind.state.viewport =
585 intel_viewport_state((XGL_VIEWPORT_STATE_OBJECT) state);
586 break;
587 case XGL_STATE_BIND_RASTER:
588 cmd->bind.state.raster =
589 intel_raster_state((XGL_RASTER_STATE_OBJECT) state);
590 break;
591 case XGL_STATE_BIND_DEPTH_STENCIL:
592 cmd->bind.state.ds =
593 intel_ds_state((XGL_DEPTH_STENCIL_STATE_OBJECT) state);
594 break;
595 case XGL_STATE_BIND_COLOR_BLEND:
596 cmd->bind.state.blend =
597 intel_blend_state((XGL_COLOR_BLEND_STATE_OBJECT) state);
598 break;
599 case XGL_STATE_BIND_MSAA:
600 cmd->bind.state.msaa =
601 intel_msaa_state((XGL_MSAA_STATE_OBJECT) state);
602 break;
603 default:
604 break;
605 }
606}
607
608XGL_VOID XGLAPI intelCmdBindDescriptorSet(
609 XGL_CMD_BUFFER cmdBuffer,
610 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
611 XGL_UINT index,
612 XGL_DESCRIPTOR_SET descriptorSet,
613 XGL_UINT slotOffset)
614{
615 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
616 struct intel_dset *dset = intel_dset(descriptorSet);
617
618 assert(!index);
619
620 switch (pipelineBindPoint) {
621 case XGL_PIPELINE_BIND_POINT_COMPUTE:
622 cmd->bind.dset.compute = dset;
623 cmd->bind.dset.compute_offset = slotOffset;
624 break;
625 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
626 cmd->bind.dset.graphics = dset;
627 cmd->bind.dset.graphics_offset = slotOffset;
628 break;
629 default:
630 break;
631 }
632}
633
634XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
635 XGL_CMD_BUFFER cmdBuffer,
636 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
637 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView)
638{
639 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
640
641 switch (pipelineBindPoint) {
642 case XGL_PIPELINE_BIND_POINT_COMPUTE:
643 intel_mem_view_init(&cmd->bind.mem_view.compute, cmd->dev, pMemView);
644 break;
645 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
646 intel_mem_view_init(&cmd->bind.mem_view.graphics, cmd->dev, pMemView);
647 break;
648 default:
649 break;
650 }
651}
652
653XGL_VOID XGLAPI intelCmdBindIndexData(
654 XGL_CMD_BUFFER cmdBuffer,
655 XGL_GPU_MEMORY mem_,
656 XGL_GPU_SIZE offset,
657 XGL_INDEX_TYPE indexType)
658{
659 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
660 struct intel_mem *mem = intel_mem(mem_);
661
Chia-I Wu9f039862014-08-20 15:39:56 +0800662 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
663 gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false);
664 } else {
665 cmd->bind.index.mem = mem;
666 cmd->bind.index.offset = offset;
667 cmd->bind.index.type = indexType;
668 }
Chia-I Wub2755562014-08-20 13:38:52 +0800669}
670
671XGL_VOID XGLAPI intelCmdBindAttachments(
672 XGL_CMD_BUFFER cmdBuffer,
673 XGL_UINT colorAttachmentCount,
674 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
675 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment)
676{
677 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800678 const struct intel_ds_view *ds;
Chia-I Wub2755562014-08-20 13:38:52 +0800679 XGL_UINT i;
680
681 for (i = 0; i < colorAttachmentCount; i++) {
682 const XGL_COLOR_ATTACHMENT_BIND_INFO *att = &pColorAttachments[i];
683 struct intel_rt_view *rt = intel_rt_view(att->view);
684
685 cmd->bind.att.rt[i] = rt;
686 }
687
688 cmd->bind.att.rt_count = colorAttachmentCount;
689
690 if (pDepthStencilAttachment) {
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800691 cmd->bind.att.ds = intel_ds_view(pDepthStencilAttachment->view);
692 ds = cmd->bind.att.ds;
693
Chia-I Wub2755562014-08-20 13:38:52 +0800694 } else {
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800695 /* all zeros */
696 static const struct intel_ds_view null_ds;
697 ds = &null_ds;
Chia-I Wub2755562014-08-20 13:38:52 +0800698 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800699
Chia-I Wu254db422014-08-21 11:54:29 +0800700 /* TODO workarounds */
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800701 gen6_3DSTATE_DEPTH_BUFFER(cmd, ds);
702 gen6_3DSTATE_STENCIL_BUFFER(cmd, ds);
703 gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds);
Chia-I Wub2755562014-08-20 13:38:52 +0800704}
705
706XGL_VOID XGLAPI intelCmdDraw(
707 XGL_CMD_BUFFER cmdBuffer,
708 XGL_UINT firstVertex,
709 XGL_UINT vertexCount,
710 XGL_UINT firstInstance,
711 XGL_UINT instanceCount)
712{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800713 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu254db422014-08-21 11:54:29 +0800714 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800715
Chia-I Wu52500102014-08-22 00:46:04 +0800716 emit_bounded_states(cmd);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800717
718 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu254db422014-08-21 11:54:29 +0800719 gen7_3DPRIMITIVE(cmd, p->prim_type, false, vertexCount,
720 firstVertex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800721 } else {
Chia-I Wu254db422014-08-21 11:54:29 +0800722 gen6_3DPRIMITIVE(cmd, p->prim_type, false, vertexCount,
723 firstVertex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800724 }
Chia-I Wub2755562014-08-20 13:38:52 +0800725}
726
727XGL_VOID XGLAPI intelCmdDrawIndexed(
728 XGL_CMD_BUFFER cmdBuffer,
729 XGL_UINT firstIndex,
730 XGL_UINT indexCount,
731 XGL_INT vertexOffset,
732 XGL_UINT firstInstance,
733 XGL_UINT instanceCount)
734{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800735 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu254db422014-08-21 11:54:29 +0800736 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800737
Chia-I Wu52500102014-08-22 00:46:04 +0800738 emit_bounded_states(cmd);
Chia-I Wu254db422014-08-21 11:54:29 +0800739
740 if (p->primitive_restart && !gen6_can_primitive_restart(cmd))
741 cmd->result = XGL_ERROR_UNKNOWN;
742
743 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
744 gen75_3DSTATE_VF(cmd, p->primitive_restart,
745 p->primitive_restart_index);
746 } else {
747 gen6_3DSTATE_INDEX_BUFFER(cmd, cmd->bind.index.mem,
748 cmd->bind.index.offset, cmd->bind.index.type,
749 p->primitive_restart);
750 }
Chia-I Wu59c097e2014-08-21 10:51:07 +0800751
752 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu254db422014-08-21 11:54:29 +0800753 gen7_3DPRIMITIVE(cmd, p->prim_type, true, indexCount,
754 firstIndex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800755 } else {
Chia-I Wu254db422014-08-21 11:54:29 +0800756 gen6_3DPRIMITIVE(cmd, p->prim_type, true, indexCount,
757 firstIndex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800758 }
Chia-I Wub2755562014-08-20 13:38:52 +0800759}
760
761XGL_VOID XGLAPI intelCmdDrawIndirect(
762 XGL_CMD_BUFFER cmdBuffer,
763 XGL_GPU_MEMORY mem,
764 XGL_GPU_SIZE offset,
765 XGL_UINT32 count,
766 XGL_UINT32 stride)
767{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800768 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
769
770 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800771}
772
773XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
774 XGL_CMD_BUFFER cmdBuffer,
775 XGL_GPU_MEMORY mem,
776 XGL_GPU_SIZE offset,
777 XGL_UINT32 count,
778 XGL_UINT32 stride)
779{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800780 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
781
782 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800783}
784
785XGL_VOID XGLAPI intelCmdDispatch(
786 XGL_CMD_BUFFER cmdBuffer,
787 XGL_UINT x,
788 XGL_UINT y,
789 XGL_UINT z)
790{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800791 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
792
793 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800794}
795
796XGL_VOID XGLAPI intelCmdDispatchIndirect(
797 XGL_CMD_BUFFER cmdBuffer,
798 XGL_GPU_MEMORY mem,
799 XGL_GPU_SIZE offset)
800{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800801 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
802
803 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800804}