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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qca-wifi-host-cmn / 36ce817b7ebbf6da4a7fe61ecfa2b1f00342f7f8 / . / wlan_cfg / cfg_dp.h
blob: 69aac6c892b56408aa4ee4d321d7c2fbfac5db05 [file] [log] [blame]
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]1/*
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800[diff] [blame]2 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]3 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/**
20 * DOC: This file contains definitions of Data Path configuration.
21 */
22
23#ifndef _CFG_DP_H_
24#define _CFG_DP_H_
25
26#include "cfg_define.h"
27
28#define WLAN_CFG_MAX_CLIENTS 64
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]29#define WLAN_CFG_MAX_CLIENTS_MIN 8
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]30#define WLAN_CFG_MAX_CLIENTS_MAX 64
31
32/* Change this to a lower value to enforce scattered idle list mode */
33#define WLAN_CFG_MAX_ALLOC_SIZE 0x200000
sumedh baikady3c05f972019-04-18 15:30:30 -0700[diff] [blame]34#define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]35#define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000
36
37#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
38#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
39#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
40
hangtian04f0ad42019-06-07 11:04:02 +0800[diff] [blame]41#if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \
42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL)
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]43#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
44#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]45#else
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]46#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
47#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]48#endif
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]49
50#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
51#define WLAN_CFG_PER_PDEV_TX_RING_MAX 1
52
Vevek Venkatesan4a6c3e82019-06-24 14:29:19 +0530[diff] [blame]53#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]54#define WLAN_CFG_PER_PDEV_RX_RING 0
55#define WLAN_CFG_PER_PDEV_LMAC_RING 0
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]56#define WLAN_LRO_ENABLE 0
Venkata Sharath Chandra Manchala8d583a82019-04-21 12:32:24 -0700[diff] [blame]57#define WLAN_CFG_MAC_PER_TARGET 2
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]58#ifdef IPA_OFFLOAD
Mohit Khanna81179cb2018-08-16 20:50:43 -0700[diff] [blame]59/* Size of TCL TX Ring */
60#define WLAN_CFG_TX_RING_SIZE 1024
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]61#define WLAN_CFG_PER_PDEV_TX_RING 0
62#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
63#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
64#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]65#else
66#define WLAN_CFG_TX_RING_SIZE 512
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]67#define WLAN_CFG_PER_PDEV_TX_RING 1
68#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
69#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
70#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]71#endif
72#define WLAN_CFG_TX_COMP_RING_SIZE 1024
73
74/* Tx Descriptor and Tx Extension Descriptor pool sizes */
75#define WLAN_CFG_NUM_TX_DESC 1024
76#define WLAN_CFG_NUM_TX_EXT_DESC 1024
77
78/* Interrupt Mitigation - Batch threshold in terms of number of frames */
79#define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1
80#define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1
81#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1
82
83/* Interrupt Mitigation - Timer threshold in us */
84#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
85#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
86#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]87#endif
88
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]89#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256
90#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 256
91
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]92#define WLAN_CFG_PER_PDEV_RX_RING_MIN 0
93#define WLAN_CFG_PER_PDEV_RX_RING_MAX 0
94
95#define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0
96#define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1
97
98#define WLAN_CFG_TX_RING_SIZE_MIN 512
99#define WLAN_CFG_TX_RING_SIZE_MAX 2048
100
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]101#define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]102#define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000
103
104#define WLAN_CFG_NUM_TX_DESC_MIN 1024
Shashikala Prabhu550e69c2019-03-13 17:41:17 +0530[diff] [blame]105#define WLAN_CFG_NUM_TX_DESC_MAX 32768
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]106
107#define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024
108#define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000
109
110#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1
111#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256
112
113#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1
114#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128
115
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]116#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1
117#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128
118
119#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1
120#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128
121
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]122#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1
123#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1
124
125#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8
126#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100
127
128#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8
129#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500
130
131#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8
132#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000
133
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]134#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8
135#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 500
136
137#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8
138#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500
139
Aniruddha Paul7d991b32018-09-03 17:40:00 +0530[diff] [blame]140#define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000
141#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000
Aniruddha Paul1b267242019-03-15 12:01:06 +0530[diff] [blame]142#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]143
144#ifdef QCA_LL_TX_FLOW_CONTROL_V2
145
146/* Per vdev pools */
147#define WLAN_CFG_NUM_TX_DESC_POOL 3
148#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
149
150#else /* QCA_LL_TX_FLOW_CONTROL_V2 */
151
152#ifdef TX_PER_PDEV_DESC_POOL
153#define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT
154#define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT
155
156#else /* TX_PER_PDEV_DESC_POOL */
157
158#define WLAN_CFG_NUM_TX_DESC_POOL 3
159#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
160
161#endif /* TX_PER_PDEV_DESC_POOL */
162#endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
163
164#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1
165#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4
166
167#define WLAN_CFG_HTT_PKT_TYPE 2
168#define WLAN_CFG_HTT_PKT_TYPE_MIN 2
169#define WLAN_CFG_HTT_PKT_TYPE_MAX 2
170
171#define WLAN_CFG_MAX_PEER_ID 64
172#define WLAN_CFG_MAX_PEER_ID_MIN 64
173#define WLAN_CFG_MAX_PEER_ID_MAX 64
174
175#define WLAN_CFG_RX_DEFRAG_TIMEOUT 100
176#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100
177#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100
178
179#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
180#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
181#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
182
183#define WLAN_CFG_NUM_REO_DEST_RING 4
184#define WLAN_CFG_NUM_REO_DEST_RING_MIN 4
185#define WLAN_CFG_NUM_REO_DEST_RING_MAX 4
186
187#define WLAN_CFG_WBM_RELEASE_RING_SIZE 64
188#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64
189#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64
190
191#define WLAN_CFG_TCL_CMD_RING_SIZE 32
192#define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32
193#define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32
194
195#define WLAN_CFG_TCL_STATUS_RING_SIZE 32
196#define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32
197#define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32
198
199#if defined(QCA_WIFI_QCA6290)
200#define WLAN_CFG_REO_DST_RING_SIZE 1024
201#else
202#define WLAN_CFG_REO_DST_RING_SIZE 2048
203#endif
204
205#define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024
206#define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048
207
208#define WLAN_CFG_REO_REINJECT_RING_SIZE 32
209#define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32
210#define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32
211
212#define WLAN_CFG_RX_RELEASE_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]213#define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530[diff] [blame]214#if defined(QCA_WIFI_QCA6390)
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]215#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530[diff] [blame]216#else
217#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192
218#endif
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]219
220#define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128
221#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128
222#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128
223
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700[diff] [blame]224#define WLAN_CFG_REO_CMD_RING_SIZE 128
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]225#define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700[diff] [blame]226#define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]227
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700[diff] [blame]228#define WLAN_CFG_REO_STATUS_RING_SIZE 256
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]229#define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800[diff] [blame]230#define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]231
232#define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024
233#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024
234#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024
235
236#define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]237#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]238#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096
239
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530[diff] [blame^]240#define WLAN_CFG_TX_DESC_LIMIT_0 0
241#define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096
242#define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768
243
244#define WLAN_CFG_TX_DESC_LIMIT_1 0
245#define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096
246#define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768
247
248#define WLAN_CFG_TX_DESC_LIMIT_2 0
249#define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096
250#define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768
251
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]252#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]253#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]254#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]255
256#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]257#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]258#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]259
260#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]261#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]262#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]263
264#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096
265#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]266#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]267
268#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024
269#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024
Karunakar Dasineni79768452018-09-07 11:32:34 -0700[diff] [blame]270#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]271
272/* DP INI Declerations */
273#define CFG_DP_HTT_PACKET_TYPE \
274 CFG_INI_UINT("dp_htt_packet_type", \
275 WLAN_CFG_HTT_PKT_TYPE_MIN, \
276 WLAN_CFG_HTT_PKT_TYPE_MAX, \
277 WLAN_CFG_HTT_PKT_TYPE, \
278 CFG_VALUE_OR_DEFAULT, "DP HTT packet type")
279
280#define CFG_DP_INT_BATCH_THRESHOLD_OTHER \
281 CFG_INI_UINT("dp_int_batch_threshold_other", \
Karunakar Dasineni2b7628c2018-10-23 22:59:37 -0700[diff] [blame]282 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \
283 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \
284 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]285 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other")
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]286
287#define CFG_DP_INT_BATCH_THRESHOLD_RX \
288 CFG_INI_UINT("dp_int_batch_threshold_rx", \
289 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \
290 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \
291 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]292 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx")
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]293
294#define CFG_DP_INT_BATCH_THRESHOLD_TX \
295 CFG_INI_UINT("dp_int_batch_threshold_tx", \
296 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \
297 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \
298 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \
299 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx")
300
301#define CFG_DP_INT_TIMER_THRESHOLD_OTHER \
302 CFG_INI_UINT("dp_int_timer_threshold_other", \
303 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \
304 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \
305 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \
306 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other")
307
308#define CFG_DP_INT_TIMER_THRESHOLD_RX \
309 CFG_INI_UINT("dp_int_timer_threshold_rx", \
310 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \
311 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \
312 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \
313 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx")
314
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]315#define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \
316 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \
317 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \
318 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \
319 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \
320 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring")
321
322#define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \
323 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \
324 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \
325 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \
326 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \
327 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring")
328
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]329#define CFG_DP_INT_TIMER_THRESHOLD_TX \
330 CFG_INI_UINT("dp_int_timer_threshold_tx", \
331 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \
332 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \
333 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \
334 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx")
335
336#define CFG_DP_MAX_ALLOC_SIZE \
337 CFG_INI_UINT("dp_max_alloc_size", \
338 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \
339 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \
340 WLAN_CFG_MAX_ALLOC_SIZE, \
341 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size")
342
343#define CFG_DP_MAX_CLIENTS \
344 CFG_INI_UINT("dp_max_clients", \
345 WLAN_CFG_MAX_CLIENTS_MIN, \
346 WLAN_CFG_MAX_CLIENTS_MAX, \
347 WLAN_CFG_MAX_CLIENTS, \
348 CFG_VALUE_OR_DEFAULT, "DP Max Clients")
349
350#define CFG_DP_MAX_PEER_ID \
351 CFG_INI_UINT("dp_max_peer_id", \
352 WLAN_CFG_MAX_PEER_ID_MIN, \
353 WLAN_CFG_MAX_PEER_ID_MAX, \
354 WLAN_CFG_MAX_PEER_ID, \
355 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID")
356
357#define CFG_DP_REO_DEST_RINGS \
358 CFG_INI_UINT("dp_reo_dest_rings", \
359 WLAN_CFG_NUM_REO_DEST_RING_MIN, \
360 WLAN_CFG_NUM_REO_DEST_RING_MAX, \
361 WLAN_CFG_NUM_REO_DEST_RING, \
362 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings")
363
364#define CFG_DP_TCL_DATA_RINGS \
365 CFG_INI_UINT("dp_tcl_data_rings", \
366 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \
367 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \
368 WLAN_CFG_NUM_TCL_DATA_RINGS, \
369 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings")
370
371#define CFG_DP_TX_DESC \
372 CFG_INI_UINT("dp_tx_desc", \
373 WLAN_CFG_NUM_TX_DESC_MIN, \
374 WLAN_CFG_NUM_TX_DESC_MAX, \
375 WLAN_CFG_NUM_TX_DESC, \
376 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors")
377
378#define CFG_DP_TX_EXT_DESC \
379 CFG_INI_UINT("dp_tx_ext_desc", \
380 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \
381 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \
382 WLAN_CFG_NUM_TX_EXT_DESC, \
383 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors")
384
385#define CFG_DP_TX_EXT_DESC_POOLS \
386 CFG_INI_UINT("dp_tx_ext_desc_pool", \
387 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \
388 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \
389 WLAN_CFG_NUM_TXEXT_DESC_POOL, \
390 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool")
391
392#define CFG_DP_PDEV_RX_RING \
393 CFG_INI_UINT("dp_pdev_rx_ring", \
394 WLAN_CFG_PER_PDEV_RX_RING_MIN, \
395 WLAN_CFG_PER_PDEV_RX_RING_MAX, \
396 WLAN_CFG_PER_PDEV_RX_RING, \
397 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring")
398
399#define CFG_DP_PDEV_TX_RING \
400 CFG_INI_UINT("dp_pdev_tx_ring", \
401 WLAN_CFG_PER_PDEV_TX_RING_MIN, \
402 WLAN_CFG_PER_PDEV_TX_RING_MAX, \
403 WLAN_CFG_PER_PDEV_TX_RING, \
404 CFG_VALUE_OR_DEFAULT, \
405 "DP PDEV Tx Ring")
406
407#define CFG_DP_RX_DEFRAG_TIMEOUT \
408 CFG_INI_UINT("dp_rx_defrag_timeout", \
409 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \
410 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \
411 WLAN_CFG_RX_DEFRAG_TIMEOUT, \
412 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout")
413
414#define CFG_DP_TX_COMPL_RING_SIZE \
415 CFG_INI_UINT("dp_tx_compl_ring_size", \
416 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \
417 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \
418 WLAN_CFG_TX_COMP_RING_SIZE, \
419 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size")
420
421#define CFG_DP_TX_RING_SIZE \
422 CFG_INI_UINT("dp_tx_ring_size", \
423 WLAN_CFG_TX_RING_SIZE_MIN,\
424 WLAN_CFG_TX_RING_SIZE_MAX,\
425 WLAN_CFG_TX_RING_SIZE,\
426 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size")
427
428#define CFG_DP_NSS_COMP_RING_SIZE \
429 CFG_INI_UINT("dp_nss_comp_ring_size", \
430 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \
431 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \
432 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \
433 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size")
434
435#define CFG_DP_PDEV_LMAC_RING \
436 CFG_INI_UINT("dp_pdev_lmac_ring", \
437 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \
438 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \
439 WLAN_CFG_PER_PDEV_LMAC_RING, \
440 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring")
441
442#define CFG_DP_BASE_HW_MAC_ID \
443 CFG_INI_UINT("dp_base_hw_macid", \
444 0, 1, 1, \
445 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID")
446
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]447#define CFG_DP_RX_HASH \
448 CFG_INI_BOOL("dp_rx_hash", true, \
449 "DP Rx Hash")
450
451#define CFG_DP_TSO \
452 CFG_INI_BOOL("TSOEnable", false, \
453 "DP TSO Enabled")
454
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530[diff] [blame]455#define CFG_DP_LRO \
456 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
457 "DP LRO Enable")
458
459#define CFG_DP_SG \
460 CFG_INI_BOOL("dp_sg_support", false, \
461 "DP SG Enable")
462
463#define CFG_DP_GRO \
464 CFG_INI_BOOL("GROEnable", false, \
465 "DP GRO Enable")
466
467#define CFG_DP_OL_TX_CSUM \
468 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \
469 "DP tx csum Enable")
470
471#define CFG_DP_OL_RX_CSUM \
472 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \
473 "DP rx csum Enable")
474
475#define CFG_DP_RAWMODE \
476 CFG_INI_BOOL("dp_rawmode_support", false, \
477 "DP rawmode Enable")
478
479#define CFG_DP_PEER_FLOW_CTRL \
480 CFG_INI_BOOL("dp_peer_flow_control_support", false, \
481 "DP peer flow ctrl Enable")
482
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]483#define CFG_DP_NAPI \
Vivek7047d0d2019-07-09 19:30:40 +0530[diff] [blame]484 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]485 "DP Napi Enabled")
486
487#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]488 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]489 "DP TCP UDP Checksum Offload")
490
491#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
492 CFG_INI_BOOL("dp_defrag_timeout_check", true, \
493 "DP Defrag Timeout Check")
494
495#define CFG_DP_WBM_RELEASE_RING \
496 CFG_INI_UINT("dp_wbm_release_ring", \
497 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \
498 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \
499 WLAN_CFG_WBM_RELEASE_RING_SIZE, \
500 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring")
501
502#define CFG_DP_TCL_CMD_RING \
503 CFG_INI_UINT("dp_tcl_cmd_ring", \
504 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \
505 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \
506 WLAN_CFG_TCL_CMD_RING_SIZE, \
507 CFG_VALUE_OR_DEFAULT, "DP TCL command ring")
508
509#define CFG_DP_TCL_STATUS_RING \
510 CFG_INI_UINT("dp_tcl_status_ring",\
511 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \
512 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \
513 WLAN_CFG_TCL_STATUS_RING_SIZE, \
514 CFG_VALUE_OR_DEFAULT, "DP TCL status ring")
515
516#define CFG_DP_REO_REINJECT_RING \
517 CFG_INI_UINT("dp_reo_reinject_ring", \
518 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \
519 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \
520 WLAN_CFG_REO_REINJECT_RING_SIZE, \
521 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring")
522
523#define CFG_DP_RX_RELEASE_RING \
524 CFG_INI_UINT("dp_rx_release_ring", \
525 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \
526 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \
527 WLAN_CFG_RX_RELEASE_RING_SIZE, \
528 CFG_VALUE_OR_DEFAULT, "DP Rx release ring")
529
530#define CFG_DP_REO_EXCEPTION_RING \
531 CFG_INI_UINT("dp_reo_exception_ring", \
532 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \
533 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \
534 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \
535 CFG_VALUE_OR_DEFAULT, "DP REO exception ring")
536
537#define CFG_DP_REO_CMD_RING \
538 CFG_INI_UINT("dp_reo_cmd_ring", \
539 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \
540 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \
541 WLAN_CFG_REO_CMD_RING_SIZE, \
542 CFG_VALUE_OR_DEFAULT, "DP REO command ring")
543
544#define CFG_DP_REO_STATUS_RING \
545 CFG_INI_UINT("dp_reo_status_ring", \
546 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \
547 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \
548 WLAN_CFG_REO_STATUS_RING_SIZE, \
549 CFG_VALUE_OR_DEFAULT, "DP REO status ring")
550
551#define CFG_DP_RXDMA_BUF_RING \
552 CFG_INI_UINT("dp_rxdma_buf_ring", \
553 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \
554 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \
555 WLAN_CFG_RXDMA_BUF_RING_SIZE, \
556 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring")
557
558#define CFG_DP_RXDMA_REFILL_RING \
559 CFG_INI_UINT("dp_rxdma_refill_ring", \
560 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \
561 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \
562 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \
563 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring")
564
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530[diff] [blame^]565#define CFG_DP_TX_DESC_LIMIT_0 \
566 CFG_INI_UINT("dp_tx_desc_limit_0", \
567 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \
568 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \
569 WLAN_CFG_TX_DESC_LIMIT_0, \
570 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0")
571
572#define CFG_DP_TX_DESC_LIMIT_1 \
573 CFG_INI_UINT("dp_tx_desc_limit_1", \
574 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \
575 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \
576 WLAN_CFG_TX_DESC_LIMIT_1, \
577 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1")
578
579#define CFG_DP_TX_DESC_LIMIT_2 \
580 CFG_INI_UINT("dp_tx_desc_limit_2", \
581 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \
582 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \
583 WLAN_CFG_TX_DESC_LIMIT_2, \
584 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2")
585
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]586#define CFG_DP_RXDMA_MONITOR_BUF_RING \
587 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \
588 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \
589 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \
590 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \
591 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring")
592
593#define CFG_DP_RXDMA_MONITOR_DST_RING \
594 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \
595 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \
596 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \
597 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \
598 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
599
600#define CFG_DP_RXDMA_MONITOR_STATUS_RING \
601 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \
602 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \
603 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \
604 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \
605 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring")
606
607#define CFG_DP_RXDMA_MONITOR_DESC_RING \
608 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \
609 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \
610 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \
611 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \
612 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
613
614#define CFG_DP_RXDMA_ERR_DST_RING \
615 CFG_INI_UINT("dp_rxdma_err_dst_ring", \
616 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \
617 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \
618 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
619 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
620
Krunal Soni03ba0f52019-02-12 11:44:46 -0800[diff] [blame]621#define CFG_DP_PER_PKT_LOGGING \
622 CFG_INI_UINT("enable_verbose_debug", \
623 0, 0xffff, 0, \
624 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging")
625
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]626#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
627 CFG_INI_UINT("TxFlowStartQueueOffset", \
628 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
629 CFG_VALUE_OR_DEFAULT, "Start queue offset")
630
631#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
632 CFG_INI_UINT("TxFlowStopQueueThreshold", \
633 0, 50, 15, \
634 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
635
636#define CFG_DP_IPA_UC_TX_BUF_SIZE \
637 CFG_INI_UINT("IpaUcTxBufSize", \
638 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
639 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
640
641#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
642 CFG_INI_UINT("IpaUcTxPartitionBase", \
643 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
644 CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
645
646#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
647 CFG_INI_UINT("IpaUcRxIndRingCount", \
648 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
649 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
650
651#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
652 CFG_INI_UINT("gReorderOffloadSupported", \
653 0, 1, 1, \
654 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
655
656#define CFG_DP_AP_STA_SECURITY_SEPERATION \
657 CFG_INI_BOOL("gDisableIntraBssFwd", \
658 false, "Disable intrs BSS Rx packets")
659
660#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
661 CFG_INI_BOOL("gEnableDataStallDetection", \
662 true, "Enable/Disable Data stall detection")
663
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]664#define CFG_DP \
665 CFG(CFG_DP_HTT_PACKET_TYPE) \
666 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
667 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \
668 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \
669 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \
670 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \
671 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \
672 CFG(CFG_DP_MAX_ALLOC_SIZE) \
673 CFG(CFG_DP_MAX_CLIENTS) \
674 CFG(CFG_DP_MAX_PEER_ID) \
675 CFG(CFG_DP_REO_DEST_RINGS) \
676 CFG(CFG_DP_TCL_DATA_RINGS) \
677 CFG(CFG_DP_TX_DESC) \
678 CFG(CFG_DP_TX_EXT_DESC) \
679 CFG(CFG_DP_TX_EXT_DESC_POOLS) \
680 CFG(CFG_DP_PDEV_RX_RING) \
681 CFG(CFG_DP_PDEV_TX_RING) \
682 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \
683 CFG(CFG_DP_TX_COMPL_RING_SIZE) \
684 CFG(CFG_DP_TX_RING_SIZE) \
685 CFG(CFG_DP_NSS_COMP_RING_SIZE) \
686 CFG(CFG_DP_PDEV_LMAC_RING) \
687 CFG(CFG_DP_BASE_HW_MAC_ID) \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]688 CFG(CFG_DP_RX_HASH) \
689 CFG(CFG_DP_TSO) \
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530[diff] [blame]690 CFG(CFG_DP_LRO) \
691 CFG(CFG_DP_SG) \
692 CFG(CFG_DP_GRO) \
693 CFG(CFG_DP_OL_TX_CSUM) \
694 CFG(CFG_DP_OL_RX_CSUM) \
695 CFG(CFG_DP_RAWMODE) \
696 CFG(CFG_DP_PEER_FLOW_CTRL) \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]697 CFG(CFG_DP_NAPI) \
698 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \
699 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \
700 CFG(CFG_DP_WBM_RELEASE_RING) \
701 CFG(CFG_DP_TCL_CMD_RING) \
702 CFG(CFG_DP_TCL_STATUS_RING) \
703 CFG(CFG_DP_REO_REINJECT_RING) \
704 CFG(CFG_DP_RX_RELEASE_RING) \
705 CFG(CFG_DP_REO_EXCEPTION_RING) \
706 CFG(CFG_DP_REO_CMD_RING) \
707 CFG(CFG_DP_REO_STATUS_RING) \
708 CFG(CFG_DP_RXDMA_BUF_RING) \
709 CFG(CFG_DP_RXDMA_REFILL_RING) \
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530[diff] [blame^]710 CFG(CFG_DP_TX_DESC_LIMIT_0) \
711 CFG(CFG_DP_TX_DESC_LIMIT_1) \
712 CFG(CFG_DP_TX_DESC_LIMIT_2) \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]713 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \
714 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
715 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
716 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]717 CFG(CFG_DP_RXDMA_ERR_DST_RING) \
Krunal Soni03ba0f52019-02-12 11:44:46 -0800[diff] [blame]718 CFG(CFG_DP_PER_PKT_LOGGING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]719 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
720 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
721 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
722 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
723 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
724 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
725 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
726 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]727
728#endif /* _CFG_DP_H_ */