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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qca-wifi-host-cmn / 973308ae130690e9da8b3729fb16dd29024d5f52 / . / hif / src / ce / ce_reg.h
blob: cb12694f38d9e11a5f9ff8ec6346bf34423067ce [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1/*
Nirav Shah8e930272018-07-10 16:28:21 +0530[diff] [blame]2 * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]3 *
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]19#ifndef __CE_REG_H__
20#define __CE_REG_H__
21
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]22#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
23 - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
24
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]25#define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
26#define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
27#define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
28#define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
29#define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
30#define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
31#define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
32#define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
33
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame]34#define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
35#define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
36#define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
37#define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
38#define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
39#define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
40#define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
41#define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
42#define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
43#define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
44#define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
45#define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
46#define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
47#define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
48#define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
49#define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
50#define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
51#define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
52#define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
53#define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
54#define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
55#define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
56#define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
57#define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
58#define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
59#define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
60#define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
61#define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
62#define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
63#define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
64#define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
65#define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
66#define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
67#define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
68#define SHADOW_ADDRESS10 \
69 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
70#define SHADOW_ADDRESS11 \
71 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
72#define SHADOW_ADDRESS12 \
73 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
74#define SHADOW_ADDRESS13 \
75 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
76#define SHADOW_ADDRESS14 \
77 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
78#define SHADOW_ADDRESS15 \
79 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
80#define SHADOW_ADDRESS16 \
81 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
82#define SHADOW_ADDRESS17 \
83 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
84#define SHADOW_ADDRESS18 \
85 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
86#define SHADOW_ADDRESS19 \
87 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
88#define SHADOW_ADDRESS20 \
89 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
90#define SHADOW_ADDRESS21 \
91 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
92#define SHADOW_ADDRESS22 \
93 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
94#define SHADOW_ADDRESS23 \
95 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]96
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame]97#define SHADOW_ADDRESS(i) \
98 (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]99
100#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
101 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
102#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
103 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
104#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
105 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
106#define HOST_IS_DST_RING_LOW_WATERMARK_MASK \
107 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
108#define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS)
109#define HOST_IS_COPY_COMPLETE_MASK \
110 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
111#define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
112#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
113 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]114#define CE_DDR_ADDRESS_FOR_RRI_LOW \
115 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
116#define CE_DDR_ADDRESS_FOR_RRI_HIGH \
117 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]118#define HOST_IE_COPY_COMPLETE_MASK \
119 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
120#define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
121#define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
122#define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS)
123#define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
124#define CE_CTRL1_DMAX_LENGTH_MASK \
125 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
126#define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS)
127#define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
128#define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS)
129#define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER)
130#define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS)
131#define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
132#define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA)
133#define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
134#define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS)
135#define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
136#define MISC_IS_DST_ADDR_ERR_MASK \
137 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
138#define MISC_IS_SRC_LEN_ERR_MASK \
139 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
140#define MISC_IS_DST_MAX_LEN_VIO_MASK \
141 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
142#define MISC_IS_DST_RING_OVERFLOW_MASK \
143 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
144#define MISC_IS_SRC_RING_OVERFLOW_MASK \
145 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
146#define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
147#define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
148#define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
149#define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
150#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
151 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
152#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
153 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame]154#define CE_CTRL1_DMAX_LENGTH_LSB \
155 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]156#define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]157#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
158 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
159#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
160 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
161#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
162 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
163#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
164 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
165#define WLAN_DEBUG_INPUT_SEL_OFFSET \
166 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
167#define WLAN_DEBUG_INPUT_SEL_SRC_MSB \
168 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
169#define WLAN_DEBUG_INPUT_SEL_SRC_LSB \
170 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
171#define WLAN_DEBUG_INPUT_SEL_SRC_MASK \
172 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
173#define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
174#define WLAN_DEBUG_CONTROL_ENABLE_MSB \
175 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
176#define WLAN_DEBUG_CONTROL_ENABLE_LSB \
177 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
178#define WLAN_DEBUG_CONTROL_ENABLE_MASK \
179 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
180#define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
181#define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
182#define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
183#define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
184#define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
185#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \
186 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
187#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \
188 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
189#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \
190 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
191#define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
192#define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
193#define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame]194#define CE_WRAPPER_DEBUG_OFFSET \
195 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
196#define CE_WRAPPER_DEBUG_SEL_MSB \
197 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
198#define CE_WRAPPER_DEBUG_SEL_LSB \
199 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
200#define CE_WRAPPER_DEBUG_SEL_MASK \
201 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]202#define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET)
203#define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
204#define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
205#define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
206#define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
Karunakar Dasineni7b61c6c2017-05-30 11:17:47 -0700[diff] [blame]207#define HOST_IE_REG1_CE_LSB (scn->target_ce_def->d_HOST_IE_REG1_CE_LSB)
Venkateswara Swamy Bandaru2aa2c692016-09-20 20:25:39 +0530[diff] [blame]208#define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2)
Karunakar Dasineni7b61c6c2017-05-30 11:17:47 -0700[diff] [blame]209#define HOST_IE_REG2_CE_LSB (scn->target_ce_def->d_HOST_IE_REG2_CE_LSB)
210#define HOST_IE_ADDRESS_3 (scn->target_ce_def->d_HOST_IE_ADDRESS_3)
211#define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]212#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
213
214#define SRC_WATERMARK_LOW_SET(x) \
215 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
216#define SRC_WATERMARK_HIGH_SET(x) \
217 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
218#define DST_WATERMARK_LOW_SET(x) \
219 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
220#define DST_WATERMARK_HIGH_SET(x) \
221 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
222#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
223 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
224 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
225#define CE_CTRL1_DMAX_LENGTH_SET(x) \
226 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
227#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
228 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
229 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
230#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
231 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
232 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
233#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \
234 (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \
235 WLAN_DEBUG_INPUT_SEL_SRC_LSB)
236#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \
237 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \
238 WLAN_DEBUG_INPUT_SEL_SRC_MASK)
239#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \
240 (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \
241 WLAN_DEBUG_CONTROL_ENABLE_LSB)
242#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \
243 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \
244 WLAN_DEBUG_CONTROL_ENABLE_MASK)
245#define WLAN_DEBUG_OUT_DATA_GET(x) \
246 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
247#define WLAN_DEBUG_OUT_DATA_SET(x) \
248 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
249#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \
250 (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \
251 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
252#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \
253 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \
254 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
255#define AMBA_DEBUG_BUS_SEL_GET(x) \
256 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
257#define AMBA_DEBUG_BUS_SEL_SET(x) \
258 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
259#define CE_WRAPPER_DEBUG_SEL_GET(x) \
260 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
261#define CE_WRAPPER_DEBUG_SEL_SET(x) \
262 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
263#define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
264#define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
Karunakar Dasineni7b61c6c2017-05-30 11:17:47 -0700[diff] [blame]265#define HOST_IE_REG1_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG1_CE_LSB))
266#define HOST_IE_REG2_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG2_CE_LSB))
267#define HOST_IE_REG3_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG3_CE_LSB))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]268
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]269uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]270 uint32_t CE_ctrl_addr);
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]271uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]272 uint32_t CE_ctrl_addr);
273
Nirav Shah8e930272018-07-10 16:28:21 +0530[diff] [blame]274#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]275 & (uint64_t)(0xFFFFFFFF)))
Nirav Shah8e930272018-07-10 16:28:21 +0530[diff] [blame]276#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]277 & (uint64_t)(0xF00000000))>>32))
278
279#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
Hardik Kantilal Patel34373922016-07-13 22:14:14 +0530[diff] [blame]280 ((scn->vaddr_rri_on_ddr) + COPY_ENGINE_ID(CE_ctrl_addr))
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]281
282#define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
283#define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
284
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]285#define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
286 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
287#define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
288 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
289
Houston Hoffman5998d5f2015-12-03 13:25:05 -0800[diff] [blame]290#ifdef ADRASTEA_RRI_ON_DDR
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]291#ifdef SHADOW_REG_DEBUG
292#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
293 DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
294#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
295 DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)
296#else
297#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
298 SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
299#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
300 DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
301#endif
302
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]303unsigned int hif_get_src_ring_read_index(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]304 uint32_t CE_ctrl_addr);
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]305unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]306 uint32_t CE_ctrl_addr);
307
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]308#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
309 hif_get_src_ring_read_index(scn, CE_ctrl_addr)
310#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
311 hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
312#else
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]313#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]314 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]315#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]316 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
Houston Hoffman5998d5f2015-12-03 13:25:05 -0800[diff] [blame]317
318/**
319 * if RRI on DDR is not enabled, get idx from ddr defaults to
320 * using the register value & force wake must be used for
321 * non interrupt processing.
322 */
323#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
324 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]325#endif
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]326
327#define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
328 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
329
330#define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
331 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr))
332
333#define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
334 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH)
335
336#define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \
337 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n))
338
339#define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \
340 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
341 (A_TARGET_READ(scn, (CE_ctrl_addr) + \
342 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \
343 CE_CTRL1_DMAX_LENGTH_SET(n))
344
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]345#define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \
346 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
347 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
348 | CE_CTRL1_IDX_UPD_EN))
349
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]350#define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \
351 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
352
353#define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \
354 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n)
355
356#define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \
357 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr))
358
359#define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
360 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr))
361
362#define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \
363 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data))
364
365#define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \
366 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val)
367
368#define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \
369 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS)
370
371#define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
372 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
Houston Hoffman6296c3e2016-07-12 18:43:32 -0700[diff] [blame]373 (A_TARGET_READ(scn, \
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]374 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
375 & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \
376 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n))
377
378#define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
379 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \
Houston Hoffman6296c3e2016-07-12 18:43:32 -0700[diff] [blame]380 (A_TARGET_READ(scn, \
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]381 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
382 & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
383 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
384
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]385
386#define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
387 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
388
389#define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
390 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr))
391
392#define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
393 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH)
394
395#define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \
396 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n))
397
398#define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
399 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
400 (A_TARGET_READ(scn, \
401 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
402 & ~SRC_WATERMARK_HIGH_MASK) | \
403 SRC_WATERMARK_HIGH_SET(n))
404
405#define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
406 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
407 (A_TARGET_READ(scn, \
408 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
409 & ~SRC_WATERMARK_LOW_MASK) | \
410 SRC_WATERMARK_LOW_SET(n))
411
412#define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
413 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
414 (A_TARGET_READ(scn, \
415 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
416 & ~DST_WATERMARK_HIGH_MASK) | \
417 DST_WATERMARK_HIGH_SET(n))
418
419#define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
420 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
421 (A_TARGET_READ(scn, \
422 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
423 & ~DST_WATERMARK_LOW_MASK) | \
424 DST_WATERMARK_LOW_SET(n))
425
426#define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \
427 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
428 A_TARGET_READ(scn, \
429 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
430 HOST_IE_COPY_COMPLETE_MASK)
431
432#define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \
433 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
434 A_TARGET_READ(scn, \
435 (CE_ctrl_addr) + HOST_IE_ADDRESS) \
436 & ~HOST_IE_COPY_COMPLETE_MASK)
437
438#define CE_BASE_ADDRESS(CE_id) \
439 CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \
440 CE0_BASE_ADDRESS)*(CE_id))
441
442#define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \
443 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
444 A_TARGET_READ(scn, \
445 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
446 CE_WATERMARK_MASK)
447
448#define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \
449 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
450 A_TARGET_READ(scn, \
451 (CE_ctrl_addr) + HOST_IE_ADDRESS) \
452 & ~CE_WATERMARK_MASK)
453
454#define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \
455 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \
456 A_TARGET_READ(scn, \
457 (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK)
458
459#define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \
460 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS)
461
462#define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \
463 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS)
464
465#define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \
466 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
467
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]468#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
469 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
470 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
471 HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
472
473#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
474 MISC_IS_DST_ADDR_ERR_MASK | \
475 MISC_IS_SRC_LEN_ERR_MASK | \
476 MISC_IS_DST_MAX_LEN_VIO_MASK | \
477 MISC_IS_DST_RING_OVERFLOW_MASK | \
478 MISC_IS_SRC_RING_OVERFLOW_MASK)
479
480#define CE_SRC_RING_TO_DESC(baddr, idx) \
481 (&(((struct CE_src_desc *)baddr)[idx]))
482#define CE_DEST_RING_TO_DESC(baddr, idx) \
483 (&(((struct CE_dest_desc *)baddr)[idx]))
484
485/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
486#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
487 (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
488
489#define CE_RING_IDX_INCR(nentries_mask, idx) \
490 (((idx) + 1) & (nentries_mask))
491
492#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
493 (((idx) + (num)) & (nentries_mask))
494
495#define CE_INTERRUPT_SUMMARY(scn) \
496 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
497 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
498 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
499
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]500#define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \
501 (A_TARGET_READ(scn, \
502 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW))
503
504#define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \
505 (A_TARGET_READ(scn, \
506 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH))
507
508#define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \
509 (A_TARGET_WRITE(scn, \
510 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \
511 val))
512
513#define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \
514 (A_TARGET_WRITE(scn, \
515 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \
516 val))
517
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]518/*Macro to increment CE packet errors*/
519#define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \
520 do { if (_ce_ecode == CE_RING_DELTA_FAIL) \
521 (_scn->pkt_stats.ce_ring_delta_fail_count) \
522 += 1; } while (0)
523
524/* Given a Copy Engine's ID, determine the interrupt number for that
525 * copy engine's interrupts.
526 */
527#define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id))
528#define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE)
529#define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS)
530#define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS)
531
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]532
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]533#ifdef ADRASTEA_SHADOW_REGISTERS
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]534#define NUM_SHADOW_REGISTERS 24
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]535u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
536u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]537#endif
538
539
540#ifdef ADRASTEA_SHADOW_REGISTERS
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]541#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
542 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]543#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
544 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n)
545
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]546#else
547
548#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
549 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]550#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
551 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]552#endif
553
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]554/* The write index read is only needed durring initialization because
555 * we keep track of the index that was last written. Thus the register
556 * is the only hardware supported location to read the initial value from.
557 */
558#define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
559 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS)
560#define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
561 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS)
562
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]563#endif /* __CE_REG_H__ */