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gerrit-public.fairphone.software / toolchain / llvm-project / 02d9851c1c7dcdbcb52eb295c1e802efaa11d8f5 / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 46adb841d539d673d919ca53e00108eb8be7aad8 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]31#include "llvm/Support/BranchProbability.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Target/TargetLoweringObjectFile.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]38#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]39#include <cctype>
40using namespace llvm;
41
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]42static cl::opt<bool> JumpIsExpensiveOverride(
43 "jump-is-expensive", cl::init(false),
44 cl::desc("Do not create extra branches to split comparison logic."),
45 cl::Hidden);
46
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]47// Although this default value is arbitrary, it is not random. It is assumed
48// that a condition that evaluates the same way by a higher percentage than this
49// is best represented as control flow. Therefore, the default value N should be
50// set such that the win from N% correct executions is greater than the loss
51// from (100 - N)% mispredicted executions for the majority of intended targets.
52static cl::opt<int> MinPercentageForPredictableBranch(
53 "min-predictable-branch", cl::init(99),
54 cl::desc("Minimum percentage (0-100) that a condition must be either true "
55 "or false to assume that the condition is predictable"),
56 cl::Hidden);
57
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]58/// InitLibcallNames - Set default libcall names.
59///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]60static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]61 Names[RTLIB::SHL_I16] = "__ashlhi3";
62 Names[RTLIB::SHL_I32] = "__ashlsi3";
63 Names[RTLIB::SHL_I64] = "__ashldi3";
64 Names[RTLIB::SHL_I128] = "__ashlti3";
65 Names[RTLIB::SRL_I16] = "__lshrhi3";
66 Names[RTLIB::SRL_I32] = "__lshrsi3";
67 Names[RTLIB::SRL_I64] = "__lshrdi3";
68 Names[RTLIB::SRL_I128] = "__lshrti3";
69 Names[RTLIB::SRA_I16] = "__ashrhi3";
70 Names[RTLIB::SRA_I32] = "__ashrsi3";
71 Names[RTLIB::SRA_I64] = "__ashrdi3";
72 Names[RTLIB::SRA_I128] = "__ashrti3";
73 Names[RTLIB::MUL_I8] = "__mulqi3";
74 Names[RTLIB::MUL_I16] = "__mulhi3";
75 Names[RTLIB::MUL_I32] = "__mulsi3";
76 Names[RTLIB::MUL_I64] = "__muldi3";
77 Names[RTLIB::MUL_I128] = "__multi3";
78 Names[RTLIB::MULO_I32] = "__mulosi4";
79 Names[RTLIB::MULO_I64] = "__mulodi4";
80 Names[RTLIB::MULO_I128] = "__muloti4";
81 Names[RTLIB::SDIV_I8] = "__divqi3";
82 Names[RTLIB::SDIV_I16] = "__divhi3";
83 Names[RTLIB::SDIV_I32] = "__divsi3";
84 Names[RTLIB::SDIV_I64] = "__divdi3";
85 Names[RTLIB::SDIV_I128] = "__divti3";
86 Names[RTLIB::UDIV_I8] = "__udivqi3";
87 Names[RTLIB::UDIV_I16] = "__udivhi3";
88 Names[RTLIB::UDIV_I32] = "__udivsi3";
89 Names[RTLIB::UDIV_I64] = "__udivdi3";
90 Names[RTLIB::UDIV_I128] = "__udivti3";
91 Names[RTLIB::SREM_I8] = "__modqi3";
92 Names[RTLIB::SREM_I16] = "__modhi3";
93 Names[RTLIB::SREM_I32] = "__modsi3";
94 Names[RTLIB::SREM_I64] = "__moddi3";
95 Names[RTLIB::SREM_I128] = "__modti3";
96 Names[RTLIB::UREM_I8] = "__umodqi3";
97 Names[RTLIB::UREM_I16] = "__umodhi3";
98 Names[RTLIB::UREM_I32] = "__umodsi3";
99 Names[RTLIB::UREM_I64] = "__umoddi3";
100 Names[RTLIB::UREM_I128] = "__umodti3";
101
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]102 Names[RTLIB::NEG_I32] = "__negsi2";
103 Names[RTLIB::NEG_I64] = "__negdi2";
104 Names[RTLIB::ADD_F32] = "__addsf3";
105 Names[RTLIB::ADD_F64] = "__adddf3";
106 Names[RTLIB::ADD_F80] = "__addxf3";
107 Names[RTLIB::ADD_F128] = "__addtf3";
108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
109 Names[RTLIB::SUB_F32] = "__subsf3";
110 Names[RTLIB::SUB_F64] = "__subdf3";
111 Names[RTLIB::SUB_F80] = "__subxf3";
112 Names[RTLIB::SUB_F128] = "__subtf3";
113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
114 Names[RTLIB::MUL_F32] = "__mulsf3";
115 Names[RTLIB::MUL_F64] = "__muldf3";
116 Names[RTLIB::MUL_F80] = "__mulxf3";
117 Names[RTLIB::MUL_F128] = "__multf3";
118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
119 Names[RTLIB::DIV_F32] = "__divsf3";
120 Names[RTLIB::DIV_F64] = "__divdf3";
121 Names[RTLIB::DIV_F80] = "__divxf3";
122 Names[RTLIB::DIV_F128] = "__divtf3";
123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
124 Names[RTLIB::REM_F32] = "fmodf";
125 Names[RTLIB::REM_F64] = "fmod";
126 Names[RTLIB::REM_F80] = "fmodl";
127 Names[RTLIB::REM_F128] = "fmodl";
128 Names[RTLIB::REM_PPCF128] = "fmodl";
129 Names[RTLIB::FMA_F32] = "fmaf";
130 Names[RTLIB::FMA_F64] = "fma";
131 Names[RTLIB::FMA_F80] = "fmal";
132 Names[RTLIB::FMA_F128] = "fmal";
133 Names[RTLIB::FMA_PPCF128] = "fmal";
134 Names[RTLIB::POWI_F32] = "__powisf2";
135 Names[RTLIB::POWI_F64] = "__powidf2";
136 Names[RTLIB::POWI_F80] = "__powixf2";
137 Names[RTLIB::POWI_F128] = "__powitf2";
138 Names[RTLIB::POWI_PPCF128] = "__powitf2";
139 Names[RTLIB::SQRT_F32] = "sqrtf";
140 Names[RTLIB::SQRT_F64] = "sqrt";
141 Names[RTLIB::SQRT_F80] = "sqrtl";
142 Names[RTLIB::SQRT_F128] = "sqrtl";
143 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
144 Names[RTLIB::LOG_F32] = "logf";
145 Names[RTLIB::LOG_F64] = "log";
146 Names[RTLIB::LOG_F80] = "logl";
147 Names[RTLIB::LOG_F128] = "logl";
148 Names[RTLIB::LOG_PPCF128] = "logl";
149 Names[RTLIB::LOG2_F32] = "log2f";
150 Names[RTLIB::LOG2_F64] = "log2";
151 Names[RTLIB::LOG2_F80] = "log2l";
152 Names[RTLIB::LOG2_F128] = "log2l";
153 Names[RTLIB::LOG2_PPCF128] = "log2l";
154 Names[RTLIB::LOG10_F32] = "log10f";
155 Names[RTLIB::LOG10_F64] = "log10";
156 Names[RTLIB::LOG10_F80] = "log10l";
157 Names[RTLIB::LOG10_F128] = "log10l";
158 Names[RTLIB::LOG10_PPCF128] = "log10l";
159 Names[RTLIB::EXP_F32] = "expf";
160 Names[RTLIB::EXP_F64] = "exp";
161 Names[RTLIB::EXP_F80] = "expl";
162 Names[RTLIB::EXP_F128] = "expl";
163 Names[RTLIB::EXP_PPCF128] = "expl";
164 Names[RTLIB::EXP2_F32] = "exp2f";
165 Names[RTLIB::EXP2_F64] = "exp2";
166 Names[RTLIB::EXP2_F80] = "exp2l";
167 Names[RTLIB::EXP2_F128] = "exp2l";
168 Names[RTLIB::EXP2_PPCF128] = "exp2l";
169 Names[RTLIB::SIN_F32] = "sinf";
170 Names[RTLIB::SIN_F64] = "sin";
171 Names[RTLIB::SIN_F80] = "sinl";
172 Names[RTLIB::SIN_F128] = "sinl";
173 Names[RTLIB::SIN_PPCF128] = "sinl";
174 Names[RTLIB::COS_F32] = "cosf";
175 Names[RTLIB::COS_F64] = "cos";
176 Names[RTLIB::COS_F80] = "cosl";
177 Names[RTLIB::COS_F128] = "cosl";
178 Names[RTLIB::COS_PPCF128] = "cosl";
179 Names[RTLIB::POW_F32] = "powf";
180 Names[RTLIB::POW_F64] = "pow";
181 Names[RTLIB::POW_F80] = "powl";
182 Names[RTLIB::POW_F128] = "powl";
183 Names[RTLIB::POW_PPCF128] = "powl";
184 Names[RTLIB::CEIL_F32] = "ceilf";
185 Names[RTLIB::CEIL_F64] = "ceil";
186 Names[RTLIB::CEIL_F80] = "ceill";
187 Names[RTLIB::CEIL_F128] = "ceill";
188 Names[RTLIB::CEIL_PPCF128] = "ceill";
189 Names[RTLIB::TRUNC_F32] = "truncf";
190 Names[RTLIB::TRUNC_F64] = "trunc";
191 Names[RTLIB::TRUNC_F80] = "truncl";
192 Names[RTLIB::TRUNC_F128] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_F128] = "rintl";
198 Names[RTLIB::RINT_PPCF128] = "rintl";
199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
200 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]204 Names[RTLIB::ROUND_F32] = "roundf";
205 Names[RTLIB::ROUND_F64] = "round";
206 Names[RTLIB::ROUND_F80] = "roundl";
207 Names[RTLIB::ROUND_F128] = "roundl";
208 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]209 Names[RTLIB::FLOOR_F32] = "floorf";
210 Names[RTLIB::FLOOR_F64] = "floor";
211 Names[RTLIB::FLOOR_F80] = "floorl";
212 Names[RTLIB::FLOOR_F128] = "floorl";
213 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]214 Names[RTLIB::FMIN_F32] = "fminf";
215 Names[RTLIB::FMIN_F64] = "fmin";
216 Names[RTLIB::FMIN_F80] = "fminl";
217 Names[RTLIB::FMIN_F128] = "fminl";
218 Names[RTLIB::FMIN_PPCF128] = "fminl";
219 Names[RTLIB::FMAX_F32] = "fmaxf";
220 Names[RTLIB::FMAX_F64] = "fmax";
221 Names[RTLIB::FMAX_F80] = "fmaxl";
222 Names[RTLIB::FMAX_F128] = "fmaxl";
223 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]224 Names[RTLIB::ROUND_F32] = "roundf";
225 Names[RTLIB::ROUND_F64] = "round";
226 Names[RTLIB::ROUND_F80] = "roundl";
227 Names[RTLIB::ROUND_F128] = "roundl";
228 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]229 Names[RTLIB::COPYSIGN_F32] = "copysignf";
230 Names[RTLIB::COPYSIGN_F64] = "copysign";
231 Names[RTLIB::COPYSIGN_F80] = "copysignl";
232 Names[RTLIB::COPYSIGN_F128] = "copysignl";
233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]234 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
235 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]236 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
237 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
238 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]239 if (TT.isOSDarwin()) {
240 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
241 // of the gnueabi-style __gnu_*_ieee.
242 // FIXME: What about other targets?
243 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
244 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
245 } else {
246 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
247 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
248 }
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]249 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
250 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
251 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
252 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]253 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
254 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
255 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]256 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]257 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
258 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]259 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]260 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
261 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
262 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]263 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
264 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
265 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
266 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
267 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
268 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
269 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
270 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
271 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]272 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]273 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
274 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]275 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
276 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
277 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]278 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
279 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
280 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
281 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
282 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
283 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
284 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
285 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
286 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
287 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
288 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
289 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
290 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
291 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
292 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
293 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]294 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]295 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
296 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
297 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
298 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
299 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
300 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
301 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
302 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
303 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
304 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
305 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
306 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
307 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
308 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]309 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]310 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
311 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
312 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
313 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
314 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
315 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
316 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
317 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
318 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
319 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
320 Names[RTLIB::OEQ_F32] = "__eqsf2";
321 Names[RTLIB::OEQ_F64] = "__eqdf2";
322 Names[RTLIB::OEQ_F128] = "__eqtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]323 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]324 Names[RTLIB::UNE_F32] = "__nesf2";
325 Names[RTLIB::UNE_F64] = "__nedf2";
326 Names[RTLIB::UNE_F128] = "__netf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]327 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]328 Names[RTLIB::OGE_F32] = "__gesf2";
329 Names[RTLIB::OGE_F64] = "__gedf2";
330 Names[RTLIB::OGE_F128] = "__getf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]331 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]332 Names[RTLIB::OLT_F32] = "__ltsf2";
333 Names[RTLIB::OLT_F64] = "__ltdf2";
334 Names[RTLIB::OLT_F128] = "__lttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]335 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]336 Names[RTLIB::OLE_F32] = "__lesf2";
337 Names[RTLIB::OLE_F64] = "__ledf2";
338 Names[RTLIB::OLE_F128] = "__letf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]339 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]340 Names[RTLIB::OGT_F32] = "__gtsf2";
341 Names[RTLIB::OGT_F64] = "__gtdf2";
342 Names[RTLIB::OGT_F128] = "__gttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]343 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]344 Names[RTLIB::UO_F32] = "__unordsf2";
345 Names[RTLIB::UO_F64] = "__unorddf2";
346 Names[RTLIB::UO_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]347 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]348 Names[RTLIB::O_F32] = "__unordsf2";
349 Names[RTLIB::O_F64] = "__unorddf2";
350 Names[RTLIB::O_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]351 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]352 Names[RTLIB::MEMCPY] = "memcpy";
353 Names[RTLIB::MEMMOVE] = "memmove";
354 Names[RTLIB::MEMSET] = "memset";
355 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
356 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
357 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
358 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
359 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]360 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
362 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
363 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
364 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]365 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
367 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
368 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
369 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]370 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]371 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
372 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
373 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
374 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]375 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]376 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
377 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
378 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
379 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]380 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]381 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
382 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
383 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
384 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]385 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]386 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
387 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
388 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
389 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]390 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]391 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
392 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
393 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
394 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]395 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]396 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
397 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
398 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
399 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
400 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
401 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
402 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
403 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
404 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
405 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
406 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
407 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
408 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
409 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
410 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
411 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
412 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
413 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
414 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
415 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]416
417 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
418 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1";
419 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2";
420 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4";
421 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8";
422 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16";
423
424 Names[RTLIB::ATOMIC_STORE] = "__atomic_store";
425 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1";
426 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2";
427 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4";
428 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8";
429 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16";
430
431 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange";
432 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1";
433 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2";
434 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4";
435 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8";
436 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16";
437
438 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange";
439 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1";
440 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2";
441 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4";
442 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8";
443 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16";
444
445 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1";
446 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2";
447 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4";
448 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8";
449 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16";
450 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1";
451 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2";
452 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4";
453 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8";
454 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16";
455 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1";
456 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2";
457 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4";
458 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8";
459 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16";
460 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1";
461 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2";
462 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4";
463 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8";
464 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16";
465 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1";
466 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2";
467 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4";
468 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8";
469 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16";
470 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1";
471 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2";
472 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4";
473 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8";
474 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16";
475
Daniel Sandersbf2c03e2016-06-21 12:29:03 +0000[diff] [blame]476 if (TT.isGNUEnvironment()) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]477 Names[RTLIB::SINCOS_F32] = "sincosf";
478 Names[RTLIB::SINCOS_F64] = "sincos";
479 Names[RTLIB::SINCOS_F80] = "sincosl";
480 Names[RTLIB::SINCOS_F128] = "sincosl";
481 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]482 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]483
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]484 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]485 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]486 }
Sanjoy Dasdf9ae702016-03-24 20:23:29 +0000[diff] [blame]487
488 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]489}
490
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame^]491/// Set default libcall CallingConvs.
492static void InitLibcallCallingConvs(CallingConv::ID *CCs, const Triple &T) {
493 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
494 CCs[LC] = CallingConv::C;
495
496 // The builtins on ARM always use AAPCS, irrespective of wheter C is AAPCS or
497 // AAPCS_VFP.
498 if (T.getArch() == Triple::arm || T.getArch() == Triple::thumb)
499 for (const auto LC : {
500 RTLIB::SHL_I16,
501 RTLIB::SHL_I32,
502 RTLIB::SHL_I64,
503 RTLIB::SHL_I128,
504 RTLIB::SRL_I16,
505 RTLIB::SRL_I32,
506 RTLIB::SRL_I64,
507 RTLIB::SRL_I128,
508 RTLIB::SRA_I16,
509 RTLIB::SRA_I32,
510 RTLIB::SRA_I64,
511 RTLIB::SRA_I128,
512 RTLIB::MUL_I8,
513 RTLIB::MUL_I16,
514 RTLIB::MUL_I32,
515 RTLIB::MUL_I64,
516 RTLIB::MUL_I128,
517 RTLIB::MULO_I32,
518 RTLIB::MULO_I64,
519 RTLIB::MULO_I128,
520 RTLIB::SDIV_I8,
521 RTLIB::SDIV_I16,
522 RTLIB::SDIV_I32,
523 RTLIB::SDIV_I64,
524 RTLIB::SDIV_I128,
525 RTLIB::UDIV_I8,
526 RTLIB::UDIV_I16,
527 RTLIB::UDIV_I32,
528 RTLIB::UDIV_I64,
529 RTLIB::UDIV_I128,
530 RTLIB::SREM_I8,
531 RTLIB::SREM_I16,
532 RTLIB::SREM_I32,
533 RTLIB::SREM_I64,
534 RTLIB::SREM_I128,
535 RTLIB::UREM_I8,
536 RTLIB::UREM_I16,
537 RTLIB::UREM_I32,
538 RTLIB::UREM_I64,
539 RTLIB::UREM_I128,
540 RTLIB::SDIVREM_I8,
541 RTLIB::SDIVREM_I16,
542 RTLIB::SDIVREM_I32,
543 RTLIB::SDIVREM_I64,
544 RTLIB::SDIVREM_I128,
545 RTLIB::UDIVREM_I8,
546 RTLIB::UDIVREM_I16,
547 RTLIB::UDIVREM_I32,
548 RTLIB::UDIVREM_I64,
549 RTLIB::UDIVREM_I128,
550 RTLIB::NEG_I32,
551 RTLIB::NEG_I64,
552 RTLIB::ADD_F32,
553 RTLIB::ADD_F64,
554 RTLIB::ADD_F80,
555 RTLIB::ADD_F128,
556 RTLIB::SUB_F32,
557 RTLIB::SUB_F64,
558 RTLIB::SUB_F80,
559 RTLIB::SUB_F128,
560 RTLIB::MUL_F32,
561 RTLIB::MUL_F64,
562 RTLIB::MUL_F80,
563 RTLIB::MUL_F128,
564 RTLIB::DIV_F32,
565 RTLIB::DIV_F64,
566 RTLIB::DIV_F80,
567 RTLIB::DIV_F128,
568 RTLIB::POWI_F32,
569 RTLIB::POWI_F64,
570 RTLIB::POWI_F80,
571 RTLIB::POWI_F128,
572 RTLIB::FPEXT_F64_F128,
573 RTLIB::FPEXT_F32_F128,
574 RTLIB::FPEXT_F32_F64,
575 RTLIB::FPEXT_F16_F32,
576 RTLIB::FPROUND_F32_F16,
577 RTLIB::FPROUND_F64_F16,
578 RTLIB::FPROUND_F80_F16,
579 RTLIB::FPROUND_F128_F16,
580 RTLIB::FPROUND_F64_F32,
581 RTLIB::FPROUND_F80_F32,
582 RTLIB::FPROUND_F128_F32,
583 RTLIB::FPROUND_F80_F64,
584 RTLIB::FPROUND_F128_F64,
585 RTLIB::FPTOSINT_F32_I32,
586 RTLIB::FPTOSINT_F32_I64,
587 RTLIB::FPTOSINT_F32_I128,
588 RTLIB::FPTOSINT_F64_I32,
589 RTLIB::FPTOSINT_F64_I64,
590 RTLIB::FPTOSINT_F64_I128,
591 RTLIB::FPTOSINT_F80_I32,
592 RTLIB::FPTOSINT_F80_I64,
593 RTLIB::FPTOSINT_F80_I128,
594 RTLIB::FPTOSINT_F128_I32,
595 RTLIB::FPTOSINT_F128_I64,
596 RTLIB::FPTOSINT_F128_I128,
597 RTLIB::FPTOUINT_F32_I32,
598 RTLIB::FPTOUINT_F32_I64,
599 RTLIB::FPTOUINT_F32_I128,
600 RTLIB::FPTOUINT_F64_I32,
601 RTLIB::FPTOUINT_F64_I64,
602 RTLIB::FPTOUINT_F64_I128,
603 RTLIB::FPTOUINT_F80_I32,
604 RTLIB::FPTOUINT_F80_I64,
605 RTLIB::FPTOUINT_F80_I128,
606 RTLIB::FPTOUINT_F128_I32,
607 RTLIB::FPTOUINT_F128_I64,
608 RTLIB::FPTOUINT_F128_I128,
609 RTLIB::SINTTOFP_I32_F32,
610 RTLIB::SINTTOFP_I32_F64,
611 RTLIB::SINTTOFP_I32_F80,
612 RTLIB::SINTTOFP_I32_F128,
613 RTLIB::SINTTOFP_I64_F32,
614 RTLIB::SINTTOFP_I64_F64,
615 RTLIB::SINTTOFP_I64_F80,
616 RTLIB::SINTTOFP_I64_F128,
617 RTLIB::SINTTOFP_I128_F32,
618 RTLIB::SINTTOFP_I128_F64,
619 RTLIB::SINTTOFP_I128_F80,
620 RTLIB::SINTTOFP_I128_F128,
621 RTLIB::UINTTOFP_I32_F32,
622 RTLIB::UINTTOFP_I32_F64,
623 RTLIB::UINTTOFP_I32_F80,
624 RTLIB::UINTTOFP_I32_F128,
625 RTLIB::UINTTOFP_I64_F32,
626 RTLIB::UINTTOFP_I64_F64,
627 RTLIB::UINTTOFP_I64_F80,
628 RTLIB::UINTTOFP_I64_F128,
629 RTLIB::UINTTOFP_I128_F32,
630 RTLIB::UINTTOFP_I128_F64,
631 RTLIB::UINTTOFP_I128_F80,
632 RTLIB::UINTTOFP_I128_F128,
633 RTLIB::OEQ_F32,
634 RTLIB::OEQ_F64,
635 RTLIB::OEQ_F128,
636 RTLIB::UNE_F32,
637 RTLIB::UNE_F64,
638 RTLIB::UNE_F128,
639 RTLIB::OGE_F32,
640 RTLIB::OGE_F64,
641 RTLIB::OGE_F128,
642 RTLIB::OLT_F32,
643 RTLIB::OLT_F64,
644 RTLIB::OLT_F128,
645 RTLIB::OLE_F32,
646 RTLIB::OLE_F64,
647 RTLIB::OLE_F128,
648 RTLIB::OGT_F32,
649 RTLIB::OGT_F64,
650 RTLIB::OGT_F128,
651 RTLIB::UO_F32,
652 RTLIB::UO_F64,
653 RTLIB::UO_F128,
654 RTLIB::O_F32,
655 RTLIB::O_F64,
656 RTLIB::O_F128,
657 })
658 CCs[LC] = CallingConv::ARM_AAPCS;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]659}
660
661/// getFPEXT - Return the FPEXT_*_* value for the given types, or
662/// UNKNOWN_LIBCALL if there is none.
663RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]664 if (OpVT == MVT::f16) {
665 if (RetVT == MVT::f32)
666 return FPEXT_F16_F32;
667 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]668 if (RetVT == MVT::f64)
669 return FPEXT_F32_F64;
670 if (RetVT == MVT::f128)
671 return FPEXT_F32_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]672 if (RetVT == MVT::ppcf128)
673 return FPEXT_F32_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]674 } else if (OpVT == MVT::f64) {
675 if (RetVT == MVT::f128)
676 return FPEXT_F64_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]677 else if (RetVT == MVT::ppcf128)
678 return FPEXT_F64_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]679 }
680
681 return UNKNOWN_LIBCALL;
682}
683
684/// getFPROUND - Return the FPROUND_*_* value for the given types, or
685/// UNKNOWN_LIBCALL if there is none.
686RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]687 if (RetVT == MVT::f16) {
688 if (OpVT == MVT::f32)
689 return FPROUND_F32_F16;
690 if (OpVT == MVT::f64)
691 return FPROUND_F64_F16;
692 if (OpVT == MVT::f80)
693 return FPROUND_F80_F16;
694 if (OpVT == MVT::f128)
695 return FPROUND_F128_F16;
696 if (OpVT == MVT::ppcf128)
697 return FPROUND_PPCF128_F16;
698 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]699 if (OpVT == MVT::f64)
700 return FPROUND_F64_F32;
701 if (OpVT == MVT::f80)
702 return FPROUND_F80_F32;
703 if (OpVT == MVT::f128)
704 return FPROUND_F128_F32;
705 if (OpVT == MVT::ppcf128)
706 return FPROUND_PPCF128_F32;
707 } else if (RetVT == MVT::f64) {
708 if (OpVT == MVT::f80)
709 return FPROUND_F80_F64;
710 if (OpVT == MVT::f128)
711 return FPROUND_F128_F64;
712 if (OpVT == MVT::ppcf128)
713 return FPROUND_PPCF128_F64;
714 }
715
716 return UNKNOWN_LIBCALL;
717}
718
719/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
720/// UNKNOWN_LIBCALL if there is none.
721RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
722 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]723 if (RetVT == MVT::i32)
724 return FPTOSINT_F32_I32;
725 if (RetVT == MVT::i64)
726 return FPTOSINT_F32_I64;
727 if (RetVT == MVT::i128)
728 return FPTOSINT_F32_I128;
729 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]730 if (RetVT == MVT::i32)
731 return FPTOSINT_F64_I32;
732 if (RetVT == MVT::i64)
733 return FPTOSINT_F64_I64;
734 if (RetVT == MVT::i128)
735 return FPTOSINT_F64_I128;
736 } else if (OpVT == MVT::f80) {
737 if (RetVT == MVT::i32)
738 return FPTOSINT_F80_I32;
739 if (RetVT == MVT::i64)
740 return FPTOSINT_F80_I64;
741 if (RetVT == MVT::i128)
742 return FPTOSINT_F80_I128;
743 } else if (OpVT == MVT::f128) {
744 if (RetVT == MVT::i32)
745 return FPTOSINT_F128_I32;
746 if (RetVT == MVT::i64)
747 return FPTOSINT_F128_I64;
748 if (RetVT == MVT::i128)
749 return FPTOSINT_F128_I128;
750 } else if (OpVT == MVT::ppcf128) {
751 if (RetVT == MVT::i32)
752 return FPTOSINT_PPCF128_I32;
753 if (RetVT == MVT::i64)
754 return FPTOSINT_PPCF128_I64;
755 if (RetVT == MVT::i128)
756 return FPTOSINT_PPCF128_I128;
757 }
758 return UNKNOWN_LIBCALL;
759}
760
761/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
762/// UNKNOWN_LIBCALL if there is none.
763RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
764 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]765 if (RetVT == MVT::i32)
766 return FPTOUINT_F32_I32;
767 if (RetVT == MVT::i64)
768 return FPTOUINT_F32_I64;
769 if (RetVT == MVT::i128)
770 return FPTOUINT_F32_I128;
771 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]772 if (RetVT == MVT::i32)
773 return FPTOUINT_F64_I32;
774 if (RetVT == MVT::i64)
775 return FPTOUINT_F64_I64;
776 if (RetVT == MVT::i128)
777 return FPTOUINT_F64_I128;
778 } else if (OpVT == MVT::f80) {
779 if (RetVT == MVT::i32)
780 return FPTOUINT_F80_I32;
781 if (RetVT == MVT::i64)
782 return FPTOUINT_F80_I64;
783 if (RetVT == MVT::i128)
784 return FPTOUINT_F80_I128;
785 } else if (OpVT == MVT::f128) {
786 if (RetVT == MVT::i32)
787 return FPTOUINT_F128_I32;
788 if (RetVT == MVT::i64)
789 return FPTOUINT_F128_I64;
790 if (RetVT == MVT::i128)
791 return FPTOUINT_F128_I128;
792 } else if (OpVT == MVT::ppcf128) {
793 if (RetVT == MVT::i32)
794 return FPTOUINT_PPCF128_I32;
795 if (RetVT == MVT::i64)
796 return FPTOUINT_PPCF128_I64;
797 if (RetVT == MVT::i128)
798 return FPTOUINT_PPCF128_I128;
799 }
800 return UNKNOWN_LIBCALL;
801}
802
803/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
804/// UNKNOWN_LIBCALL if there is none.
805RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
806 if (OpVT == MVT::i32) {
807 if (RetVT == MVT::f32)
808 return SINTTOFP_I32_F32;
809 if (RetVT == MVT::f64)
810 return SINTTOFP_I32_F64;
811 if (RetVT == MVT::f80)
812 return SINTTOFP_I32_F80;
813 if (RetVT == MVT::f128)
814 return SINTTOFP_I32_F128;
815 if (RetVT == MVT::ppcf128)
816 return SINTTOFP_I32_PPCF128;
817 } else if (OpVT == MVT::i64) {
818 if (RetVT == MVT::f32)
819 return SINTTOFP_I64_F32;
820 if (RetVT == MVT::f64)
821 return SINTTOFP_I64_F64;
822 if (RetVT == MVT::f80)
823 return SINTTOFP_I64_F80;
824 if (RetVT == MVT::f128)
825 return SINTTOFP_I64_F128;
826 if (RetVT == MVT::ppcf128)
827 return SINTTOFP_I64_PPCF128;
828 } else if (OpVT == MVT::i128) {
829 if (RetVT == MVT::f32)
830 return SINTTOFP_I128_F32;
831 if (RetVT == MVT::f64)
832 return SINTTOFP_I128_F64;
833 if (RetVT == MVT::f80)
834 return SINTTOFP_I128_F80;
835 if (RetVT == MVT::f128)
836 return SINTTOFP_I128_F128;
837 if (RetVT == MVT::ppcf128)
838 return SINTTOFP_I128_PPCF128;
839 }
840 return UNKNOWN_LIBCALL;
841}
842
843/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
844/// UNKNOWN_LIBCALL if there is none.
845RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
846 if (OpVT == MVT::i32) {
847 if (RetVT == MVT::f32)
848 return UINTTOFP_I32_F32;
849 if (RetVT == MVT::f64)
850 return UINTTOFP_I32_F64;
851 if (RetVT == MVT::f80)
852 return UINTTOFP_I32_F80;
853 if (RetVT == MVT::f128)
854 return UINTTOFP_I32_F128;
855 if (RetVT == MVT::ppcf128)
856 return UINTTOFP_I32_PPCF128;
857 } else if (OpVT == MVT::i64) {
858 if (RetVT == MVT::f32)
859 return UINTTOFP_I64_F32;
860 if (RetVT == MVT::f64)
861 return UINTTOFP_I64_F64;
862 if (RetVT == MVT::f80)
863 return UINTTOFP_I64_F80;
864 if (RetVT == MVT::f128)
865 return UINTTOFP_I64_F128;
866 if (RetVT == MVT::ppcf128)
867 return UINTTOFP_I64_PPCF128;
868 } else if (OpVT == MVT::i128) {
869 if (RetVT == MVT::f32)
870 return UINTTOFP_I128_F32;
871 if (RetVT == MVT::f64)
872 return UINTTOFP_I128_F64;
873 if (RetVT == MVT::f80)
874 return UINTTOFP_I128_F80;
875 if (RetVT == MVT::f128)
876 return UINTTOFP_I128_F128;
877 if (RetVT == MVT::ppcf128)
878 return UINTTOFP_I128_PPCF128;
879 }
880 return UNKNOWN_LIBCALL;
881}
882
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]883RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]884#define OP_TO_LIBCALL(Name, Enum) \
885 case Name: \
886 switch (VT.SimpleTy) { \
887 default: \
888 return UNKNOWN_LIBCALL; \
889 case MVT::i8: \
890 return Enum##_1; \
891 case MVT::i16: \
892 return Enum##_2; \
893 case MVT::i32: \
894 return Enum##_4; \
895 case MVT::i64: \
896 return Enum##_8; \
897 case MVT::i128: \
898 return Enum##_16; \
899 }
900
901 switch (Opc) {
902 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
903 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
904 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
905 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
906 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
907 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
908 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
909 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
910 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
911 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
912 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
913 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
914 }
915
916#undef OP_TO_LIBCALL
917
918 return UNKNOWN_LIBCALL;
919}
920
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]921/// InitCmpLibcallCCs - Set default comparison libcall CC.
922///
923static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
924 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
925 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
926 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
927 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]928 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]929 CCs[RTLIB::UNE_F32] = ISD::SETNE;
930 CCs[RTLIB::UNE_F64] = ISD::SETNE;
931 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]932 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]933 CCs[RTLIB::OGE_F32] = ISD::SETGE;
934 CCs[RTLIB::OGE_F64] = ISD::SETGE;
935 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]936 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]937 CCs[RTLIB::OLT_F32] = ISD::SETLT;
938 CCs[RTLIB::OLT_F64] = ISD::SETLT;
939 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]940 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]941 CCs[RTLIB::OLE_F32] = ISD::SETLE;
942 CCs[RTLIB::OLE_F64] = ISD::SETLE;
943 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]944 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]945 CCs[RTLIB::OGT_F32] = ISD::SETGT;
946 CCs[RTLIB::OGT_F64] = ISD::SETGT;
947 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]948 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]949 CCs[RTLIB::UO_F32] = ISD::SETNE;
950 CCs[RTLIB::UO_F64] = ISD::SETNE;
951 CCs[RTLIB::UO_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]952 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]953 CCs[RTLIB::O_F32] = ISD::SETEQ;
954 CCs[RTLIB::O_F64] = ISD::SETEQ;
955 CCs[RTLIB::O_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]956 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]957}
958
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]959/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]960TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]961 initActions();
962
963 // Perform these initializations only once.
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]964 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
965 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
966 = MaxStoresPerMemmoveOptSize = 4;
967 UseUnderscoreSetJmp = false;
968 UseUnderscoreLongJmp = false;
969 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]970 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]971 HasExtractBitsInsn = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]972 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]973 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]974 MaskAndBranchFoldingIsLegal = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]975 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]976 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]977 StackPointerRegisterToSaveRestore = 0;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]978 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]979 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]980 BooleanVectorContents = UndefinedBooleanContent;
981 SchedPreferenceInfo = Sched::ILP;
982 JumpBufSize = 0;
983 JumpBufAlignment = 0;
984 MinFunctionAlignment = 0;
985 PrefFunctionAlignment = 0;
986 PrefLoopAlignment = 0;
Matt Arsenaultd8fed1b2015-11-11 18:44:33 +0000[diff] [blame]987 GatherAllAliasesMaxDepth = 6;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]988 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]989 MinimumJumpTableEntries = 4;
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]990 // TODO: the default will be switched to 0 in the next commit, along
991 // with the Target-specific changes necessary.
992 MaxAtomicSizeInBitsSupported = 1024;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]993
James Y Knight148a6462016-06-17 18:11:48 +0000[diff] [blame]994 MinCmpXchgSizeInBits = 0;
995
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]996 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
997
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]998 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]999 InitCmpLibcallCCs(CmpLibcallCCs);
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame^]1000 InitLibcallCallingConvs(LibcallCallingConvs, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]1001}
1002
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]1003void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1004 // All operations default to being supported.
1005 memset(OpActions, 0, sizeof(OpActions));
1006 memset(LoadExtActions, 0, sizeof(LoadExtActions));
1007 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
1008 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
1009 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Craig Topper00230802016-04-08 07:10:46 +0000[diff] [blame]1010 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
1011 std::fill(std::begin(TargetDAGCombineArray),
1012 std::end(TargetDAGCombineArray), 0);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1013
1014 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]1015 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1016 // Default all indexed load / store to expand.
1017 for (unsigned IM = (unsigned)ISD::PRE_INC;
1018 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]1019 setIndexedLoadAction(IM, VT, Expand);
1020 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1021 }
1022
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]1023 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]1024 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]1025
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1026 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]1027 setOperationAction(ISD::FGETSIGN, VT, Expand);
1028 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
1029 setOperationAction(ISD::FMINNUM, VT, Expand);
1030 setOperationAction(ISD::FMAXNUM, VT, Expand);
James Molloy01cdecc2015-08-11 09:13:05 +0000[diff] [blame]1031 setOperationAction(ISD::FMINNAN, VT, Expand);
1032 setOperationAction(ISD::FMAXNAN, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]1033 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]1034 setOperationAction(ISD::SMIN, VT, Expand);
1035 setOperationAction(ISD::SMAX, VT, Expand);
1036 setOperationAction(ISD::UMIN, VT, Expand);
1037 setOperationAction(ISD::UMAX, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]1038
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]1039 // Overflow operations default to expand
1040 setOperationAction(ISD::SADDO, VT, Expand);
1041 setOperationAction(ISD::SSUBO, VT, Expand);
1042 setOperationAction(ISD::UADDO, VT, Expand);
1043 setOperationAction(ISD::USUBO, VT, Expand);
1044 setOperationAction(ISD::SMULO, VT, Expand);
1045 setOperationAction(ISD::UMULO, VT, Expand);
Hal Finkelcd8664c2015-12-11 23:11:52 +0000[diff] [blame]1046
Craig Topper33772c52016-04-28 03:34:31 +0000[diff] [blame]1047 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
1048 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
1049 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
1050
James Molloy90111f72015-11-12 12:29:09 +0000[diff] [blame]1051 setOperationAction(ISD::BITREVERSE, VT, Expand);
1052
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]1053 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]1054 setOperationAction(ISD::FROUND, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]1055
1056 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]1057 if (VT.isVector()) {
1058 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
1059 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
1060 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
1061 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]1062 }
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]1063
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]1064 // For most targets @llvm.get.dynamic.area.offset just returns 0.
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]1065 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1066 }
1067
1068 // Most targets ignore the @llvm.prefetch intrinsic.
1069 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
1070
Ahmed Bougachaf9c19da2015-08-28 01:49:59 +0000[diff] [blame]1071 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
1072 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
1073
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1074 // ConstantFP nodes default to expand. Targets can either change this to
1075 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
1076 // to optimize expansions for certain constants.
1077 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
1078 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
1079 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
1080 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
1081 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
1082
1083 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]1084 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
1085 setOperationAction(ISD::FLOG , VT, Expand);
1086 setOperationAction(ISD::FLOG2, VT, Expand);
1087 setOperationAction(ISD::FLOG10, VT, Expand);
1088 setOperationAction(ISD::FEXP , VT, Expand);
1089 setOperationAction(ISD::FEXP2, VT, Expand);
1090 setOperationAction(ISD::FFLOOR, VT, Expand);
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]1091 setOperationAction(ISD::FNEARBYINT, VT, Expand);
1092 setOperationAction(ISD::FCEIL, VT, Expand);
1093 setOperationAction(ISD::FRINT, VT, Expand);
1094 setOperationAction(ISD::FTRUNC, VT, Expand);
1095 setOperationAction(ISD::FROUND, VT, Expand);
1096 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1097
1098 // Default ISD::TRAP to expand (which turns it into abort).
1099 setOperationAction(ISD::TRAP, MVT::Other, Expand);
1100
1101 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1102 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1103 //
1104 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1105}
1106
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]1107MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1108 EVT) const {
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]1109 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1110}
1111
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]1112EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1113 const DataLayout &DL) const {
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]1114 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1115 if (LHSTy.isVector())
1116 return LHSTy;
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]1117 return getScalarShiftAmountTy(DL, LHSTy);
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]1118}
1119
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1120bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1121 assert(isTypeLegal(VT));
1122 switch (Op) {
1123 default:
1124 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1125 case ISD::SDIV:
1126 case ISD::UDIV:
1127 case ISD::SREM:
1128 case ISD::UREM:
1129 return true;
1130 }
1131}
1132
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]1133void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1134 // If the command-line option was specified, ignore this request.
1135 if (!JumpIsExpensiveOverride.getNumOccurrences())
1136 JumpIsExpensive = isExpensive;
1137}
1138
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]1139TargetLoweringBase::LegalizeKind
1140TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1141 // If this is a simple type, use the ComputeRegisterProp mechanism.
1142 if (VT.isSimple()) {
1143 MVT SVT = VT.getSimpleVT();
1144 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1145 MVT NVT = TransformToType[SVT.SimpleTy];
1146 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1147
1148 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1149 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
1150 "Promote may not follow Expand or Promote");
1151
1152 if (LA == TypeSplitVector)
1153 return LegalizeKind(LA,
1154 EVT::getVectorVT(Context, SVT.getVectorElementType(),
1155 SVT.getVectorNumElements() / 2));
1156 if (LA == TypeScalarizeVector)
1157 return LegalizeKind(LA, SVT.getVectorElementType());
1158 return LegalizeKind(LA, NVT);
1159 }
1160
1161 // Handle Extended Scalar Types.
1162 if (!VT.isVector()) {
1163 assert(VT.isInteger() && "Float types must be simple");
1164 unsigned BitSize = VT.getSizeInBits();
1165 // First promote to a power-of-two size, then expand if necessary.
1166 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1167 EVT NVT = VT.getRoundIntegerType(Context);
1168 assert(NVT != VT && "Unable to round integer VT");
1169 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1170 // Avoid multi-step promotion.
1171 if (NextStep.first == TypePromoteInteger)
1172 return NextStep;
1173 // Return rounded integer type.
1174 return LegalizeKind(TypePromoteInteger, NVT);
1175 }
1176
1177 return LegalizeKind(TypeExpandInteger,
1178 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1179 }
1180
1181 // Handle vector types.
1182 unsigned NumElts = VT.getVectorNumElements();
1183 EVT EltVT = VT.getVectorElementType();
1184
1185 // Vectors with only one element are always scalarized.
1186 if (NumElts == 1)
1187 return LegalizeKind(TypeScalarizeVector, EltVT);
1188
1189 // Try to widen vector elements until the element type is a power of two and
1190 // promote it to a legal type later on, for example:
1191 // <3 x i8> -> <4 x i8> -> <4 x i32>
1192 if (EltVT.isInteger()) {
1193 // Vectors with a number of elements that is not a power of two are always
1194 // widened, for example <3 x i8> -> <4 x i8>.
1195 if (!VT.isPow2VectorType()) {
1196 NumElts = (unsigned)NextPowerOf2(NumElts);
1197 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1198 return LegalizeKind(TypeWidenVector, NVT);
1199 }
1200
1201 // Examine the element type.
1202 LegalizeKind LK = getTypeConversion(Context, EltVT);
1203
1204 // If type is to be expanded, split the vector.
1205 // <4 x i140> -> <2 x i140>
1206 if (LK.first == TypeExpandInteger)
1207 return LegalizeKind(TypeSplitVector,
1208 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1209
1210 // Promote the integer element types until a legal vector type is found
1211 // or until the element integer type is too big. If a legal type was not
1212 // found, fallback to the usual mechanism of widening/splitting the
1213 // vector.
1214 EVT OldEltVT = EltVT;
1215 while (1) {
1216 // Increase the bitwidth of the element to the next pow-of-two
1217 // (which is greater than 8 bits).
1218 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1219 .getRoundIntegerType(Context);
1220
1221 // Stop trying when getting a non-simple element type.
1222 // Note that vector elements may be greater than legal vector element
1223 // types. Example: X86 XMM registers hold 64bit element on 32bit
1224 // systems.
1225 if (!EltVT.isSimple())
1226 break;
1227
1228 // Build a new vector type and check if it is legal.
1229 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1230 // Found a legal promoted vector type.
1231 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1232 return LegalizeKind(TypePromoteInteger,
1233 EVT::getVectorVT(Context, EltVT, NumElts));
1234 }
1235
1236 // Reset the type to the unexpanded type if we did not find a legal vector
1237 // type with a promoted vector element type.
1238 EltVT = OldEltVT;
1239 }
1240
1241 // Try to widen the vector until a legal type is found.
1242 // If there is no wider legal type, split the vector.
1243 while (1) {
1244 // Round up to the next power of 2.
1245 NumElts = (unsigned)NextPowerOf2(NumElts);
1246
1247 // If there is no simple vector type with this many elements then there
1248 // cannot be a larger legal vector type. Note that this assumes that
1249 // there are no skipped intermediate vector types in the simple types.
1250 if (!EltVT.isSimple())
1251 break;
1252 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1253 if (LargerVector == MVT())
1254 break;
1255
1256 // If this type is legal then widen the vector.
1257 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1258 return LegalizeKind(TypeWidenVector, LargerVector);
1259 }
1260
1261 // Widen odd vectors to next power of two.
1262 if (!VT.isPow2VectorType()) {
1263 EVT NVT = VT.getPow2VectorType(Context);
1264 return LegalizeKind(TypeWidenVector, NVT);
1265 }
1266
1267 // Vectors with illegal element types are expanded.
1268 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1269 return LegalizeKind(TypeSplitVector, NVT);
1270}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1271
1272static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1273 unsigned &NumIntermediates,
1274 MVT &RegisterVT,
1275 TargetLoweringBase *TLI) {
1276 // Figure out the right, legal destination reg to copy into.
1277 unsigned NumElts = VT.getVectorNumElements();
1278 MVT EltTy = VT.getVectorElementType();
1279
1280 unsigned NumVectorRegs = 1;
1281
1282 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1283 // could break down into LHS/RHS like LegalizeDAG does.
1284 if (!isPowerOf2_32(NumElts)) {
1285 NumVectorRegs = NumElts;
1286 NumElts = 1;
1287 }
1288
1289 // Divide the input until we get to a supported size. This will always
1290 // end with a scalar if the target doesn't support vectors.
1291 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1292 NumElts >>= 1;
1293 NumVectorRegs <<= 1;
1294 }
1295
1296 NumIntermediates = NumVectorRegs;
1297
1298 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1299 if (!TLI->isTypeLegal(NewVT))
1300 NewVT = EltTy;
1301 IntermediateVT = NewVT;
1302
1303 unsigned NewVTSize = NewVT.getSizeInBits();
1304
1305 // Convert sizes such as i33 to i64.
1306 if (!isPowerOf2_32(NewVTSize))
1307 NewVTSize = NextPowerOf2(NewVTSize);
1308
1309 MVT DestVT = TLI->getRegisterType(NewVT);
1310 RegisterVT = DestVT;
1311 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1312 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1313
1314 // Otherwise, promotion or legal types use the same number of registers as
1315 // the vector decimated to the appropriate level.
1316 return NumVectorRegs;
1317}
1318
1319/// isLegalRC - Return true if the value types that can be represented by the
1320/// specified register class are all legal.
1321bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
1322 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1323 I != E; ++I) {
1324 if (isTypeLegal(*I))
1325 return true;
1326 }
1327 return false;
1328}
1329
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1330/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1331/// sequence of memory operands that is recognized by PrologEpilogInserter.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1332MachineBasicBlock *
1333TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1334 MachineBasicBlock *MBB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1335 MachineInstr *MI = &InitialMI;
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1336 MachineFunction &MF = *MI->getParent()->getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]1337 MachineFrameInfo &MFI = MF.getFrameInfo();
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1338
1339 // We're handling multiple types of operands here:
1340 // PATCHPOINT MetaArgs - live-in, read only, direct
1341 // STATEPOINT Deopt Spill - live-through, read only, indirect
1342 // STATEPOINT Deopt Alloca - live-through, read only, direct
1343 // (We're currently conservative and mark the deopt slots read/write in
1344 // practice.)
1345 // STATEPOINT GC Spill - live-through, read/write, indirect
1346 // STATEPOINT GC Alloca - live-through, read/write, direct
1347 // The live-in vs live-through is handled already (the live through ones are
1348 // all stack slots), but we need to handle the different type of stackmap
1349 // operands and memory effects here.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1350
1351 // MI changes inside this loop as we grow operands.
1352 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1353 MachineOperand &MO = MI->getOperand(OperIdx);
1354 if (!MO.isFI())
1355 continue;
1356
1357 // foldMemoryOperand builds a new MI after replacing a single FI operand
1358 // with the canonical set of five x86 addressing-mode operands.
1359 int FI = MO.getIndex();
1360 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1361
1362 // Copy operands before the frame-index.
1363 for (unsigned i = 0; i < OperIdx; ++i)
1364 MIB.addOperand(MI->getOperand(i));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1365 // Add frame index operands recognized by stackmaps.cpp
1366 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1367 // indirect-mem-ref tag, size, #FI, offset.
1368 // Used for spills inserted by StatepointLowering. This codepath is not
1369 // used for patchpoints/stackmaps at all, for these spilling is done via
1370 // foldMemoryOperand callback only.
1371 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1372 MIB.addImm(StackMaps::IndirectMemRefOp);
1373 MIB.addImm(MFI.getObjectSize(FI));
1374 MIB.addOperand(MI->getOperand(OperIdx));
1375 MIB.addImm(0);
1376 } else {
1377 // direct-mem-ref tag, #FI, offset.
1378 // Used by patchpoint, and direct alloca arguments to statepoints
1379 MIB.addImm(StackMaps::DirectMemRefOp);
1380 MIB.addOperand(MI->getOperand(OperIdx));
1381 MIB.addImm(0);
1382 }
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1383 // Copy the operands after the frame index.
1384 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1385 MIB.addOperand(MI->getOperand(i));
1386
1387 // Inherit previous memory operands.
1388 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1389 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1390
1391 // Add a new memory operand for this FI.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1392 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1393
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]1394 auto Flags = MachineMemOperand::MOLoad;
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1395 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1396 Flags |= MachineMemOperand::MOStore;
1397 Flags |= MachineMemOperand::MOVolatile;
1398 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1399 MachineMemOperand *MMO = MF.getMachineMemOperand(
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]1400 MachinePointerInfo::getFixedStack(MF, FI), Flags,
Mehdi Aminibd7287e2015-07-16 06:11:10 +0000[diff] [blame]1401 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1402 MIB->addMemOperand(MF, MMO);
1403
1404 // Replace the instruction and update the operand index.
1405 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1406 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1407 MI->eraseFromParent();
1408 MI = MIB;
1409 }
1410 return MBB;
1411}
1412
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1413/// findRepresentativeClass - Return the largest legal super-reg register class
1414/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1415// This function is in TargetLowering because it uses RegClassForVT which would
1416// need to be moved to TargetRegisterInfo and would necessitate moving
1417// isTypeLegal over as well - a massive change that would just require
1418// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1419std::pair<const TargetRegisterClass *, uint8_t>
1420TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1421 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1422 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1423 if (!RC)
1424 return std::make_pair(RC, 0);
1425
1426 // Compute the set of all super-register classes.
1427 BitVector SuperRegRC(TRI->getNumRegClasses());
1428 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1429 SuperRegRC.setBitsInMask(RCI.getMask());
1430
1431 // Find the first legal register class with the largest spill size.
1432 const TargetRegisterClass *BestRC = RC;
1433 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1434 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1435 // We want the largest possible spill size.
1436 if (SuperRC->getSize() <= BestRC->getSize())
1437 continue;
1438 if (!isLegalRC(SuperRC))
1439 continue;
1440 BestRC = SuperRC;
1441 }
1442 return std::make_pair(BestRC, 1);
1443}
1444
1445/// computeRegisterProperties - Once all of the register classes are added,
1446/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1447void TargetLoweringBase::computeRegisterProperties(
1448 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1449 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1450 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1451
1452 // Everything defaults to needing one register.
1453 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1454 NumRegistersForVT[i] = 1;
1455 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1456 }
1457 // ...except isVoid, which doesn't need any registers.
1458 NumRegistersForVT[MVT::isVoid] = 0;
1459
1460 // Find the largest integer register class.
1461 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1462 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1463 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1464
1465 // Every integer value type larger than this largest register takes twice as
1466 // many registers to represent as the previous ValueType.
1467 for (unsigned ExpandedReg = LargestIntReg + 1;
1468 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1469 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1470 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1471 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1472 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1473 TypeExpandInteger);
1474 }
1475
1476 // Inspect all of the ValueType's smaller than the largest integer
1477 // register to see which ones need promotion.
1478 unsigned LegalIntReg = LargestIntReg;
1479 for (unsigned IntReg = LargestIntReg - 1;
1480 IntReg >= (unsigned)MVT::i1; --IntReg) {
1481 MVT IVT = (MVT::SimpleValueType)IntReg;
1482 if (isTypeLegal(IVT)) {
1483 LegalIntReg = IntReg;
1484 } else {
1485 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1486 (const MVT::SimpleValueType)LegalIntReg;
1487 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1488 }
1489 }
1490
1491 // ppcf128 type is really two f64's.
1492 if (!isTypeLegal(MVT::ppcf128)) {
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]1493 if (isTypeLegal(MVT::f64)) {
1494 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1495 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1496 TransformToType[MVT::ppcf128] = MVT::f64;
1497 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1498 } else {
1499 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1500 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1501 TransformToType[MVT::ppcf128] = MVT::i128;
1502 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1503 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1504 }
1505
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1506 // Decide how to handle f128. If the target does not have native f128 support,
1507 // expand it to i128 and we will be generating soft float library calls.
1508 if (!isTypeLegal(MVT::f128)) {
1509 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1510 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1511 TransformToType[MVT::f128] = MVT::i128;
1512 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1513 }
1514
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1515 // Decide how to handle f64. If the target does not have native f64 support,
1516 // expand it to i64 and we will be generating soft float library calls.
1517 if (!isTypeLegal(MVT::f64)) {
1518 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1519 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1520 TransformToType[MVT::f64] = MVT::i64;
1521 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1522 }
1523
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1524 // Decide how to handle f32. If the target does not have native f32 support,
1525 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1526 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1527 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1528 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1529 TransformToType[MVT::f32] = MVT::i32;
1530 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1531 }
1532
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1533 // Decide how to handle f16. If the target does not have native f16 support,
1534 // promote it to f32, because there are no f16 library calls (except for
1535 // conversions).
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1536 if (!isTypeLegal(MVT::f16)) {
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1537 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1538 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1539 TransformToType[MVT::f16] = MVT::f32;
1540 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1541 }
1542
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1543 // Loop over all of the vector value types to see which need transformations.
1544 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1545 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1546 MVT VT = (MVT::SimpleValueType) i;
1547 if (isTypeLegal(VT))
1548 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1549
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1550 MVT EltVT = VT.getVectorElementType();
1551 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1552 bool IsLegalWiderType = false;
1553 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1554 switch (PreferredAction) {
1555 case TypePromoteInteger: {
1556 // Try to promote the elements of integer vectors. If no legal
1557 // promotion was found, fall through to the widen-vector method.
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1558 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1559 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1560 // Promote vectors of integers to vectors with the same number
1561 // of elements, with a wider element type.
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1562 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() &&
1563 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1564 TransformToType[i] = SVT;
1565 RegisterTypeForVT[i] = SVT;
1566 NumRegistersForVT[i] = 1;
1567 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1568 IsLegalWiderType = true;
1569 break;
1570 }
1571 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1572 if (IsLegalWiderType)
1573 break;
1574 }
1575 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1576 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1577 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1578 MVT SVT = (MVT::SimpleValueType) nVT;
1579 if (SVT.getVectorElementType() == EltVT
1580 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1581 TransformToType[i] = SVT;
1582 RegisterTypeForVT[i] = SVT;
1583 NumRegistersForVT[i] = 1;
1584 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1585 IsLegalWiderType = true;
1586 break;
1587 }
1588 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1589 if (IsLegalWiderType)
1590 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1591 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1592 case TypeSplitVector:
1593 case TypeScalarizeVector: {
1594 MVT IntermediateVT;
1595 MVT RegisterVT;
1596 unsigned NumIntermediates;
1597 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1598 NumIntermediates, RegisterVT, this);
1599 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1600
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1601 MVT NVT = VT.getPow2VectorType();
1602 if (NVT == VT) {
1603 // Type is already a power of 2. The default action is to split.
1604 TransformToType[i] = MVT::Other;
1605 if (PreferredAction == TypeScalarizeVector)
1606 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1607 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1608 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1609 else
1610 // Set type action according to the number of elements.
1611 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1612 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1613 } else {
1614 TransformToType[i] = NVT;
1615 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1616 }
1617 break;
1618 }
1619 default:
1620 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1621 }
1622 }
1623
1624 // Determine the 'representative' register class for each value type.
1625 // An representative register class is the largest (meaning one which is
1626 // not a sub-register class / subreg register class) legal register class for
1627 // a group of value types. For example, on i386, i8, i16, and i32
1628 // representative would be GR32; while on x86_64 it's GR64.
1629 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1630 const TargetRegisterClass* RRC;
1631 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1632 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1633 RepRegClassForVT[i] = RRC;
1634 RepRegClassCostForVT[i] = Cost;
1635 }
1636}
1637
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1638EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1639 EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1640 assert(!VT.isVector() && "No default SetCC type for vectors!");
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1641 return getPointerTy(DL).SimpleTy;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1642}
1643
1644MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1645 return MVT::i32; // return the default value
1646}
1647
1648/// getVectorTypeBreakdown - Vector types are broken down into some number of
1649/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1650/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1651/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1652///
1653/// This method returns the number of registers needed, and the VT for each
1654/// register. It also returns the VT and quantity of the intermediate values
1655/// before they are promoted/expanded.
1656///
1657unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1658 EVT &IntermediateVT,
1659 unsigned &NumIntermediates,
1660 MVT &RegisterVT) const {
1661 unsigned NumElts = VT.getVectorNumElements();
1662
1663 // If there is a wider vector type with the same element type as this one,
1664 // or a promoted vector type that has the same number of elements which
1665 // are wider, then we should convert to that legal vector type.
1666 // This handles things like <2 x float> -> <4 x float> and
1667 // <4 x i1> -> <4 x i32>.
1668 LegalizeTypeAction TA = getTypeAction(Context, VT);
1669 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1670 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1671 if (isTypeLegal(RegisterEVT)) {
1672 IntermediateVT = RegisterEVT;
1673 RegisterVT = RegisterEVT.getSimpleVT();
1674 NumIntermediates = 1;
1675 return 1;
1676 }
1677 }
1678
1679 // Figure out the right, legal destination reg to copy into.
1680 EVT EltTy = VT.getVectorElementType();
1681
1682 unsigned NumVectorRegs = 1;
1683
1684 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1685 // could break down into LHS/RHS like LegalizeDAG does.
1686 if (!isPowerOf2_32(NumElts)) {
1687 NumVectorRegs = NumElts;
1688 NumElts = 1;
1689 }
1690
1691 // Divide the input until we get to a supported size. This will always
1692 // end with a scalar if the target doesn't support vectors.
1693 while (NumElts > 1 && !isTypeLegal(
1694 EVT::getVectorVT(Context, EltTy, NumElts))) {
1695 NumElts >>= 1;
1696 NumVectorRegs <<= 1;
1697 }
1698
1699 NumIntermediates = NumVectorRegs;
1700
1701 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1702 if (!isTypeLegal(NewVT))
1703 NewVT = EltTy;
1704 IntermediateVT = NewVT;
1705
1706 MVT DestVT = getRegisterType(Context, NewVT);
1707 RegisterVT = DestVT;
1708 unsigned NewVTSize = NewVT.getSizeInBits();
1709
1710 // Convert sizes such as i33 to i64.
1711 if (!isPowerOf2_32(NewVTSize))
1712 NewVTSize = NextPowerOf2(NewVTSize);
1713
1714 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1715 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1716
1717 // Otherwise, promotion or legal types use the same number of registers as
1718 // the vector decimated to the appropriate level.
1719 return NumVectorRegs;
1720}
1721
1722/// Get the EVTs and ArgFlags collections that represent the legalized return
1723/// type of the given function. This does not require a DAG or a return value,
1724/// and is suitable for use before any DAGs for the function are constructed.
1725/// TODO: Move this out of TargetLowering.cpp.
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1726void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1727 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1728 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1729 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1730 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1731 unsigned NumValues = ValueVTs.size();
1732 if (NumValues == 0) return;
1733
1734 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1735 EVT VT = ValueVTs[j];
1736 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1737
1738 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1739 ExtendKind = ISD::SIGN_EXTEND;
1740 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1741 ExtendKind = ISD::ZERO_EXTEND;
1742
1743 // FIXME: C calling convention requires the return type to be promoted to
1744 // at least 32-bit. But this is not necessary for non-C calling
1745 // conventions. The frontend should mark functions whose return values
1746 // require promoting with signext or zeroext attributes.
1747 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1748 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1749 if (VT.bitsLT(MinVT))
1750 VT = MinVT;
1751 }
1752
1753 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1754 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1755
1756 // 'inreg' on function refers to return value
1757 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1758 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1759 Flags.setInReg();
1760
1761 // Propagate extension type if any
1762 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1763 Flags.setSExt();
1764 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1765 Flags.setZExt();
1766
1767 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1768 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1769 }
1770}
1771
1772/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1773/// function arguments in the caller parameter area. This is the actual
1774/// alignment, not its logarithm.
Mehdi Amini5c183d52015-07-09 02:09:28 +0000[diff] [blame]1775unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1776 const DataLayout &DL) const {
1777 return DL.getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1778}
1779
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1780bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1781 const DataLayout &DL, EVT VT,
1782 unsigned AddrSpace,
1783 unsigned Alignment,
1784 bool *Fast) const {
1785 // Check if the specified alignment is sufficient based on the data layout.
1786 // TODO: While using the data layout works in practice, a better solution
1787 // would be to implement this check directly (make this a virtual function).
1788 // For example, the ABI alignment may change based on software platform while
1789 // this function should only be affected by hardware implementation.
1790 Type *Ty = VT.getTypeForEVT(Context);
1791 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1792 // Assume that an access that meets the ABI-specified alignment is fast.
1793 if (Fast != nullptr)
1794 *Fast = true;
1795 return true;
1796 }
1797
1798 // This is a misaligned access.
1799 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1800}
1801
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]1802BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1803 return BranchProbability(MinPercentageForPredictableBranch, 100);
1804}
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1805
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1806//===----------------------------------------------------------------------===//
1807// TargetTransformInfo Helpers
1808//===----------------------------------------------------------------------===//
1809
1810int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1811 enum InstructionOpcodes {
1812#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1813#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1814#include "llvm/IR/Instruction.def"
1815 };
1816 switch (static_cast<InstructionOpcodes>(Opcode)) {
1817 case Ret: return 0;
1818 case Br: return 0;
1819 case Switch: return 0;
1820 case IndirectBr: return 0;
1821 case Invoke: return 0;
1822 case Resume: return 0;
1823 case Unreachable: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1824 case CleanupRet: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1825 case CatchRet: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1826 case CatchPad: return 0;
1827 case CatchSwitch: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1828 case CleanupPad: return 0;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1829 case Add: return ISD::ADD;
1830 case FAdd: return ISD::FADD;
1831 case Sub: return ISD::SUB;
1832 case FSub: return ISD::FSUB;
1833 case Mul: return ISD::MUL;
1834 case FMul: return ISD::FMUL;
1835 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1836 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1837 case FDiv: return ISD::FDIV;
1838 case URem: return ISD::UREM;
1839 case SRem: return ISD::SREM;
1840 case FRem: return ISD::FREM;
1841 case Shl: return ISD::SHL;
1842 case LShr: return ISD::SRL;
1843 case AShr: return ISD::SRA;
1844 case And: return ISD::AND;
1845 case Or: return ISD::OR;
1846 case Xor: return ISD::XOR;
1847 case Alloca: return 0;
1848 case Load: return ISD::LOAD;
1849 case Store: return ISD::STORE;
1850 case GetElementPtr: return 0;
1851 case Fence: return 0;
1852 case AtomicCmpXchg: return 0;
1853 case AtomicRMW: return 0;
1854 case Trunc: return ISD::TRUNCATE;
1855 case ZExt: return ISD::ZERO_EXTEND;
1856 case SExt: return ISD::SIGN_EXTEND;
1857 case FPToUI: return ISD::FP_TO_UINT;
1858 case FPToSI: return ISD::FP_TO_SINT;
1859 case UIToFP: return ISD::UINT_TO_FP;
1860 case SIToFP: return ISD::SINT_TO_FP;
1861 case FPTrunc: return ISD::FP_ROUND;
1862 case FPExt: return ISD::FP_EXTEND;
1863 case PtrToInt: return ISD::BITCAST;
1864 case IntToPtr: return ISD::BITCAST;
1865 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1866 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1867 case ICmp: return ISD::SETCC;
1868 case FCmp: return ISD::SETCC;
1869 case PHI: return 0;
1870 case Call: return 0;
1871 case Select: return ISD::SELECT;
1872 case UserOp1: return 0;
1873 case UserOp2: return 0;
1874 case VAArg: return 0;
1875 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1876 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1877 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1878 case ExtractValue: return ISD::MERGE_VALUES;
1879 case InsertValue: return ISD::MERGE_VALUES;
1880 case LandingPad: return 0;
1881 }
1882
1883 llvm_unreachable("Unknown instruction type encountered!");
1884}
1885
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1886std::pair<int, MVT>
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1887TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1888 Type *Ty) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1889 LLVMContext &C = Ty->getContext();
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1890 EVT MTy = getValueType(DL, Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1891
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1892 int Cost = 1;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1893 // We keep legalizing the type until we find a legal kind. We assume that
1894 // the only operation that costs anything is the split. After splitting
1895 // we need to handle two types.
1896 while (true) {
1897 LegalizeKind LK = getTypeConversion(C, MTy);
1898
1899 if (LK.first == TypeLegal)
1900 return std::make_pair(Cost, MTy.getSimpleVT());
1901
1902 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1903 Cost *= 2;
1904
Chih-Hung Hsiehed7d81e2015-12-03 22:02:40 +0000[diff] [blame]1905 // Do not loop with f128 type.
1906 if (MTy == LK.second)
1907 return std::make_pair(Cost, MTy.getSimpleVT());
1908
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1909 // Keep legalizing the type.
1910 MTy = LK.second;
1911 }
1912}
1913
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1914Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1915 if (!TM.getTargetTriple().isAndroid())
1916 return nullptr;
1917
1918 // Android provides a libc function to retrieve the address of the current
1919 // thread's unsafe stack pointer.
1920 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1921 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1922 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1923 StackPtrTy->getPointerTo(0), nullptr);
1924 return IRB.CreateCall(Fn);
1925}
1926
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1927//===----------------------------------------------------------------------===//
1928// Loop Strength Reduction hooks
1929//===----------------------------------------------------------------------===//
1930
1931/// isLegalAddressingMode - Return true if the addressing mode represented
1932/// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]1933bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1934 const AddrMode &AM, Type *Ty,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1935 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1936 // The default implementation of this implements a conservative RISCy, r+r and
1937 // r+i addr mode.
1938
1939 // Allows a sign-extended 16-bit immediate field.
1940 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1941 return false;
1942
1943 // No global is ever allowed as a base.
1944 if (AM.BaseGV)
1945 return false;
1946
1947 // Only support r+r,
1948 switch (AM.Scale) {
1949 case 0: // "r+i" or just "i", depending on HasBaseReg.
1950 break;
1951 case 1:
1952 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1953 return false;
1954 // Otherwise we have r+r or r+i.
1955 break;
1956 case 2:
1957 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1958 return false;
1959 // Allow 2*r as r+r.
1960 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1961 default: // Don't allow n * r
1962 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1963 }
1964
1965 return true;
1966}
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1967
1968//===----------------------------------------------------------------------===//
1969// Stack Protector
1970//===----------------------------------------------------------------------===//
1971
1972// For OpenBSD return its special guard variable. Otherwise return nullptr,
1973// so that SelectionDAG handle SSP.
1974Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1975 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1976 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1977 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
Tim Shena5cc25e2016-08-22 18:26:27 +0000[diff] [blame]1978 return M.getOrInsertGlobal("__guard_local", PtrTy);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1979 }
1980 return nullptr;
1981}
1982
1983// Currently only support "standard" __stack_chk_guard.
1984// TODO: add LOAD_STACK_GUARD support.
1985void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1986 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext()));
1987}
1988
1989// Currently only support "standard" __stack_chk_guard.
1990// TODO: add LOAD_STACK_GUARD support.
Tim Shena1d8bc52016-04-19 20:14:52 +0000[diff] [blame]1991Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
Davide Italianobd4243c2016-06-09 14:23:38 +0000[diff] [blame]1992 return M.getGlobalVariable("__stack_chk_guard", true);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1993}
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]1994
1995Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1996 return nullptr;
1997}