Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file implements the MachineIRBuidler class. |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" |
| 13 | |
| 14 | #include "llvm/CodeGen/MachineFunction.h" |
| 15 | #include "llvm/CodeGen/MachineInstr.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetInstrInfo.h" |
Quentin Colombet | 8fd6718 | 2016-02-11 21:16:56 +0000 | [diff] [blame] | 19 | #include "llvm/Target/TargetOpcodes.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetSubtargetInfo.h" |
| 21 | |
| 22 | using namespace llvm; |
| 23 | |
Quentin Colombet | 000b580 | 2016-03-11 17:27:51 +0000 | [diff] [blame] | 24 | void MachineIRBuilder::setMF(MachineFunction &MF) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 25 | this->MF = &MF; |
| 26 | this->MBB = nullptr; |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 27 | this->MRI = &MF.getRegInfo(); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 28 | this->TII = MF.getSubtarget().getInstrInfo(); |
| 29 | this->DL = DebugLoc(); |
| 30 | this->MI = nullptr; |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 31 | this->InsertedInstr = nullptr; |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 34 | void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 35 | this->MBB = &MBB; |
Tim Northover | b18ea16 | 2016-09-20 15:20:36 +0000 | [diff] [blame] | 36 | this->MI = nullptr; |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 37 | Before = Beginning; |
| 38 | assert(&getMF() == MBB.getParent() && |
| 39 | "Basic block is in a different function"); |
| 40 | } |
| 41 | |
| 42 | void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) { |
| 43 | assert(MI.getParent() && "Instruction is not part of a basic block"); |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 44 | setMBB(*MI.getParent()); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 45 | this->MI = &MI; |
| 46 | this->Before = Before; |
| 47 | } |
| 48 | |
| 49 | MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() { |
| 50 | if (MI) { |
| 51 | if (Before) |
| 52 | return MI; |
| 53 | if (!MI->getNextNode()) |
| 54 | return getMBB().end(); |
| 55 | return MI->getNextNode(); |
| 56 | } |
| 57 | return Before ? getMBB().begin() : getMBB().end(); |
| 58 | } |
| 59 | |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 60 | void MachineIRBuilder::recordInsertions( |
| 61 | std::function<void(MachineInstr *)> Inserted) { |
| 62 | InsertedInstr = Inserted; |
| 63 | } |
| 64 | |
| 65 | void MachineIRBuilder::stopRecordingInsertions() { |
| 66 | InsertedInstr = nullptr; |
| 67 | } |
| 68 | |
Quentin Colombet | f9b4934 | 2016-03-11 17:27:58 +0000 | [diff] [blame] | 69 | //------------------------------------------------------------------------------ |
| 70 | // Build instruction variants. |
| 71 | //------------------------------------------------------------------------------ |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 72 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 73 | MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { |
Tim Northover | a5e38fa | 2016-09-22 13:49:25 +0000 | [diff] [blame] | 74 | return insertInstr(buildInstrNoInsert(Opcode)); |
| 75 | } |
| 76 | |
| 77 | MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 78 | MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode)); |
Tim Northover | a5e38fa | 2016-09-22 13:49:25 +0000 | [diff] [blame] | 79 | return MIB; |
| 80 | } |
| 81 | |
| 82 | |
| 83 | MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 84 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 85 | if (InsertedInstr) |
| 86 | InsertedInstr(MIB); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 87 | return MIB; |
Quentin Colombet | 74d7d2f | 2016-02-11 18:53:28 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 90 | MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 91 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 92 | return buildInstr(TargetOpcode::G_FRAME_INDEX) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 93 | .addDef(Res) |
| 94 | .addFrameIndex(Idx); |
Tim Northover | bd50546 | 2016-07-22 16:59:52 +0000 | [diff] [blame] | 95 | } |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 96 | |
Tim Northover | 032548f | 2016-09-12 12:10:41 +0000 | [diff] [blame] | 97 | MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res, |
| 98 | const GlobalValue *GV) { |
| 99 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
| 100 | assert(MRI->getType(Res).getAddressSpace() == |
| 101 | GV->getType()->getAddressSpace() && |
| 102 | "address space mismatch"); |
| 103 | |
| 104 | return buildInstr(TargetOpcode::G_GLOBAL_VALUE) |
| 105 | .addDef(Res) |
| 106 | .addGlobalAddress(GV); |
| 107 | } |
| 108 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 109 | MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0, |
| 110 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 111 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 112 | "invalid operand type"); |
| 113 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 114 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 115 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 116 | return buildInstr(TargetOpcode::G_ADD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 117 | .addDef(Res) |
| 118 | .addUse(Op0) |
| 119 | .addUse(Op1); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 120 | } |
| 121 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 122 | MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0, |
| 123 | unsigned Op1) { |
| 124 | assert(MRI->getType(Res).isPointer() && |
| 125 | MRI->getType(Res) == MRI->getType(Op0) && "type mismatch"); |
| 126 | assert(MRI->getType(Op1).isScalar() && "invalid offset type"); |
| 127 | |
| 128 | return buildInstr(TargetOpcode::G_GEP) |
| 129 | .addDef(Res) |
| 130 | .addUse(Op0) |
| 131 | .addUse(Op1); |
| 132 | } |
| 133 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 134 | MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0, |
| 135 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 136 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 137 | "invalid operand type"); |
| 138 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 139 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 140 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 141 | return buildInstr(TargetOpcode::G_SUB) |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 142 | .addDef(Res) |
| 143 | .addUse(Op0) |
| 144 | .addUse(Op1); |
| 145 | } |
| 146 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 147 | MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0, |
| 148 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 149 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 150 | "invalid operand type"); |
| 151 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 152 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 153 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 154 | return buildInstr(TargetOpcode::G_MUL) |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 155 | .addDef(Res) |
| 156 | .addUse(Op0) |
| 157 | .addUse(Op1); |
| 158 | } |
| 159 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 160 | MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 161 | return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 162 | } |
| 163 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 164 | MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) { |
| 165 | return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); |
Tim Northover | 756eca3 | 2016-07-26 16:45:30 +0000 | [diff] [blame] | 166 | } |
| 167 | |
Tim Northover | 9267ac5 | 2016-12-05 21:47:07 +0000 | [diff] [blame] | 168 | MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, |
| 169 | const ConstantInt &Val) { |
| 170 | LLT Ty = MRI->getType(Res); |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 171 | |
Sam McCall | 03435f5 | 2016-12-06 10:14:36 +0000 | [diff] [blame^] | 172 | assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type"); |
Tim Northover | 9267ac5 | 2016-12-05 21:47:07 +0000 | [diff] [blame] | 173 | |
| 174 | const ConstantInt *NewVal = &Val; |
| 175 | if (Ty.getSizeInBits() != Val.getBitWidth()) |
| 176 | NewVal = ConstantInt::get(MF->getFunction()->getContext(), |
| 177 | Val.getValue().sextOrTrunc(Ty.getSizeInBits())); |
| 178 | |
| 179 | return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal); |
| 180 | } |
| 181 | |
| 182 | MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, |
| 183 | int64_t Val) { |
| 184 | auto IntN = IntegerType::get(MF->getFunction()->getContext(), |
| 185 | MRI->getType(Res).getSizeInBits()); |
| 186 | ConstantInt *CI = ConstantInt::get(IntN, Val, true); |
| 187 | return buildConstant(Res, *CI); |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 188 | } |
| 189 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 190 | MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res, |
| 191 | const ConstantFP &Val) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 192 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 193 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 194 | return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); |
Tim Northover | b16734f | 2016-08-19 20:09:15 +0000 | [diff] [blame] | 195 | } |
| 196 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 197 | MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst, |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 198 | MachineBasicBlock &Dest) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 199 | assert(MRI->getType(Tst).isScalar() && "invalid operand type"); |
| 200 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 201 | return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 204 | MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, |
| 205 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 206 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 207 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 208 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 209 | return buildInstr(TargetOpcode::G_LOAD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 210 | .addDef(Res) |
| 211 | .addUse(Addr) |
| 212 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 213 | } |
| 214 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 215 | MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, |
| 216 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 217 | assert(MRI->getType(Val).isValid() && "invalid operand type"); |
| 218 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 219 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 220 | return buildInstr(TargetOpcode::G_STORE) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 221 | .addUse(Val) |
| 222 | .addUse(Addr) |
| 223 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 224 | } |
| 225 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 226 | MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res, |
| 227 | unsigned CarryOut, |
| 228 | unsigned Op0, unsigned Op1, |
| 229 | unsigned CarryIn) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 230 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 231 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 232 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 233 | assert(MRI->getType(CarryOut).isScalar() && "invalid operand type"); |
| 234 | assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch"); |
| 235 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 236 | return buildInstr(TargetOpcode::G_UADDE) |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 237 | .addDef(Res) |
| 238 | .addDef(CarryOut) |
| 239 | .addUse(Op0) |
| 240 | .addUse(Op1) |
| 241 | .addUse(CarryIn); |
| 242 | } |
| 243 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 244 | MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) { |
| 245 | validateTruncExt(Res, Op, true); |
| 246 | return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 247 | } |
| 248 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 249 | MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) { |
| 250 | validateTruncExt(Res, Op, true); |
| 251 | return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 252 | } |
| 253 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 254 | MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) { |
| 255 | validateTruncExt(Res, Op, true); |
| 256 | return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 257 | } |
| 258 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 259 | MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res, |
| 260 | unsigned Op) { |
| 261 | unsigned Opcode = TargetOpcode::COPY; |
| 262 | if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits()) |
| 263 | Opcode = TargetOpcode::G_SEXT; |
| 264 | else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits()) |
| 265 | Opcode = TargetOpcode::G_TRUNC; |
| 266 | |
| 267 | return buildInstr(Opcode).addDef(Res).addUse(Op); |
| 268 | } |
| 269 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 270 | MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results, |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 271 | ArrayRef<uint64_t> Indices, |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 272 | unsigned Src) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 273 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 274 | assert(Results.size() == Indices.size() && "inconsistent number of regs"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 275 | assert(!Results.empty() && "invalid trivial extract"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 276 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 277 | "extract offsets must be in ascending order"); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 278 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 279 | assert(MRI->getType(Src).isValid() && "invalid operand type"); |
| 280 | for (auto Res : Results) |
| 281 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 282 | #endif |
| 283 | |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 284 | auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT)); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 285 | for (auto Res : Results) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 286 | MIB.addDef(Res); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 287 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 288 | MIB.addUse(Src); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 289 | |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 290 | for (auto Idx : Indices) |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 291 | MIB.addImm(Idx); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 292 | |
| 293 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 294 | if (InsertedInstr) |
| 295 | InsertedInstr(MIB); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 296 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 297 | return MIB; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 298 | } |
| 299 | |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 300 | MachineInstrBuilder |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 301 | MachineIRBuilder::buildSequence(unsigned Res, |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 302 | ArrayRef<unsigned> Ops, |
Tim Northover | b18ea16 | 2016-09-20 15:20:36 +0000 | [diff] [blame] | 303 | ArrayRef<uint64_t> Indices) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 304 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 305 | assert(Ops.size() == Indices.size() && "incompatible args"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 306 | assert(!Ops.empty() && "invalid trivial sequence"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 307 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 308 | "sequence offsets must be in ascending order"); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 309 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 310 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 311 | for (auto Op : Ops) |
| 312 | assert(MRI->getType(Op).isValid() && "invalid operand type"); |
| 313 | #endif |
| 314 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 315 | MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 316 | MIB.addDef(Res); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 317 | for (unsigned i = 0; i < Ops.size(); ++i) { |
| 318 | MIB.addUse(Ops[i]); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 319 | MIB.addImm(Indices[i]); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 320 | } |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 321 | return MIB; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 322 | } |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 323 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 324 | MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 325 | unsigned Res, |
| 326 | bool HasSideEffects) { |
| 327 | auto MIB = |
| 328 | buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 329 | : TargetOpcode::G_INTRINSIC); |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 330 | if (Res) |
| 331 | MIB.addDef(Res); |
| 332 | MIB.addIntrinsicID(ID); |
| 333 | return MIB; |
| 334 | } |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 335 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 336 | MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) { |
| 337 | validateTruncExt(Res, Op, false); |
| 338 | return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 339 | } |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 340 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 341 | MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) { |
| 342 | validateTruncExt(Res, Op, false); |
| 343 | return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op); |
Tim Northover | a11be04 | 2016-08-19 22:40:08 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 346 | MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 347 | unsigned Res, unsigned Op0, |
| 348 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 349 | #ifndef NDEBUG |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 350 | assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch"); |
| 351 | assert(CmpInst::isIntPredicate(Pred) && "invalid predicate"); |
Tim Northover | 4cf0a48 | 2016-09-15 10:40:38 +0000 | [diff] [blame] | 352 | if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer()) |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 353 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 354 | else |
| 355 | assert(MRI->getType(Res).isVector() && |
| 356 | MRI->getType(Res).getNumElements() == |
| 357 | MRI->getType(Op0).getNumElements() && |
| 358 | "type mismatch"); |
| 359 | #endif |
| 360 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 361 | return buildInstr(TargetOpcode::G_ICMP) |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 362 | .addDef(Res) |
| 363 | .addPredicate(Pred) |
| 364 | .addUse(Op0) |
| 365 | .addUse(Op1); |
| 366 | } |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 367 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 368 | MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 369 | unsigned Res, unsigned Op0, |
| 370 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 371 | #ifndef NDEBUG |
| 372 | assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) && |
| 373 | "invalid operand type"); |
| 374 | assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch"); |
| 375 | assert(CmpInst::isFPPredicate(Pred) && "invalid predicate"); |
| 376 | if (MRI->getType(Op0).isScalar()) |
| 377 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 378 | else |
| 379 | assert(MRI->getType(Res).isVector() && |
| 380 | MRI->getType(Res).getNumElements() == |
| 381 | MRI->getType(Op0).getNumElements() && |
| 382 | "type mismatch"); |
| 383 | #endif |
| 384 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 385 | return buildInstr(TargetOpcode::G_FCMP) |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 386 | .addDef(Res) |
| 387 | .addPredicate(Pred) |
| 388 | .addUse(Op0) |
| 389 | .addUse(Op1); |
| 390 | } |
| 391 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 392 | MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst, |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 393 | unsigned Op0, unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 394 | #ifndef NDEBUG |
| 395 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 396 | "invalid operand type"); |
| 397 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 398 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 399 | if (MRI->getType(Res).isScalar()) |
| 400 | assert(MRI->getType(Tst).isScalar() && "type mismatch"); |
| 401 | else |
| 402 | assert(MRI->getType(Tst).isVector() && |
| 403 | MRI->getType(Tst).getNumElements() == |
| 404 | MRI->getType(Op0).getNumElements() && |
| 405 | "type mismatch"); |
| 406 | #endif |
| 407 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 408 | return buildInstr(TargetOpcode::G_SELECT) |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 409 | .addDef(Res) |
| 410 | .addUse(Tst) |
| 411 | .addUse(Op0) |
| 412 | .addUse(Op1); |
| 413 | } |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 414 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 415 | void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src, |
| 416 | bool IsExtend) { |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 417 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 418 | LLT SrcTy = MRI->getType(Src); |
| 419 | LLT DstTy = MRI->getType(Dst); |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 420 | |
| 421 | if (DstTy.isVector()) { |
| 422 | assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector"); |
| 423 | assert(SrcTy.getNumElements() == DstTy.getNumElements() && |
| 424 | "different number of elements in a trunc/ext"); |
| 425 | } else |
| 426 | assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc"); |
| 427 | |
| 428 | if (IsExtend) |
| 429 | assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() && |
| 430 | "invalid narrowing extend"); |
| 431 | else |
| 432 | assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() && |
| 433 | "invalid widening trunc"); |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 434 | #endif |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 435 | } |