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gerrit-public.fairphone.software / toolchain / llvm-project / 3b2ff1faa9466ad30b40b8740c047107591a70b1 / . / llvm / lib / Target / X86 / X86SchedSkylakeClient.td
blob: aea893cc21d44f3d425f378bc944a2284984cd7d [file] [log] [blame]
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Skylake Client to support
11// instruction scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15def SkylakeClientModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SKylake can
17 // decode 6 instructions per cycle.
18 let IssueWidth = 6;
19 let MicroOpBufferSize = 224; // Based on the reorder buffer.
20 let LoadLatency = 5;
21 let MispredictPenalty = 14;
22
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
25
26 // This flag is set to allow the scheduler to assign a default model to
27 // unrecognized opcodes.
28 let CompleteModel = 0;
29}
30
31let SchedModel = SkylakeClientModel in {
32
33// Skylake Client can issue micro-ops to 8 different ports in one cycle.
34
35// Ports 0, 1, 5, and 6 handle all computation.
36// Port 4 gets the data half of stores. Store data can be available later than
37// the store address, but since we don't model the latency of stores, we can
38// ignore that.
39// Ports 2 and 3 are identical. They handle loads and the address half of
40// stores. Port 7 can handle address calculations.
41def SKLPort0 : ProcResource<1>;
42def SKLPort1 : ProcResource<1>;
43def SKLPort2 : ProcResource<1>;
44def SKLPort3 : ProcResource<1>;
45def SKLPort4 : ProcResource<1>;
46def SKLPort5 : ProcResource<1>;
47def SKLPort6 : ProcResource<1>;
48def SKLPort7 : ProcResource<1>;
49
50// Many micro-ops are capable of issuing on multiple ports.
51def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>;
52def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>;
53def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
54def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>;
55def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>;
56def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>;
57def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>;
58def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>;
59def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>;
60def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
61def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
62def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
63
64// 60 Entry Unified Scheduler
65def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
66 SKLPort5, SKLPort6, SKLPort7]> {
67 let BufferSize=60;
68}
69
70// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
71// cycles after the memory operand.
72def : ReadAdvance<ReadAfterLd, 5>;
73
74// Many SchedWrites are defined in pairs with and without a folded load.
75// Instructions with folded loads are usually micro-fused, so they only appear
76// as two micro-ops when queued in the reservation station.
77// This multiclass defines the resource usage for variants with and without
78// folded loads.
79multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]80 list<ProcResourceKind> ExePorts,
81 int Lat, list<int> Res = [1], int UOps = 1> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]82 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]83 def : WriteRes<SchedRW, ExePorts> {
84 let Latency = Lat;
85 let ResourceCycles = Res;
86 let NumMicroOps = UOps;
87 }
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]88
89 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
90 // latency.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]91 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
92 let Latency = !add(Lat, 5);
93 let ResourceCycles = !listconcat([1], Res);
94 let NumMicroOps = UOps;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]95 }
96}
97
98// A folded store needs a cycle on port 4 for the store data, but it does not
99// need an extra port 2/3 cycle to recompute the address.
100def : WriteRes<WriteRMW, [SKLPort4]>;
101
102// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]103defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
104defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]105def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
106def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
107def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.
108 let Latency = 25;
109 let ResourceCycles = [1, 10];
110}
111def : WriteRes<WriteIDivLd, [SKLPort23, SKLPort0, SKLDivider]> {
112 let Latency = 29;
113 let ResourceCycles = [1, 1, 10];
114}
115
116def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
117
118// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]119defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]120
121// Loads, stores, and moves, not folded with other operations.
122def : WriteRes<WriteLoad, [SKLPort23]> { let Latency = 5; }
123def : WriteRes<WriteStore, [SKLPort237, SKLPort4]>;
124def : WriteRes<WriteMove, [SKLPort0156]>;
125
126// Idioms that clear a register, like xorps %xmm0, %xmm0.
127// These can often bypass execution ports completely.
128def : WriteRes<WriteZero, []>;
129
130// Branches don't produce values, so they have no latency, but they still
131// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]132defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]133
134// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]135def : WriteRes<WriteFLoad, [SKLPort23]> { let Latency = 6; }
136def : WriteRes<WriteFStore, [SKLPort237, SKLPort4]>;
137def : WriteRes<WriteFMove, [SKLPort015]>;
138
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]139defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3>; // Floating point add/sub/compare.
140defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication.
141defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12>; // 10-14 cycles. // Floating point division.
142defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square root.
143defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate.
144defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate.
145defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add.
146defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles.
147defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends.
148defm : SKLWriteResPair<WriteFVarBlend, [SKLPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]149
150// FMA Scheduling helper class.
151// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
152
153// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]154def : WriteRes<WriteVecLoad, [SKLPort23]> { let Latency = 6; }
155def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>;
156def : WriteRes<WriteVecMove, [SKLPort015]>;
157
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]158defm : SKLWriteResPair<WriteVecALU, [SKLPort15], 1>; // Vector integer ALU op, no logicals.
159defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1>; // Vector integer shifts.
160defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply.
161defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1>; // Vector shuffles.
162defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends.
163defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable blends.
164defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]165
166// Vector bitwise operations.
167// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]168defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1>; // Vector and/or/xor.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]169
170// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]171defm : SKLWriteResPair<WriteCvtF2I, [SKLPort1], 3>; // Float -> Integer.
172defm : SKLWriteResPair<WriteCvtI2F, [SKLPort1], 4>; // Integer -> Float.
173defm : SKLWriteResPair<WriteCvtF2F, [SKLPort1], 3>; // Float -> Float size conversion.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]174
175// Strings instructions.
176// Packed Compare Implicit Length Strings, Return Mask
177// String instructions.
178def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
179 let Latency = 10;
180 let ResourceCycles = [3];
181}
182def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
183 let Latency = 10;
184 let ResourceCycles = [3, 1];
185}
186// Packed Compare Explicit Length Strings, Return Mask
187def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort16, SKLPort5]> {
188 let Latency = 10;
189 let ResourceCycles = [3, 2, 4];
190}
191def : WriteRes<WritePCmpEStrMLd, [SKLPort05, SKLPort16, SKLPort23]> {
192 let Latency = 10;
193 let ResourceCycles = [6, 2, 1];
194}
195 // Packed Compare Implicit Length Strings, Return Index
196def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
197 let Latency = 11;
198 let ResourceCycles = [3];
199}
200def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
201 let Latency = 11;
202 let ResourceCycles = [3, 1];
203}
204// Packed Compare Explicit Length Strings, Return Index
205def : WriteRes<WritePCmpEStrI, [SKLPort05, SKLPort16]> {
206 let Latency = 11;
207 let ResourceCycles = [6, 2];
208}
209def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort16, SKLPort5, SKLPort23]> {
210 let Latency = 11;
211 let ResourceCycles = [3, 2, 2, 1];
212}
213
214// AES instructions.
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]215def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
216 let Latency = 4;
217 let NumMicroOps = 1;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]218 let ResourceCycles = [1];
219}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]220def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
221 let Latency = 10;
222 let NumMicroOps = 2;
223 let ResourceCycles = [1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]224}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]225
226def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
227 let Latency = 8;
228 let NumMicroOps = 2;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]229 let ResourceCycles = [2];
230}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]231def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]232 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]233 let NumMicroOps = 3;
234 let ResourceCycles = [2,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]235}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]236
237def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
238 let Latency = 20;
239 let NumMicroOps = 11;
240 let ResourceCycles = [3,6,2];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]241}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]242def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
243 let Latency = 25;
244 let NumMicroOps = 11;
245 let ResourceCycles = [3,6,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]246}
247
248// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame^]249def : WriteRes<WriteCLMul, [SKLPort5]> {
250 let Latency = 6;
251 let NumMicroOps = 1;
252 let ResourceCycles = [1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]253}
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame^]254def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
255 let Latency = 12;
256 let NumMicroOps = 2;
257 let ResourceCycles = [1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]258}
259
260// Catch-all for expensive system instructions.
261def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
262
263// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]264defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3>; // Fp 256-bit width vector shuffles.
265defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3>; // 256-bit width vector shuffles.
266defm : SKLWriteResPair<WriteVarVecShift, [SKLPort0, SKLPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]267
268// Old microcoded instructions that nobody use.
269def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
270
271// Fence instructions.
272def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
273
274// Nop, not very useful expect it provides a model for nops!
275def : WriteRes<WriteNop, []>;
276
277////////////////////////////////////////////////////////////////////////////////
278// Horizontal add/sub instructions.
279////////////////////////////////////////////////////////////////////////////////
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]280
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]281defm : SKLWriteResPair<WriteFHAdd, [SKLPort1], 3>;
282defm : SKLWriteResPair<WritePHAdd, [SKLPort15], 1>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]283
284// Remaining instrs.
285
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]286def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]287 let Latency = 1;
288 let NumMicroOps = 1;
289 let ResourceCycles = [1];
290}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]291def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr",
292 "MMX_PADDSWirr",
293 "MMX_PADDUSBirr",
294 "MMX_PADDUSWirr",
295 "MMX_PAVGBirr",
296 "MMX_PAVGWirr",
297 "MMX_PCMPEQBirr",
298 "MMX_PCMPEQDirr",
299 "MMX_PCMPEQWirr",
300 "MMX_PCMPGTBirr",
301 "MMX_PCMPGTDirr",
302 "MMX_PCMPGTWirr",
303 "MMX_PMAXSWirr",
304 "MMX_PMAXUBirr",
305 "MMX_PMINSWirr",
306 "MMX_PMINUBirr",
307 "MMX_PSLLDri",
308 "MMX_PSLLDrr",
309 "MMX_PSLLQri",
310 "MMX_PSLLQrr",
311 "MMX_PSLLWri",
312 "MMX_PSLLWrr",
313 "MMX_PSRADri",
314 "MMX_PSRADrr",
315 "MMX_PSRAWri",
316 "MMX_PSRAWrr",
317 "MMX_PSRLDri",
318 "MMX_PSRLDrr",
319 "MMX_PSRLQri",
320 "MMX_PSRLQrr",
321 "MMX_PSRLWri",
322 "MMX_PSRLWrr",
323 "MMX_PSUBSBirr",
324 "MMX_PSUBSWirr",
325 "MMX_PSUBUSBirr",
326 "MMX_PSUBUSWirr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]327
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]328def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]329 let Latency = 1;
330 let NumMicroOps = 1;
331 let ResourceCycles = [1];
332}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]333def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
334 "COM_FST0r",
335 "INSERTPSrr",
336 "MMX_MOVD64rr",
337 "MMX_MOVD64to64rr",
338 "MMX_PALIGNRrri",
339 "MMX_PSHUFBrr",
340 "MMX_PSHUFWri",
341 "MMX_PUNPCKHBWirr",
342 "MMX_PUNPCKHDQirr",
343 "MMX_PUNPCKHWDirr",
344 "MMX_PUNPCKLBWirr",
345 "MMX_PUNPCKLDQirr",
346 "MMX_PUNPCKLWDirr",
347 "MOV64toPQIrr",
348 "MOVDDUPrr",
349 "MOVDI2PDIrr",
350 "MOVHLPSrr",
351 "MOVLHPSrr",
352 "MOVSDrr",
353 "MOVSHDUPrr",
354 "MOVSLDUPrr",
355 "MOVUPDrr",
356 "MOVUPSrr",
357 "PACKSSDWrr",
358 "PACKSSWBrr",
359 "PACKUSDWrr",
360 "PACKUSWBrr",
361 "PALIGNRrri",
362 "PBLENDWrri",
363 "PMOVSXBDrr",
364 "PMOVSXBQrr",
365 "PMOVSXBWrr",
366 "PMOVSXDQrr",
367 "PMOVSXWDrr",
368 "PMOVSXWQrr",
369 "PMOVZXBDrr",
370 "PMOVZXBQrr",
371 "PMOVZXBWrr",
372 "PMOVZXDQrr",
373 "PMOVZXWDrr",
374 "PMOVZXWQrr",
375 "PSHUFBrr",
376 "PSHUFDri",
377 "PSHUFHWri",
378 "PSHUFLWri",
379 "PSLLDQri",
380 "PSRLDQri",
381 "PUNPCKHBWrr",
382 "PUNPCKHDQrr",
383 "PUNPCKHQDQrr",
384 "PUNPCKHWDrr",
385 "PUNPCKLBWrr",
386 "PUNPCKLDQrr",
387 "PUNPCKLQDQrr",
388 "PUNPCKLWDrr",
389 "SHUFPDrri",
390 "SHUFPSrri",
391 "UCOM_FPr",
392 "UCOM_Fr",
393 "UNPCKHPDrr",
394 "UNPCKHPSrr",
395 "UNPCKLPDrr",
396 "UNPCKLPSrr",
397 "VBROADCASTSSrr",
398 "VINSERTPSrr",
399 "VMOV64toPQIrr",
400 "VMOVDDUPYrr",
401 "VMOVDDUPrr",
402 "VMOVDI2PDIrr",
403 "VMOVHLPSrr",
404 "VMOVLHPSrr",
405 "VMOVSDrr",
406 "VMOVSHDUPYrr",
407 "VMOVSHDUPrr",
408 "VMOVSLDUPYrr",
409 "VMOVSLDUPrr",
410 "VMOVUPDYrr",
411 "VMOVUPDrr",
412 "VMOVUPSYrr",
413 "VMOVUPSrr",
414 "VPACKSSDWYrr",
415 "VPACKSSDWrr",
416 "VPACKSSWBYrr",
417 "VPACKSSWBrr",
418 "VPACKUSDWYrr",
419 "VPACKUSDWrr",
420 "VPACKUSWBYrr",
421 "VPACKUSWBrr",
422 "VPALIGNRYrri",
423 "VPALIGNRrri",
424 "VPBLENDWYrri",
425 "VPBLENDWrri",
426 "VPBROADCASTDrr",
427 "VPBROADCASTQrr",
428 "VPERMILPDYri",
429 "VPERMILPDYrr",
430 "VPERMILPDri",
431 "VPERMILPDrr",
432 "VPERMILPSYri",
433 "VPERMILPSYrr",
434 "VPERMILPSri",
435 "VPERMILPSrr",
436 "VPMOVSXBDrr",
437 "VPMOVSXBQrr",
438 "VPMOVSXBWrr",
439 "VPMOVSXDQrr",
440 "VPMOVSXWDrr",
441 "VPMOVSXWQrr",
442 "VPMOVZXBDrr",
443 "VPMOVZXBQrr",
444 "VPMOVZXBWrr",
445 "VPMOVZXDQrr",
446 "VPMOVZXWDrr",
447 "VPMOVZXWQrr",
448 "VPSHUFBYrr",
449 "VPSHUFBrr",
450 "VPSHUFDYri",
451 "VPSHUFDri",
452 "VPSHUFHWYri",
453 "VPSHUFHWri",
454 "VPSHUFLWYri",
455 "VPSHUFLWri",
456 "VPSLLDQYri",
457 "VPSLLDQri",
458 "VPSRLDQYri",
459 "VPSRLDQri",
460 "VPUNPCKHBWYrr",
461 "VPUNPCKHBWrr",
462 "VPUNPCKHDQYrr",
463 "VPUNPCKHDQrr",
464 "VPUNPCKHQDQYrr",
465 "VPUNPCKHQDQrr",
466 "VPUNPCKHWDYrr",
467 "VPUNPCKHWDrr",
468 "VPUNPCKLBWYrr",
469 "VPUNPCKLBWrr",
470 "VPUNPCKLDQYrr",
471 "VPUNPCKLDQrr",
472 "VPUNPCKLQDQYrr",
473 "VPUNPCKLQDQrr",
474 "VPUNPCKLWDYrr",
475 "VPUNPCKLWDrr",
476 "VSHUFPDYrri",
477 "VSHUFPDrri",
478 "VSHUFPSYrri",
479 "VSHUFPSrri",
480 "VUNPCKHPDYrr",
481 "VUNPCKHPDrr",
482 "VUNPCKHPSYrr",
483 "VUNPCKHPSrr",
484 "VUNPCKLPDYrr",
485 "VUNPCKLPDrr",
486 "VUNPCKLPSYrr",
487 "VUNPCKLPSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]488
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]489def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]490 let Latency = 1;
491 let NumMicroOps = 1;
492 let ResourceCycles = [1];
493}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]494def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]495
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]496def SKLWriteResGroup5 : SchedWriteRes<[SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]497 let Latency = 1;
498 let NumMicroOps = 1;
499 let ResourceCycles = [1];
500}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]501def: InstRW<[SKLWriteResGroup5], (instregex "PABSBrr",
502 "PABSDrr",
503 "PABSWrr",
504 "PADDSBrr",
505 "PADDSWrr",
506 "PADDUSBrr",
507 "PADDUSWrr",
508 "PAVGBrr",
509 "PAVGWrr",
510 "PCMPEQBrr",
511 "PCMPEQDrr",
512 "PCMPEQQrr",
513 "PCMPEQWrr",
514 "PCMPGTBrr",
515 "PCMPGTDrr",
516 "PCMPGTWrr",
517 "PMAXSBrr",
518 "PMAXSDrr",
519 "PMAXSWrr",
520 "PMAXUBrr",
521 "PMAXUDrr",
522 "PMAXUWrr",
523 "PMINSBrr",
524 "PMINSDrr",
525 "PMINSWrr",
526 "PMINUBrr",
527 "PMINUDrr",
528 "PMINUWrr",
529 "PSIGNBrr",
530 "PSIGNDrr",
531 "PSIGNWrr",
532 "PSLLDri",
533 "PSLLQri",
534 "PSLLWri",
535 "PSRADri",
536 "PSRAWri",
537 "PSRLDri",
538 "PSRLQri",
539 "PSRLWri",
540 "PSUBSBrr",
541 "PSUBSWrr",
542 "PSUBUSBrr",
543 "PSUBUSWrr",
544 "VPABSBYrr",
545 "VPABSBrr",
546 "VPABSDYrr",
547 "VPABSDrr",
548 "VPABSWYrr",
549 "VPABSWrr",
550 "VPADDSBYrr",
551 "VPADDSBrr",
552 "VPADDSWYrr",
553 "VPADDSWrr",
554 "VPADDUSBYrr",
555 "VPADDUSBrr",
556 "VPADDUSWYrr",
557 "VPADDUSWrr",
558 "VPAVGBYrr",
559 "VPAVGBrr",
560 "VPAVGWYrr",
561 "VPAVGWrr",
562 "VPCMPEQBYrr",
563 "VPCMPEQBrr",
564 "VPCMPEQDYrr",
565 "VPCMPEQDrr",
566 "VPCMPEQQYrr",
567 "VPCMPEQQrr",
568 "VPCMPEQWYrr",
569 "VPCMPEQWrr",
570 "VPCMPGTBYrr",
571 "VPCMPGTBrr",
572 "VPCMPGTDYrr",
573 "VPCMPGTDrr",
574 "VPCMPGTWYrr",
575 "VPCMPGTWrr",
576 "VPMAXSBYrr",
577 "VPMAXSBrr",
578 "VPMAXSDYrr",
579 "VPMAXSDrr",
580 "VPMAXSWYrr",
581 "VPMAXSWrr",
582 "VPMAXUBYrr",
583 "VPMAXUBrr",
584 "VPMAXUDYrr",
585 "VPMAXUDrr",
586 "VPMAXUWYrr",
587 "VPMAXUWrr",
588 "VPMINSBYrr",
589 "VPMINSBrr",
590 "VPMINSDYrr",
591 "VPMINSDrr",
592 "VPMINSWYrr",
593 "VPMINSWrr",
594 "VPMINUBYrr",
595 "VPMINUBrr",
596 "VPMINUDYrr",
597 "VPMINUDrr",
598 "VPMINUWYrr",
599 "VPMINUWrr",
600 "VPSIGNBYrr",
601 "VPSIGNBrr",
602 "VPSIGNDYrr",
603 "VPSIGNDrr",
604 "VPSIGNWYrr",
605 "VPSIGNWrr",
606 "VPSLLDYri",
607 "VPSLLDri",
608 "VPSLLQYri",
609 "VPSLLQri",
610 "VPSLLVDYrr",
611 "VPSLLVDrr",
612 "VPSLLVQYrr",
613 "VPSLLVQrr",
614 "VPSLLWYri",
615 "VPSLLWri",
616 "VPSRADYri",
617 "VPSRADri",
618 "VPSRAVDYrr",
619 "VPSRAVDrr",
620 "VPSRAWYri",
621 "VPSRAWri",
622 "VPSRLDYri",
623 "VPSRLDri",
624 "VPSRLQYri",
625 "VPSRLQri",
626 "VPSRLVDYrr",
627 "VPSRLVDrr",
628 "VPSRLVQYrr",
629 "VPSRLVQrr",
630 "VPSRLWYri",
631 "VPSRLWri",
632 "VPSUBSBYrr",
633 "VPSUBSBrr",
634 "VPSUBSWYrr",
635 "VPSUBSWrr",
636 "VPSUBUSBYrr",
637 "VPSUBUSBrr",
638 "VPSUBUSWYrr",
639 "VPSUBUSWrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]640
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]641def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]642 let Latency = 1;
643 let NumMicroOps = 1;
644 let ResourceCycles = [1];
645}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]646def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP",
647 "FNOP",
648 "MMX_MOVQ64rr",
649 "MMX_PABSBrr",
650 "MMX_PABSDrr",
651 "MMX_PABSWrr",
652 "MMX_PADDBirr",
653 "MMX_PADDDirr",
654 "MMX_PADDQirr",
655 "MMX_PADDWirr",
656 "MMX_PANDNirr",
657 "MMX_PANDirr",
658 "MMX_PORirr",
659 "MMX_PSIGNBrr",
660 "MMX_PSIGNDrr",
661 "MMX_PSIGNWrr",
662 "MMX_PSUBBirr",
663 "MMX_PSUBDirr",
664 "MMX_PSUBQirr",
665 "MMX_PSUBWirr",
666 "MMX_PXORirr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]667
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]668def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]669 let Latency = 1;
670 let NumMicroOps = 1;
671 let ResourceCycles = [1];
672}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]673def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
674 "ADC(16|32|64)i",
675 "ADC(8|16|32|64)rr",
676 "ADCX(32|64)rr",
677 "ADOX(32|64)rr",
678 "BT(16|32|64)ri8",
679 "BT(16|32|64)rr",
680 "BTC(16|32|64)ri8",
681 "BTC(16|32|64)rr",
682 "BTR(16|32|64)ri8",
683 "BTR(16|32|64)rr",
684 "BTS(16|32|64)ri8",
685 "BTS(16|32|64)rr",
686 "CDQ",
687 "CLAC",
688 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
689 "CQO",
690 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
691 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
692 "JMP_1",
693 "JMP_4",
694 "RORX(32|64)ri",
695 "SAR(8|16|32|64)r1",
696 "SAR(8|16|32|64)ri",
697 "SARX(32|64)rr",
698 "SBB(16|32|64)ri",
699 "SBB(16|32|64)i",
700 "SBB(8|16|32|64)rr",
701 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
702 "SHL(8|16|32|64)r1",
703 "SHL(8|16|32|64)ri",
704 "SHLX(32|64)rr",
705 "SHR(8|16|32|64)r1",
706 "SHR(8|16|32|64)ri",
707 "SHRX(32|64)rr",
708 "STAC")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]709
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]710def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
711 let Latency = 1;
712 let NumMicroOps = 1;
713 let ResourceCycles = [1];
714}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]715def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
716 "BLSI(32|64)rr",
717 "BLSMSK(32|64)rr",
718 "BLSR(32|64)rr",
719 "BZHI(32|64)rr",
720 "LEA(16|32|64)(_32)?r")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]721
722def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
723 let Latency = 1;
724 let NumMicroOps = 1;
725 let ResourceCycles = [1];
726}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]727def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPDrr",
728 "ANDNPSrr",
729 "ANDPDrr",
730 "ANDPSrr",
731 "BLENDPDrri",
732 "BLENDPSrri",
733 "MOVAPDrr",
734 "MOVAPSrr",
735 "MOVDQArr",
736 "MOVDQUrr",
737 "MOVPQI2QIrr",
738 "MOVSSrr",
739 "ORPDrr",
740 "ORPSrr",
741 "PADDBrr",
742 "PADDDrr",
743 "PADDQrr",
744 "PADDWrr",
745 "PANDNrr",
746 "PANDrr",
747 "PORrr",
748 "PSUBBrr",
749 "PSUBDrr",
750 "PSUBQrr",
751 "PSUBWrr",
752 "PXORrr",
753 "VANDNPDYrr",
754 "VANDNPDrr",
755 "VANDNPSYrr",
756 "VANDNPSrr",
757 "VANDPDYrr",
758 "VANDPDrr",
759 "VANDPSYrr",
760 "VANDPSrr",
761 "VBLENDPDYrri",
762 "VBLENDPDrri",
763 "VBLENDPSYrri",
764 "VBLENDPSrri",
765 "VMOVAPDYrr",
766 "VMOVAPDrr",
767 "VMOVAPSYrr",
768 "VMOVAPSrr",
769 "VMOVDQAYrr",
770 "VMOVDQArr",
771 "VMOVDQUYrr",
772 "VMOVDQUrr",
773 "VMOVPQI2QIrr",
774 "VMOVSSrr",
775 "VMOVZPQILo2PQIrr",
776 "VORPDYrr",
777 "VORPDrr",
778 "VORPSYrr",
779 "VORPSrr",
780 "VPADDBYrr",
781 "VPADDBrr",
782 "VPADDDYrr",
783 "VPADDDrr",
784 "VPADDQYrr",
785 "VPADDQrr",
786 "VPADDWYrr",
787 "VPADDWrr",
788 "VPANDNYrr",
789 "VPANDNrr",
790 "VPANDYrr",
791 "VPANDrr",
792 "VPBLENDDYrri",
793 "VPBLENDDrri",
794 "VPORYrr",
795 "VPORrr",
796 "VPSUBBYrr",
797 "VPSUBBrr",
798 "VPSUBDYrr",
799 "VPSUBDrr",
800 "VPSUBQYrr",
801 "VPSUBQrr",
802 "VPSUBWYrr",
803 "VPSUBWrr",
804 "VPXORYrr",
805 "VPXORrr",
806 "VXORPDYrr",
807 "VXORPDrr",
808 "VXORPSYrr",
809 "VXORPSrr",
810 "XORPDrr",
811 "XORPSrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]812
813def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
814 let Latency = 1;
815 let NumMicroOps = 1;
816 let ResourceCycles = [1];
817}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]818def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]819def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
820 "ADD(8|16|32|64)rr",
821 "ADD(8|16|32|64)i",
822 "AND(8|16|32|64)ri",
823 "AND(8|16|32|64)rr",
824 "AND(8|16|32|64)i",
825 "CBW",
826 "CLC",
827 "CMC",
828 "CMP(8|16|32|64)ri",
829 "CMP(8|16|32|64)rr",
830 "CMP(8|16|32|64)i",
831 "DEC(8|16|32|64)r",
832 "INC(8|16|32|64)r",
833 "LAHF",
834 "MOV(8|16|32|64)rr",
835 "MOV(8|16|32|64)ri",
836 "MOVSX(16|32|64)rr16",
837 "MOVSX(16|32|64)rr32",
838 "MOVSX(16|32|64)rr8",
839 "MOVZX(16|32|64)rr16",
840 "MOVZX(16|32|64)rr8",
841 "NEG(8|16|32|64)r",
842 "NOOP",
843 "NOT(8|16|32|64)r",
844 "OR(8|16|32|64)ri",
845 "OR(8|16|32|64)rr",
846 "OR(8|16|32|64)i",
847 "SAHF",
848 "SGDT64m",
849 "SIDT64m",
850 "SLDT64m",
851 "SMSW16m",
852 "STC",
853 "STRm",
854 "SUB(8|16|32|64)ri",
855 "SUB(8|16|32|64)rr",
856 "SUB(8|16|32|64)i",
857 "SYSCALL",
858 "TEST(8|16|32|64)rr",
859 "TEST(8|16|32|64)i",
860 "TEST(8|16|32|64)ri",
861 "XCHG(16|32|64)rr",
862 "XOR(8|16|32|64)ri",
863 "XOR(8|16|32|64)rr",
864 "XOR(8|16|32|64)i")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]865
866def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]867 let Latency = 1;
868 let NumMicroOps = 2;
869 let ResourceCycles = [1,1];
870}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]871def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
872 "MMX_MOVD64from64rm",
873 "MMX_MOVD64mr",
874 "MMX_MOVNTQmr",
875 "MMX_MOVQ64mr",
876 "MOV(8|16|32|64)mr",
877 "MOV8mi",
878 "MOVAPDmr",
879 "MOVAPSmr",
880 "MOVDQAmr",
881 "MOVDQUmr",
882 "MOVHPDmr",
883 "MOVHPSmr",
884 "MOVLPDmr",
885 "MOVLPSmr",
886 "MOVNTDQmr",
887 "MOVNTI_64mr",
888 "MOVNTImr",
889 "MOVNTPDmr",
890 "MOVNTPSmr",
891 "MOVPDI2DImr",
892 "MOVPQI2QImr",
893 "MOVPQIto64mr",
894 "MOVSDmr",
895 "MOVSSmr",
896 "MOVUPDmr",
897 "MOVUPSmr",
898 "ST_FP32m",
899 "ST_FP64m",
900 "ST_FP80m",
901 "VEXTRACTF128mr",
902 "VEXTRACTI128mr",
903 "VMOVAPDYmr",
904 "VMOVAPDmr",
905 "VMOVAPSYmr",
906 "VMOVAPSmr",
907 "VMOVDQAYmr",
908 "VMOVDQAmr",
909 "VMOVDQUYmr",
910 "VMOVDQUmr",
911 "VMOVHPDmr",
912 "VMOVHPSmr",
913 "VMOVLPDmr",
914 "VMOVLPSmr",
915 "VMOVNTDQYmr",
916 "VMOVNTDQmr",
917 "VMOVNTPDYmr",
918 "VMOVNTPDmr",
919 "VMOVNTPSYmr",
920 "VMOVNTPSmr",
921 "VMOVPDI2DImr",
922 "VMOVPQI2QImr",
923 "VMOVPQIto64mr",
924 "VMOVSDmr",
925 "VMOVSSmr",
926 "VMOVUPDYmr",
927 "VMOVUPDmr",
928 "VMOVUPSYmr",
929 "VMOVUPSmr",
930 "VMPTRSTm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]931
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]932def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]933 let Latency = 2;
934 let NumMicroOps = 1;
935 let ResourceCycles = [1];
936}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]937def: InstRW<[SKLWriteResGroup12], (instregex "COMISDrr",
938 "COMISSrr",
939 "MMX_MOVD64from64rr",
940 "MMX_MOVD64grr",
941 "MMX_PMOVMSKBrr",
942 "MOVMSKPDrr",
943 "MOVMSKPSrr",
944 "MOVPDI2DIrr",
945 "MOVPQIto64rr",
946 "PMOVMSKBrr",
947 "UCOMISDrr",
948 "UCOMISSrr",
949 "VCOMISDrr",
950 "VCOMISSrr",
951 "VMOVMSKPDYrr",
952 "VMOVMSKPDrr",
953 "VMOVMSKPSYrr",
954 "VMOVMSKPSrr",
955 "VMOVPDI2DIrr",
956 "VMOVPQIto64rr",
957 "VPMOVMSKBYrr",
958 "VPMOVMSKBrr",
959 "VTESTPDYrr",
960 "VTESTPDrr",
961 "VTESTPSYrr",
962 "VTESTPSrr",
963 "VUCOMISDrr",
964 "VUCOMISSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]965
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]966def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]967 let Latency = 2;
968 let NumMicroOps = 2;
969 let ResourceCycles = [2];
970}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]971def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr",
972 "MMX_PINSRWrr",
973 "PINSRBrr",
974 "PINSRDrr",
975 "PINSRQrr",
976 "PINSRWrr",
977 "VPINSRBrr",
978 "VPINSRDrr",
979 "VPINSRQrr",
980 "VPINSRWrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]981
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]982def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]983 let Latency = 2;
984 let NumMicroOps = 2;
985 let ResourceCycles = [2];
986}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]987def: InstRW<[SKLWriteResGroup14], (instregex "FDECSTP",
988 "MMX_MOVDQ2Qrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]989
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]990def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]991 let Latency = 2;
992 let NumMicroOps = 2;
993 let ResourceCycles = [2];
994}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]995def: InstRW<[SKLWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr",
996 "ROL(8|16|32|64)r1",
997 "ROL(8|16|32|64)ri",
998 "ROR(8|16|32|64)r1",
999 "ROR(8|16|32|64)ri",
1000 "SET(A|BE)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1001
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1002def SKLWriteResGroup16 : SchedWriteRes<[SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1003 let Latency = 2;
1004 let NumMicroOps = 2;
1005 let ResourceCycles = [2];
1006}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1007def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPDrr0",
1008 "BLENDVPSrr0",
1009 "PBLENDVBrr0",
1010 "VBLENDVPDYrr",
1011 "VBLENDVPDrr",
1012 "VBLENDVPSYrr",
1013 "VBLENDVPSrr",
1014 "VPBLENDVBYrr",
1015 "VPBLENDVBrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1016
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1017def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1018 let Latency = 2;
1019 let NumMicroOps = 2;
1020 let ResourceCycles = [2];
1021}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1022def: InstRW<[SKLWriteResGroup17], (instregex "LFENCE",
1023 "WAIT",
1024 "XGETBV")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1025
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1026def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,SKLPort237]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1027 let Latency = 2;
1028 let NumMicroOps = 2;
1029 let ResourceCycles = [1,1];
1030}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1031def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr",
1032 "VMASKMOVPDmr",
1033 "VMASKMOVPSYmr",
1034 "VMASKMOVPSmr",
1035 "VPMASKMOVDYmr",
1036 "VPMASKMOVDmr",
1037 "VPMASKMOVQYmr",
1038 "VPMASKMOVQmr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1039
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1040def SKLWriteResGroup19 : SchedWriteRes<[SKLPort5,SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1041 let Latency = 2;
1042 let NumMicroOps = 2;
1043 let ResourceCycles = [1,1];
1044}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1045def: InstRW<[SKLWriteResGroup19], (instregex "PSLLDrr",
1046 "PSLLQrr",
1047 "PSLLWrr",
1048 "PSRADrr",
1049 "PSRAWrr",
1050 "PSRLDrr",
1051 "PSRLQrr",
1052 "PSRLWrr",
1053 "VPSLLDrr",
1054 "VPSLLQrr",
1055 "VPSLLWrr",
1056 "VPSRADrr",
1057 "VPSRAWrr",
1058 "VPSRLDrr",
1059 "VPSRLQrr",
1060 "VPSRLWrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1061
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1062def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1063 let Latency = 2;
1064 let NumMicroOps = 2;
1065 let ResourceCycles = [1,1];
1066}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1067def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1068
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1069def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1070 let Latency = 2;
1071 let NumMicroOps = 2;
1072 let ResourceCycles = [1,1];
1073}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1074def: InstRW<[SKLWriteResGroup21], (instregex "SFENCE")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1075
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1076def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,SKLPort15]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1077 let Latency = 2;
1078 let NumMicroOps = 2;
1079 let ResourceCycles = [1,1];
1080}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1081def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR(32|64)rr",
1082 "BSWAP(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1083
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1084def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1085 let Latency = 2;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1086 let NumMicroOps = 2;
1087 let ResourceCycles = [1,1];
1088}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1089def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]1090def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1091def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8",
1092 "ADC8ri",
1093 "SBB8i8",
1094 "SBB8ri")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1095
1096def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
1097 let Latency = 2;
1098 let NumMicroOps = 3;
1099 let ResourceCycles = [1,1,1];
1100}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1101def: InstRW<[SKLWriteResGroup24], (instregex "EXTRACTPSmr",
1102 "PEXTRBmr",
1103 "PEXTRDmr",
1104 "PEXTRQmr",
1105 "PEXTRWmr",
1106 "STMXCSR",
1107 "VEXTRACTPSmr",
1108 "VPEXTRBmr",
1109 "VPEXTRDmr",
1110 "VPEXTRQmr",
1111 "VPEXTRWmr",
1112 "VSTMXCSR")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1113
1114def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
1115 let Latency = 2;
1116 let NumMicroOps = 3;
1117 let ResourceCycles = [1,1,1];
1118}
1119def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;
1120
1121def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1122 let Latency = 2;
1123 let NumMicroOps = 3;
1124 let ResourceCycles = [1,1,1];
1125}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1126def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1127
1128def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
1129 let Latency = 2;
1130 let NumMicroOps = 3;
1131 let ResourceCycles = [1,1,1];
1132}
1133def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
1134
1135def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
1136 let Latency = 2;
1137 let NumMicroOps = 3;
1138 let ResourceCycles = [1,1,1];
1139}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1140def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1141def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
1142 "PUSH64i8",
1143 "STOSB",
1144 "STOSL",
1145 "STOSQ",
1146 "STOSW")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1147
1148def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
1149 let Latency = 3;
1150 let NumMicroOps = 1;
1151 let ResourceCycles = [1];
1152}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1153def: InstRW<[SKLWriteResGroup29], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1154def: InstRW<[SKLWriteResGroup29], (instrs IMUL8r, MUL8r)>;
1155def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr",
1156 "BSR(16|32|64)rr",
1157 "LZCNT(16|32|64)rr",
1158 "PDEP(32|64)rr",
1159 "PEXT(32|64)rr",
1160 "POPCNT(16|32|64)rr",
1161 "SHLD(16|32|64)rri8",
1162 "SHRD(16|32|64)rri8",
1163 "TZCNT(16|32|64)rr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1164
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1165def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> {
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1166 let Latency = 3;
1167 let NumMicroOps = 2;
1168 let ResourceCycles = [1,1];
1169}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1170def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1171
1172def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
1173 let Latency = 3;
1174 let NumMicroOps = 1;
1175 let ResourceCycles = [1];
1176}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1177def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0",
1178 "ADD_FST0r",
1179 "ADD_FrST0",
1180 "MMX_PSADBWirr",
1181 "PCMPGTQrr",
1182 "PSADBWrr",
1183 "SUBR_FPrST0",
1184 "SUBR_FST0r",
1185 "SUBR_FrST0",
1186 "SUB_FPrST0",
1187 "SUB_FST0r",
1188 "SUB_FrST0",
1189 "VBROADCASTSDYrr",
1190 "VBROADCASTSSYrr",
1191 "VEXTRACTF128rr",
1192 "VEXTRACTI128rr",
1193 "VINSERTF128rr",
1194 "VINSERTI128rr",
1195 "VPBROADCASTBYrr",
1196 "VPBROADCASTBrr",
1197 "VPBROADCASTDYrr",
1198 "VPBROADCASTQYrr",
1199 "VPBROADCASTWYrr",
1200 "VPBROADCASTWrr",
1201 "VPCMPGTQYrr",
1202 "VPCMPGTQrr",
1203 "VPERM2F128rr",
1204 "VPERM2I128rr",
1205 "VPERMDYrr",
1206 "VPERMPDYri",
1207 "VPERMPSYrr",
1208 "VPERMQYri",
1209 "VPMOVSXBDYrr",
1210 "VPMOVSXBQYrr",
1211 "VPMOVSXBWYrr",
1212 "VPMOVSXDQYrr",
1213 "VPMOVSXWDYrr",
1214 "VPMOVSXWQYrr",
1215 "VPMOVZXBDYrr",
1216 "VPMOVZXBQYrr",
1217 "VPMOVZXBWYrr",
1218 "VPMOVZXDQYrr",
1219 "VPMOVZXWDYrr",
1220 "VPMOVZXWQYrr",
1221 "VPSADBWYrr",
1222 "VPSADBWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1223
1224def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1225 let Latency = 3;
1226 let NumMicroOps = 2;
1227 let ResourceCycles = [1,1];
1228}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1229def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr",
1230 "MMX_PEXTRWrr",
1231 "PEXTRBrr",
1232 "PEXTRDrr",
1233 "PEXTRQrr",
1234 "PEXTRWrr",
1235 "PTESTrr",
1236 "VEXTRACTPSrr",
1237 "VPEXTRBrr",
1238 "VPEXTRDrr",
1239 "VPEXTRQrr",
1240 "VPEXTRWrr",
1241 "VPTESTYrr",
1242 "VPTESTrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1243
1244def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
1245 let Latency = 3;
1246 let NumMicroOps = 2;
1247 let ResourceCycles = [1,1];
1248}
1249def: InstRW<[SKLWriteResGroup32], (instregex "FNSTSW16r")>;
1250
1251def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
1252 let Latency = 3;
1253 let NumMicroOps = 3;
1254 let ResourceCycles = [3];
1255}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1256def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL",
1257 "ROR(8|16|32|64)rCL",
1258 "SAR(8|16|32|64)rCL",
1259 "SHL(8|16|32|64)rCL",
1260 "SHR(8|16|32|64)rCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1261
1262def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
1263 let Latency = 3;
1264 let NumMicroOps = 3;
1265 let ResourceCycles = [3];
1266}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1267def: InstRW<[SKLWriteResGroup34], (instregex "XADD(8|16|32|64)rr",
1268 "XCHG8rr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1269
1270def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1271 let Latency = 3;
1272 let NumMicroOps = 3;
1273 let ResourceCycles = [1,2];
1274}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1275def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr",
1276 "MMX_PHSUBSWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1277
1278def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1279 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1280 let NumMicroOps = 3;
1281 let ResourceCycles = [2,1];
1282}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1283def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr",
1284 "PHSUBSWrr",
1285 "VPHADDSWrr",
1286 "VPHADDSWYrr",
1287 "VPHSUBSWrr",
1288 "VPHSUBSWYrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1289
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1290def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
1291 let Latency = 3;
1292 let NumMicroOps = 3;
1293 let ResourceCycles = [2,1];
1294}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1295def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDDrr",
1296 "MMX_PHADDWrr",
1297 "MMX_PHSUBDrr",
1298 "MMX_PHSUBWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1299
1300def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort015]> {
1301 let Latency = 3;
1302 let NumMicroOps = 3;
1303 let ResourceCycles = [2,1];
1304}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1305def: InstRW<[SKLWriteResGroup38], (instregex "PHADDDrr",
1306 "PHADDWrr",
1307 "PHSUBDrr",
1308 "PHSUBWrr",
1309 "VPHADDDYrr",
1310 "VPHADDDrr",
1311 "VPHADDWYrr",
1312 "VPHADDWrr",
1313 "VPHSUBDYrr",
1314 "VPHSUBDrr",
1315 "VPHSUBWYrr",
1316 "VPHSUBWrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1317
1318def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1319 let Latency = 3;
1320 let NumMicroOps = 3;
1321 let ResourceCycles = [2,1];
1322}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1323def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr",
1324 "MMX_PACKSSWBirr",
1325 "MMX_PACKUSWBirr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1326
1327def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1328 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1329 let NumMicroOps = 3;
1330 let ResourceCycles = [1,2];
1331}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1332def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1333
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1334def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
1335 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1336 let NumMicroOps = 3;
1337 let ResourceCycles = [1,2];
1338}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1339def: InstRW<[SKLWriteResGroup41], (instregex "MFENCE")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1340
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1341def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1342 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1343 let NumMicroOps = 3;
1344 let ResourceCycles = [1,2];
1345}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1346def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",
1347 "RCL(8|16|32|64)ri",
1348 "RCR(8|16|32|64)r1",
1349 "RCR(8|16|32|64)ri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1350
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1351def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
1352 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1353 let NumMicroOps = 3;
1354 let ResourceCycles = [1,1,1];
1355}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1356def: InstRW<[SKLWriteResGroup43], (instregex "FNSTSWm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1357
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1358def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1359 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1360 let NumMicroOps = 4;
1361 let ResourceCycles = [1,1,2];
1362}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1363def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1364
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1365def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
1366 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1367 let NumMicroOps = 4;
1368 let ResourceCycles = [1,1,1,1];
1369}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1370def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1371
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1372def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
1373 let Latency = 3;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1374 let NumMicroOps = 4;
1375 let ResourceCycles = [1,1,1,1];
1376}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1377def: InstRW<[SKLWriteResGroup46], (instregex "CALL64pcrel32")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1378
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1379def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1380 let Latency = 4;
1381 let NumMicroOps = 1;
1382 let ResourceCycles = [1];
1383}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]1384def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1385 "MMX_PMADDWDirr",
1386 "MMX_PMULHRSWrr",
1387 "MMX_PMULHUWirr",
1388 "MMX_PMULHWirr",
1389 "MMX_PMULLWirr",
1390 "MMX_PMULUDQirr",
1391 "MUL_FPrST0",
1392 "MUL_FST0r",
1393 "MUL_FrST0",
1394 "RCPPSr",
1395 "RCPSSr",
1396 "RSQRTPSr",
1397 "RSQRTSSr",
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1398 "VRCPPSYr",
1399 "VRCPPSr",
1400 "VRCPSSr",
1401 "VRSQRTPSYr",
1402 "VRSQRTPSr",
1403 "VRSQRTSSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1404
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1405def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1406 let Latency = 4;
1407 let NumMicroOps = 1;
1408 let ResourceCycles = [1];
1409}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1410def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr",
1411 "ADDPSrr",
1412 "ADDSDrr",
1413 "ADDSSrr",
1414 "ADDSUBPDrr",
1415 "ADDSUBPSrr",
1416 "MULPDrr",
1417 "MULPSrr",
1418 "MULSDrr",
1419 "MULSSrr",
1420 "SUBPDrr",
1421 "SUBPSrr",
1422 "SUBSDrr",
1423 "SUBSSrr",
1424 "VADDPDYrr",
1425 "VADDPDrr",
1426 "VADDPSYrr",
1427 "VADDPSrr",
1428 "VADDSDrr",
1429 "VADDSSrr",
1430 "VADDSUBPDYrr",
1431 "VADDSUBPDrr",
1432 "VADDSUBPSYrr",
1433 "VADDSUBPSrr",
1434 "VMULPDYrr",
1435 "VMULPDrr",
1436 "VMULPSYrr",
1437 "VMULPSrr",
1438 "VMULSDrr",
1439 "VMULSSrr",
1440 "VSUBPDYrr",
1441 "VSUBPDrr",
1442 "VSUBPSYrr",
1443 "VSUBPSrr",
1444 "VSUBSDrr",
1445 "VSUBSSrr")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1446def: InstRW<[SKLWriteResGroup48],
1447 (instregex
1448 "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1449 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1450
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1451def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1452 let Latency = 4;
1453 let NumMicroOps = 1;
1454 let ResourceCycles = [1];
1455}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1456def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
1457 "CMPPSrri",
1458 "CMPSDrr",
1459 "CMPSSrr",
1460 "CVTDQ2PSrr",
1461 "CVTPS2DQrr",
1462 "CVTTPS2DQrr",
1463 "MAX(C?)PDrr",
1464 "MAX(C?)PSrr",
1465 "MAX(C?)SDrr",
1466 "MAX(C?)SSrr",
1467 "MIN(C?)PDrr",
1468 "MIN(C?)PSrr",
1469 "MIN(C?)SDrr",
1470 "MIN(C?)SSrr",
1471 "PHMINPOSUWrr",
1472 "PMADDUBSWrr",
1473 "PMADDWDrr",
1474 "PMULDQrr",
1475 "PMULHRSWrr",
1476 "PMULHUWrr",
1477 "PMULHWrr",
1478 "PMULLWrr",
1479 "PMULUDQrr",
1480 "VCMPPDYrri",
1481 "VCMPPDrri",
1482 "VCMPPSYrri",
1483 "VCMPPSrri",
1484 "VCMPSDrr",
1485 "VCMPSSrr",
1486 "VCVTDQ2PSYrr",
1487 "VCVTDQ2PSrr",
1488 "VCVTPS2DQYrr",
1489 "VCVTPS2DQrr",
1490 "VCVTTPS2DQYrr",
1491 "VCVTTPS2DQrr",
1492 "VMAX(C?)PDYrr",
1493 "VMAX(C?)PDrr",
1494 "VMAX(C?)PSYrr",
1495 "VMAX(C?)PSrr",
1496 "VMAX(C?)SDrr",
1497 "VMAX(C?)SSrr",
1498 "VMIN(C?)PDYrr",
1499 "VMIN(C?)PDrr",
1500 "VMIN(C?)PSYrr",
1501 "VMIN(C?)PSrr",
1502 "VMIN(C?)SDrr",
1503 "VMIN(C?)SSrr",
1504 "VPHMINPOSUWrr",
1505 "VPMADDUBSWYrr",
1506 "VPMADDUBSWrr",
1507 "VPMADDWDYrr",
1508 "VPMADDWDrr",
1509 "VPMULDQYrr",
1510 "VPMULDQrr",
1511 "VPMULHRSWYrr",
1512 "VPMULHRSWrr",
1513 "VPMULHUWYrr",
1514 "VPMULHUWrr",
1515 "VPMULHWYrr",
1516 "VPMULHWrr",
1517 "VPMULLWYrr",
1518 "VPMULLWrr",
1519 "VPMULUDQYrr",
1520 "VPMULUDQrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1521
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1522def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1523 let Latency = 4;
1524 let NumMicroOps = 2;
1525 let ResourceCycles = [2];
1526}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1527def: InstRW<[SKLWriteResGroup50], (instregex "MPSADBWrri",
1528 "VMPSADBWYrri",
1529 "VMPSADBWrri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1530
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1531def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1532 let Latency = 4;
1533 let NumMicroOps = 2;
1534 let ResourceCycles = [1,1];
1535}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1536def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r,
1537 MULX64rr)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1538
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1539def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1540 let Latency = 4;
1541 let NumMicroOps = 4;
1542}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1543def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1544
1545def SKLWriteResGroup52 : SchedWriteRes<[SKLPort5,SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1546 let Latency = 4;
1547 let NumMicroOps = 2;
1548 let ResourceCycles = [1,1];
1549}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1550def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLDYrr",
1551 "VPSLLQYrr",
1552 "VPSLLWYrr",
1553 "VPSRADYrr",
1554 "VPSRAWYrr",
1555 "VPSRLDYrr",
1556 "VPSRLQYrr",
1557 "VPSRLWYrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1558
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1559def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1560 let Latency = 4;
1561 let NumMicroOps = 3;
1562 let ResourceCycles = [1,1,1];
1563}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1564def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP16m",
1565 "ISTT_FP32m",
1566 "ISTT_FP64m",
1567 "IST_F16m",
1568 "IST_F32m",
1569 "IST_FP16m",
1570 "IST_FP32m",
1571 "IST_FP64m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1572
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1573def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1574 let Latency = 4;
1575 let NumMicroOps = 4;
1576 let ResourceCycles = [4];
1577}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1578def: InstRW<[SKLWriteResGroup54], (instregex "FNCLEX")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1579
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1580def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1581 let Latency = 4;
1582 let NumMicroOps = 4;
1583 let ResourceCycles = [1,3];
1584}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1585def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1586
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1587def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1588 let Latency = 4;
1589 let NumMicroOps = 4;
1590 let ResourceCycles = [1,3];
1591}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1592def: InstRW<[SKLWriteResGroup56], (instregex "VZEROUPPER")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1593
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1594def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1595 let Latency = 4;
1596 let NumMicroOps = 4;
1597 let ResourceCycles = [1,1,2];
1598}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1599def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1600
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1601def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
1602 let Latency = 5;
1603 let NumMicroOps = 1;
1604 let ResourceCycles = [1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1605}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1606def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm",
1607 "MMX_MOVD64to64rm",
1608 "MMX_MOVQ64rm",
1609 "MOV(8|16|32|64)rm",
1610 "MOV64toPQIrm",
1611 "MOVDDUPrm",
1612 "MOVDI2PDIrm",
1613 "MOVQI2PQIrm",
1614 "MOVSDrm",
1615 "MOVSSrm",
1616 "MOVSX(16|32|64)rm16",
1617 "MOVSX(16|32|64)rm32",
1618 "MOVSX(16|32|64)rm8",
1619 "MOVZX(16|32|64)rm16",
1620 "MOVZX(16|32|64)rm8",
1621 "PREFETCHNTA",
1622 "PREFETCHT0",
1623 "PREFETCHT1",
1624 "PREFETCHT2",
1625 "VMOV64toPQIrm",
1626 "VMOVDDUPrm",
1627 "VMOVDI2PDIrm",
1628 "VMOVQI2PQIrm",
1629 "VMOVSDrm",
1630 "VMOVSSrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1631
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1632def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1633 let Latency = 5;
1634 let NumMicroOps = 2;
1635 let ResourceCycles = [1,1];
1636}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1637def: InstRW<[SKLWriteResGroup59], (instregex "CVTDQ2PDrr",
1638 "MMX_CVTPI2PDirr",
1639 "VCVTDQ2PDrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1640
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1641def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1642 let Latency = 5;
1643 let NumMicroOps = 2;
1644 let ResourceCycles = [1,1];
1645}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1646def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2DQrr",
1647 "CVTPD2PSrr",
1648 "CVTPS2PDrr",
1649 "CVTSD2SSrr",
1650 "CVTSI642SDrr",
1651 "CVTSI2SDrr",
1652 "CVTSI2SSrr",
1653 "CVTSS2SDrr",
1654 "CVTTPD2DQrr",
1655 "MMX_CVTPD2PIirr",
1656 "MMX_CVTPS2PIirr",
1657 "MMX_CVTTPD2PIirr",
1658 "MMX_CVTTPS2PIirr",
1659 "VCVTPD2DQrr",
1660 "VCVTPD2PSrr",
1661 "VCVTPH2PSrr",
1662 "VCVTPS2PDrr",
1663 "VCVTPS2PHrr",
1664 "VCVTSD2SSrr",
1665 "VCVTSI642SDrr",
1666 "VCVTSI2SDrr",
1667 "VCVTSI2SSrr",
1668 "VCVTSS2SDrr",
1669 "VCVTTPD2DQrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1670
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1671def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1672 let Latency = 5;
1673 let NumMicroOps = 3;
1674 let ResourceCycles = [1,1,1];
1675}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1676def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1677
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1678def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1679 let Latency = 5;
1680 let NumMicroOps = 3;
1681 let ResourceCycles = [1,1,1];
1682}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1683def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1684def: InstRW<[SKLWriteResGroup62], (instrs MULX32rr)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1685
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1686def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1687 let Latency = 5;
1688 let NumMicroOps = 5;
1689 let ResourceCycles = [1,4];
1690}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1691def: InstRW<[SKLWriteResGroup63], (instregex "XSETBV")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1692
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1693def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1694 let Latency = 5;
1695 let NumMicroOps = 5;
1696 let ResourceCycles = [2,3];
1697}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]1698def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1699
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1700def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1701 let Latency = 5;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1702 let NumMicroOps = 6;
1703 let ResourceCycles = [1,1,4];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1704}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1705def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF16",
1706 "PUSHF64")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1707
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1708def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
1709 let Latency = 6;
1710 let NumMicroOps = 1;
1711 let ResourceCycles = [1];
1712}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1713def: InstRW<[SKLWriteResGroup67], (instregex "LDDQUrm",
1714 "MOVAPDrm",
1715 "MOVAPSrm",
1716 "MOVDQArm",
1717 "MOVDQUrm",
1718 "MOVNTDQArm",
1719 "MOVSHDUPrm",
1720 "MOVSLDUPrm",
1721 "MOVUPDrm",
1722 "MOVUPSrm",
1723 "VBROADCASTSSrm",
1724 "VLDDQUrm",
1725 "VMOVAPDrm",
1726 "VMOVAPSrm",
1727 "VMOVDQArm",
1728 "VMOVDQUrm",
1729 "VMOVNTDQArm",
1730 "VMOVSHDUPrm",
1731 "VMOVSLDUPrm",
1732 "VMOVUPDrm",
1733 "VMOVUPSrm",
1734 "VPBROADCASTDrm",
1735 "VPBROADCASTQrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1736
1737def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1738 let Latency = 6;
1739 let NumMicroOps = 2;
1740 let ResourceCycles = [2];
1741}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1742def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1743
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1744def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1745 let Latency = 6;
1746 let NumMicroOps = 2;
1747 let ResourceCycles = [1,1];
1748}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1749def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
1750 "MMX_PADDSWirm",
1751 "MMX_PADDUSBirm",
1752 "MMX_PADDUSWirm",
1753 "MMX_PAVGBirm",
1754 "MMX_PAVGWirm",
1755 "MMX_PCMPEQBirm",
1756 "MMX_PCMPEQDirm",
1757 "MMX_PCMPEQWirm",
1758 "MMX_PCMPGTBirm",
1759 "MMX_PCMPGTDirm",
1760 "MMX_PCMPGTWirm",
1761 "MMX_PMAXSWirm",
1762 "MMX_PMAXUBirm",
1763 "MMX_PMINSWirm",
1764 "MMX_PMINUBirm",
1765 "MMX_PSLLDrm",
1766 "MMX_PSLLQrm",
1767 "MMX_PSLLWrm",
1768 "MMX_PSRADrm",
1769 "MMX_PSRAWrm",
1770 "MMX_PSRLDrm",
1771 "MMX_PSRLQrm",
1772 "MMX_PSRLWrm",
1773 "MMX_PSUBSBirm",
1774 "MMX_PSUBSWirm",
1775 "MMX_PSUBUSBirm",
1776 "MMX_PSUBUSWirm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1777
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1778def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1779 let Latency = 6;
1780 let NumMicroOps = 2;
1781 let ResourceCycles = [1,1];
1782}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1783def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SI64rr",
1784 "CVTSD2SIrr",
1785 "CVTSS2SI64rr",
1786 "CVTSS2SIrr",
1787 "CVTTSD2SI64rr",
1788 "CVTTSD2SIrr",
1789 "VCVTSD2SI64rr",
1790 "VCVTSD2SIrr",
1791 "VCVTSS2SI64rr",
1792 "VCVTSS2SIrr",
1793 "VCVTTSD2SI64rr",
1794 "VCVTTSD2SIrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1795
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1796def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1797 let Latency = 6;
1798 let NumMicroOps = 2;
1799 let ResourceCycles = [1,1];
1800}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1801def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi",
1802 "MMX_PINSRWrm",
1803 "MMX_PSHUFBrm",
1804 "MMX_PSHUFWmi",
1805 "MMX_PUNPCKHBWirm",
1806 "MMX_PUNPCKHDQirm",
1807 "MMX_PUNPCKHWDirm",
1808 "MMX_PUNPCKLBWirm",
1809 "MMX_PUNPCKLDQirm",
1810 "MMX_PUNPCKLWDirm",
1811 "MOVHPDrm",
1812 "MOVHPSrm",
1813 "MOVLPDrm",
1814 "MOVLPSrm",
1815 "PINSRBrm",
1816 "PINSRDrm",
1817 "PINSRQrm",
1818 "PINSRWrm",
1819 "PMOVSXBDrm",
1820 "PMOVSXBQrm",
1821 "PMOVSXBWrm",
1822 "PMOVSXDQrm",
1823 "PMOVSXWDrm",
1824 "PMOVSXWQrm",
1825 "PMOVZXBDrm",
1826 "PMOVZXBQrm",
1827 "PMOVZXBWrm",
1828 "PMOVZXDQrm",
1829 "PMOVZXWDrm",
1830 "PMOVZXWQrm",
1831 "VMOVHPDrm",
1832 "VMOVHPSrm",
1833 "VMOVLPDrm",
1834 "VMOVLPSrm",
1835 "VPINSRBrm",
1836 "VPINSRDrm",
1837 "VPINSRQrm",
1838 "VPINSRWrm",
1839 "VPMOVSXBDrm",
1840 "VPMOVSXBQrm",
1841 "VPMOVSXBWrm",
1842 "VPMOVSXDQrm",
1843 "VPMOVSXWDrm",
1844 "VPMOVSXWQrm",
1845 "VPMOVZXBDrm",
1846 "VPMOVZXBQrm",
1847 "VPMOVZXBWrm",
1848 "VPMOVZXDQrm",
1849 "VPMOVZXWDrm",
1850 "VPMOVZXWQrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1851
1852def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1853 let Latency = 6;
1854 let NumMicroOps = 2;
1855 let ResourceCycles = [1,1];
1856}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1857def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64",
1858 "JMP(16|32|64)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1859
1860def SKLWriteResGroup73 : SchedWriteRes<[SKLPort23,SKLPort05]> {
1861 let Latency = 6;
1862 let NumMicroOps = 2;
1863 let ResourceCycles = [1,1];
1864}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1865def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm",
1866 "MMX_PABSDrm",
1867 "MMX_PABSWrm",
1868 "MMX_PADDBirm",
1869 "MMX_PADDDirm",
1870 "MMX_PADDQirm",
1871 "MMX_PADDWirm",
1872 "MMX_PANDNirm",
1873 "MMX_PANDirm",
1874 "MMX_PORirm",
1875 "MMX_PSIGNBrm",
1876 "MMX_PSIGNDrm",
1877 "MMX_PSIGNWrm",
1878 "MMX_PSUBBirm",
1879 "MMX_PSUBDirm",
1880 "MMX_PSUBQirm",
1881 "MMX_PSUBWirm",
1882 "MMX_PXORirm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1883
1884def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
1885 let Latency = 6;
1886 let NumMicroOps = 2;
1887 let ResourceCycles = [1,1];
1888}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1889def: InstRW<[SKLWriteResGroup74], (instregex "ADC(8|16|32|64)rm",
1890 "ADCX(32|64)rm",
1891 "ADOX(32|64)rm",
1892 "BT(16|32|64)mi8",
1893 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1894 "RORX(32|64)mi",
1895 "SARX(32|64)rm",
1896 "SBB(8|16|32|64)rm",
1897 "SHLX(32|64)rm",
1898 "SHRX(32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1899
1900def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1901 let Latency = 6;
1902 let NumMicroOps = 2;
1903 let ResourceCycles = [1,1];
1904}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1905def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1906 "BLSI(32|64)rm",
1907 "BLSMSK(32|64)rm",
1908 "BLSR(32|64)rm",
1909 "BZHI(32|64)rm",
1910 "MOVBE(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1911
1912def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1913 let Latency = 6;
1914 let NumMicroOps = 2;
1915 let ResourceCycles = [1,1];
1916}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1917def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1918def: InstRW<[SKLWriteResGroup76], (instregex "ADD(8|16|32|64)rm",
1919 "AND(8|16|32|64)rm",
1920 "CMP(8|16|32|64)mi",
1921 "CMP(8|16|32|64)mr",
1922 "CMP(8|16|32|64)rm",
1923 "OR(8|16|32|64)rm",
1924 "POP(16|32|64)rmr",
1925 "SUB(8|16|32|64)rm",
1926 "TEST(8|16|32|64)mr",
1927 "TEST(8|16|32|64)mi",
1928 "XOR(8|16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1929
1930def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1931 let Latency = 6;
1932 let NumMicroOps = 3;
1933 let ResourceCycles = [2,1];
1934}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1935def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr",
1936 "HADDPSrr",
1937 "HSUBPDrr",
1938 "HSUBPSrr",
1939 "VHADDPDYrr",
1940 "VHADDPDrr",
1941 "VHADDPSYrr",
1942 "VHADDPSrr",
1943 "VHSUBPDYrr",
1944 "VHSUBPDrr",
1945 "VHSUBPSYrr",
1946 "VHSUBPSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1947
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1948def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1949 let Latency = 6;
1950 let NumMicroOps = 3;
1951 let ResourceCycles = [2,1];
1952}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1953def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1954
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1955def SKLWriteResGroup79 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1956 let Latency = 6;
1957 let NumMicroOps = 4;
1958 let ResourceCycles = [1,2,1];
1959}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1960def: InstRW<[SKLWriteResGroup79], (instregex "SHLD(16|32|64)rrCL",
1961 "SHRD(16|32|64)rrCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1962
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1963def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1964 let Latency = 6;
1965 let NumMicroOps = 4;
1966 let ResourceCycles = [1,1,1,1];
1967}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1968def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]1969
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1970def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
1971 let Latency = 6;
1972 let NumMicroOps = 4;
1973 let ResourceCycles = [1,1,1,1];
1974}
1975def: InstRW<[SKLWriteResGroup81], (instregex "VCVTPS2PHmr")>;
1976
1977def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1978 let Latency = 6;
1979 let NumMicroOps = 4;
1980 let ResourceCycles = [1,1,1,1];
1981}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1982def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",
1983 "BTR(16|32|64)mi8",
1984 "BTS(16|32|64)mi8",
1985 "SAR(8|16|32|64)m1",
1986 "SAR(8|16|32|64)mi",
1987 "SHL(8|16|32|64)m1",
1988 "SHL(8|16|32|64)mi",
1989 "SHR(8|16|32|64)m1",
1990 "SHR(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]1991
1992def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1993 let Latency = 6;
1994 let NumMicroOps = 4;
1995 let ResourceCycles = [1,1,1,1];
1996}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]1997def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mi",
1998 "ADD(8|16|32|64)mr",
1999 "AND(8|16|32|64)mi",
2000 "AND(8|16|32|64)mr",
2001 "DEC(8|16|32|64)m",
2002 "INC(8|16|32|64)m",
2003 "NEG(8|16|32|64)m",
2004 "NOT(8|16|32|64)m",
2005 "OR(8|16|32|64)mi",
2006 "OR(8|16|32|64)mr",
2007 "POP(16|32|64)rmm",
2008 "PUSH(16|32|64)rmm",
2009 "SUB(8|16|32|64)mi",
2010 "SUB(8|16|32|64)mr",
2011 "XOR(8|16|32|64)mi",
2012 "XOR(8|16|32|64)mr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2013
2014def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2015 let Latency = 6;
2016 let NumMicroOps = 6;
2017 let ResourceCycles = [1,5];
2018}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2019def: InstRW<[SKLWriteResGroup84], (instregex "STD")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2020
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2021def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
2022 let Latency = 7;
2023 let NumMicroOps = 1;
2024 let ResourceCycles = [1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2025}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2026def: InstRW<[SKLWriteResGroup85], (instregex "LD_F32m",
2027 "LD_F64m",
2028 "LD_F80m",
2029 "VBROADCASTF128",
2030 "VBROADCASTI128",
2031 "VBROADCASTSDYrm",
2032 "VBROADCASTSSYrm",
2033 "VLDDQUYrm",
2034 "VMOVAPDYrm",
2035 "VMOVAPSYrm",
2036 "VMOVDDUPYrm",
2037 "VMOVDQAYrm",
2038 "VMOVDQUYrm",
2039 "VMOVNTDQAYrm",
2040 "VMOVSHDUPYrm",
2041 "VMOVSLDUPYrm",
2042 "VMOVUPDYrm",
2043 "VMOVUPSYrm",
2044 "VPBROADCASTDYrm",
2045 "VPBROADCASTQYrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2046
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2047def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2048 let Latency = 7;
2049 let NumMicroOps = 2;
2050 let ResourceCycles = [1,1];
2051}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2052def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2053
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2054def SKLWriteResGroup87 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2055 let Latency = 7;
2056 let NumMicroOps = 2;
2057 let ResourceCycles = [1,1];
2058}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2059def: InstRW<[SKLWriteResGroup87], (instregex "COMISDrm",
2060 "COMISSrm",
2061 "UCOMISDrm",
2062 "UCOMISSrm",
2063 "VCOMISDrm",
2064 "VCOMISSrm",
2065 "VUCOMISDrm",
2066 "VUCOMISSrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2067
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2068def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2069 let Latency = 7;
2070 let NumMicroOps = 2;
2071 let ResourceCycles = [1,1];
2072}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2073def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm",
2074 "PACKSSDWrm",
2075 "PACKSSWBrm",
2076 "PACKUSDWrm",
2077 "PACKUSWBrm",
2078 "PALIGNRrmi",
2079 "PBLENDWrmi",
2080 "PSHUFBrm",
2081 "PSHUFDmi",
2082 "PSHUFHWmi",
2083 "PSHUFLWmi",
2084 "PUNPCKHBWrm",
2085 "PUNPCKHDQrm",
2086 "PUNPCKHQDQrm",
2087 "PUNPCKHWDrm",
2088 "PUNPCKLBWrm",
2089 "PUNPCKLDQrm",
2090 "PUNPCKLQDQrm",
2091 "PUNPCKLWDrm",
2092 "SHUFPDrmi",
2093 "SHUFPSrmi",
2094 "UNPCKHPDrm",
2095 "UNPCKHPSrm",
2096 "UNPCKLPDrm",
2097 "UNPCKLPSrm",
2098 "VINSERTPSrm",
2099 "VPACKSSDWrm",
2100 "VPACKSSWBrm",
2101 "VPACKUSDWrm",
2102 "VPACKUSWBrm",
2103 "VPALIGNRrmi",
2104 "VPBLENDWrmi",
2105 "VPBROADCASTBrm",
2106 "VPBROADCASTWrm",
2107 "VPERMILPDmi",
2108 "VPERMILPDrm",
2109 "VPERMILPSmi",
2110 "VPERMILPSrm",
2111 "VPSHUFBrm",
2112 "VPSHUFDmi",
2113 "VPSHUFHWmi",
2114 "VPSHUFLWmi",
2115 "VPUNPCKHBWrm",
2116 "VPUNPCKHDQrm",
2117 "VPUNPCKHQDQrm",
2118 "VPUNPCKHWDrm",
2119 "VPUNPCKLBWrm",
2120 "VPUNPCKLDQrm",
2121 "VPUNPCKLQDQrm",
2122 "VPUNPCKLWDrm",
2123 "VSHUFPDrmi",
2124 "VSHUFPSrmi",
2125 "VUNPCKHPDrm",
2126 "VUNPCKHPSrm",
2127 "VUNPCKLPDrm",
2128 "VUNPCKLPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2129
2130def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort015]> {
2131 let Latency = 7;
2132 let NumMicroOps = 2;
2133 let ResourceCycles = [1,1];
2134}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2135def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr",
2136 "VCVTPD2PSYrr",
2137 "VCVTPH2PSYrr",
2138 "VCVTPS2PDYrr",
2139 "VCVTPS2PHYrr",
2140 "VCVTTPD2DQYrr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2141
2142def SKLWriteResGroup90 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2143 let Latency = 7;
2144 let NumMicroOps = 2;
2145 let ResourceCycles = [1,1];
2146}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2147def: InstRW<[SKLWriteResGroup90], (instregex "PABSBrm",
2148 "PABSDrm",
2149 "PABSWrm",
2150 "PADDSBrm",
2151 "PADDSWrm",
2152 "PADDUSBrm",
2153 "PADDUSWrm",
2154 "PAVGBrm",
2155 "PAVGWrm",
2156 "PCMPEQBrm",
2157 "PCMPEQDrm",
2158 "PCMPEQQrm",
2159 "PCMPEQWrm",
2160 "PCMPGTBrm",
2161 "PCMPGTDrm",
2162 "PCMPGTWrm",
2163 "PMAXSBrm",
2164 "PMAXSDrm",
2165 "PMAXSWrm",
2166 "PMAXUBrm",
2167 "PMAXUDrm",
2168 "PMAXUWrm",
2169 "PMINSBrm",
2170 "PMINSDrm",
2171 "PMINSWrm",
2172 "PMINUBrm",
2173 "PMINUDrm",
2174 "PMINUWrm",
2175 "PSIGNBrm",
2176 "PSIGNDrm",
2177 "PSIGNWrm",
2178 "PSLLDrm",
2179 "PSLLQrm",
2180 "PSLLWrm",
2181 "PSRADrm",
2182 "PSRAWrm",
2183 "PSRLDrm",
2184 "PSRLQrm",
2185 "PSRLWrm",
2186 "PSUBSBrm",
2187 "PSUBSWrm",
2188 "PSUBUSBrm",
2189 "PSUBUSWrm",
2190 "VPABSBrm",
2191 "VPABSDrm",
2192 "VPABSWrm",
2193 "VPADDSBrm",
2194 "VPADDSWrm",
2195 "VPADDUSBrm",
2196 "VPADDUSWrm",
2197 "VPAVGBrm",
2198 "VPAVGWrm",
2199 "VPCMPEQBrm",
2200 "VPCMPEQDrm",
2201 "VPCMPEQQrm",
2202 "VPCMPEQWrm",
2203 "VPCMPGTBrm",
2204 "VPCMPGTDrm",
2205 "VPCMPGTWrm",
2206 "VPMAXSBrm",
2207 "VPMAXSDrm",
2208 "VPMAXSWrm",
2209 "VPMAXUBrm",
2210 "VPMAXUDrm",
2211 "VPMAXUWrm",
2212 "VPMINSBrm",
2213 "VPMINSDrm",
2214 "VPMINSWrm",
2215 "VPMINUBrm",
2216 "VPMINUDrm",
2217 "VPMINUWrm",
2218 "VPSIGNBrm",
2219 "VPSIGNDrm",
2220 "VPSIGNWrm",
2221 "VPSLLDrm",
2222 "VPSLLQrm",
2223 "VPSLLVDrm",
2224 "VPSLLVQrm",
2225 "VPSLLWrm",
2226 "VPSRADrm",
2227 "VPSRAVDrm",
2228 "VPSRAWrm",
2229 "VPSRLDrm",
2230 "VPSRLQrm",
2231 "VPSRLVDrm",
2232 "VPSRLVQrm",
2233 "VPSRLWrm",
2234 "VPSUBSBrm",
2235 "VPSUBSWrm",
2236 "VPSUBUSBrm",
2237 "VPSUBUSWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2238
2239def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2240 let Latency = 7;
2241 let NumMicroOps = 2;
2242 let ResourceCycles = [1,1];
2243}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2244def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPDrm",
2245 "ANDNPSrm",
2246 "ANDPDrm",
2247 "ANDPSrm",
2248 "BLENDPDrmi",
2249 "BLENDPSrmi",
2250 "ORPDrm",
2251 "ORPSrm",
2252 "PADDBrm",
2253 "PADDDrm",
2254 "PADDQrm",
2255 "PADDWrm",
2256 "PANDNrm",
2257 "PANDrm",
2258 "PORrm",
2259 "PSUBBrm",
2260 "PSUBDrm",
2261 "PSUBQrm",
2262 "PSUBWrm",
2263 "PXORrm",
2264 "VANDNPDrm",
2265 "VANDNPSrm",
2266 "VANDPDrm",
2267 "VANDPSrm",
2268 "VBLENDPDrmi",
2269 "VBLENDPSrmi",
2270 "VINSERTF128rm",
2271 "VINSERTI128rm",
2272 "VMASKMOVPDrm",
2273 "VMASKMOVPSrm",
2274 "VORPDrm",
2275 "VORPSrm",
2276 "VPADDBrm",
2277 "VPADDDrm",
2278 "VPADDQrm",
2279 "VPADDWrm",
2280 "VPANDNrm",
2281 "VPANDrm",
2282 "VPBLENDDrmi",
2283 "VPMASKMOVDrm",
2284 "VPMASKMOVQrm",
2285 "VPORrm",
2286 "VPSUBBrm",
2287 "VPSUBDrm",
2288 "VPSUBQrm",
2289 "VPSUBWrm",
2290 "VPXORrm",
2291 "VXORPDrm",
2292 "VXORPSrm",
2293 "XORPDrm",
2294 "XORPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2295
2296def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2297 let Latency = 7;
2298 let NumMicroOps = 3;
2299 let ResourceCycles = [2,1];
2300}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2301def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm",
2302 "MMX_PACKSSWBirm",
2303 "MMX_PACKUSWBirm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2304
2305def SKLWriteResGroup93 : SchedWriteRes<[SKLPort23,SKLPort06]> {
2306 let Latency = 7;
2307 let NumMicroOps = 3;
2308 let ResourceCycles = [1,2];
2309}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]2310def: InstRW<[SKLWriteResGroup93], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2311
2312def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
2313 let Latency = 7;
2314 let NumMicroOps = 3;
2315 let ResourceCycles = [1,2];
2316}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2317def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64",
2318 "SCASB",
2319 "SCASL",
2320 "SCASQ",
2321 "SCASW")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2322
2323def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2324 let Latency = 7;
2325 let NumMicroOps = 3;
2326 let ResourceCycles = [1,1,1];
2327}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2328def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI64rr",
2329 "(V?)CVTTSS2SIrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2330
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2331def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2332 let Latency = 7;
2333 let NumMicroOps = 3;
2334 let ResourceCycles = [1,1,1];
2335}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2336def: InstRW<[SKLWriteResGroup96], (instregex "FLDCW16m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2337
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2338def SKLWriteResGroup97 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2339 let Latency = 7;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2340 let NumMicroOps = 3;
2341 let ResourceCycles = [1,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2342}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2343def: InstRW<[SKLWriteResGroup97], (instregex "(V?)LDMXCSR")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2344
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2345def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2346 let Latency = 7;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2347 let NumMicroOps = 3;
2348 let ResourceCycles = [1,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2349}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2350def: InstRW<[SKLWriteResGroup98], (instregex "LRETQ",
2351 "RETQ")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2352
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2353def SKLWriteResGroup99 : SchedWriteRes<[SKLPort23,SKLPort06,SKLPort15]> {
2354 let Latency = 7;
2355 let NumMicroOps = 3;
2356 let ResourceCycles = [1,1,1];
2357}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]2358def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR(32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2359
2360def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
2361 let Latency = 7;
2362 let NumMicroOps = 5;
2363 let ResourceCycles = [1,1,1,2];
2364}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2365def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",
2366 "ROL(8|16|32|64)mi",
2367 "ROR(8|16|32|64)m1",
2368 "ROR(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2369
2370def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
2371 let Latency = 7;
2372 let NumMicroOps = 5;
2373 let ResourceCycles = [1,1,1,2];
2374}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2375def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2376
2377def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
2378 let Latency = 7;
2379 let NumMicroOps = 5;
2380 let ResourceCycles = [1,1,1,1,1];
2381}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2382def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m",
2383 "FARCALL64")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2384
2385def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2386 let Latency = 7;
2387 let NumMicroOps = 7;
2388 let ResourceCycles = [1,3,1,2];
2389}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2390def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2391
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2392def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2393 let Latency = 8;
2394 let NumMicroOps = 2;
2395 let ResourceCycles = [2];
2396}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2397def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr",
2398 "ROUNDPSr",
2399 "ROUNDSDr",
2400 "ROUNDSSr",
2401 "VROUNDPDr",
2402 "VROUNDPSr",
2403 "VROUNDSDr",
2404 "VROUNDSSr",
2405 "VROUNDYPDr",
2406 "VROUNDYPSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2407
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]2408def SKLWriteResGroup105_2 : SchedWriteRes<[SKLPort01]> {
2409 let Latency = 10;
2410 let NumMicroOps = 2;
2411 let ResourceCycles = [2];
2412}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2413def: InstRW<[SKLWriteResGroup105_2], (instregex "PMULLDrr",
2414 "VPMULLDYrr",
2415 "VPMULLDrr")>;
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]2416
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2417def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2418 let Latency = 8;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2419 let NumMicroOps = 2;
2420 let ResourceCycles = [1,1];
2421}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2422def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPDrm",
2423 "VTESTPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2424
2425def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
2426 let Latency = 8;
2427 let NumMicroOps = 2;
2428 let ResourceCycles = [1,1];
2429}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2430def: InstRW<[SKLWriteResGroup107], (instrs IMUL64m, MUL64m)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2431def: InstRW<[SKLWriteResGroup107], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>;
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2432def: InstRW<[SKLWriteResGroup107], (instrs IMUL8m, MUL8m)>;
2433def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm",
2434 "BSR(16|32|64)rm",
2435 "LZCNT(16|32|64)rm",
2436 "PDEP(32|64)rm",
2437 "PEXT(32|64)rm",
2438 "POPCNT(16|32|64)rm",
2439 "TZCNT(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2440
2441def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2442 let Latency = 8;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2443 let NumMicroOps = 3;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2444 let ResourceCycles = [1,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2445}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2446def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2447
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2448def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2449 let Latency = 8;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2450 let NumMicroOps = 5;
2451}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2452def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2453
2454def SKLWriteResGroup107_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2455 let Latency = 8;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2456 let NumMicroOps = 3;
2457 let ResourceCycles = [1,1,1];
2458}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2459def: InstRW<[SKLWriteResGroup107_32], (instrs IMUL32m, MUL32m)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2460
2461def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2462 let Latency = 8;
2463 let NumMicroOps = 2;
2464 let ResourceCycles = [1,1];
2465}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2466def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m",
2467 "FCOM64m",
2468 "FCOMP32m",
2469 "FCOMP64m",
2470 "MMX_PSADBWirm",
2471 "VPACKSSDWYrm",
2472 "VPACKSSWBYrm",
2473 "VPACKUSDWYrm",
2474 "VPACKUSWBYrm",
2475 "VPALIGNRYrmi",
2476 "VPBLENDWYrmi",
2477 "VPBROADCASTBYrm",
2478 "VPBROADCASTWYrm",
2479 "VPERMILPDYmi",
2480 "VPERMILPDYrm",
2481 "VPERMILPSYmi",
2482 "VPERMILPSYrm",
2483 "VPMOVSXBDYrm",
2484 "VPMOVSXBQYrm",
2485 "VPMOVSXWQYrm",
2486 "VPSHUFBYrm",
2487 "VPSHUFDYmi",
2488 "VPSHUFHWYmi",
2489 "VPSHUFLWYmi",
2490 "VPUNPCKHBWYrm",
2491 "VPUNPCKHDQYrm",
2492 "VPUNPCKHQDQYrm",
2493 "VPUNPCKHWDYrm",
2494 "VPUNPCKLBWYrm",
2495 "VPUNPCKLDQYrm",
2496 "VPUNPCKLQDQYrm",
2497 "VPUNPCKLWDYrm",
2498 "VSHUFPDYrmi",
2499 "VSHUFPSYrmi",
2500 "VUNPCKHPDYrm",
2501 "VUNPCKHPSYrm",
2502 "VUNPCKLPDYrm",
2503 "VUNPCKLPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2504
2505def SKLWriteResGroup109 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2506 let Latency = 8;
2507 let NumMicroOps = 2;
2508 let ResourceCycles = [1,1];
2509}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2510def: InstRW<[SKLWriteResGroup109], (instregex "VPABSBYrm",
2511 "VPABSDYrm",
2512 "VPABSWYrm",
2513 "VPADDSBYrm",
2514 "VPADDSWYrm",
2515 "VPADDUSBYrm",
2516 "VPADDUSWYrm",
2517 "VPAVGBYrm",
2518 "VPAVGWYrm",
2519 "VPCMPEQBYrm",
2520 "VPCMPEQDYrm",
2521 "VPCMPEQQYrm",
2522 "VPCMPEQWYrm",
2523 "VPCMPGTBYrm",
2524 "VPCMPGTDYrm",
2525 "VPCMPGTWYrm",
2526 "VPMAXSBYrm",
2527 "VPMAXSDYrm",
2528 "VPMAXSWYrm",
2529 "VPMAXUBYrm",
2530 "VPMAXUDYrm",
2531 "VPMAXUWYrm",
2532 "VPMINSBYrm",
2533 "VPMINSDYrm",
2534 "VPMINSWYrm",
2535 "VPMINUBYrm",
2536 "VPMINUDYrm",
2537 "VPMINUWYrm",
2538 "VPSIGNBYrm",
2539 "VPSIGNDYrm",
2540 "VPSIGNWYrm",
2541 "VPSLLDYrm",
2542 "VPSLLQYrm",
2543 "VPSLLVDYrm",
2544 "VPSLLVQYrm",
2545 "VPSLLWYrm",
2546 "VPSRADYrm",
2547 "VPSRAVDYrm",
2548 "VPSRAWYrm",
2549 "VPSRLDYrm",
2550 "VPSRLQYrm",
2551 "VPSRLVDYrm",
2552 "VPSRLVQYrm",
2553 "VPSRLWYrm",
2554 "VPSUBSBYrm",
2555 "VPSUBSWYrm",
2556 "VPSUBUSBYrm",
2557 "VPSUBUSWYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2558
2559def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2560 let Latency = 8;
2561 let NumMicroOps = 2;
2562 let ResourceCycles = [1,1];
2563}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2564def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPDYrm",
2565 "VANDNPSYrm",
2566 "VANDPDYrm",
2567 "VANDPSYrm",
2568 "VBLENDPDYrmi",
2569 "VBLENDPSYrmi",
2570 "VMASKMOVPDYrm",
2571 "VMASKMOVPSYrm",
2572 "VORPDYrm",
2573 "VORPSYrm",
2574 "VPADDBYrm",
2575 "VPADDDYrm",
2576 "VPADDQYrm",
2577 "VPADDWYrm",
2578 "VPANDNYrm",
2579 "VPANDYrm",
2580 "VPBLENDDYrmi",
2581 "VPMASKMOVDYrm",
2582 "VPMASKMOVQYrm",
2583 "VPORYrm",
2584 "VPSUBBYrm",
2585 "VPSUBDYrm",
2586 "VPSUBQYrm",
2587 "VPSUBWYrm",
2588 "VPXORYrm",
2589 "VXORPDYrm",
2590 "VXORPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2591
2592def SKLWriteResGroup111 : SchedWriteRes<[SKLPort23,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2593 let Latency = 8;
2594 let NumMicroOps = 3;
2595 let ResourceCycles = [1,2];
2596}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2597def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPDrm0",
2598 "BLENDVPSrm0",
2599 "PBLENDVBrm0",
2600 "VBLENDVPDrm",
2601 "VBLENDVPSrm",
2602 "VPBLENDVBYrm",
2603 "VPBLENDVBrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2604
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2605def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
2606 let Latency = 8;
2607 let NumMicroOps = 4;
2608 let ResourceCycles = [1,2,1];
2609}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2610def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm",
2611 "MMX_PHSUBSWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2612
2613def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
2614 let Latency = 8;
2615 let NumMicroOps = 4;
2616 let ResourceCycles = [2,1,1];
2617}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2618def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm",
2619 "MMX_PHADDWrm",
2620 "MMX_PHSUBDrm",
2621 "MMX_PHSUBWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2622
2623def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
2624 let Latency = 8;
2625 let NumMicroOps = 4;
2626 let ResourceCycles = [1,1,1,1];
2627}
2628def: InstRW<[SKLWriteResGroup114], (instregex "VCVTPS2PHYmr")>;
2629
2630def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
2631 let Latency = 8;
2632 let NumMicroOps = 5;
2633 let ResourceCycles = [1,1,3];
2634}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2635def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2636
2637def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
2638 let Latency = 8;
2639 let NumMicroOps = 5;
2640 let ResourceCycles = [1,1,1,2];
2641}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2642def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",
2643 "RCL(8|16|32|64)mi",
2644 "RCR(8|16|32|64)m1",
2645 "RCR(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2646
2647def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
2648 let Latency = 8;
2649 let NumMicroOps = 6;
2650 let ResourceCycles = [1,1,1,3];
2651}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2652def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
2653 "SAR(8|16|32|64)mCL",
2654 "SHL(8|16|32|64)mCL",
2655 "SHR(8|16|32|64)mCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2656
2657def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
2658 let Latency = 8;
2659 let NumMicroOps = 6;
2660 let ResourceCycles = [1,1,1,3];
2661}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2662def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2663
2664def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
2665 let Latency = 8;
2666 let NumMicroOps = 6;
2667 let ResourceCycles = [1,1,1,2,1];
2668}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2669def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr",
2670 "CMPXCHG(8|16|32|64)rm",
2671 "SBB(8|16|32|64)mi",
2672 "SBB(8|16|32|64)mr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2673
2674def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
2675 let Latency = 9;
2676 let NumMicroOps = 2;
2677 let ResourceCycles = [1,1];
2678}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2679def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm",
2680 "MMX_PMADDUBSWrm",
2681 "MMX_PMADDWDirm",
2682 "MMX_PMULHRSWrm",
2683 "MMX_PMULHUWirm",
2684 "MMX_PMULHWirm",
2685 "MMX_PMULLWirm",
2686 "MMX_PMULUDQirm",
2687 "RCPSSm",
2688 "RSQRTSSm",
2689 "VRCPSSm",
2690 "VRSQRTSSm",
2691 "VTESTPDYrm",
2692 "VTESTPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2693
2694def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2695 let Latency = 9;
2696 let NumMicroOps = 2;
2697 let ResourceCycles = [1,1];
2698}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2699def: InstRW<[SKLWriteResGroup121], (instregex "PCMPGTQrm",
2700 "PSADBWrm",
2701 "VPCMPGTQrm",
2702 "VPMOVSXBWYrm",
2703 "VPMOVSXDQYrm",
2704 "VPMOVSXWDYrm",
2705 "VPMOVZXWDYrm",
2706 "VPSADBWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2707
2708def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2709 let Latency = 9;
2710 let NumMicroOps = 2;
2711 let ResourceCycles = [1,1];
2712}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2713def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm",
2714 "ADDSSrm",
2715 "MULSDrm",
2716 "MULSSrm",
2717 "SUBSDrm",
2718 "SUBSSrm",
2719 "VADDSDrm",
2720 "VADDSSrm",
2721 "VMULSDrm",
2722 "VMULSSrm",
2723 "VSUBSDrm",
2724 "VSUBSSrm")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2725def: InstRW<[SKLWriteResGroup122],
2726 (instregex "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2727
2728def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2729 let Latency = 9;
2730 let NumMicroOps = 2;
2731 let ResourceCycles = [1,1];
2732}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2733def: InstRW<[SKLWriteResGroup123], (instregex "CMPSDrm",
2734 "CMPSSrm",
2735 "CVTPS2PDrm",
2736 "MAX(C?)SDrm",
2737 "MAX(C?)SSrm",
2738 "MIN(C?)SDrm",
2739 "MIN(C?)SSrm",
2740 "MMX_CVTPS2PIirm",
2741 "MMX_CVTTPS2PIirm",
2742 "VCMPSDrm",
2743 "VCMPSSrm",
2744 "VCVTPH2PSrm",
2745 "VCVTPS2PDrm",
2746 "VMAX(C?)SDrm",
2747 "VMAX(C?)SSrm",
2748 "VMIN(C?)SDrm",
2749 "VMIN(C?)SSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2750
2751def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2752 let Latency = 9;
2753 let NumMicroOps = 3;
2754 let ResourceCycles = [1,2];
2755}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2756def: InstRW<[SKLWriteResGroup124], (instregex "(V?)DPPDrri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2757
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2758def SKLWriteResGroup125 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2759 let Latency = 9;
2760 let NumMicroOps = 3;
2761 let ResourceCycles = [1,2];
2762}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2763def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPDYrm",
2764 "VBLENDVPSYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2765
2766def SKLWriteResGroup126 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
2767 let Latency = 9;
2768 let NumMicroOps = 3;
2769 let ResourceCycles = [1,1,1];
2770}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2771def: InstRW<[SKLWriteResGroup126], (instregex "(V?)PTESTrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2772
2773def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
2774 let Latency = 9;
2775 let NumMicroOps = 3;
2776 let ResourceCycles = [1,1,1];
2777}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2778def: InstRW<[SKLWriteResGroup127], (instrs MULX64rm)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2779
2780def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2781 let Latency = 9;
2782 let NumMicroOps = 4;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2783 let ResourceCycles = [2,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2784}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2785def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
2786 "(V?)PHSUBSWrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2787
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2788def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
2789 let Latency = 9;
2790 let NumMicroOps = 4;
2791 let ResourceCycles = [2,1,1];
2792}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2793def: InstRW<[SKLWriteResGroup129], (instregex "(V?)PHADDDrm",
2794 "(V?)PHADDWrm",
2795 "(V?)PHSUBDrm",
2796 "(V?)PHSUBWrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2797
2798def SKLWriteResGroup130 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort0156]> {
2799 let Latency = 9;
2800 let NumMicroOps = 4;
2801 let ResourceCycles = [1,1,1,1];
2802}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2803def: InstRW<[SKLWriteResGroup130], (instregex "SHLD(16|32|64)mri8",
2804 "SHRD(16|32|64)mri8")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2805
2806def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
2807 let Latency = 9;
2808 let NumMicroOps = 5;
2809 let ResourceCycles = [1,2,1,1];
2810}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2811def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
2812 "LSL(16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2813
2814def SKLWriteResGroup132 : SchedWriteRes<[SKLPort0,SKLPort23]> {
2815 let Latency = 10;
2816 let NumMicroOps = 2;
2817 let ResourceCycles = [1,1];
2818}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]2819def: InstRW<[SKLWriteResGroup132], (instregex "(V?)RCPPSm",
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2820 "(V?)RSQRTPSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2821
2822def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2823 let Latency = 10;
2824 let NumMicroOps = 2;
2825 let ResourceCycles = [1,1];
2826}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2827def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F32m",
2828 "ADD_F64m",
2829 "ILD_F16m",
2830 "ILD_F32m",
2831 "ILD_F64m",
2832 "SUBR_F32m",
2833 "SUBR_F64m",
2834 "SUB_F32m",
2835 "SUB_F64m",
2836 "VPCMPGTQYrm",
2837 "VPERM2F128rm",
2838 "VPERM2I128rm",
2839 "VPERMDYrm",
2840 "VPERMPDYmi",
2841 "VPERMPSYrm",
2842 "VPERMQYmi",
2843 "VPMOVZXBDYrm",
2844 "VPMOVZXBQYrm",
2845 "VPMOVZXBWYrm",
2846 "VPMOVZXDQYrm",
2847 "VPMOVZXWQYrm",
2848 "VPSADBWYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2849
2850def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
2851 let Latency = 10;
2852 let NumMicroOps = 2;
2853 let ResourceCycles = [1,1];
2854}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2855def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm",
2856 "ADDPSrm",
2857 "ADDSUBPDrm",
2858 "ADDSUBPSrm",
2859 "MULPDrm",
2860 "MULPSrm",
2861 "SUBPDrm",
2862 "SUBPSrm",
2863 "VADDPDrm",
2864 "VADDPSrm",
2865 "VADDSUBPDrm",
2866 "VADDSUBPSrm",
2867 "VMULPDrm",
2868 "VMULPSrm",
2869 "VSUBPDrm",
2870 "VSUBPSrm")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2871def: InstRW<[SKLWriteResGroup134],
2872 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2873
2874def SKLWriteResGroup135 : SchedWriteRes<[SKLPort23,SKLPort015]> {
2875 let Latency = 10;
2876 let NumMicroOps = 2;
2877 let ResourceCycles = [1,1];
2878}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2879def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
2880 "CMPPSrmi",
2881 "CVTDQ2PSrm",
2882 "CVTPS2DQrm",
2883 "CVTSS2SDrm",
2884 "CVTTPS2DQrm",
2885 "MAX(C?)PDrm",
2886 "MAX(C?)PSrm",
2887 "MIN(C?)PDrm",
2888 "MIN(C?)PSrm",
2889 "PHMINPOSUWrm",
2890 "PMADDUBSWrm",
2891 "PMADDWDrm",
2892 "PMULDQrm",
2893 "PMULHRSWrm",
2894 "PMULHUWrm",
2895 "PMULHWrm",
2896 "PMULLWrm",
2897 "PMULUDQrm",
2898 "VCMPPDrmi",
2899 "VCMPPSrmi",
2900 "VCVTDQ2PSrm",
2901 "VCVTPH2PSYrm",
2902 "VCVTPS2DQrm",
2903 "VCVTSS2SDrm",
2904 "VCVTTPS2DQrm",
2905 "VMAX(C?)PDrm",
2906 "VMAX(C?)PSrm",
2907 "VMIN(C?)PDrm",
2908 "VMIN(C?)PSrm",
2909 "VPHMINPOSUWrm",
2910 "VPMADDUBSWrm",
2911 "VPMADDWDrm",
2912 "VPMULDQrm",
2913 "VPMULHRSWrm",
2914 "VPMULHUWrm",
2915 "VPMULHWrm",
2916 "VPMULLWrm",
2917 "VPMULUDQrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2918
2919def SKLWriteResGroup136 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2920 let Latency = 10;
2921 let NumMicroOps = 3;
2922 let ResourceCycles = [3];
2923}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2924def: InstRW<[SKLWriteResGroup136], (instregex "(V?)PCMPISTRIrr",
2925 "(V?)PCMPISTRM128rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2926
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2927def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> {
2928 let Latency = 10;
2929 let NumMicroOps = 3;
2930 let ResourceCycles = [2,1];
2931}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2932def: InstRW<[SKLWriteResGroup137], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2933
2934def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
2935 let Latency = 10;
2936 let NumMicroOps = 3;
2937 let ResourceCycles = [1,1,1];
2938}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2939def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm",
2940 "VPTESTYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2941
2942def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
2943 let Latency = 10;
2944 let NumMicroOps = 3;
2945 let ResourceCycles = [1,1,1];
2946}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2947def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2948
2949def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2950 let Latency = 10;
2951 let NumMicroOps = 4;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2952 let ResourceCycles = [2,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2953}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2954def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm",
2955 "VPHSUBSWYrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2956
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2957def SKLWriteResGroup141 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
2958 let Latency = 10;
2959 let NumMicroOps = 4;
2960 let ResourceCycles = [2,1,1];
2961}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2962def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDDYrm",
2963 "VPHADDWYrm",
2964 "VPHSUBDYrm",
2965 "VPHSUBWYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2966
2967def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
2968 let Latency = 10;
2969 let NumMicroOps = 4;
2970 let ResourceCycles = [1,1,1,1];
2971}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2972def: InstRW<[SKLWriteResGroup142], (instrs MULX32rm)>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2973
2974def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
2975 let Latency = 10;
2976 let NumMicroOps = 8;
2977 let ResourceCycles = [1,1,1,1,1,3];
2978}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2979def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2980
2981def SKLWriteResGroup144 : SchedWriteRes<[SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2982 let Latency = 10;
2983 let NumMicroOps = 10;
2984 let ResourceCycles = [9,1];
2985}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2986def: InstRW<[SKLWriteResGroup144], (instregex "MMX_EMMS")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2987
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2988def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2989 let Latency = 11;
2990 let NumMicroOps = 1;
2991 let ResourceCycles = [1];
2992}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]2993def: InstRW<[SKLWriteResGroup145], (instregex "DIVPSrr",
2994 "DIVSSrr",
2995 "VDIVPSYrr",
2996 "VDIVPSrr",
2997 "VDIVSSrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]2998
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]2999def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3000 let Latency = 11;
3001 let NumMicroOps = 2;
3002 let ResourceCycles = [1,1];
3003}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3004def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F32m",
3005 "MUL_F64m",
3006 "VRCPPSYm",
3007 "VRSQRTPSYm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3008
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3009def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
3010 let Latency = 11;
3011 let NumMicroOps = 2;
3012 let ResourceCycles = [1,1];
3013}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3014def: InstRW<[SKLWriteResGroup147], (instregex "VADDPDYrm",
3015 "VADDPSYrm",
3016 "VADDSUBPDYrm",
3017 "VADDSUBPSYrm",
3018 "VMULPDYrm",
3019 "VMULPSYrm",
3020 "VSUBPDYrm",
3021 "VSUBPSYrm")>;
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]3022def: InstRW<[SKLWriteResGroup147],
3023 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3024
3025def SKLWriteResGroup148 : SchedWriteRes<[SKLPort23,SKLPort015]> {
3026 let Latency = 11;
3027 let NumMicroOps = 2;
3028 let ResourceCycles = [1,1];
3029}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3030def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi",
3031 "VCMPPSYrmi",
3032 "VCVTDQ2PSYrm",
3033 "VCVTPS2DQYrm",
3034 "VCVTPS2PDYrm",
3035 "VCVTTPS2DQYrm",
3036 "VMAX(C?)PDYrm",
3037 "VMAX(C?)PSYrm",
3038 "VMIN(C?)PDYrm",
3039 "VMIN(C?)PSYrm",
3040 "VPMADDUBSWYrm",
3041 "VPMADDWDYrm",
3042 "VPMULDQYrm",
3043 "VPMULHRSWYrm",
3044 "VPMULHUWYrm",
3045 "VPMULHWYrm",
3046 "VPMULLWYrm",
3047 "VPMULUDQYrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3048
3049def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
3050 let Latency = 11;
3051 let NumMicroOps = 3;
3052 let ResourceCycles = [2,1];
3053}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3054def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m",
3055 "FICOM32m",
3056 "FICOMP16m",
3057 "FICOMP32m",
3058 "VMPSADBWYrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3059
3060def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3061 let Latency = 11;
3062 let NumMicroOps = 3;
3063 let ResourceCycles = [1,1,1];
3064}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3065def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3066
3067def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {
3068 let Latency = 11;
3069 let NumMicroOps = 3;
3070 let ResourceCycles = [1,1,1];
3071}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3072def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm",
3073 "CVTSD2SIrm",
3074 "CVTSS2SI64rm",
3075 "CVTSS2SIrm",
3076 "CVTTSD2SI64rm",
3077 "CVTTSD2SIrm",
3078 "CVTTSS2SIrm",
3079 "VCVTSD2SI64rm",
3080 "VCVTSD2SIrm",
3081 "VCVTSS2SI64rm",
3082 "VCVTSS2SIrm",
3083 "VCVTTSD2SI64rm",
3084 "VCVTTSD2SIrm",
3085 "VCVTTSS2SI64rm",
3086 "VCVTTSS2SIrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3087
3088def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3089 let Latency = 11;
3090 let NumMicroOps = 3;
3091 let ResourceCycles = [1,1,1];
3092}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3093def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm",
3094 "CVTPD2PSrm",
3095 "CVTTPD2DQrm",
3096 "MMX_CVTPD2PIirm",
3097 "MMX_CVTTPD2PIirm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3098
3099def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3100 let Latency = 11;
3101 let NumMicroOps = 6;
3102 let ResourceCycles = [1,1,1,2,1];
3103}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3104def: InstRW<[SKLWriteResGroup153], (instregex "SHLD(16|32|64)mrCL",
3105 "SHRD(16|32|64)mrCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3106
3107def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3108 let Latency = 11;
3109 let NumMicroOps = 7;
3110 let ResourceCycles = [2,3,2];
3111}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3112def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
3113 "RCR(16|32|64)rCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3114
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3115def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3116 let Latency = 11;
3117 let NumMicroOps = 9;
3118 let ResourceCycles = [1,5,1,2];
3119}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3120def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3121
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3122def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3123 let Latency = 11;
3124 let NumMicroOps = 11;
3125 let ResourceCycles = [2,9];
3126}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3127def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3128
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3129def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3130 let Latency = 12;
3131 let NumMicroOps = 1;
3132 let ResourceCycles = [1];
3133}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3134def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr",
3135 "VSQRTPSr",
3136 "VSQRTSSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3137
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3138def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
3139 let Latency = 12;
3140 let NumMicroOps = 4;
3141 let ResourceCycles = [2,1,1];
3142}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3143def: InstRW<[SKLWriteResGroup159], (instregex "(V?)HADDPDrm",
3144 "(V?)HADDPSrm",
3145 "(V?)HSUBPDrm",
3146 "(V?)HSUBPSrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3147
3148def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
3149 let Latency = 12;
3150 let NumMicroOps = 4;
3151 let ResourceCycles = [1,1,1,1];
3152}
3153def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
3154
3155def SKLWriteResGroup161 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3156 let Latency = 13;
3157 let NumMicroOps = 1;
3158 let ResourceCycles = [1];
3159}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3160def: InstRW<[SKLWriteResGroup161], (instregex "SQRTPSr",
3161 "SQRTSSr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3162
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3163def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3164 let Latency = 13;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3165 let NumMicroOps = 3;
3166 let ResourceCycles = [2,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3167}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3168def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI16m",
3169 "ADD_FI32m",
3170 "SUBR_FI16m",
3171 "SUBR_FI32m",
3172 "SUB_FI16m",
3173 "SUB_FI32m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3174
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3175def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3176 let Latency = 13;
3177 let NumMicroOps = 3;
3178 let ResourceCycles = [1,1,1];
3179}
3180def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
3181
3182def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3183 let Latency = 13;
3184 let NumMicroOps = 4;
3185 let ResourceCycles = [1,3];
3186}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3187def: InstRW<[SKLWriteResGroup164], (instregex "DPPSrri",
3188 "VDPPSYrri",
3189 "VDPPSrri")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3190
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3191def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3192 let Latency = 13;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3193 let NumMicroOps = 4;
3194 let ResourceCycles = [2,1,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3195}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3196def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPDYrm",
3197 "VHADDPSYrm",
3198 "VHSUBPDYrm",
3199 "VHSUBPSYrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3200
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3201def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3202 let Latency = 14;
3203 let NumMicroOps = 1;
3204 let ResourceCycles = [1];
3205}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3206def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr",
3207 "DIVSDrr",
3208 "VDIVPDYrr",
3209 "VDIVPDrr",
3210 "VDIVSDrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3211
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3212def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> {
3213 let Latency = 14;
3214 let NumMicroOps = 3;
3215 let ResourceCycles = [1,2];
3216}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3217def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDPDm")>;
3218def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDPSm")>;
3219def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDSDm")>;
3220def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDSSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3221
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]3222def SKLWriteResGroup168_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {
3223 let Latency = 16;
3224 let NumMicroOps = 3;
3225 let ResourceCycles = [1,2];
3226}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3227def: InstRW<[SKLWriteResGroup168_2], (instregex "(V?)PMULLDrm")>;
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]3228
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3229def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3230 let Latency = 14;
3231 let NumMicroOps = 3;
3232 let ResourceCycles = [1,1,1];
3233}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3234def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI16m",
3235 "MUL_FI32m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3236
3237def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3238 let Latency = 14;
3239 let NumMicroOps = 10;
3240 let ResourceCycles = [2,4,1,3];
3241}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3242def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3243
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3244def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3245 let Latency = 15;
3246 let NumMicroOps = 1;
3247 let ResourceCycles = [1];
3248}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3249def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FPrST0",
3250 "DIVR_FST0r",
3251 "DIVR_FrST0")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3252
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3253def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort015]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3254 let Latency = 15;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3255 let NumMicroOps = 3;
3256 let ResourceCycles = [1,2];
3257}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3258def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm",
3259 "VROUNDYPSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3260
Craig Topperd25f1ac2018-03-20 23:39:48 +0000[diff] [blame]3261def SKLWriteResGroup172_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {
3262 let Latency = 17;
3263 let NumMicroOps = 3;
3264 let ResourceCycles = [1,2];
3265}
3266def: InstRW<[SKLWriteResGroup172_2], (instregex "VPMULLDYrm")>;
3267
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3268def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3269 let Latency = 15;
3270 let NumMicroOps = 4;
3271 let ResourceCycles = [1,1,2];
3272}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3273def: InstRW<[SKLWriteResGroup173], (instregex "(V?)DPPDrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3274
3275def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
3276 let Latency = 15;
3277 let NumMicroOps = 10;
3278 let ResourceCycles = [1,1,1,5,1,1];
3279}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3280def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3281
3282def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3283 let Latency = 16;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3284 let NumMicroOps = 2;
3285 let ResourceCycles = [1,1];
3286}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3287def: InstRW<[SKLWriteResGroup175], (instregex "(V?)DIVSSrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3288
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3289def SKLWriteResGroup176 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3290 let Latency = 16;
3291 let NumMicroOps = 4;
3292 let ResourceCycles = [3,1];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3293}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3294def: InstRW<[SKLWriteResGroup176], (instregex "(V?)PCMPISTRIrm",
3295 "(V?)PCMPISTRM128rm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3296
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3297def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
3298 let Latency = 16;
3299 let NumMicroOps = 14;
3300 let ResourceCycles = [1,1,1,4,2,5];
3301}
3302def: InstRW<[SKLWriteResGroup177], (instregex "CMPXCHG8B")>;
3303
3304def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3305 let Latency = 16;
3306 let NumMicroOps = 16;
3307 let ResourceCycles = [16];
3308}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3309def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3310
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3311def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3312 let Latency = 17;
3313 let NumMicroOps = 2;
3314 let ResourceCycles = [1,1];
3315}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3316def: InstRW<[SKLWriteResGroup179], (instregex "(V?)DIVPSrm",
3317 "VSQRTSSm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3318
3319def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3320 let Latency = 17;
3321 let NumMicroOps = 15;
3322 let ResourceCycles = [2,1,2,4,2,4];
3323}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3324def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3325
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3326def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3327 let Latency = 18;
3328 let NumMicroOps = 1;
3329 let ResourceCycles = [1];
3330}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3331def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDYr",
3332 "VSQRTPDr",
3333 "VSQRTSDr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3334
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3335def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3336 let Latency = 18;
3337 let NumMicroOps = 2;
3338 let ResourceCycles = [1,1];
3339}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3340def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm",
3341 "VDIVPSYrm",
3342 "VSQRTPSm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3343
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3344def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3345 let Latency = 18;
3346 let NumMicroOps = 8;
3347 let ResourceCycles = [4,3,1];
3348}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3349def: InstRW<[SKLWriteResGroup183], (instregex "(V?)PCMPESTRIrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3350
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3351def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3352 let Latency = 18;
3353 let NumMicroOps = 8;
3354 let ResourceCycles = [1,1,1,5];
3355}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3356def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3357
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3358def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3359 let Latency = 18;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3360 let NumMicroOps = 11;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3361 let ResourceCycles = [2,1,1,4,1,2];
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3362}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3363def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3364
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3365def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3366 let Latency = 19;
3367 let NumMicroOps = 2;
3368 let ResourceCycles = [1,1];
3369}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3370def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm",
3371 "SQRTPSm",
3372 "VDIVSDrm",
3373 "VSQRTPSYm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3374
3375def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3376 let Latency = 19;
3377 let NumMicroOps = 5;
3378 let ResourceCycles = [1,1,3];
3379}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3380def: InstRW<[SKLWriteResGroup187], (instregex "(V?)DPPSrmi")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3381
3382def SKLWriteResGroup188 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {
3383 let Latency = 19;
3384 let NumMicroOps = 9;
3385 let ResourceCycles = [4,3,1,1];
3386}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3387def: InstRW<[SKLWriteResGroup188], (instregex "(V?)PCMPESTRM128rr")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3388
3389def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3390 let Latency = 20;
3391 let NumMicroOps = 1;
3392 let ResourceCycles = [1];
3393}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3394def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FPrST0",
3395 "DIV_FST0r",
3396 "DIV_FrST0",
3397 "SQRTPDr",
3398 "SQRTSDr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3399
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3400def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3401 let Latency = 20;
3402 let NumMicroOps = 2;
3403 let ResourceCycles = [1,1];
3404}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3405def: InstRW<[SKLWriteResGroup190], (instregex "(V?)DIVPDrm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3406
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3407def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
3408 let Latency = 20;
3409 let NumMicroOps = 5;
3410 let ResourceCycles = [1,1,3];
3411}
3412def: InstRW<[SKLWriteResGroup191], (instregex "VDPPSYrmi")>;
3413
3414def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3415 let Latency = 20;
3416 let NumMicroOps = 8;
3417 let ResourceCycles = [1,1,1,1,1,1,2];
3418}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3419def: InstRW<[SKLWriteResGroup192], (instregex "INSB",
3420 "INSL",
3421 "INSW")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3422
3423def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3424 let Latency = 20;
3425 let NumMicroOps = 10;
3426 let ResourceCycles = [1,2,7];
3427}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3428def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3429
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3430def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3431 let Latency = 21;
3432 let NumMicroOps = 2;
3433 let ResourceCycles = [1,1];
3434}
3435def: InstRW<[SKLWriteResGroup195], (instregex "VDIVPDYrm")>;
3436
3437def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3438 let Latency = 22;
3439 let NumMicroOps = 2;
3440 let ResourceCycles = [1,1];
3441}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3442def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F32m",
3443 "DIV_F64m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3444
3445def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
3446 let Latency = 22;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3447 let NumMicroOps = 5;
3448 let ResourceCycles = [1,2,1,1];
3449}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3450def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
3451 VGATHERDPDrm,
3452 VGATHERQPDrm,
3453 VGATHERQPSrm,
3454 VPGATHERDDrm,
3455 VPGATHERDQrm,
3456 VPGATHERQDrm,
3457 VPGATHERQQrm)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3458
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3459def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
3460 let Latency = 25;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3461 let NumMicroOps = 5;
3462 let ResourceCycles = [1,2,1,1];
3463}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3464def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
3465 VGATHERQPDYrm,
3466 VGATHERQPSYrm,
3467 VPGATHERDDYrm,
3468 VPGATHERDQYrm,
3469 VPGATHERQDYrm,
3470 VPGATHERQQYrm,
3471 VGATHERDPDYrm)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3472
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3473def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3474 let Latency = 23;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3475 let NumMicroOps = 2;
3476 let ResourceCycles = [1,1];
3477}
3478def: InstRW<[SKLWriteResGroup197], (instregex "VSQRTSDm")>;
3479
3480def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3481 let Latency = 23;
3482 let NumMicroOps = 19;
3483 let ResourceCycles = [2,1,4,1,1,4,6];
3484}
3485def: InstRW<[SKLWriteResGroup198], (instregex "CMPXCHG16B")>;
3486
3487def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3488 let Latency = 24;
3489 let NumMicroOps = 2;
3490 let ResourceCycles = [1,1];
3491}
3492def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;
3493
3494def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
3495 let Latency = 24;
3496 let NumMicroOps = 9;
3497 let ResourceCycles = [4,3,1,1];
3498}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3499def: InstRW<[SKLWriteResGroup200], (instregex "(V?)PCMPESTRIrm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3500
3501def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3502 let Latency = 25;
3503 let NumMicroOps = 2;
3504 let ResourceCycles = [1,1];
3505}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3506def: InstRW<[SKLWriteResGroup201], (instregex "SQRTSDm",
3507 "VSQRTPDYm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3508
3509def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
3510 let Latency = 25;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3511 let NumMicroOps = 3;
3512 let ResourceCycles = [1,1,1];
3513}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3514def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m",
3515 "DIV_FI32m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3516
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3517def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {
3518 let Latency = 25;
3519 let NumMicroOps = 10;
3520 let ResourceCycles = [4,3,1,1,1];
3521}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3522def: InstRW<[SKLWriteResGroup203], (instregex "(V?)PCMPESTRM128rm")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3523
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3524def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3525 let Latency = 26;
3526 let NumMicroOps = 2;
3527 let ResourceCycles = [1,1];
3528}
3529def: InstRW<[SKLWriteResGroup205], (instregex "SQRTPDm")>;
3530
3531def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
3532 let Latency = 27;
3533 let NumMicroOps = 2;
3534 let ResourceCycles = [1,1];
3535}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3536def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F32m",
3537 "DIVR_F64m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3538
3539def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
3540 let Latency = 28;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3541 let NumMicroOps = 8;
3542 let ResourceCycles = [2,4,1,1];
3543}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3544def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3545
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3546def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3547 let Latency = 30;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3548 let NumMicroOps = 3;
3549 let ResourceCycles = [1,1,1];
3550}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3551def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI16m",
3552 "DIVR_FI32m")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3553
3554def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
3555 let Latency = 35;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3556 let NumMicroOps = 23;
3557 let ResourceCycles = [1,5,3,4,10];
3558}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3559def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
3560 "IN(8|16|32)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3561
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3562def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
3563 let Latency = 35;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3564 let NumMicroOps = 23;
3565 let ResourceCycles = [1,5,2,1,4,10];
3566}
Craig Topperfc179c62018-03-22 04:23:41 +0000[diff] [blame]3567def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
3568 "OUT(8|16|32)rr")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3569
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3570def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
3571 let Latency = 37;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3572 let NumMicroOps = 31;
3573 let ResourceCycles = [1,8,1,21];
3574}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3575def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3576
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3577def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
3578 let Latency = 40;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3579 let NumMicroOps = 18;
3580 let ResourceCycles = [1,1,2,3,1,1,1,8];
3581}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3582def: InstRW<[SKLWriteResGroup212], (instregex "VMCLEARm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3583
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3584def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
3585 let Latency = 41;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3586 let NumMicroOps = 39;
3587 let ResourceCycles = [1,10,1,1,26];
3588}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3589def: InstRW<[SKLWriteResGroup213], (instregex "XSAVE64")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3590
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3591def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3592 let Latency = 42;
3593 let NumMicroOps = 22;
3594 let ResourceCycles = [2,20];
3595}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3596def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3597
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3598def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
3599 let Latency = 42;
3600 let NumMicroOps = 40;
3601 let ResourceCycles = [1,11,1,1,26];
3602}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3603def: InstRW<[SKLWriteResGroup215], (instregex "^XSAVE$", "XSAVEC", "XSAVES")>;
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3604
3605def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
3606 let Latency = 46;
3607 let NumMicroOps = 44;
3608 let ResourceCycles = [1,11,1,1,30];
3609}
3610def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
3611
3612def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
3613 let Latency = 62;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3614 let NumMicroOps = 64;
3615 let ResourceCycles = [2,8,5,10,39];
3616}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3617def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3618
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3619def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
3620 let Latency = 63;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3621 let NumMicroOps = 88;
3622 let ResourceCycles = [4,4,31,1,2,1,45];
3623}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3624def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3625
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3626def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
3627 let Latency = 63;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3628 let NumMicroOps = 90;
3629 let ResourceCycles = [4,2,33,1,2,1,47];
3630}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3631def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3632
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3633def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3634 let Latency = 75;
3635 let NumMicroOps = 15;
3636 let ResourceCycles = [6,3,6];
3637}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3638def: InstRW<[SKLWriteResGroup220], (instregex "FNINIT")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3639
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3640def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3641 let Latency = 76;
3642 let NumMicroOps = 32;
3643 let ResourceCycles = [7,2,8,3,1,11];
3644}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3645def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3646
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3647def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3648 let Latency = 102;
3649 let NumMicroOps = 66;
3650 let ResourceCycles = [4,2,4,8,14,34];
3651}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3652def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3653
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3654def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
3655 let Latency = 106;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3656 let NumMicroOps = 100;
3657 let ResourceCycles = [9,1,11,16,1,11,21,30];
3658}
Gadi Haber1e0f1f42017-10-17 06:47:04 +0000[diff] [blame]3659def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;
Gadi Haber6f8fbf42017-09-19 06:19:27 +0000[diff] [blame]3660
3661} // SchedModel