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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000015#ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16#define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
Tom Stellard75aadc22012-12-11 21:25:42 +000017
Tom Stellard75aadc22012-12-11 21:25:42 +000018#include "AMDGPUInstrInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000019#include "R600RegisterInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000020
21namespace llvm {
Matt Arsenault43e92fe2016-06-24 06:30:11 +000022class AMDGPUTargetMachine;
23class DFAPacketizer;
24class MachineFunction;
25class MachineInstr;
26class MachineInstrBuilder;
27class R600Subtarget;
Tom Stellard75aadc22012-12-11 21:25:42 +000028
Matt Arsenault43e92fe2016-06-24 06:30:11 +000029class R600InstrInfo final : public AMDGPUInstrInfo {
30private:
Tom Stellard75aadc22012-12-11 21:25:42 +000031 const R600RegisterInfo RI;
Matt Arsenault43e92fe2016-06-24 06:30:11 +000032 const R600Subtarget &ST;
Tom Stellard75aadc22012-12-11 21:25:42 +000033
Matt Arsenault43e92fe2016-06-24 06:30:11 +000034 std::vector<std::pair<int, unsigned>>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000035 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
Matt Arsenault43e92fe2016-06-24 06:30:11 +000036 unsigned &ConstCount) const;
Tom Stellard880a80a2014-06-17 16:53:14 +000037
38 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
39 MachineBasicBlock::iterator I,
40 unsigned ValueReg, unsigned Address,
41 unsigned OffsetReg,
42 unsigned AddrChan) const;
43
44 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
Matt Arsenault43e92fe2016-06-24 06:30:11 +000045 MachineBasicBlock::iterator I,
46 unsigned ValueReg, unsigned Address,
47 unsigned OffsetReg,
48 unsigned AddrChan) const;
49public:
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000050 enum BankSwizzle {
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000051 ALU_VEC_012_SCL_210 = 0,
52 ALU_VEC_021_SCL_122,
53 ALU_VEC_120_SCL_212,
54 ALU_VEC_102_SCL_221,
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000055 ALU_VEC_201,
56 ALU_VEC_210
57 };
58
Matt Arsenault43e92fe2016-06-24 06:30:11 +000059 explicit R600InstrInfo(const R600Subtarget &);
Tom Stellard75aadc22012-12-11 21:25:42 +000060
Matt Arsenault43e92fe2016-06-24 06:30:11 +000061 const R600RegisterInfo &getRegisterInfo() const {
62 return RI;
63 }
64
Benjamin Kramerbdc49562016-06-12 15:39:02 +000065 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
66 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
Craig Topper5656db42014-04-29 07:57:24 +000067 bool KillSrc) const override;
Tom Stellardcd6b0a62013-11-22 00:41:08 +000068 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
Craig Topper5656db42014-04-29 07:57:24 +000069 MachineBasicBlock::iterator MBBI) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +000070
Tom Stellard75aadc22012-12-11 21:25:42 +000071 bool isReductionOp(unsigned opcode) const;
72 bool isCubeOp(unsigned opcode) const;
73
74 /// \returns true if this \p Opcode represents an ALU instruction.
75 bool isALUInstr(unsigned Opcode) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +000076 bool hasInstrModifiers(unsigned Opcode) const;
77 bool isLDSInstr(unsigned Opcode) const;
Tom Stellard8f9fc202013-11-15 00:12:45 +000078 bool isLDSRetInstr(unsigned Opcode) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000079
Vincent Lejeunea4da6fb2013-10-01 19:32:58 +000080 /// \returns true if this \p Opcode represents an ALU instruction or an
81 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000082 bool canBeConsideredALU(const MachineInstr &MI) const;
Vincent Lejeunea4da6fb2013-10-01 19:32:58 +000083
Vincent Lejeune076c0b22013-04-30 00:14:17 +000084 bool isTransOnly(unsigned Opcode) const;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000085 bool isTransOnly(const MachineInstr &MI) const;
Vincent Lejeune4d5c5e52013-09-04 19:53:30 +000086 bool isVectorOnly(unsigned Opcode) const;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000087 bool isVectorOnly(const MachineInstr &MI) const;
Tom Stellard676c16d2013-08-16 01:11:51 +000088 bool isExport(unsigned Opcode) const;
Vincent Lejeune076c0b22013-04-30 00:14:17 +000089
Vincent Lejeunec2991642013-04-30 00:13:39 +000090 bool usesVertexCache(unsigned Opcode) const;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000091 bool usesVertexCache(const MachineInstr &MI) const;
Vincent Lejeunec2991642013-04-30 00:13:39 +000092 bool usesTextureCache(unsigned Opcode) const;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000093 bool usesTextureCache(const MachineInstr &MI) const;
Vincent Lejeunec2991642013-04-30 00:13:39 +000094
Tom Stellardce540332013-06-28 15:46:59 +000095 bool mustBeLastInClause(unsigned Opcode) const;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000096 bool usesAddressRegister(MachineInstr &MI) const;
97 bool definesAddressRegister(MachineInstr &MI) const;
98 bool readsLDSSrcReg(const MachineInstr &MI) const;
Tom Stellardce540332013-06-28 15:46:59 +000099
Tom Stellard84021442013-07-23 01:48:24 +0000100 /// \returns The operand Index for the Sel operand given an index to one
101 /// of the instruction's src operands.
102 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
103
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000104 /// \returns a pair for each src of an ALU instructions.
105 /// The first member of a pair is the register id.
106 /// If register is ALU_CONST, second member is SEL.
107 /// If register is ALU_LITERAL, second member is IMM.
108 /// Otherwise, second member value is undefined.
109 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000110 getSrcs(MachineInstr &MI) const;
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000111
Vincent Lejeune77a83522013-06-29 19:32:43 +0000112 unsigned isLegalUpTo(
113 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
114 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
115 const std::vector<std::pair<int, unsigned> > &TransSrcs,
116 R600InstrInfo::BankSwizzle TransSwz) const;
117
118 bool FindSwizzleForVectorSlot(
119 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
121 const std::vector<std::pair<int, unsigned> > &TransSrcs,
122 R600InstrInfo::BankSwizzle TransSwz) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +0000123
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000124 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
125 /// returns true and the first (in lexical order) BankSwizzle affectation
126 /// starting from the one already provided in the Instruction Group MIs that
127 /// fits Read Port limitations in BS if available. Otherwise returns false
128 /// and undefined content in BS.
Vincent Lejeune77a83522013-06-29 19:32:43 +0000129 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
130 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
131 /// apply to the last instruction.
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000132 /// PV holds GPR to PV registers in the Instruction Group MIs.
133 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
134 const DenseMap<unsigned, unsigned> &PV,
Vincent Lejeune77a83522013-06-29 19:32:43 +0000135 std::vector<BankSwizzle> &BS,
136 bool isLastAluTrans) const;
137
138 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
139 /// from KCache bank on R700+. This function check if MI set in input meet
140 /// this limitations
141 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
142 /// Same but using const index set instead of MI set.
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000143 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000144
Alp Tokercb402912014-01-24 17:20:08 +0000145 /// \brief Vector instructions are instructions that must fill all
Tom Stellard75aadc22012-12-11 21:25:42 +0000146 /// instruction slots within an instruction group.
147 bool isVector(const MachineInstr &MI) const;
148
Tom Stellard2ff72622016-01-28 16:04:37 +0000149 bool isMov(unsigned Opcode) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000150
Eric Christopher143f02c2014-10-09 01:59:35 +0000151 DFAPacketizer *
152 CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000153
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000154 bool ReverseBranchCondition(
155 SmallVectorImpl<MachineOperand> &Cond) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000156
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000157 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000158 MachineBasicBlock *&FBB,
159 SmallVectorImpl<MachineOperand> &Cond,
160 bool AllowModify) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000161
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000162 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
163 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000164 const DebugLoc &DL) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000165
Craig Topper5656db42014-04-29 07:57:24 +0000166 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000167
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000168 bool isPredicated(const MachineInstr &MI) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000169
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000170 bool isPredicable(MachineInstr &MI) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000171
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000172 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
173 BranchProbability Probability) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000174
175 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
176 unsigned ExtraPredCycles,
Cong Houc536bd92015-09-10 23:10:42 +0000177 BranchProbability Probability) const override ;
Tom Stellard75aadc22012-12-11 21:25:42 +0000178
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000179 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
180 unsigned NumTCycles, unsigned ExtraTCycles,
181 MachineBasicBlock &FMBB,
182 unsigned NumFCycles, unsigned ExtraFCycles,
183 BranchProbability Probability) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000184
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000185 bool DefinesPredicate(MachineInstr &MI,
186 std::vector<MachineOperand> &Pred) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000187
Tom Stellard75aadc22012-12-11 21:25:42 +0000188 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000189 MachineBasicBlock &FMBB) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000190
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000191 bool PredicateInstruction(MachineInstr &MI,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000192 ArrayRef<MachineOperand> Pred) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000193
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000194 unsigned int getPredicationCost(const MachineInstr &) const override;
Arnold Schwaighoferd2f96b92013-09-30 15:28:56 +0000195
Tom Stellard75aadc22012-12-11 21:25:42 +0000196 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000197 const MachineInstr &MI,
Craig Topper5656db42014-04-29 07:57:24 +0000198 unsigned *PredCost = nullptr) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000199
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000200 bool expandPostRAPseudo(MachineInstr &MI) const override;
Tom Stellard880a80a2014-06-17 16:53:14 +0000201
Tom Stellard81d871d2013-11-13 23:36:50 +0000202 /// \brief Reserve the registers that may be accesed using indirect addressing.
203 void reserveIndirectRegisters(BitVector &Reserved,
204 const MachineFunction &MF) const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000205
Tom Stellard1242ce92016-02-05 18:44:57 +0000206 /// Calculate the "Indirect Address" for the given \p RegIndex and
207 /// \p Channel
208 ///
209 /// We model indirect addressing using a virtual address space that can be
210 /// accesed with loads and stores. The "Indirect Address" is the memory
211 /// address in this virtual address space that maps to the given \p RegIndex
212 /// and \p Channel.
213 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
214
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000215
Matt Arsenault52a4d9b2016-07-09 18:11:15 +0000216 /// \returns The register class to be used for loading and storing values
217 /// from an "Indirect Address" .
218 const TargetRegisterClass *getIndirectAddrRegClass() const;
219
220 /// \returns the smallest register index that will be accessed by an indirect
221 /// read or write or -1 if indirect addressing is not used by this program.
222 int getIndirectIndexBegin(const MachineFunction &MF) const;
223
224 /// \returns the largest register index that will be accessed by an indirect
225 /// read or write or -1 if indirect addressing is not used by this program.
226 int getIndirectIndexEnd(const MachineFunction &MF) const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000227
Tom Stellard1242ce92016-02-05 18:44:57 +0000228 /// \brief Build instruction(s) for an indirect register write.
229 ///
230 /// \returns The instruction that performs the indirect register write
Craig Topper5656db42014-04-29 07:57:24 +0000231 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
Tom Stellard1242ce92016-02-05 18:44:57 +0000232 MachineBasicBlock::iterator I,
233 unsigned ValueReg, unsigned Address,
234 unsigned OffsetReg) const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000235
Tom Stellard1242ce92016-02-05 18:44:57 +0000236 /// \brief Build instruction(s) for an indirect register read.
237 ///
238 /// \returns The instruction that performs the indirect register read
Craig Topper5656db42014-04-29 07:57:24 +0000239 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
240 MachineBasicBlock::iterator I,
241 unsigned ValueReg, unsigned Address,
Tom Stellard1242ce92016-02-05 18:44:57 +0000242 unsigned OffsetReg) const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000243
Vincent Lejeune80031d9f2013-04-03 16:49:34 +0000244 unsigned getMaxAlusPerClause() const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000245
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000246 /// buildDefaultInstruction - This function returns a MachineInstr with all
247 /// the instruction modifiers initialized to their default values. You can
248 /// use this function to avoid manually specifying each instruction modifier
249 /// operand when building a new instruction.
Tom Stellard75aadc22012-12-11 21:25:42 +0000250 ///
251 /// \returns a MachineInstr with all the instruction modifiers initialized
252 /// to their default values.
253 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator I,
255 unsigned Opcode,
256 unsigned DstReg,
257 unsigned Src0Reg,
258 unsigned Src1Reg = 0) const;
259
Vincent Lejeune519f21e2013-05-17 16:50:32 +0000260 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
261 MachineInstr *MI,
262 unsigned Slot,
263 unsigned DstReg) const;
264
Tom Stellard75aadc22012-12-11 21:25:42 +0000265 MachineInstr *buildMovImm(MachineBasicBlock &BB,
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000266 MachineBasicBlock::iterator I,
267 unsigned DstReg,
268 uint64_t Imm) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000269
Tom Stellard26a3b672013-10-22 18:19:10 +0000270 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
271 MachineBasicBlock::iterator I,
Tom Stellard2ff72622016-01-28 16:04:37 +0000272 unsigned DstReg, unsigned SrcReg) const;
Tom Stellard26a3b672013-10-22 18:19:10 +0000273
Tom Stellard75aadc22012-12-11 21:25:42 +0000274 /// \brief Get the index of Op in the MachineInstr.
275 ///
276 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000277 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000278
279 /// \brief Get the index of \p Op for the given Opcode.
280 ///
281 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000282 int getOperandIdx(unsigned Opcode, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000283
284 /// \brief Helper function for setting instruction flag values.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000285 void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000286
Tom Stellard75aadc22012-12-11 21:25:42 +0000287 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000288 void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000289
290 ///\brief Determine if the specified \p Flag is set on this \p Operand.
291 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
292
293 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
294 /// \param Flag The flag being set.
295 ///
296 /// \returns the operand containing the flags for this instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000297 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
Tom Stellard75aadc22012-12-11 21:25:42 +0000298 unsigned Flag = 0) const;
299
300 /// \brief Clear the specified flag on the instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000301 void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
Tom Stellard2ff72622016-01-28 16:04:37 +0000302
303 // Helper functions that check the opcode for status information
304 bool isRegisterStore(const MachineInstr &MI) const;
305 bool isRegisterLoad(const MachineInstr &MI) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000306};
307
Tom Stellard13c68ef2013-09-05 18:38:09 +0000308namespace AMDGPU {
309
310int getLDSNoRetOp(uint16_t Opcode);
311
312} //End namespace AMDGPU
313
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000314} // End llvm namespace
Tom Stellard75aadc22012-12-11 21:25:42 +0000315
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000316#endif