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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
Tom Stellard75aadc22012-12-11 21:25:42 +000018#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000021#include <map>
22
23namespace llvm {
24
25 class AMDGPUTargetMachine;
26 class DFAPacketizer;
27 class ScheduleDAG;
28 class MachineFunction;
29 class MachineInstr;
30 class MachineInstrBuilder;
31
32 class R600InstrInfo : public AMDGPUInstrInfo {
33 private:
34 const R600RegisterInfo RI;
35
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000036 std::vector<std::pair<int, unsigned> >
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000037 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000038
Tom Stellard880a80a2014-06-17 16:53:14 +000039
40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator I,
42 unsigned ValueReg, unsigned Address,
43 unsigned OffsetReg,
44 unsigned AddrChan) const;
45
46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
47 MachineBasicBlock::iterator I,
48 unsigned ValueReg, unsigned Address,
49 unsigned OffsetReg,
50 unsigned AddrChan) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000051 public:
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000052 enum BankSwizzle {
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000053 ALU_VEC_012_SCL_210 = 0,
54 ALU_VEC_021_SCL_122,
55 ALU_VEC_120_SCL_212,
56 ALU_VEC_102_SCL_221,
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000057 ALU_VEC_201,
58 ALU_VEC_210
59 };
60
Tom Stellard2e59a452014-06-13 01:32:00 +000061 explicit R600InstrInfo(const AMDGPUSubtarget &st);
Tom Stellard75aadc22012-12-11 21:25:42 +000062
Craig Topper5656db42014-04-29 07:57:24 +000063 const R600RegisterInfo &getRegisterInfo() const override;
64 void copyPhysReg(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI, DebugLoc DL,
66 unsigned DestReg, unsigned SrcReg,
67 bool KillSrc) const override;
Tom Stellardcd6b0a62013-11-22 00:41:08 +000068 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
Craig Topper5656db42014-04-29 07:57:24 +000069 MachineBasicBlock::iterator MBBI) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +000070
71 bool isTrig(const MachineInstr &MI) const;
72 bool isPlaceHolderOpcode(unsigned opcode) const;
73 bool isReductionOp(unsigned opcode) const;
74 bool isCubeOp(unsigned opcode) const;
75
76 /// \returns true if this \p Opcode represents an ALU instruction.
77 bool isALUInstr(unsigned Opcode) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +000078 bool hasInstrModifiers(unsigned Opcode) const;
79 bool isLDSInstr(unsigned Opcode) const;
Tom Stellard8f9fc202013-11-15 00:12:45 +000080 bool isLDSNoRetInstr(unsigned Opcode) const;
81 bool isLDSRetInstr(unsigned Opcode) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000082
Vincent Lejeunea4da6fb2013-10-01 19:32:58 +000083 /// \returns true if this \p Opcode represents an ALU instruction or an
84 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
85 bool canBeConsideredALU(const MachineInstr *MI) const;
86
Vincent Lejeune076c0b22013-04-30 00:14:17 +000087 bool isTransOnly(unsigned Opcode) const;
88 bool isTransOnly(const MachineInstr *MI) const;
Vincent Lejeune4d5c5e52013-09-04 19:53:30 +000089 bool isVectorOnly(unsigned Opcode) const;
90 bool isVectorOnly(const MachineInstr *MI) const;
Tom Stellard676c16d2013-08-16 01:11:51 +000091 bool isExport(unsigned Opcode) const;
Vincent Lejeune076c0b22013-04-30 00:14:17 +000092
Vincent Lejeunec2991642013-04-30 00:13:39 +000093 bool usesVertexCache(unsigned Opcode) const;
94 bool usesVertexCache(const MachineInstr *MI) const;
95 bool usesTextureCache(unsigned Opcode) const;
96 bool usesTextureCache(const MachineInstr *MI) const;
97
Tom Stellardce540332013-06-28 15:46:59 +000098 bool mustBeLastInClause(unsigned Opcode) const;
Tom Stellard26a3b672013-10-22 18:19:10 +000099 bool usesAddressRegister(MachineInstr *MI) const;
100 bool definesAddressRegister(MachineInstr *MI) const;
Tom Stellard7f6fa4c2013-09-12 02:55:06 +0000101 bool readsLDSSrcReg(const MachineInstr *MI) const;
Tom Stellardce540332013-06-28 15:46:59 +0000102
Tom Stellard84021442013-07-23 01:48:24 +0000103 /// \returns The operand index for the given source number. Legal values
104 /// for SrcNum are 0, 1, and 2.
105 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
106 /// \returns The operand Index for the Sel operand given an index to one
107 /// of the instruction's src operands.
108 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
109
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000110 /// \returns a pair for each src of an ALU instructions.
111 /// The first member of a pair is the register id.
112 /// If register is ALU_CONST, second member is SEL.
113 /// If register is ALU_LITERAL, second member is IMM.
114 /// Otherwise, second member value is undefined.
115 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
116 getSrcs(MachineInstr *MI) const;
117
Vincent Lejeune77a83522013-06-29 19:32:43 +0000118 unsigned isLegalUpTo(
119 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
121 const std::vector<std::pair<int, unsigned> > &TransSrcs,
122 R600InstrInfo::BankSwizzle TransSwz) const;
123
124 bool FindSwizzleForVectorSlot(
125 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
127 const std::vector<std::pair<int, unsigned> > &TransSrcs,
128 R600InstrInfo::BankSwizzle TransSwz) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +0000129
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000130 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
131 /// returns true and the first (in lexical order) BankSwizzle affectation
132 /// starting from the one already provided in the Instruction Group MIs that
133 /// fits Read Port limitations in BS if available. Otherwise returns false
134 /// and undefined content in BS.
Vincent Lejeune77a83522013-06-29 19:32:43 +0000135 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
136 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
137 /// apply to the last instruction.
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000138 /// PV holds GPR to PV registers in the Instruction Group MIs.
139 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
140 const DenseMap<unsigned, unsigned> &PV,
Vincent Lejeune77a83522013-06-29 19:32:43 +0000141 std::vector<BankSwizzle> &BS,
142 bool isLastAluTrans) const;
143
144 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
145 /// from KCache bank on R700+. This function check if MI set in input meet
146 /// this limitations
147 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
148 /// Same but using const index set instead of MI set.
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000149 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000150
Alp Tokercb402912014-01-24 17:20:08 +0000151 /// \brief Vector instructions are instructions that must fill all
Tom Stellard75aadc22012-12-11 21:25:42 +0000152 /// instruction slots within an instruction group.
153 bool isVector(const MachineInstr &MI) const;
154
Craig Topper5656db42014-04-29 07:57:24 +0000155 unsigned getIEQOpcode() const override;
156 bool isMov(unsigned Opcode) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000157
158 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
Craig Topper5656db42014-04-29 07:57:24 +0000159 const ScheduleDAG *DAG) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000160
Craig Topper5656db42014-04-29 07:57:24 +0000161 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000162
163 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
Craig Topper5656db42014-04-29 07:57:24 +0000164 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000165
Craig Topper5656db42014-04-29 07:57:24 +0000166 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000167
Craig Topper5656db42014-04-29 07:57:24 +0000168 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000169
Craig Topper5656db42014-04-29 07:57:24 +0000170 bool isPredicated(const MachineInstr *MI) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000171
Craig Topper5656db42014-04-29 07:57:24 +0000172 bool isPredicable(MachineInstr *MI) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000173
174 bool
175 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
Craig Topper5656db42014-04-29 07:57:24 +0000176 const BranchProbability &Probability) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000177
178 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
179 unsigned ExtraPredCycles,
Craig Topper5656db42014-04-29 07:57:24 +0000180 const BranchProbability &Probability) const override ;
Tom Stellard75aadc22012-12-11 21:25:42 +0000181
182 bool
183 isProfitableToIfCvt(MachineBasicBlock &TMBB,
184 unsigned NumTCycles, unsigned ExtraTCycles,
185 MachineBasicBlock &FMBB,
186 unsigned NumFCycles, unsigned ExtraFCycles,
Craig Topper5656db42014-04-29 07:57:24 +0000187 const BranchProbability &Probability) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000188
189 bool DefinesPredicate(MachineInstr *MI,
Craig Topper5656db42014-04-29 07:57:24 +0000190 std::vector<MachineOperand> &Pred) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000191
192 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
Craig Topper5656db42014-04-29 07:57:24 +0000193 const SmallVectorImpl<MachineOperand> &Pred2) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000194
195 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
Craig Topper5656db42014-04-29 07:57:24 +0000196 MachineBasicBlock &FMBB) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000197
198 bool PredicateInstruction(MachineInstr *MI,
Craig Topper5656db42014-04-29 07:57:24 +0000199 const SmallVectorImpl<MachineOperand> &Pred) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000200
Craig Topper5656db42014-04-29 07:57:24 +0000201 unsigned int getPredicationCost(const MachineInstr *) const override;
Arnold Schwaighoferd2f96b92013-09-30 15:28:56 +0000202
Tom Stellard75aadc22012-12-11 21:25:42 +0000203 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
204 const MachineInstr *MI,
Craig Topper5656db42014-04-29 07:57:24 +0000205 unsigned *PredCost = nullptr) const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000206
Craig Topper5656db42014-04-29 07:57:24 +0000207 int getInstrLatency(const InstrItineraryData *ItinData,
208 SDNode *Node) const override { return 1;}
Tom Stellard75aadc22012-12-11 21:25:42 +0000209
Tom Stellard880a80a2014-06-17 16:53:14 +0000210 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
211
Tom Stellard81d871d2013-11-13 23:36:50 +0000212 /// \brief Reserve the registers that may be accesed using indirect addressing.
213 void reserveIndirectRegisters(BitVector &Reserved,
214 const MachineFunction &MF) const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000215
Craig Topper5656db42014-04-29 07:57:24 +0000216 unsigned calculateIndirectAddress(unsigned RegIndex,
217 unsigned Channel) const override;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000218
Craig Topper5656db42014-04-29 07:57:24 +0000219 const TargetRegisterClass *getIndirectAddrRegClass() const override;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000220
Craig Topper5656db42014-04-29 07:57:24 +0000221 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
222 MachineBasicBlock::iterator I,
223 unsigned ValueReg, unsigned Address,
224 unsigned OffsetReg) const override;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000225
Craig Topper5656db42014-04-29 07:57:24 +0000226 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
227 MachineBasicBlock::iterator I,
228 unsigned ValueReg, unsigned Address,
229 unsigned OffsetReg) const override;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000230
Vincent Lejeune80031d9f2013-04-03 16:49:34 +0000231 unsigned getMaxAlusPerClause() const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000232
233 ///buildDefaultInstruction - This function returns a MachineInstr with
234 /// all the instruction modifiers initialized to their default values.
Tom Stellard75aadc22012-12-11 21:25:42 +0000235 /// You can use this function to avoid manually specifying each instruction
236 /// modifier operand when building a new instruction.
237 ///
238 /// \returns a MachineInstr with all the instruction modifiers initialized
239 /// to their default values.
240 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
241 MachineBasicBlock::iterator I,
242 unsigned Opcode,
243 unsigned DstReg,
244 unsigned Src0Reg,
245 unsigned Src1Reg = 0) const;
246
Vincent Lejeune519f21e2013-05-17 16:50:32 +0000247 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
248 MachineInstr *MI,
249 unsigned Slot,
250 unsigned DstReg) const;
251
Tom Stellard75aadc22012-12-11 21:25:42 +0000252 MachineInstr *buildMovImm(MachineBasicBlock &BB,
253 MachineBasicBlock::iterator I,
254 unsigned DstReg,
255 uint64_t Imm) const;
256
Tom Stellard26a3b672013-10-22 18:19:10 +0000257 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
258 MachineBasicBlock::iterator I,
Craig Topper5656db42014-04-29 07:57:24 +0000259 unsigned DstReg, unsigned SrcReg) const override;
Tom Stellard26a3b672013-10-22 18:19:10 +0000260
Tom Stellard75aadc22012-12-11 21:25:42 +0000261 /// \brief Get the index of Op in the MachineInstr.
262 ///
263 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000264 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000265
266 /// \brief Get the index of \p Op for the given Opcode.
267 ///
268 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000269 int getOperandIdx(unsigned Opcode, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000270
271 /// \brief Helper function for setting instruction flag values.
Tom Stellard02661d92013-06-25 21:22:18 +0000272 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000273
274 /// \returns true if this instruction has an operand for storing target flags.
275 bool hasFlagOperand(const MachineInstr &MI) const;
276
277 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
278 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
279
280 ///\brief Determine if the specified \p Flag is set on this \p Operand.
281 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
282
283 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
284 /// \param Flag The flag being set.
285 ///
286 /// \returns the operand containing the flags for this instruction.
287 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
288 unsigned Flag = 0) const;
289
290 /// \brief Clear the specified flag on the instruction.
291 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
292};
293
Tom Stellard13c68ef2013-09-05 18:38:09 +0000294namespace AMDGPU {
295
296int getLDSNoRetOp(uint16_t Opcode);
297
298} //End namespace AMDGPU
299
Tom Stellard75aadc22012-12-11 21:25:42 +0000300} // End llvm namespace
301
302#endif // R600INSTRINFO_H_