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gerrit-public.fairphone.software / toolchain / llvm-project / 5714860ee4a62726e086acedd7cc236b41bdce52 / . / llvm / lib / Target / AMDGPU / DSInstructions.td
blob: 65dcd27ae7a026386fa89de82b2fc932b0a24cfb [file] [log] [blame]
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
13
14 let SubtargetPredicate = isGCN;
15
16 let LGKM_CNT = 1;
17 let DS = 1;
Matt Arsenault10c17ca2016-10-06 10:13:23 +0000[diff] [blame]18 let Size = 8;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
21
22 // Most instruction load and store data, so set this as the default.
23 let mayLoad = 1;
24 let mayStore = 1;
25
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
28
29 let isPseudo = 1;
30 let isCodeGenOnly = 1;
31
32 let AsmMatchConverter = "cvtDS";
33
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
36
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
39 bits<1> has_vdst = 1;
40 bits<1> has_addr = 1;
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
43
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
47
48 bits<1> has_gds = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50}
51
52class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
54 Enc64 {
55
56 let isPseudo = 0;
57 let isCodeGenOnly = 0;
58
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
62
63 // encoding fields
64 bits<8> vdst;
65 bits<1> gds;
66 bits<8> addr;
67 bits<8> data0;
68 bits<8> data1;
69 bits<8> offset0;
70 bits<8> offset1;
71
72 bits<16> offset;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
75}
76
77
78// DS Pseudo instructions
79
80class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
81: DS_Pseudo<opName,
82 (outs),
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
86
87 let has_data1 = 0;
88 let has_vdst = 0;
89}
90
91class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName,
92 (outs),
93 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
94 "$addr $offset0$offset1$gds"> {
95
96 let has_data0 = 0;
97 let has_data1 = 0;
98 let has_vdst = 0;
99 let has_offset = 0;
100 let AsmMatchConverter = "cvtDSOffset01";
101}
102
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]103class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]104: DS_Pseudo<opName,
105 (outs),
106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107 "$addr, $data0, $data1"#"$offset"#"$gds">,
108 AtomicNoRet<opName, 0> {
109
110 let has_vdst = 0;
111}
112
113class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
114: DS_Pseudo<opName,
115 (outs),
116 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
117 offset0:$offset0, offset1:$offset1, gds:$gds),
118 "$addr, $data0, $data1$offset0$offset1$gds"> {
119
120 let has_vdst = 0;
121 let has_offset = 0;
122 let AsmMatchConverter = "cvtDSOffset01";
123}
124
125class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
126: DS_Pseudo<opName,
127 (outs rc:$vdst),
128 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0$offset$gds"> {
130
131 let hasPostISelHook = 1;
132 let has_data1 = 0;
133}
134
135class DS_1A2D_RET<string opName,
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]136 RegisterClass rc = VGPR_32,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]137 RegisterClass src = rc>
138: DS_Pseudo<opName,
139 (outs rc:$vdst),
140 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
141 "$vdst, $addr, $data0, $data1$offset$gds"> {
142
143 let hasPostISelHook = 1;
144}
145
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]146class DS_1A2D_Off8_RET<string opName,
147 RegisterClass rc = VGPR_32,
148 RegisterClass src = rc>
149: DS_Pseudo<opName,
150 (outs rc:$vdst),
151 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
152 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
153
154 let has_offset = 0;
155 let AsmMatchConverter = "cvtDSOffset01";
156
157 let hasPostISelHook = 1;
158}
159
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]160class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
161: DS_Pseudo<opName,
162 (outs rc:$vdst),
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]163 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]164 "$vdst, $addr$offset$gds"> {
165
166 let has_data0 = 0;
167 let has_data1 = 0;
168}
169
170class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
171: DS_Pseudo<opName,
172 (outs rc:$vdst),
173 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
174 "$vdst, $addr$offset0$offset1$gds"> {
175
176 let has_offset = 0;
177 let has_data0 = 0;
178 let has_data1 = 0;
179 let AsmMatchConverter = "cvtDSOffset01";
180}
181
182class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
183 (outs VGPR_32:$vdst),
184 (ins VGPR_32:$addr, offset:$offset),
185 "$vdst, $addr$offset gds"> {
186
187 let has_data0 = 0;
188 let has_data1 = 0;
189 let has_gds = 0;
190 let gdsValue = 1;
Artem Tamazov43b61562017-02-03 12:47:30 +0000[diff] [blame]191 let AsmMatchConverter = "cvtDSGds";
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]192}
193
194class DS_0A_RET <string opName> : DS_Pseudo<opName,
195 (outs VGPR_32:$vdst),
196 (ins offset:$offset, gds:$gds),
197 "$vdst$offset$gds"> {
198
199 let mayLoad = 1;
200 let mayStore = 1;
201
202 let has_addr = 0;
203 let has_data0 = 0;
204 let has_data1 = 0;
205}
206
207class DS_1A <string opName> : DS_Pseudo<opName,
208 (outs),
209 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
210 "$addr$offset$gds"> {
211
212 let mayLoad = 1;
213 let mayStore = 1;
214
215 let has_vdst = 0;
216 let has_data0 = 0;
217 let has_data1 = 0;
218}
219
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]220class DS_GWS <string opName, dag ins, string asmOps>
221: DS_Pseudo<opName, (outs), ins, asmOps> {
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]222
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]223 let has_vdst = 0;
224 let has_addr = 0;
225 let has_data0 = 0;
226 let has_data1 = 0;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]227
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]228 let has_gds = 0;
229 let gdsValue = 1;
230 let AsmMatchConverter = "cvtDSGds";
231}
232
233class DS_GWS_0D <string opName>
234: DS_GWS<opName,
235 (ins offset:$offset, gds:$gds), "$offset gds">;
236
237class DS_GWS_1D <string opName>
238: DS_GWS<opName,
239 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
240
241 let has_data0 = 1;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]242}
243
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]244class DS_VOID <string opName> : DS_Pseudo<opName,
245 (outs), (ins), ""> {
246 let mayLoad = 0;
247 let mayStore = 0;
248 let hasSideEffects = 1;
249 let UseNamedOperandTable = 0;
250 let AsmMatchConverter = "";
251
252 let has_vdst = 0;
253 let has_addr = 0;
254 let has_data0 = 0;
255 let has_data1 = 0;
256 let has_offset = 0;
257 let has_offset0 = 0;
258 let has_offset1 = 0;
259 let has_gds = 0;
260}
261
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]262class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
263: DS_Pseudo<opName,
264 (outs VGPR_32:$vdst),
265 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
266 "$vdst, $addr, $data0$offset",
267 [(set i32:$vdst,
268 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
269
Kannan Narayananacb089e2017-04-12 03:25:12 +0000[diff] [blame]270 let LGKM_CNT = 0;
271
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]272 let mayLoad = 0;
273 let mayStore = 0;
274 let isConvergent = 1;
275
276 let has_data1 = 0;
277 let has_gds = 0;
278}
279
280def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
281def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
282def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
283def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
284def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
285def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
286def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
287def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
288def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
289def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
290def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
291def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]292def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]293def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
294def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]295
296let mayLoad = 0 in {
297def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
298def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
299def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
300def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
301def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
302}
303
304def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
305def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
306def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]307
308def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
309def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
310def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
311def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
312def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
313def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
314def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
315def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
316def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
317def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
318def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
319def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
320def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
321let mayLoad = 0 in {
322def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
323def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
324def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
325}
326def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
327def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
328def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
329def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
330
331def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
332 AtomicNoRet<"ds_add_u32", 1>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]333def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
334 AtomicNoRet<"ds_add_f32", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]335def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
336 AtomicNoRet<"ds_sub_u32", 1>;
337def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
338 AtomicNoRet<"ds_rsub_u32", 1>;
339def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
340 AtomicNoRet<"ds_inc_u32", 1>;
341def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
342 AtomicNoRet<"ds_dec_u32", 1>;
343def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
344 AtomicNoRet<"ds_min_i32", 1>;
345def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
346 AtomicNoRet<"ds_max_i32", 1>;
347def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
348 AtomicNoRet<"ds_min_u32", 1>;
349def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
350 AtomicNoRet<"ds_max_u32", 1>;
351def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
352 AtomicNoRet<"ds_and_b32", 1>;
353def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
354 AtomicNoRet<"ds_or_b32", 1>;
355def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
356 AtomicNoRet<"ds_xor_b32", 1>;
357def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
358 AtomicNoRet<"ds_mskor_b32", 1>;
359def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
360 AtomicNoRet<"ds_cmpst_b32", 1>;
361def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
362 AtomicNoRet<"ds_cmpst_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]363def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]364 AtomicNoRet<"ds_min_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]365def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]366 AtomicNoRet<"ds_max_f32", 1>;
367
368def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
369 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]370def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]371 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]372def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]373 AtomicNoRet<"", 1>;
374
375def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
376 AtomicNoRet<"ds_add_u64", 1>;
377def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
378 AtomicNoRet<"ds_sub_u64", 1>;
379def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
380 AtomicNoRet<"ds_rsub_u64", 1>;
381def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
382 AtomicNoRet<"ds_inc_u64", 1>;
383def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
384 AtomicNoRet<"ds_dec_u64", 1>;
385def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
386 AtomicNoRet<"ds_min_i64", 1>;
387def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
388 AtomicNoRet<"ds_max_i64", 1>;
389def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
390 AtomicNoRet<"ds_min_u64", 1>;
391def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
392 AtomicNoRet<"ds_max_u64", 1>;
393def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
394 AtomicNoRet<"ds_and_b64", 1>;
395def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
396 AtomicNoRet<"ds_or_b64", 1>;
397def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
398 AtomicNoRet<"ds_xor_b64", 1>;
399def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
400 AtomicNoRet<"ds_mskor_b64", 1>;
401def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
402 AtomicNoRet<"ds_cmpst_b64", 1>;
403def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
404 AtomicNoRet<"ds_cmpst_f64", 1>;
405def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
406 AtomicNoRet<"ds_min_f64", 1>;
407def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
408 AtomicNoRet<"ds_max_f64", 1>;
409
410def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]411 AtomicNoRet<"", 1>;
412def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
413 AtomicNoRet<"", 1>;
414def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
415 AtomicNoRet<"", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]416
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]417def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
418def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
419def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
420def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
421def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]422
423def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
424def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
425def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
426def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
427def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
428def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
429def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
430def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
431def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]432def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]433def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
434def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
435def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
436def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
437
438def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
439def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
440def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
441def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
442def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
443def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
444def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
445def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
446def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
447def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
448def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
449def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
450def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
451def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
452
453def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">;
454def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">;
455
456let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
457def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
458}
459
460let mayStore = 0 in {
461def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
462def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
463def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
464def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
465def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
466def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
467
468def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
469def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
470
471def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
472def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
473}
474
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]475def DS_CONSUME : DS_0A_RET<"ds_consume">;
476def DS_APPEND : DS_0A_RET<"ds_append">;
477def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]478
479//===----------------------------------------------------------------------===//
480// Instruction definitions for CI and newer.
481//===----------------------------------------------------------------------===//
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]482
483let SubtargetPredicate = isCIVI in {
484
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]485def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
486
487def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
488 AtomicNoRet<"", 1>;
489
490def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]491
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]492let mayStore = 0 in {
493def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
494def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
495} // End mayStore = 0
496
497let mayLoad = 0 in {
498def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
499def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
500} // End mayLoad = 0
501
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]502def DS_NOP : DS_VOID<"ds_nop">;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]503
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]504} // let SubtargetPredicate = isCIVI
505
506//===----------------------------------------------------------------------===//
507// Instruction definitions for VI and newer.
508//===----------------------------------------------------------------------===//
509
510let SubtargetPredicate = isVI in {
511
512let Uses = [EXEC] in {
513def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
514 int_amdgcn_ds_permute>;
515def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
516 int_amdgcn_ds_bpermute>;
517}
518
519} // let SubtargetPredicate = isVI
520
521//===----------------------------------------------------------------------===//
522// DS Patterns
523//===----------------------------------------------------------------------===//
524
525let Predicates = [isGCN] in {
526
527def : Pat <
528 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
529 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
530>;
531
532class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
533 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
534 (inst $ptr, (as_i16imm $offset), (i1 0))
535>;
536
537def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
538def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]539def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
540def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
541def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]542def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
543def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]544def : DSReadPat <DS_READ_U16, i16, si_load_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]545def : DSReadPat <DS_READ_B32, i32, si_load_local>;
546
547let AddedComplexity = 100 in {
548
549def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
550
551} // End AddedComplexity = 100
552
553def : Pat <
554 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
555 i8:$offset1))),
556 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
557>;
558
559class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
560 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
561 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
562>;
563
564def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
565def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]566def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
567def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]568def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
569
570let AddedComplexity = 100 in {
571
572def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
573} // End AddedComplexity = 100
574
575def : Pat <
576 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
577 i8:$offset1)),
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]578 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
579 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]580 (i1 0))
581>;
582
583class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
584 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
585 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
586>;
587
588class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
589 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
590 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
591>;
592
593
594// 32-bit atomics.
595def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
596def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
597def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
598def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
599def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
600def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
601def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
602def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
603def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
604def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
605def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
606def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
607def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
608
609// 64-bit atomics.
610def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
611def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
612def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
613def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
614def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
615def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
616def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
617def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
618def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
619def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
620def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
621def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
622
623def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
624
625} // let Predicates = [isGCN]
626
627//===----------------------------------------------------------------------===//
628// Real instructions
629//===----------------------------------------------------------------------===//
630
631//===----------------------------------------------------------------------===//
632// SIInstructions.td
633//===----------------------------------------------------------------------===//
634
635class DS_Real_si <bits<8> op, DS_Pseudo ds> :
636 DS_Real <ds>,
637 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
638 let AssemblerPredicates=[isSICI];
639 let DecoderNamespace="SICI";
640
641 // encoding
642 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
643 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
644 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
645 let Inst{25-18} = op;
646 let Inst{31-26} = 0x36; // ds prefix
647 let Inst{39-32} = !if(ds.has_addr, addr, 0);
648 let Inst{47-40} = !if(ds.has_data0, data0, 0);
649 let Inst{55-48} = !if(ds.has_data1, data1, 0);
650 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
651}
652
653def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
654def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
655def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
656def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
657def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
658def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
659def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
660def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
661def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
662def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
663def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
664def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
665def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
666def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
667def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
668def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
669def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
670def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
671def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
672def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]673def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]674def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
675def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
676def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
677def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
678def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
679def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
680def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
681def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
682def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
683def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
684def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
685def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
686def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
687def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
688def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
689def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
690def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
691def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
692def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
693def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
694def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
695def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
696def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
697def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
698def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
699def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
700def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
701
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]702// These instruction are CI/VI only
703def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
704def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
705def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]706
707def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
708def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
709def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
710def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
711def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
712def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
713def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
714def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
715def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
716def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
717def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
718def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
719def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
720def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
721def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
722def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
723def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
724def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
725def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
726def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
727def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
728def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
729def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
730def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
731def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
732def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
733def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
734def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
735def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
736def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
737def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
738
739def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
740def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
741def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
742def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
743def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
744def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
745def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
746def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
747def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
748def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
749def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
750def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
751def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
752def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
753def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
754def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
755def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
756def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
757def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
758def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
759
760def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
761def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
762def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
763
764def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
765def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
766def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
767def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
768def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
769def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
770def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
771def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
772def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
773def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
774def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
775def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
776def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
777
778def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
779def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
780
781def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
782def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
783def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
784def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
785def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
786def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
787def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
788def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
789def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
790def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
791def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
792def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
793def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
794
795def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
796def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]797def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
798def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
799def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
800def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]801
802//===----------------------------------------------------------------------===//
803// VIInstructions.td
804//===----------------------------------------------------------------------===//
805
806class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
807 DS_Real <ds>,
808 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
809 let AssemblerPredicates = [isVI];
810 let DecoderNamespace="VI";
811
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]812 // encoding
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]813 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
814 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
815 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
816 let Inst{24-17} = op;
817 let Inst{31-26} = 0x36; // ds prefix
818 let Inst{39-32} = !if(ds.has_addr, addr, 0);
819 let Inst{47-40} = !if(ds.has_data0, data0, 0);
820 let Inst{55-48} = !if(ds.has_data1, data1, 0);
821 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
822}
823
824def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
825def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
826def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
827def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
828def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
829def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
830def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
831def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
832def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
833def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
834def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
835def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
836def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
837def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
838def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
839def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
840def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
841def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
842def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
843def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]844def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]845def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]846def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
847def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
848def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
849def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
850def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]851def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
852def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
853def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
854def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
855def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
856def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
857def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
858def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
859def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
860def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
861def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
862def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
863def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
864def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
865def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
866def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
867def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
868def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
869def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
870def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
871def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
872def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]873def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]874def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]875def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
876def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
877def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
878def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
879def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
880def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
881def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]882def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
883def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
884def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]885def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
886def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
887def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
888
889def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
890def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
891def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
892def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
893def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
894def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
895def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
896def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
897def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
898def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
899def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
900def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
901def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
902def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
903def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
904def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
905def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
906def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
907def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
908def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
909
910def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
911def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
912def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
913def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
914def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
915def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
916def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
917def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
918def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
919def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
920def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
921def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
922def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
923def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
924def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
925def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]926def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
927def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]928def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
929def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
930def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
931def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
932
933def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
934def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
935def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
936
937def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
938def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
939def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
940def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
941def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
942def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
943def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
944def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
945def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
946def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
947def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
948def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
949def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
950def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
951def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
952def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
953def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
954def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
955def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
956def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
957def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
958def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
959def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
960def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
961def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
962def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
963def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
964def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
965def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
966def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]967def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
968def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
969def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
970def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;