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Dan Gohman10e730a2015-06-29 23:51:55 +00001//=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief This file implements the WebAssemblyTargetLowering class.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblyISelLowering.h"
16#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17#include "WebAssemblyMachineFunctionInfo.h"
18#include "WebAssemblySubtarget.h"
19#include "WebAssemblyTargetMachine.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000020#include "llvm/CodeGen/Analysis.h"
JF Bastienaf111db2015-08-24 22:16:48 +000021#include "llvm/CodeGen/CallingConvLower.h"
Dan Gohmancdd48b82017-11-28 01:13:40 +000022#include "llvm/CodeGen/MachineInstrBuilder.h"
Dan Gohman950a13c2015-09-16 16:51:30 +000023#include "llvm/CodeGen/MachineJumpTableInfo.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/SelectionDAG.h"
Oliver Stannard02fa1c82016-01-28 13:19:47 +000026#include "llvm/IR/DiagnosticInfo.h"
JF Bastienb9073fb2015-07-22 21:28:15 +000027#include "llvm/IR/DiagnosticPrinter.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000028#include "llvm/IR/Function.h"
29#include "llvm/IR/Intrinsics.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000030#include "llvm/Support/Debug.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/Target/TargetOptions.h"
34using namespace llvm;
35
36#define DEBUG_TYPE "wasm-lower"
37
38WebAssemblyTargetLowering::WebAssemblyTargetLowering(
39 const TargetMachine &TM, const WebAssemblySubtarget &STI)
Dan Gohmanbfaf7e12015-07-02 21:36:25 +000040 : TargetLowering(TM), Subtarget(&STI) {
JF Bastienaf111db2015-08-24 22:16:48 +000041 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
42
JF Bastien71d29ac2015-08-12 17:53:29 +000043 // Booleans always contain 0 or 1.
44 setBooleanContents(ZeroOrOneBooleanContent);
Dan Gohmanbfaf7e12015-07-02 21:36:25 +000045 // WebAssembly does not produce floating-point exceptions on normal floating
46 // point operations.
47 setHasFloatingPointExceptions(false);
Dan Gohman489abd72015-07-07 22:38:06 +000048 // We don't know the microarchitecture here, so just reduce register pressure.
49 setSchedulingPreference(Sched::RegPressure);
JF Bastienb9073fb2015-07-22 21:28:15 +000050 // Tell ISel that we have a stack pointer.
51 setStackPointerRegisterToSaveRestore(
52 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
53 // Set up the register classes.
Dan Gohmand0bf9812015-09-26 01:09:44 +000054 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
55 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
56 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
57 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
Derek Schuff39bf39f2016-08-02 23:16:09 +000058 if (Subtarget->hasSIMD128()) {
59 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
60 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
61 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
62 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
63 }
JF Bastienb9073fb2015-07-22 21:28:15 +000064 // Compute derived properties from the register classes.
65 computeRegisterProperties(Subtarget->getRegisterInfo());
66
JF Bastienaf111db2015-08-24 22:16:48 +000067 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
Dan Gohman2c8fe6a2015-11-25 16:44:29 +000068 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
Dan Gohman950a13c2015-09-16 16:51:30 +000069 setOperationAction(ISD::JumpTable, MVTPtr, Custom);
Derek Schuff51699a82016-02-12 22:56:03 +000070 setOperationAction(ISD::BlockAddress, MVTPtr, Custom);
71 setOperationAction(ISD::BRIND, MVT::Other, Custom);
JF Bastienaf111db2015-08-24 22:16:48 +000072
Dan Gohman35bfb242015-12-04 23:22:35 +000073 // Take the default expansion for va_arg, va_copy, and va_end. There is no
74 // default action for va_start, so we do that custom.
75 setOperationAction(ISD::VASTART, MVT::Other, Custom);
76 setOperationAction(ISD::VAARG, MVT::Other, Expand);
77 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
78 setOperationAction(ISD::VAEND, MVT::Other, Expand);
79
JF Bastienda06bce2015-08-11 21:02:46 +000080 for (auto T : {MVT::f32, MVT::f64}) {
81 // Don't expand the floating-point types to constant pools.
82 setOperationAction(ISD::ConstantFP, T, Legal);
83 // Expand floating-point comparisons.
84 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
85 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
86 setCondCodeAction(CC, T, Expand);
Dan Gohman32907a62015-08-20 22:57:13 +000087 // Expand floating-point library function operators.
Craig Topperf6d4dc52017-05-30 15:27:55 +000088 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM,
89 ISD::FMA})
Dan Gohman32907a62015-08-20 22:57:13 +000090 setOperationAction(Op, T, Expand);
Dan Gohman896e53f2015-08-24 18:23:13 +000091 // Note supported floating-point library function operators that otherwise
92 // default to expand.
Dan Gohman7a6b9822015-11-29 22:32:02 +000093 for (auto Op :
94 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
Dan Gohman896e53f2015-08-24 18:23:13 +000095 setOperationAction(Op, T, Legal);
Dan Gohmanb84ae9b2015-11-10 21:40:21 +000096 // Support minnan and maxnan, which otherwise default to expand.
97 setOperationAction(ISD::FMINNAN, T, Legal);
98 setOperationAction(ISD::FMAXNAN, T, Legal);
Dan Gohmana63e8eb2017-02-22 16:28:00 +000099 // WebAssembly currently has no builtin f16 support.
100 setOperationAction(ISD::FP16_TO_FP, T, Expand);
101 setOperationAction(ISD::FP_TO_FP16, T, Expand);
102 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand);
103 setTruncStoreAction(T, MVT::f16, Expand);
JF Bastienda06bce2015-08-11 21:02:46 +0000104 }
Dan Gohman32907a62015-08-20 22:57:13 +0000105
106 for (auto T : {MVT::i32, MVT::i64}) {
107 // Expand unavailable integer operations.
Dan Gohman7a6b9822015-11-29 22:32:02 +0000108 for (auto Op :
Dan Gohman665d7e32016-03-22 18:01:49 +0000109 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
Dan Gohman7a6b9822015-11-29 22:32:02 +0000110 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
111 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
Craig Topper33772c52016-04-28 03:34:31 +0000112 ISD::SUBE}) {
Dan Gohman32907a62015-08-20 22:57:13 +0000113 setOperationAction(Op, T, Expand);
114 }
115 }
116
117 // As a special case, these operators use the type to mean the type to
118 // sign-extend from.
Derek Schuffa519fe52017-09-13 00:29:06 +0000119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 if (!Subtarget->hasAtomics()) {
121 // The Atomics feature includes signext intructions.
122 for (auto T : {MVT::i8, MVT::i16, MVT::i32})
123 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
124 }
Dan Gohman32907a62015-08-20 22:57:13 +0000125
126 // Dynamic stack allocation: use the default expansion.
127 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
128 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Dan Gohman2683a552015-08-24 22:31:52 +0000129 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
JF Bastien73ff6af2015-08-31 22:24:11 +0000130
Derek Schuff9769deb2015-12-11 23:49:46 +0000131 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
Derek Schuffaadc89c2016-02-16 18:18:36 +0000132 setOperationAction(ISD::CopyToReg, MVT::Other, Custom);
Derek Schuff9769deb2015-12-11 23:49:46 +0000133
Dan Gohman950a13c2015-09-16 16:51:30 +0000134 // Expand these forms; we pattern-match the forms that we can handle in isel.
135 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
136 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
137 setOperationAction(Op, T, Expand);
138
139 // We have custom switch handling.
140 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
141
JF Bastien73ff6af2015-08-31 22:24:11 +0000142 // WebAssembly doesn't have:
143 // - Floating-point extending loads.
144 // - Floating-point truncating stores.
145 // - i1 extending loads.
Dan Gohman60bddf12015-12-10 02:07:53 +0000146 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
JF Bastien73ff6af2015-08-31 22:24:11 +0000147 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
148 for (auto T : MVT::integer_valuetypes())
149 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
150 setLoadExtAction(Ext, T, MVT::i1, Promote);
Derek Schuffffa143c2015-11-10 00:30:57 +0000151
152 // Trap lowers to wasm unreachable
153 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Derek Schuff18ba1922017-08-30 18:07:45 +0000154
155 setMaxAtomicSizeInBitsSupported(64);
Dan Gohmanbfaf7e12015-07-02 21:36:25 +0000156}
Dan Gohman10e730a2015-06-29 23:51:55 +0000157
Dan Gohman7b634842015-08-24 18:44:37 +0000158FastISel *WebAssemblyTargetLowering::createFastISel(
159 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
160 return WebAssembly::createFastISel(FuncInfo, LibInfo);
161}
162
JF Bastienaf111db2015-08-24 22:16:48 +0000163bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
Dan Gohman7a6b9822015-11-29 22:32:02 +0000164 const GlobalAddressSDNode * /*GA*/) const {
Dan Gohmana4b710a2015-12-06 19:33:32 +0000165 // All offsets can be folded.
166 return true;
JF Bastienaf111db2015-08-24 22:16:48 +0000167}
168
Dan Gohman7a6b9822015-11-29 22:32:02 +0000169MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
JF Bastienfda53372015-08-03 00:00:11 +0000170 EVT VT) const {
Dan Gohmana8483752015-12-10 00:26:26 +0000171 unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1);
Derek Schuff3f063292016-02-11 20:57:09 +0000172 if (BitWidth > 1 && BitWidth < 8) BitWidth = 8;
Dan Gohman41729532015-12-16 23:25:51 +0000173
174 if (BitWidth > 64) {
Dan Gohmana01e8bd2016-05-14 02:15:47 +0000175 // The shift will be lowered to a libcall, and compiler-rt libcalls expect
176 // the count to be an i32.
177 BitWidth = 32;
Dan Gohman41729532015-12-16 23:25:51 +0000178 assert(BitWidth >= Log2_32_Ceil(VT.getSizeInBits()) &&
Dan Gohmana01e8bd2016-05-14 02:15:47 +0000179 "32-bit shift counts ought to be enough for anyone");
Dan Gohman41729532015-12-16 23:25:51 +0000180 }
181
Dan Gohmana8483752015-12-10 00:26:26 +0000182 MVT Result = MVT::getIntegerVT(BitWidth);
183 assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE &&
184 "Unable to represent scalar shift amount type");
185 return Result;
JF Bastienfda53372015-08-03 00:00:11 +0000186}
187
Dan Gohmancdd48b82017-11-28 01:13:40 +0000188// Lower an fp-to-int conversion operator from the LLVM opcode, which has an
189// undefined result on invalid/overflow, to the WebAssembly opcode, which
190// traps on invalid/overflow.
191static MachineBasicBlock *
192LowerFPToInt(
193 MachineInstr &MI,
194 DebugLoc DL,
195 MachineBasicBlock *BB,
196 const TargetInstrInfo &TII,
197 bool IsUnsigned,
198 bool Int64,
199 bool Float64,
200 unsigned LoweredOpcode
201) {
202 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
203
204 unsigned OutReg = MI.getOperand(0).getReg();
205 unsigned InReg = MI.getOperand(1).getReg();
206
207 unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
208 unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
209 unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
Dan Gohman580c1022017-11-29 20:20:11 +0000210 unsigned GE = Float64 ? WebAssembly::GE_F64 : WebAssembly::GE_F32;
Dan Gohmancdd48b82017-11-28 01:13:40 +0000211 unsigned IConst = Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
Dan Gohman580c1022017-11-29 20:20:11 +0000212 unsigned Eqz = WebAssembly::EQZ_I32;
213 unsigned And = WebAssembly::AND_I32;
Dan Gohmancdd48b82017-11-28 01:13:40 +0000214 int64_t Limit = Int64 ? INT64_MIN : INT32_MIN;
215 int64_t Substitute = IsUnsigned ? 0 : Limit;
216 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit;
217 auto &Context = BB->getParent()->getFunction()->getContext();
218 Type *Ty = Float64 ? Type::getDoubleTy(Context) : Type::getFloatTy(Context);
219
220 const BasicBlock *LLVM_BB = BB->getBasicBlock();
221 MachineFunction *F = BB->getParent();
222 MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(LLVM_BB);
223 MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
224 MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(LLVM_BB);
225
226 MachineFunction::iterator It = ++BB->getIterator();
227 F->insert(It, FalseMBB);
228 F->insert(It, TrueMBB);
229 F->insert(It, DoneMBB);
230
231 // Transfer the remainder of BB and its successor edges to DoneMBB.
232 DoneMBB->splice(DoneMBB->begin(), BB,
233 std::next(MachineBasicBlock::iterator(MI)),
234 BB->end());
235 DoneMBB->transferSuccessorsAndUpdatePHIs(BB);
236
237 BB->addSuccessor(TrueMBB);
238 BB->addSuccessor(FalseMBB);
239 TrueMBB->addSuccessor(DoneMBB);
240 FalseMBB->addSuccessor(DoneMBB);
241
Dan Gohman580c1022017-11-29 20:20:11 +0000242 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
Dan Gohmancdd48b82017-11-28 01:13:40 +0000243 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
244 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
Dan Gohman580c1022017-11-29 20:20:11 +0000245 CmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
246 EqzReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
247 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
248 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
Dan Gohmancdd48b82017-11-28 01:13:40 +0000249
250 MI.eraseFromParent();
Dan Gohman580c1022017-11-29 20:20:11 +0000251 // For signed numbers, we can do a single comparison to determine whether
252 // fabs(x) is within range.
Dan Gohmancdd48b82017-11-28 01:13:40 +0000253 if (IsUnsigned) {
254 Tmp0 = InReg;
255 } else {
256 BuildMI(BB, DL, TII.get(Abs), Tmp0)
257 .addReg(InReg);
258 }
259 BuildMI(BB, DL, TII.get(FConst), Tmp1)
260 .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal)));
Dan Gohman580c1022017-11-29 20:20:11 +0000261 BuildMI(BB, DL, TII.get(LT), CmpReg)
Dan Gohmancdd48b82017-11-28 01:13:40 +0000262 .addReg(Tmp0)
263 .addReg(Tmp1);
Dan Gohman580c1022017-11-29 20:20:11 +0000264
265 // For unsigned numbers, we have to do a separate comparison with zero.
266 if (IsUnsigned) {
267 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
268 unsigned SecondCmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
269 unsigned AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
270 BuildMI(BB, DL, TII.get(FConst), Tmp1)
271 .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, 0.0)));
272 BuildMI(BB, DL, TII.get(GE), SecondCmpReg)
273 .addReg(Tmp0)
274 .addReg(Tmp1);
275 BuildMI(BB, DL, TII.get(And), AndReg)
276 .addReg(CmpReg)
277 .addReg(SecondCmpReg);
278 CmpReg = AndReg;
279 }
280
281 BuildMI(BB, DL, TII.get(Eqz), EqzReg)
282 .addReg(CmpReg);
283
284 // Create the CFG diamond to select between doing the conversion or using
285 // the substitute value.
Dan Gohmancdd48b82017-11-28 01:13:40 +0000286 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF))
287 .addMBB(TrueMBB)
Dan Gohman580c1022017-11-29 20:20:11 +0000288 .addReg(EqzReg);
289 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg)
290 .addReg(InReg);
Dan Gohmancdd48b82017-11-28 01:13:40 +0000291 BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR))
292 .addMBB(DoneMBB);
Dan Gohman580c1022017-11-29 20:20:11 +0000293 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg)
294 .addImm(Substitute);
Dan Gohmancdd48b82017-11-28 01:13:40 +0000295 BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
Dan Gohman580c1022017-11-29 20:20:11 +0000296 .addReg(FalseReg)
Dan Gohmancdd48b82017-11-28 01:13:40 +0000297 .addMBB(FalseMBB)
Dan Gohman580c1022017-11-29 20:20:11 +0000298 .addReg(TrueReg)
Dan Gohmancdd48b82017-11-28 01:13:40 +0000299 .addMBB(TrueMBB);
300
301 return DoneMBB;
302}
303
304MachineBasicBlock *
305WebAssemblyTargetLowering::EmitInstrWithCustomInserter(
306 MachineInstr &MI,
307 MachineBasicBlock *BB
308) const {
309 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
310 DebugLoc DL = MI.getDebugLoc();
311
312 switch (MI.getOpcode()) {
313 default: llvm_unreachable("Unexpected instr type to insert");
314 case WebAssembly::FP_TO_SINT_I32_F32:
315 return LowerFPToInt(MI, DL, BB, TII, false, false, false,
316 WebAssembly::I32_TRUNC_S_F32);
317 case WebAssembly::FP_TO_UINT_I32_F32:
318 return LowerFPToInt(MI, DL, BB, TII, true, false, false,
319 WebAssembly::I32_TRUNC_U_F32);
320 case WebAssembly::FP_TO_SINT_I64_F32:
321 return LowerFPToInt(MI, DL, BB, TII, false, true, false,
322 WebAssembly::I64_TRUNC_S_F32);
323 case WebAssembly::FP_TO_UINT_I64_F32:
324 return LowerFPToInt(MI, DL, BB, TII, true, true, false,
325 WebAssembly::I64_TRUNC_U_F32);
326 case WebAssembly::FP_TO_SINT_I32_F64:
327 return LowerFPToInt(MI, DL, BB, TII, false, false, true,
328 WebAssembly::I32_TRUNC_S_F64);
329 case WebAssembly::FP_TO_UINT_I32_F64:
330 return LowerFPToInt(MI, DL, BB, TII, true, false, true,
331 WebAssembly::I32_TRUNC_U_F64);
332 case WebAssembly::FP_TO_SINT_I64_F64:
333 return LowerFPToInt(MI, DL, BB, TII, false, true, true,
334 WebAssembly::I64_TRUNC_S_F64);
335 case WebAssembly::FP_TO_UINT_I64_F64:
336 return LowerFPToInt(MI, DL, BB, TII, true, true, true,
337 WebAssembly::I64_TRUNC_U_F64);
338 llvm_unreachable("Unexpected instruction to emit with custom inserter");
339 }
340}
341
Derek Schuff3f063292016-02-11 20:57:09 +0000342const char *WebAssemblyTargetLowering::getTargetNodeName(
343 unsigned Opcode) const {
JF Bastien480c8402015-08-11 20:13:18 +0000344 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
Derek Schuff3f063292016-02-11 20:57:09 +0000345 case WebAssemblyISD::FIRST_NUMBER:
346 break;
347#define HANDLE_NODETYPE(NODE) \
348 case WebAssemblyISD::NODE: \
JF Bastienaf111db2015-08-24 22:16:48 +0000349 return "WebAssemblyISD::" #NODE;
350#include "WebAssemblyISD.def"
351#undef HANDLE_NODETYPE
JF Bastien480c8402015-08-11 20:13:18 +0000352 }
353 return nullptr;
354}
355
Dan Gohmanf19ed562015-11-13 01:42:29 +0000356std::pair<unsigned, const TargetRegisterClass *>
357WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
358 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
359 // First, see if this is a constraint that directly corresponds to a
360 // WebAssembly register class.
361 if (Constraint.size() == 1) {
362 switch (Constraint[0]) {
Derek Schuff3f063292016-02-11 20:57:09 +0000363 case 'r':
364 assert(VT != MVT::iPTR && "Pointer MVT not expected here");
Derek Schuff39bf39f2016-08-02 23:16:09 +0000365 if (Subtarget->hasSIMD128() && VT.isVector()) {
366 if (VT.getSizeInBits() == 128)
367 return std::make_pair(0U, &WebAssembly::V128RegClass);
368 }
Derek Schuff3f063292016-02-11 20:57:09 +0000369 if (VT.isInteger() && !VT.isVector()) {
370 if (VT.getSizeInBits() <= 32)
371 return std::make_pair(0U, &WebAssembly::I32RegClass);
372 if (VT.getSizeInBits() <= 64)
373 return std::make_pair(0U, &WebAssembly::I64RegClass);
374 }
375 break;
376 default:
377 break;
Dan Gohmanf19ed562015-11-13 01:42:29 +0000378 }
379 }
380
381 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
382}
383
Dan Gohman3192ddf2015-11-19 23:04:59 +0000384bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
385 // Assume ctz is a relatively cheap operation.
386 return true;
387}
388
389bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
390 // Assume clz is a relatively cheap operation.
391 return true;
392}
393
Dan Gohman4b9d7912015-12-15 22:01:29 +0000394bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
395 const AddrMode &AM,
396 Type *Ty,
Jonas Paulsson024e3192017-07-21 11:59:37 +0000397 unsigned AS,
398 Instruction *I) const {
Dan Gohman4b9d7912015-12-15 22:01:29 +0000399 // WebAssembly offsets are added as unsigned without wrapping. The
400 // isLegalAddressingMode gives us no way to determine if wrapping could be
401 // happening, so we approximate this by accepting only non-negative offsets.
Derek Schuff3f063292016-02-11 20:57:09 +0000402 if (AM.BaseOffs < 0) return false;
Dan Gohman4b9d7912015-12-15 22:01:29 +0000403
404 // WebAssembly has no scale register operands.
Derek Schuff3f063292016-02-11 20:57:09 +0000405 if (AM.Scale != 0) return false;
Dan Gohman4b9d7912015-12-15 22:01:29 +0000406
407 // Everything else is legal.
408 return true;
409}
410
Dan Gohmanbb372242016-01-26 03:39:31 +0000411bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
Derek Schuff3f063292016-02-11 20:57:09 +0000412 EVT /*VT*/, unsigned /*AddrSpace*/, unsigned /*Align*/, bool *Fast) const {
Dan Gohmanbb372242016-01-26 03:39:31 +0000413 // WebAssembly supports unaligned accesses, though it should be declared
414 // with the p2align attribute on loads and stores which do so, and there
415 // may be a performance impact. We tell LLVM they're "fast" because
Dan Gohmanfb619e92016-01-26 14:55:17 +0000416 // for the kinds of things that LLVM uses this for (merging adjacent stores
Dan Gohmanbb372242016-01-26 03:39:31 +0000417 // of constants, etc.), WebAssembly implementations will either want the
418 // unaligned access or they'll split anyway.
Derek Schuff3f063292016-02-11 20:57:09 +0000419 if (Fast) *Fast = true;
Dan Gohmanbb372242016-01-26 03:39:31 +0000420 return true;
421}
422
Reid Klecknerb5180542017-03-21 16:57:19 +0000423bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT,
424 AttributeList Attr) const {
Dan Gohmanb4c3c382016-05-18 14:29:42 +0000425 // The current thinking is that wasm engines will perform this optimization,
426 // so we can save on code size.
427 return true;
428}
429
Dan Gohman10e730a2015-06-29 23:51:55 +0000430//===----------------------------------------------------------------------===//
431// WebAssembly Lowering private implementation.
432//===----------------------------------------------------------------------===//
433
434//===----------------------------------------------------------------------===//
435// Lowering Code
436//===----------------------------------------------------------------------===//
437
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000438static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *msg) {
JF Bastienb9073fb2015-07-22 21:28:15 +0000439 MachineFunction &MF = DAG.getMachineFunction();
440 DAG.getContext()->diagnose(
Oliver Stannard7e7d9832016-02-02 13:52:43 +0000441 DiagnosticInfoUnsupported(*MF.getFunction(), msg, DL.getDebugLoc()));
JF Bastienb9073fb2015-07-22 21:28:15 +0000442}
443
Dan Gohman85dbdda2015-12-04 17:16:07 +0000444// Test whether the given calling convention is supported.
Dan Gohmana3f5ce52015-12-04 17:18:32 +0000445static bool CallingConvSupported(CallingConv::ID CallConv) {
Dan Gohman85dbdda2015-12-04 17:16:07 +0000446 // We currently support the language-independent target-independent
Dan Gohman1ce2b1a2015-12-04 18:27:03 +0000447 // conventions. We don't yet have a way to annotate calls with properties like
448 // "cold", and we don't have any call-clobbered registers, so these are mostly
449 // all handled the same.
Dan Gohmana3f5ce52015-12-04 17:18:32 +0000450 return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
Dan Gohman1ce2b1a2015-12-04 18:27:03 +0000451 CallConv == CallingConv::Cold ||
452 CallConv == CallingConv::PreserveMost ||
453 CallConv == CallingConv::PreserveAll ||
454 CallConv == CallingConv::CXX_FAST_TLS;
Dan Gohman85dbdda2015-12-04 17:16:07 +0000455}
456
Derek Schuff3f063292016-02-11 20:57:09 +0000457SDValue WebAssemblyTargetLowering::LowerCall(
458 CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {
JF Bastiend8a9d662015-08-24 21:59:51 +0000459 SelectionDAG &DAG = CLI.DAG;
460 SDLoc DL = CLI.DL;
461 SDValue Chain = CLI.Chain;
462 SDValue Callee = CLI.Callee;
463 MachineFunction &MF = DAG.getMachineFunction();
Derek Schuff992d83f2016-02-10 20:14:15 +0000464 auto Layout = MF.getDataLayout();
JF Bastiend8a9d662015-08-24 21:59:51 +0000465
466 CallingConv::ID CallConv = CLI.CallConv;
Dan Gohman85dbdda2015-12-04 17:16:07 +0000467 if (!CallingConvSupported(CallConv))
Dan Gohman9cc692b2015-10-02 20:54:23 +0000468 fail(DL, DAG,
469 "WebAssembly doesn't support language-specific or target-specific "
470 "calling conventions yet");
JF Bastiend8a9d662015-08-24 21:59:51 +0000471 if (CLI.IsPatchPoint)
472 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
473
Dan Gohman9cc692b2015-10-02 20:54:23 +0000474 // WebAssembly doesn't currently support explicit tail calls. If they are
475 // required, fail. Otherwise, just disable them.
476 if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
477 MF.getTarget().Options.GuaranteedTailCallOpt) ||
Peter Collingbourne081ffe22017-07-26 19:15:29 +0000478 (CLI.CS && CLI.CS.isMustTailCall()))
Dan Gohman9cc692b2015-10-02 20:54:23 +0000479 fail(DL, DAG, "WebAssembly doesn't support tail call yet");
480 CLI.IsTailCall = false;
481
JF Bastiend8a9d662015-08-24 21:59:51 +0000482 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Dan Gohmane590b332015-09-09 01:52:45 +0000483 if (Ins.size() > 1)
484 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
485
Dan Gohman2d822e72015-12-04 17:12:52 +0000486 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
Derek Schuff4dd67782016-01-27 21:17:39 +0000487 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
488 for (unsigned i = 0; i < Outs.size(); ++i) {
489 const ISD::OutputArg &Out = Outs[i];
490 SDValue &OutVal = OutVals[i];
Dan Gohman7935fa32015-12-10 00:22:40 +0000491 if (Out.Flags.isNest())
492 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
Dan Gohman2d822e72015-12-04 17:12:52 +0000493 if (Out.Flags.isInAlloca())
Dan Gohman7935fa32015-12-10 00:22:40 +0000494 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
Dan Gohman2d822e72015-12-04 17:12:52 +0000495 if (Out.Flags.isInConsecutiveRegs())
Dan Gohman7935fa32015-12-10 00:22:40 +0000496 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
Dan Gohman2d822e72015-12-04 17:12:52 +0000497 if (Out.Flags.isInConsecutiveRegsLast())
Dan Gohman7935fa32015-12-10 00:22:40 +0000498 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
Dan Gohmana6771b32016-02-12 21:30:18 +0000499 if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) {
Matthias Braun941a7052016-07-28 18:40:00 +0000500 auto &MFI = MF.getFrameInfo();
501 int FI = MFI.CreateStackObject(Out.Flags.getByValSize(),
502 Out.Flags.getByValAlign(),
503 /*isSS=*/false);
Derek Schuff4dd67782016-01-27 21:17:39 +0000504 SDValue SizeNode =
505 DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
Derek Schuff992d83f2016-02-10 20:14:15 +0000506 SDValue FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
Derek Schuff4dd67782016-01-27 21:17:39 +0000507 Chain = DAG.getMemcpy(
508 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(),
Dan Gohman476ffce2016-02-17 01:43:37 +0000509 /*isVolatile*/ false, /*AlwaysInline=*/false,
Derek Schuff4dd67782016-01-27 21:17:39 +0000510 /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
511 OutVal = FINode;
512 }
Dan Gohman2d822e72015-12-04 17:12:52 +0000513 }
514
JF Bastiend8a9d662015-08-24 21:59:51 +0000515 bool IsVarArg = CLI.IsVarArg;
Dan Gohman35bfb242015-12-04 23:22:35 +0000516 unsigned NumFixedArgs = CLI.NumFixedArgs;
Derek Schuff992d83f2016-02-10 20:14:15 +0000517
518 auto PtrVT = getPointerTy(Layout);
Dan Gohmane590b332015-09-09 01:52:45 +0000519
JF Bastiend8a9d662015-08-24 21:59:51 +0000520 // Analyze operands of the call, assigning locations to each operand.
521 SmallVector<CCValAssign, 16> ArgLocs;
522 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
JF Bastiend8a9d662015-08-24 21:59:51 +0000523
Dan Gohman35bfb242015-12-04 23:22:35 +0000524 if (IsVarArg) {
Derek Schuff27501e22016-02-10 19:51:04 +0000525 // Outgoing non-fixed arguments are placed in a buffer. First
526 // compute their offsets and the total amount of buffer space needed.
Dan Gohman35bfb242015-12-04 23:22:35 +0000527 for (SDValue Arg :
528 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
529 EVT VT = Arg.getValueType();
530 assert(VT != MVT::iPTR && "Legalized args should be concrete");
531 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
Derek Schuff992d83f2016-02-10 20:14:15 +0000532 unsigned Offset = CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty),
533 Layout.getABITypeAlignment(Ty));
Dan Gohman35bfb242015-12-04 23:22:35 +0000534 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
535 Offset, VT.getSimpleVT(),
536 CCValAssign::Full));
537 }
538 }
539
540 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
541
Derek Schuff27501e22016-02-10 19:51:04 +0000542 SDValue FINode;
543 if (IsVarArg && NumBytes) {
Dan Gohman35bfb242015-12-04 23:22:35 +0000544 // For non-fixed arguments, next emit stores to store the argument values
Derek Schuff27501e22016-02-10 19:51:04 +0000545 // to the stack buffer at the offsets computed above.
Matthias Braun941a7052016-07-28 18:40:00 +0000546 int FI = MF.getFrameInfo().CreateStackObject(NumBytes,
547 Layout.getStackAlignment(),
548 /*isSS=*/false);
Dan Gohman35bfb242015-12-04 23:22:35 +0000549 unsigned ValNo = 0;
550 SmallVector<SDValue, 8> Chains;
551 for (SDValue Arg :
552 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
553 assert(ArgLocs[ValNo].getValNo() == ValNo &&
554 "ArgLocs should remain in order and only hold varargs args");
555 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
Derek Schuff992d83f2016-02-10 20:14:15 +0000556 FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
Derek Schuff27501e22016-02-10 19:51:04 +0000557 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode,
Dan Gohman35bfb242015-12-04 23:22:35 +0000558 DAG.getConstant(Offset, DL, PtrVT));
Derek Schuff27501e22016-02-10 19:51:04 +0000559 Chains.push_back(DAG.getStore(
560 Chain, DL, Arg, Add,
Derek Schuff1a946e42016-07-15 19:35:43 +0000561 MachinePointerInfo::getFixedStack(MF, FI, Offset), 0));
Dan Gohman35bfb242015-12-04 23:22:35 +0000562 }
563 if (!Chains.empty())
564 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
Derek Schuff27501e22016-02-10 19:51:04 +0000565 } else if (IsVarArg) {
566 FINode = DAG.getIntPtrConstant(0, DL);
Dan Gohman35bfb242015-12-04 23:22:35 +0000567 }
568
569 // Compute the operands for the CALLn node.
JF Bastiend8a9d662015-08-24 21:59:51 +0000570 SmallVector<SDValue, 16> Ops;
571 Ops.push_back(Chain);
JF Bastienaf111db2015-08-24 22:16:48 +0000572 Ops.push_back(Callee);
Dan Gohman35bfb242015-12-04 23:22:35 +0000573
574 // Add all fixed arguments. Note that for non-varargs calls, NumFixedArgs
575 // isn't reliable.
576 Ops.append(OutVals.begin(),
577 IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end());
Derek Schuff27501e22016-02-10 19:51:04 +0000578 // Add a pointer to the vararg buffer.
579 if (IsVarArg) Ops.push_back(FINode);
JF Bastiend8a9d662015-08-24 21:59:51 +0000580
Derek Schuff27501e22016-02-10 19:51:04 +0000581 SmallVector<EVT, 8> InTys;
Dan Gohman2d822e72015-12-04 17:12:52 +0000582 for (const auto &In : Ins) {
Dan Gohman7935fa32015-12-10 00:22:40 +0000583 assert(!In.Flags.isByVal() && "byval is not valid for return values");
584 assert(!In.Flags.isNest() && "nest is not valid for return values");
Dan Gohman2d822e72015-12-04 17:12:52 +0000585 if (In.Flags.isInAlloca())
Dan Gohman7935fa32015-12-10 00:22:40 +0000586 fail(DL, DAG, "WebAssembly hasn't implemented inalloca return values");
Dan Gohman2d822e72015-12-04 17:12:52 +0000587 if (In.Flags.isInConsecutiveRegs())
Dan Gohman7935fa32015-12-10 00:22:40 +0000588 fail(DL, DAG, "WebAssembly hasn't implemented cons regs return values");
Dan Gohman2d822e72015-12-04 17:12:52 +0000589 if (In.Flags.isInConsecutiveRegsLast())
Dan Gohman4b9d7912015-12-15 22:01:29 +0000590 fail(DL, DAG,
591 "WebAssembly hasn't implemented cons regs last return values");
Dan Gohman2d822e72015-12-04 17:12:52 +0000592 // Ignore In.getOrigAlign() because all our arguments are passed in
593 // registers.
Derek Schuff27501e22016-02-10 19:51:04 +0000594 InTys.push_back(In.VT);
Dan Gohman2d822e72015-12-04 17:12:52 +0000595 }
Derek Schuff27501e22016-02-10 19:51:04 +0000596 InTys.push_back(MVT::Other);
597 SDVTList InTyList = DAG.getVTList(InTys);
Dan Gohmanf71abef2015-09-09 16:13:47 +0000598 SDValue Res =
599 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
Derek Schuff27501e22016-02-10 19:51:04 +0000600 DL, InTyList, Ops);
JF Bastienaf111db2015-08-24 22:16:48 +0000601 if (Ins.empty()) {
602 Chain = Res;
603 } else {
604 InVals.push_back(Res);
605 Chain = Res.getValue(1);
606 }
JF Bastiend8a9d662015-08-24 21:59:51 +0000607
JF Bastiend8a9d662015-08-24 21:59:51 +0000608 return Chain;
609}
610
JF Bastienb9073fb2015-07-22 21:28:15 +0000611bool WebAssemblyTargetLowering::CanLowerReturn(
Dan Gohman7a6b9822015-11-29 22:32:02 +0000612 CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
613 const SmallVectorImpl<ISD::OutputArg> &Outs,
614 LLVMContext & /*Context*/) const {
JF Bastienb9073fb2015-07-22 21:28:15 +0000615 // WebAssembly can't currently handle returning tuples.
616 return Outs.size() <= 1;
617}
618
619SDValue WebAssemblyTargetLowering::LowerReturn(
Dan Gohman35bfb242015-12-04 23:22:35 +0000620 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
JF Bastienb9073fb2015-07-22 21:28:15 +0000621 const SmallVectorImpl<ISD::OutputArg> &Outs,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000622 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
JF Bastienb9073fb2015-07-22 21:28:15 +0000623 SelectionDAG &DAG) const {
JF Bastienb9073fb2015-07-22 21:28:15 +0000624 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
Dan Gohman85dbdda2015-12-04 17:16:07 +0000625 if (!CallingConvSupported(CallConv))
JF Bastienb9073fb2015-07-22 21:28:15 +0000626 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
627
JF Bastien600aee92015-07-31 17:53:38 +0000628 SmallVector<SDValue, 4> RetOps(1, Chain);
629 RetOps.append(OutVals.begin(), OutVals.end());
JF Bastien4a2d5602015-07-31 21:04:18 +0000630 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
JF Bastienb9073fb2015-07-22 21:28:15 +0000631
Dan Gohman754cd112015-11-11 01:33:02 +0000632 // Record the number and types of the return values.
633 for (const ISD::OutputArg &Out : Outs) {
Dan Gohmanac132e92015-12-02 23:40:03 +0000634 assert(!Out.Flags.isByVal() && "byval is not valid for return values");
635 assert(!Out.Flags.isNest() && "nest is not valid for return values");
Dan Gohman35bfb242015-12-04 23:22:35 +0000636 assert(Out.IsFixed && "non-fixed return value is not valid");
Dan Gohman754cd112015-11-11 01:33:02 +0000637 if (Out.Flags.isInAlloca())
638 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
Dan Gohman754cd112015-11-11 01:33:02 +0000639 if (Out.Flags.isInConsecutiveRegs())
640 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
641 if (Out.Flags.isInConsecutiveRegsLast())
642 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
Dan Gohman754cd112015-11-11 01:33:02 +0000643 }
644
JF Bastienb9073fb2015-07-22 21:28:15 +0000645 return Chain;
646}
647
648SDValue WebAssemblyTargetLowering::LowerFormalArguments(
Derek Schuff27501e22016-02-10 19:51:04 +0000649 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000650 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
651 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
Dan Gohman85dbdda2015-12-04 17:16:07 +0000652 if (!CallingConvSupported(CallConv))
JF Bastienb9073fb2015-07-22 21:28:15 +0000653 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
JF Bastienb9073fb2015-07-22 21:28:15 +0000654
Dan Gohman2726b882016-10-06 22:29:32 +0000655 MachineFunction &MF = DAG.getMachineFunction();
656 auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
657
Dan Gohmanfb3e0592015-11-25 19:36:19 +0000658 // Set up the incoming ARGUMENTS value, which serves to represent the liveness
659 // of the incoming values before they're represented by virtual registers.
660 MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
661
JF Bastien600aee92015-07-31 17:53:38 +0000662 for (const ISD::InputArg &In : Ins) {
JF Bastien600aee92015-07-31 17:53:38 +0000663 if (In.Flags.isInAlloca())
664 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
665 if (In.Flags.isNest())
666 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
JF Bastien600aee92015-07-31 17:53:38 +0000667 if (In.Flags.isInConsecutiveRegs())
668 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
669 if (In.Flags.isInConsecutiveRegsLast())
670 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
Dan Gohman9c54d3b2015-11-25 18:13:18 +0000671 // Ignore In.getOrigAlign() because all our arguments are passed in
672 // registers.
JF Bastiend7fcc6f2015-07-31 18:13:27 +0000673 InVals.push_back(
674 In.Used
675 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
Dan Gohman5219ecf2015-11-14 23:28:15 +0000676 DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
Dan Gohmancb7940f2015-12-04 17:09:42 +0000677 : DAG.getUNDEF(In.VT));
Dan Gohman754cd112015-11-11 01:33:02 +0000678
679 // Record the number and types of arguments.
Derek Schuff27501e22016-02-10 19:51:04 +0000680 MFI->addParam(In.VT);
JF Bastien600aee92015-07-31 17:53:38 +0000681 }
JF Bastienb9073fb2015-07-22 21:28:15 +0000682
Derek Schuff27501e22016-02-10 19:51:04 +0000683 // Varargs are copied into a buffer allocated by the caller, and a pointer to
684 // the buffer is passed as an argument.
685 if (IsVarArg) {
686 MVT PtrVT = getPointerTy(MF.getDataLayout());
687 unsigned VarargVreg =
688 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
689 MFI->setVarargBufferVreg(VarargVreg);
690 Chain = DAG.getCopyToReg(
691 Chain, DL, VarargVreg,
692 DAG.getNode(WebAssemblyISD::ARGUMENT, DL, PtrVT,
693 DAG.getTargetConstant(Ins.size(), DL, MVT::i32)));
694 MFI->addParam(PtrVT);
695 }
Dan Gohman35bfb242015-12-04 23:22:35 +0000696
Dan Gohman2726b882016-10-06 22:29:32 +0000697 // Record the number and types of results.
698 SmallVector<MVT, 4> Params;
699 SmallVector<MVT, 4> Results;
700 ComputeSignatureVTs(*MF.getFunction(), DAG.getTarget(), Params, Results);
701 for (MVT VT : Results)
702 MFI->addResult(VT);
703
JF Bastienb9073fb2015-07-22 21:28:15 +0000704 return Chain;
705}
706
Dan Gohman10e730a2015-06-29 23:51:55 +0000707//===----------------------------------------------------------------------===//
JF Bastienaf111db2015-08-24 22:16:48 +0000708// Custom lowering hooks.
Dan Gohman10e730a2015-06-29 23:51:55 +0000709//===----------------------------------------------------------------------===//
710
JF Bastienaf111db2015-08-24 22:16:48 +0000711SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
712 SelectionDAG &DAG) const {
Derek Schuff51699a82016-02-12 22:56:03 +0000713 SDLoc DL(Op);
JF Bastienaf111db2015-08-24 22:16:48 +0000714 switch (Op.getOpcode()) {
Derek Schuff3f063292016-02-11 20:57:09 +0000715 default:
716 llvm_unreachable("unimplemented operation lowering");
717 return SDValue();
718 case ISD::FrameIndex:
719 return LowerFrameIndex(Op, DAG);
720 case ISD::GlobalAddress:
721 return LowerGlobalAddress(Op, DAG);
722 case ISD::ExternalSymbol:
723 return LowerExternalSymbol(Op, DAG);
724 case ISD::JumpTable:
725 return LowerJumpTable(Op, DAG);
726 case ISD::BR_JT:
727 return LowerBR_JT(Op, DAG);
728 case ISD::VASTART:
729 return LowerVASTART(Op, DAG);
Derek Schuff51699a82016-02-12 22:56:03 +0000730 case ISD::BlockAddress:
731 case ISD::BRIND:
732 fail(DL, DAG, "WebAssembly hasn't implemented computed gotos");
733 return SDValue();
734 case ISD::RETURNADDR: // Probably nothing meaningful can be returned here.
735 fail(DL, DAG, "WebAssembly hasn't implemented __builtin_return_address");
736 return SDValue();
Dan Gohman94c65662016-02-16 23:48:04 +0000737 case ISD::FRAMEADDR:
738 return LowerFRAMEADDR(Op, DAG);
Derek Schuffaadc89c2016-02-16 18:18:36 +0000739 case ISD::CopyToReg:
740 return LowerCopyToReg(Op, DAG);
JF Bastienaf111db2015-08-24 22:16:48 +0000741 }
742}
743
Derek Schuffaadc89c2016-02-16 18:18:36 +0000744SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op,
745 SelectionDAG &DAG) const {
746 SDValue Src = Op.getOperand(2);
747 if (isa<FrameIndexSDNode>(Src.getNode())) {
748 // CopyToReg nodes don't support FrameIndex operands. Other targets select
749 // the FI to some LEA-like instruction, but since we don't have that, we
750 // need to insert some kind of instruction that can take an FI operand and
751 // produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
752 // copy_local between Op and its FI operand.
Dan Gohman02c08712016-02-20 23:09:44 +0000753 SDValue Chain = Op.getOperand(0);
Derek Schuffaadc89c2016-02-16 18:18:36 +0000754 SDLoc DL(Op);
Dan Gohman02c08712016-02-20 23:09:44 +0000755 unsigned Reg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
Derek Schuffaadc89c2016-02-16 18:18:36 +0000756 EVT VT = Src.getValueType();
757 SDValue Copy(
Dan Gohman4fc4e422016-10-24 19:49:43 +0000758 DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_I32
759 : WebAssembly::COPY_I64,
Derek Schuffaadc89c2016-02-16 18:18:36 +0000760 DL, VT, Src),
761 0);
Dan Gohman02c08712016-02-20 23:09:44 +0000762 return Op.getNode()->getNumValues() == 1
763 ? DAG.getCopyToReg(Chain, DL, Reg, Copy)
764 : DAG.getCopyToReg(Chain, DL, Reg, Copy, Op.getNumOperands() == 4
765 ? Op.getOperand(3)
766 : SDValue());
Derek Schuffaadc89c2016-02-16 18:18:36 +0000767 }
768 return SDValue();
769}
770
Derek Schuff9769deb2015-12-11 23:49:46 +0000771SDValue WebAssemblyTargetLowering::LowerFrameIndex(SDValue Op,
772 SelectionDAG &DAG) const {
773 int FI = cast<FrameIndexSDNode>(Op)->getIndex();
774 return DAG.getTargetFrameIndex(FI, Op.getValueType());
775}
776
Dan Gohman94c65662016-02-16 23:48:04 +0000777SDValue WebAssemblyTargetLowering::LowerFRAMEADDR(SDValue Op,
778 SelectionDAG &DAG) const {
779 // Non-zero depths are not supported by WebAssembly currently. Use the
780 // legalizer's default expansion, which is to return 0 (what this function is
781 // documented to do).
Dan Gohman1d547bf2016-02-17 00:14:03 +0000782 if (Op.getConstantOperandVal(0) > 0)
Dan Gohman94c65662016-02-16 23:48:04 +0000783 return SDValue();
784
Matthias Braun941a7052016-07-28 18:40:00 +0000785 DAG.getMachineFunction().getFrameInfo().setFrameAddressIsTaken(true);
Dan Gohman94c65662016-02-16 23:48:04 +0000786 EVT VT = Op.getValueType();
787 unsigned FP =
788 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
789 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), FP, VT);
790}
791
JF Bastienaf111db2015-08-24 22:16:48 +0000792SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
793 SelectionDAG &DAG) const {
794 SDLoc DL(Op);
795 const auto *GA = cast<GlobalAddressSDNode>(Op);
796 EVT VT = Op.getValueType();
Dan Gohman26c67652016-01-11 23:38:05 +0000797 assert(GA->getTargetFlags() == 0 &&
798 "Unexpected target flags on generic GlobalAddressSDNode");
JF Bastienaf111db2015-08-24 22:16:48 +0000799 if (GA->getAddressSpace() != 0)
800 fail(DL, DAG, "WebAssembly only expects the 0 address space");
Dan Gohman4b9d7912015-12-15 22:01:29 +0000801 return DAG.getNode(
802 WebAssemblyISD::Wrapper, DL, VT,
803 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset()));
JF Bastienaf111db2015-08-24 22:16:48 +0000804}
805
Derek Schuff3f063292016-02-11 20:57:09 +0000806SDValue WebAssemblyTargetLowering::LowerExternalSymbol(
807 SDValue Op, SelectionDAG &DAG) const {
Dan Gohman2c8fe6a2015-11-25 16:44:29 +0000808 SDLoc DL(Op);
809 const auto *ES = cast<ExternalSymbolSDNode>(Op);
810 EVT VT = Op.getValueType();
Dan Gohman26c67652016-01-11 23:38:05 +0000811 assert(ES->getTargetFlags() == 0 &&
812 "Unexpected target flags on generic ExternalSymbolSDNode");
813 // Set the TargetFlags to 0x1 which indicates that this is a "function"
814 // symbol rather than a data symbol. We do this unconditionally even though
815 // we don't know anything about the symbol other than its name, because all
816 // external symbols used in target-independent SelectionDAG code are for
817 // functions.
Dan Gohman2c8fe6a2015-11-25 16:44:29 +0000818 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
Dan Gohman26c67652016-01-11 23:38:05 +0000819 DAG.getTargetExternalSymbol(ES->getSymbol(), VT,
820 /*TargetFlags=*/0x1));
Dan Gohman2c8fe6a2015-11-25 16:44:29 +0000821}
822
Dan Gohman950a13c2015-09-16 16:51:30 +0000823SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
824 SelectionDAG &DAG) const {
825 // There's no need for a Wrapper node because we always incorporate a jump
Dan Gohman14026062016-03-08 03:18:12 +0000826 // table operand into a BR_TABLE instruction, rather than ever
Dan Gohmanbb7ce8e2015-11-20 03:02:49 +0000827 // materializing it in a register.
Dan Gohman950a13c2015-09-16 16:51:30 +0000828 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
829 return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
830 JT->getTargetFlags());
831}
832
833SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
834 SelectionDAG &DAG) const {
835 SDLoc DL(Op);
836 SDValue Chain = Op.getOperand(0);
837 const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
838 SDValue Index = Op.getOperand(2);
839 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
840
841 SmallVector<SDValue, 8> Ops;
842 Ops.push_back(Chain);
843 Ops.push_back(Index);
844
845 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
846 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
847
Dan Gohman14026062016-03-08 03:18:12 +0000848 // Add an operand for each case.
849 for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB));
850
Dan Gohman950a13c2015-09-16 16:51:30 +0000851 // TODO: For now, we just pick something arbitrary for a default case for now.
852 // We really want to sniff out the guard and put in the real default case (and
853 // delete the guard).
854 Ops.push_back(DAG.getBasicBlock(MBBs[0]));
855
Dan Gohman14026062016-03-08 03:18:12 +0000856 return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops);
Dan Gohman950a13c2015-09-16 16:51:30 +0000857}
858
Dan Gohman35bfb242015-12-04 23:22:35 +0000859SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
860 SelectionDAG &DAG) const {
861 SDLoc DL(Op);
862 EVT PtrVT = getPointerTy(DAG.getMachineFunction().getDataLayout());
863
Derek Schuff27501e22016-02-10 19:51:04 +0000864 auto *MFI = DAG.getMachineFunction().getInfo<WebAssemblyFunctionInfo>();
Dan Gohman35bfb242015-12-04 23:22:35 +0000865 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Derek Schuff27501e22016-02-10 19:51:04 +0000866
867 SDValue ArgN = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
868 MFI->getVarargBufferVreg(), PtrVT);
869 return DAG.getStore(Op.getOperand(0), DL, ArgN, Op.getOperand(1),
Derek Schuff1a946e42016-07-15 19:35:43 +0000870 MachinePointerInfo(SV), 0);
Dan Gohman35bfb242015-12-04 23:22:35 +0000871}
872
Dan Gohman10e730a2015-06-29 23:51:55 +0000873//===----------------------------------------------------------------------===//
874// WebAssembly Optimization Hooks
875//===----------------------------------------------------------------------===//