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gerrit-public.fairphone.software / toolchain / llvm-project / 5965bd19f85f1fa1d80e3bba42dc7954d0ff5f73 / . / llvm / lib / Target / Sparc / SparcInstrInfo.td
blob: 3d610635ccb099e5ae93b13dc59b143d637d17ab [file] [log] [blame]
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Sparc instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Instruction format superclass
16//===----------------------------------------------------------------------===//
17
18include "SparcInstrFormats.td"
19
20//===----------------------------------------------------------------------===//
21// Feature predicates.
22//===----------------------------------------------------------------------===//
23
24// HasV9 - This predicate is true when the target processor supports V9
25// instructions. Note that the machine may be running in 32-bit mode.
26def HasV9 : Predicate<"Subtarget.isV9()">;
27
28// HasNoV9 - This predicate is true when the target doesn't have V9
29// instructions. Use of this is just a hack for the isel not having proper
30// costs for V8 instructions that are more expensive than their V9 ones.
31def HasNoV9 : Predicate<"!Subtarget.isV9()">;
32
33// HasVIS - This is true when the target processor has VIS extensions.
34def HasVIS : Predicate<"Subtarget.isVIS()">;
35
36// UseDeprecatedInsts - This predicate is true when the target processor is a
37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38// to use when appropriate. In either of these cases, the instruction selector
39// will pick deprecated instructions.
40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
41
42//===----------------------------------------------------------------------===//
43// Instruction Pattern Stuff
44//===----------------------------------------------------------------------===//
45
46def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
49}]>;
50
51def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
54}]>;
55
56def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
58}]>;
59
60def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
63}]>;
64
65def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
67}], HI22>;
68
69// Addressing modes.
70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]72
73// Address operands
74def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let NumMIOperands = 2;
77 let MIOperandInfo = (ops IntRegs, IntRegs);
78}
79def MEMri : Operand<i32> {
80 let PrintMethod = "printMemOperand";
81 let NumMIOperands = 2;
82 let MIOperandInfo = (ops IntRegs, i32imm);
83}
84
85// Branch targets have OtherVT type.
86def brtarget : Operand<OtherVT>;
87def calltarget : Operand<i32>;
88
89// Operand for printing out a condition code.
90let PrintMethod = "printCCOperand" in
91 def CCOp : Operand<i32>;
92
93def SDTSPcmpfcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]95def SDTSPbrcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]97def SDTSPselectcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]99def SDTSPFTOI :
100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
101def SDTSPITOF :
102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
103
104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]108
109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
111
112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
114
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]117
118// These are target-independent nodes, but have target-specific formats.
119def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
120def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, [SDNPHasChain]>;
121def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, [SDNPHasChain]>;
122
123def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
124def call : SDNode<"SPISD::CALL", SDT_SPCall,
125 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126
127def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
128def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
129 [SDNPHasChain, SDNPOptInFlag]>;
130
131//===----------------------------------------------------------------------===//
132// SPARC Flag Conditions
133//===----------------------------------------------------------------------===//
134
135// Note that these values must be kept in sync with the CCOp::CondCode enum
136// values.
137class ICC_VAL<int N> : PatLeaf<(i32 N)>;
138def ICC_NE : ICC_VAL< 9>; // Not Equal
139def ICC_E : ICC_VAL< 1>; // Equal
140def ICC_G : ICC_VAL<10>; // Greater
141def ICC_LE : ICC_VAL< 2>; // Less or Equal
142def ICC_GE : ICC_VAL<11>; // Greater or Equal
143def ICC_L : ICC_VAL< 3>; // Less
144def ICC_GU : ICC_VAL<12>; // Greater Unsigned
145def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
146def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
147def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
148def ICC_POS : ICC_VAL<14>; // Positive
149def ICC_NEG : ICC_VAL< 6>; // Negative
150def ICC_VC : ICC_VAL<15>; // Overflow Clear
151def ICC_VS : ICC_VAL< 7>; // Overflow Set
152
153class FCC_VAL<int N> : PatLeaf<(i32 N)>;
154def FCC_U : FCC_VAL<23>; // Unordered
155def FCC_G : FCC_VAL<22>; // Greater
156def FCC_UG : FCC_VAL<21>; // Unordered or Greater
157def FCC_L : FCC_VAL<20>; // Less
158def FCC_UL : FCC_VAL<19>; // Unordered or Less
159def FCC_LG : FCC_VAL<18>; // Less or Greater
160def FCC_NE : FCC_VAL<17>; // Not Equal
161def FCC_E : FCC_VAL<25>; // Equal
162def FCC_UE : FCC_VAL<24>; // Unordered or Equal
163def FCC_GE : FCC_VAL<25>; // Greater or Equal
164def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
165def FCC_LE : FCC_VAL<27>; // Less or Equal
166def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
167def FCC_O : FCC_VAL<29>; // Ordered
168
169
170//===----------------------------------------------------------------------===//
171// Instructions
172//===----------------------------------------------------------------------===//
173
174// Pseudo instructions.
175class Pseudo<dag ops, string asmstr, list<dag> pattern>
176 : InstSP<ops, asmstr, pattern>;
177
178def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
179 "!ADJCALLSTACKDOWN $amt",
180 [(callseq_start imm:$amt)]>;
181def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
182 "!ADJCALLSTACKUP $amt",
183 [(callseq_end imm:$amt)]>;
184def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
185 "!IMPLICIT_DEF $dst",
186 [(set IntRegs:$dst, (undef))]>;
187def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
188 [(set FPRegs:$dst, (undef))]>;
189def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
190 [(set DFPRegs:$dst, (undef))]>;
191
192// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
193// fpmover pass.
194let Predicates = [HasNoV9] in { // Only emit these in SP mode.
195 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
196 "!FpMOVD $src, $dst", []>;
197 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
198 "!FpNEGD $src, $dst",
199 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
200 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
201 "!FpABSD $src, $dst",
202 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
203}
204
205// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
206// scheduler into a branch sequence. This has to handle all permutations of
207// selection between i32/f32/f64 on ICC and FCC.
208let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
209 Predicates = [HasNoV9] in { // V9 has conditional moves
210 def SELECT_CC_Int_ICC
211 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
212 "; SELECT_CC_Int_ICC PSEUDO!",
213 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]214 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]215 def SELECT_CC_Int_FCC
216 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
217 "; SELECT_CC_Int_FCC PSEUDO!",
218 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]219 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]220 def SELECT_CC_FP_ICC
221 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
222 "; SELECT_CC_FP_ICC PSEUDO!",
223 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]224 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]225 def SELECT_CC_FP_FCC
226 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
227 "; SELECT_CC_FP_FCC PSEUDO!",
228 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]229 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]230 def SELECT_CC_DFP_ICC
231 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
232 "; SELECT_CC_DFP_ICC PSEUDO!",
233 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]234 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]235 def SELECT_CC_DFP_FCC
236 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
237 "; SELECT_CC_DFP_FCC PSEUDO!",
238 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]239 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]240}
241
242
243// Section A.3 - Synthetic Instructions, p. 85
244// special cases of JMPL:
245let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
246 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
247 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
248}
249
250// Section B.1 - Load Integer Instructions, p. 90
251def LDSBrr : F3_1<3, 0b001001,
252 (ops IntRegs:$dst, MEMrr:$addr),
253 "ldsb [$addr], $dst",
254 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
255def LDSBri : F3_2<3, 0b001001,
256 (ops IntRegs:$dst, MEMri:$addr),
257 "ldsb [$addr], $dst",
258 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
259def LDSHrr : F3_1<3, 0b001010,
260 (ops IntRegs:$dst, MEMrr:$addr),
261 "ldsh [$addr], $dst",
262 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
263def LDSHri : F3_2<3, 0b001010,
264 (ops IntRegs:$dst, MEMri:$addr),
265 "ldsh [$addr], $dst",
266 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
267def LDUBrr : F3_1<3, 0b000001,
268 (ops IntRegs:$dst, MEMrr:$addr),
269 "ldub [$addr], $dst",
270 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
271def LDUBri : F3_2<3, 0b000001,
272 (ops IntRegs:$dst, MEMri:$addr),
273 "ldub [$addr], $dst",
274 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
275def LDUHrr : F3_1<3, 0b000010,
276 (ops IntRegs:$dst, MEMrr:$addr),
277 "lduh [$addr], $dst",
278 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
279def LDUHri : F3_2<3, 0b000010,
280 (ops IntRegs:$dst, MEMri:$addr),
281 "lduh [$addr], $dst",
282 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
283def LDrr : F3_1<3, 0b000000,
284 (ops IntRegs:$dst, MEMrr:$addr),
285 "ld [$addr], $dst",
286 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
287def LDri : F3_2<3, 0b000000,
288 (ops IntRegs:$dst, MEMri:$addr),
289 "ld [$addr], $dst",
290 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
291
292// Section B.2 - Load Floating-point Instructions, p. 92
293def LDFrr : F3_1<3, 0b100000,
294 (ops FPRegs:$dst, MEMrr:$addr),
295 "ld [$addr], $dst",
296 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
297def LDFri : F3_2<3, 0b100000,
298 (ops FPRegs:$dst, MEMri:$addr),
299 "ld [$addr], $dst",
300 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
301def LDDFrr : F3_1<3, 0b100011,
302 (ops DFPRegs:$dst, MEMrr:$addr),
303 "ldd [$addr], $dst",
304 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
305def LDDFri : F3_2<3, 0b100011,
306 (ops DFPRegs:$dst, MEMri:$addr),
307 "ldd [$addr], $dst",
308 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
309
310// Section B.4 - Store Integer Instructions, p. 95
311def STBrr : F3_1<3, 0b000101,
312 (ops MEMrr:$addr, IntRegs:$src),
313 "stb $src, [$addr]",
314 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
315def STBri : F3_2<3, 0b000101,
316 (ops MEMri:$addr, IntRegs:$src),
317 "stb $src, [$addr]",
318 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
319def STHrr : F3_1<3, 0b000110,
320 (ops MEMrr:$addr, IntRegs:$src),
321 "sth $src, [$addr]",
322 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
323def STHri : F3_2<3, 0b000110,
324 (ops MEMri:$addr, IntRegs:$src),
325 "sth $src, [$addr]",
326 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
327def STrr : F3_1<3, 0b000100,
328 (ops MEMrr:$addr, IntRegs:$src),
329 "st $src, [$addr]",
330 [(store IntRegs:$src, ADDRrr:$addr)]>;
331def STri : F3_2<3, 0b000100,
332 (ops MEMri:$addr, IntRegs:$src),
333 "st $src, [$addr]",
334 [(store IntRegs:$src, ADDRri:$addr)]>;
335
336// Section B.5 - Store Floating-point Instructions, p. 97
337def STFrr : F3_1<3, 0b100100,
338 (ops MEMrr:$addr, FPRegs:$src),
339 "st $src, [$addr]",
340 [(store FPRegs:$src, ADDRrr:$addr)]>;
341def STFri : F3_2<3, 0b100100,
342 (ops MEMri:$addr, FPRegs:$src),
343 "st $src, [$addr]",
344 [(store FPRegs:$src, ADDRri:$addr)]>;
345def STDFrr : F3_1<3, 0b100111,
346 (ops MEMrr:$addr, DFPRegs:$src),
347 "std $src, [$addr]",
348 [(store DFPRegs:$src, ADDRrr:$addr)]>;
349def STDFri : F3_2<3, 0b100111,
350 (ops MEMri:$addr, DFPRegs:$src),
351 "std $src, [$addr]",
352 [(store DFPRegs:$src, ADDRri:$addr)]>;
353
354// Section B.9 - SETHI Instruction, p. 104
355def SETHIi: F2_1<0b100,
356 (ops IntRegs:$dst, i32imm:$src),
357 "sethi $src, $dst",
358 [(set IntRegs:$dst, SETHIimm:$src)]>;
359
360// Section B.10 - NOP Instruction, p. 105
361// (It's a special case of SETHI)
362let rd = 0, imm22 = 0 in
363 def NOP : F2_1<0b100, (ops), "nop", []>;
364
365// Section B.11 - Logical Instructions, p. 106
366def ANDrr : F3_1<2, 0b000001,
367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
368 "and $b, $c, $dst",
369 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
370def ANDri : F3_2<2, 0b000001,
371 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
372 "and $b, $c, $dst",
373 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
374def ANDNrr : F3_1<2, 0b000101,
375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
376 "andn $b, $c, $dst",
377 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
378def ANDNri : F3_2<2, 0b000101,
379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
380 "andn $b, $c, $dst", []>;
381def ORrr : F3_1<2, 0b000010,
382 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
383 "or $b, $c, $dst",
384 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
385def ORri : F3_2<2, 0b000010,
386 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
387 "or $b, $c, $dst",
388 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
389def ORNrr : F3_1<2, 0b000110,
390 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
391 "orn $b, $c, $dst",
392 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
393def ORNri : F3_2<2, 0b000110,
394 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
395 "orn $b, $c, $dst", []>;
396def XORrr : F3_1<2, 0b000011,
397 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
398 "xor $b, $c, $dst",
399 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
400def XORri : F3_2<2, 0b000011,
401 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
402 "xor $b, $c, $dst",
403 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
404def XNORrr : F3_1<2, 0b000111,
405 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
406 "xnor $b, $c, $dst",
407 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
408def XNORri : F3_2<2, 0b000111,
409 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
410 "xnor $b, $c, $dst", []>;
411
412// Section B.12 - Shift Instructions, p. 107
413def SLLrr : F3_1<2, 0b100101,
414 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
415 "sll $b, $c, $dst",
416 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
417def SLLri : F3_2<2, 0b100101,
418 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
419 "sll $b, $c, $dst",
420 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
421def SRLrr : F3_1<2, 0b100110,
422 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
423 "srl $b, $c, $dst",
424 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
425def SRLri : F3_2<2, 0b100110,
426 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
427 "srl $b, $c, $dst",
428 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
429def SRArr : F3_1<2, 0b100111,
430 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
431 "sra $b, $c, $dst",
432 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
433def SRAri : F3_2<2, 0b100111,
434 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
435 "sra $b, $c, $dst",
436 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
437
438// Section B.13 - Add Instructions, p. 108
439def ADDrr : F3_1<2, 0b000000,
440 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
441 "add $b, $c, $dst",
442 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
443def ADDri : F3_2<2, 0b000000,
444 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
445 "add $b, $c, $dst",
446 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]447
448// "LEA" forms of add (patterns to make tblgen happy)
449def LEA_ADDri : F3_2<2, 0b000000,
450 (ops IntRegs:$dst, MEMri:$addr),
451 "add ${addr:arith}, $dst",
452 [(set IntRegs:$dst, ADDRri:$addr)]>;
453
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]454def ADDCCrr : F3_1<2, 0b010000,
455 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]456 "addcc $b, $c, $dst",
457 [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]458def ADDCCri : F3_2<2, 0b010000,
459 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]460 "addcc $b, $c, $dst",
461 [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]462def ADDXrr : F3_1<2, 0b001000,
463 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]464 "addx $b, $c, $dst",
465 [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]466def ADDXri : F3_2<2, 0b001000,
467 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]468 "addx $b, $c, $dst",
469 [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]470
471// Section B.15 - Subtract Instructions, p. 110
472def SUBrr : F3_1<2, 0b000100,
473 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
474 "sub $b, $c, $dst",
475 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
476def SUBri : F3_2<2, 0b000100,
477 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
478 "sub $b, $c, $dst",
479 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
480def SUBXrr : F3_1<2, 0b001100,
481 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]482 "subx $b, $c, $dst",
483 [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]484def SUBXri : F3_2<2, 0b001100,
485 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]486 "subx $b, $c, $dst",
487 [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]488def SUBCCrr : F3_1<2, 0b010100,
489 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
490 "subcc $b, $c, $dst",
491 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
492def SUBCCri : F3_2<2, 0b010100,
493 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
494 "subcc $b, $c, $dst",
495 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
496def SUBXCCrr: F3_1<2, 0b011100,
497 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
498 "subxcc $b, $c, $dst", []>;
499
500// Section B.18 - Multiply Instructions, p. 113
501def UMULrr : F3_1<2, 0b001010,
502 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
503 "umul $b, $c, $dst", []>;
504def UMULri : F3_2<2, 0b001010,
505 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
506 "umul $b, $c, $dst", []>;
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]507
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]508def SMULrr : F3_1<2, 0b001011,
509 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
510 "smul $b, $c, $dst",
511 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
512def SMULri : F3_2<2, 0b001011,
513 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
514 "smul $b, $c, $dst",
515 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
516
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]517/*
518//===-------------------------
519// Sparc Example
520defm intinst<id OPC1, id OPC2, bits Opc, string asmstr, SDNode code> {
521 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
522 [(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>;
523 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
524 [(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>;
525}
526defm intinst_np<id OPC1, id OPC2, bits Opc, string asmstr> {
527 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
528 []>;
529 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
530 []>;
531}
532
533def intinstnp< ADDXrr, ADDXri, 0b001000, "addx $b, $c, $dst">;
534def intinst < SUBrr, SUBri, 0b000100, "sub $b, $c, $dst", sub>;
535def intinstnp< SUBXrr, SUBXri, 0b001100, "subx $b, $c, $dst">;
536def intinst <SUBCCrr, SUBCCri, 0b010100, "subcc $b, $c, $dst", SPcmpicc>;
537def intinst < SMULrr, SMULri, 0b001011, "smul $b, $c, $dst", mul>;
538
539//===-------------------------
540// X86 Example
541defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> {
542 def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
543 asmstr+" {$src2, $dst|$dst, $src2}",
544 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB;
545 def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
546 asmstr+" {$src2, $dst|$dst, $src2}",
547 [(set R32:$dst, (X86cmov R32:$src1,
548 (loadi32 addr:$src2), cond))]>, TB;
549}
550
551def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>;
552def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>;
553
554//===-------------------------
555// PPC Example
556
557def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr,
558 SDNode code> {
559 def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB),
560 asmstr+" $frD, $frB", FPGeneral,
561 [(set F4RC:$frD, (code F4RC:$frB))]>;
562 def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB),
563 asmstr+" $frD, $frB", FPGeneral,
564 [(set F8RC:$frD, (code F8RC:$frB))]>;
565}
566
567def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>;
568def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>;
569def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>;
570*/
571
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]572// Section B.19 - Divide Instructions, p. 115
573def UDIVrr : F3_1<2, 0b001110,
574 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
575 "udiv $b, $c, $dst", []>;
576def UDIVri : F3_2<2, 0b001110,
577 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
578 "udiv $b, $c, $dst", []>;
579def SDIVrr : F3_1<2, 0b001111,
580 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
581 "sdiv $b, $c, $dst", []>;
582def SDIVri : F3_2<2, 0b001111,
583 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
584 "sdiv $b, $c, $dst", []>;
585
586// Section B.20 - SAVE and RESTORE, p. 117
587def SAVErr : F3_1<2, 0b111100,
588 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
589 "save $b, $c, $dst", []>;
590def SAVEri : F3_2<2, 0b111100,
591 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
592 "save $b, $c, $dst", []>;
593def RESTORErr : F3_1<2, 0b111101,
594 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
595 "restore $b, $c, $dst", []>;
596def RESTOREri : F3_2<2, 0b111101,
597 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
598 "restore $b, $c, $dst", []>;
599
600// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
601
602// conditional branch class:
603class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
604 : F2_2<cc, 0b010, ops, asmstr, pattern> {
605 let isBranch = 1;
606 let isTerminator = 1;
607 let hasDelaySlot = 1;
608 let noResults = 1;
609}
610
611let isBarrier = 1 in
612 def BA : BranchSP<0b1000, (ops brtarget:$dst),
613 "ba $dst",
614 [(br bb:$dst)]>;
615
616// FIXME: the encoding for the JIT should look at the condition field.
617def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
618 "b$cc $dst",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]619 [(SPbricc bb:$dst, imm:$cc)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]620
621
622// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
623
624// floating-point conditional branch class:
625class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
626 : F2_2<cc, 0b110, ops, asmstr, pattern> {
627 let isBranch = 1;
628 let isTerminator = 1;
629 let hasDelaySlot = 1;
630 let noResults = 1;
631}
632
633// FIXME: the encoding for the JIT should look at the condition field.
634def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
635 "fb$cc $dst",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]636 [(SPbrfcc bb:$dst, imm:$cc)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]637
638
639// Section B.24 - Call and Link Instruction, p. 125
640// This is the only Format 1 instruction
641let Uses = [O0, O1, O2, O3, O4, O5],
642 hasDelaySlot = 1, isCall = 1, noResults = 1,
643 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
644 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
645 def CALL : InstSP<(ops calltarget:$dst),
646 "call $dst", []> {
647 bits<30> disp;
648 let op = 1;
649 let Inst{29-0} = disp;
650 }
651
652 // indirect calls
653 def JMPLrr : F3_1<2, 0b111000,
654 (ops MEMrr:$ptr),
655 "call $ptr",
656 [(call ADDRrr:$ptr)]>;
657 def JMPLri : F3_2<2, 0b111000,
658 (ops MEMri:$ptr),
659 "call $ptr",
660 [(call ADDRri:$ptr)]>;
661}
662
663// Section B.28 - Read State Register Instructions
664def RDY : F3_1<2, 0b101000,
665 (ops IntRegs:$dst),
666 "rd %y, $dst", []>;
667
668// Section B.29 - Write State Register Instructions
669def WRYrr : F3_1<2, 0b110000,
670 (ops IntRegs:$b, IntRegs:$c),
671 "wr $b, $c, %y", []>;
672def WRYri : F3_2<2, 0b110000,
673 (ops IntRegs:$b, i32imm:$c),
674 "wr $b, $c, %y", []>;
675
676// Convert Integer to Floating-point Instructions, p. 141
677def FITOS : F3_3<2, 0b110100, 0b011000100,
678 (ops FPRegs:$dst, FPRegs:$src),
679 "fitos $src, $dst",
680 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
681def FITOD : F3_3<2, 0b110100, 0b011001000,
682 (ops DFPRegs:$dst, FPRegs:$src),
683 "fitod $src, $dst",
684 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
685
686// Convert Floating-point to Integer Instructions, p. 142
687def FSTOI : F3_3<2, 0b110100, 0b011010001,
688 (ops FPRegs:$dst, FPRegs:$src),
689 "fstoi $src, $dst",
690 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
691def FDTOI : F3_3<2, 0b110100, 0b011010010,
692 (ops FPRegs:$dst, DFPRegs:$src),
693 "fdtoi $src, $dst",
694 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
695
696// Convert between Floating-point Formats Instructions, p. 143
697def FSTOD : F3_3<2, 0b110100, 0b011001001,
698 (ops DFPRegs:$dst, FPRegs:$src),
699 "fstod $src, $dst",
700 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
701def FDTOS : F3_3<2, 0b110100, 0b011000110,
702 (ops FPRegs:$dst, DFPRegs:$src),
703 "fdtos $src, $dst",
704 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
705
706// Floating-point Move Instructions, p. 144
707def FMOVS : F3_3<2, 0b110100, 0b000000001,
708 (ops FPRegs:$dst, FPRegs:$src),
709 "fmovs $src, $dst", []>;
710def FNEGS : F3_3<2, 0b110100, 0b000000101,
711 (ops FPRegs:$dst, FPRegs:$src),
712 "fnegs $src, $dst",
713 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
714def FABSS : F3_3<2, 0b110100, 0b000001001,
715 (ops FPRegs:$dst, FPRegs:$src),
716 "fabss $src, $dst",
717 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
718
719
720// Floating-point Square Root Instructions, p.145
721def FSQRTS : F3_3<2, 0b110100, 0b000101001,
722 (ops FPRegs:$dst, FPRegs:$src),
723 "fsqrts $src, $dst",
724 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
725def FSQRTD : F3_3<2, 0b110100, 0b000101010,
726 (ops DFPRegs:$dst, DFPRegs:$src),
727 "fsqrtd $src, $dst",
728 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
729
730
731
732// Floating-point Add and Subtract Instructions, p. 146
733def FADDS : F3_3<2, 0b110100, 0b001000001,
734 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
735 "fadds $src1, $src2, $dst",
736 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
737def FADDD : F3_3<2, 0b110100, 0b001000010,
738 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
739 "faddd $src1, $src2, $dst",
740 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
741def FSUBS : F3_3<2, 0b110100, 0b001000101,
742 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
743 "fsubs $src1, $src2, $dst",
744 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
745def FSUBD : F3_3<2, 0b110100, 0b001000110,
746 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
747 "fsubd $src1, $src2, $dst",
748 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
749
750// Floating-point Multiply and Divide Instructions, p. 147
751def FMULS : F3_3<2, 0b110100, 0b001001001,
752 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
753 "fmuls $src1, $src2, $dst",
754 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
755def FMULD : F3_3<2, 0b110100, 0b001001010,
756 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
757 "fmuld $src1, $src2, $dst",
758 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
759def FSMULD : F3_3<2, 0b110100, 0b001101001,
760 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
761 "fsmuld $src1, $src2, $dst",
762 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
763 (fextend FPRegs:$src2)))]>;
764def FDIVS : F3_3<2, 0b110100, 0b001001101,
765 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
766 "fdivs $src1, $src2, $dst",
767 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
768def FDIVD : F3_3<2, 0b110100, 0b001001110,
769 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
770 "fdivd $src1, $src2, $dst",
771 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
772
773// Floating-point Compare Instructions, p. 148
774// Note: the 2nd template arg is different for these guys.
775// Note 2: the result of a FCMP is not available until the 2nd cycle
776// after the instr is retired, but there is no interlock. This behavior
777// is modelled with a forced noop after the instruction.
778def FCMPS : F3_3<2, 0b110101, 0b001010001,
779 (ops FPRegs:$src1, FPRegs:$src2),
780 "fcmps $src1, $src2\n\tnop",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]781 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]782def FCMPD : F3_3<2, 0b110101, 0b001010010,
783 (ops DFPRegs:$src1, DFPRegs:$src2),
784 "fcmpd $src1, $src2\n\tnop",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]785 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]786
787
788//===----------------------------------------------------------------------===//
789// V9 Instructions
790//===----------------------------------------------------------------------===//
791
792// V9 Conditional Moves.
793let Predicates = [HasV9], isTwoAddress = 1 in {
794 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
795 // FIXME: Add instruction encodings for the JIT some day.
796 def MOVICCrr
797 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
798 "mov$cc %icc, $F, $dst",
799 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]800 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]801 def MOVICCri
802 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
803 "mov$cc %icc, $F, $dst",
804 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]805 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]806
807 def MOVFCCrr
808 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
809 "mov$cc %fcc0, $F, $dst",
810 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]811 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]812 def MOVFCCri
813 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
814 "mov$cc %fcc0, $F, $dst",
815 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]816 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]817
818 def FMOVS_ICC
819 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
820 "fmovs$cc %icc, $F, $dst",
821 [(set FPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]822 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]823 def FMOVD_ICC
824 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
825 "fmovd$cc %icc, $F, $dst",
826 [(set DFPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]827 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]828 def FMOVS_FCC
829 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
830 "fmovs$cc %fcc0, $F, $dst",
831 [(set FPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]832 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]833 def FMOVD_FCC
834 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
835 "fmovd$cc %fcc0, $F, $dst",
836 [(set DFPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]837 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]838
839}
840
841// Floating-Point Move Instructions, p. 164 of the V9 manual.
842let Predicates = [HasV9] in {
843 def FMOVD : F3_3<2, 0b110100, 0b000000010,
844 (ops DFPRegs:$dst, DFPRegs:$src),
845 "fmovd $src, $dst", []>;
846 def FNEGD : F3_3<2, 0b110100, 0b000000110,
847 (ops DFPRegs:$dst, DFPRegs:$src),
848 "fnegd $src, $dst",
849 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
850 def FABSD : F3_3<2, 0b110100, 0b000001010,
851 (ops DFPRegs:$dst, DFPRegs:$src),
852 "fabsd $src, $dst",
853 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
854}
855
856// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
857// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
858def POPCrr : F3_1<2, 0b101110,
859 (ops IntRegs:$dst, IntRegs:$src),
860 "popc $src, $dst", []>, Requires<[HasV9]>;
861def : Pat<(ctpop IntRegs:$src),
862 (POPCrr (SLLri IntRegs:$src, 0))>;
863
864//===----------------------------------------------------------------------===//
865// Non-Instruction Patterns
866//===----------------------------------------------------------------------===//
867
868// Small immediates.
869def : Pat<(i32 simm13:$val),
870 (ORri G0, imm:$val)>;
871// Arbitrary immediates.
872def : Pat<(i32 imm:$val),
873 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
874
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame^]875// subc
876def : Pat<(subc IntRegs:$b, IntRegs:$c),
877 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
878def : Pat<(subc IntRegs:$b, simm13:$val),
879 (SUBCCri IntRegs:$b, imm:$val)>;
880
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]881// Global addresses, constant pool entries
882def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
883def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
884def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
885def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
886
887// Add reg, lo. This is used when taking the addr of a global/constpool entry.
888def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
889 (ADDri IntRegs:$r, tglobaladdr:$in)>;
890def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
891 (ADDri IntRegs:$r, tconstpool:$in)>;
892
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]893// Calls:
894def : Pat<(call tglobaladdr:$dst),
895 (CALL tglobaladdr:$dst)>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]896def : Pat<(call texternalsym:$dst),
897 (CALL texternalsym:$dst)>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]898
899def : Pat<(ret), (RETL)>;
900
901// Map integer extload's to zextloads.
902def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
903def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
904def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
905def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
906def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
907def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
908
909// zextload bool -> zextload byte
910def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
911def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
912
913// truncstore bool -> truncstore byte.
914def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
915 (STBrr ADDRrr:$addr, IntRegs:$src)>;
916def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
917 (STBri ADDRri:$addr, IntRegs:$src)>;