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gerrit-public.fairphone.software / toolchain / llvm-project / 5a69a0011b6aaaf14b0571398956368f4f43bbfb / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: 4d39cdfd7c342a74ed6e19f1d7b045b16c81fc35 [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
83 int Lat, list<int> Res = [1], int UOps = 1> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]84 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]85 def : WriteRes<SchedRW, ExePorts> {
86 let Latency = Lat;
87 let ResourceCycles = Res;
88 let NumMicroOps = UOps;
89 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]90
91 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
92 // latency.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]93 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
94 let Latency = !add(Lat, 5);
95 let ResourceCycles = !listconcat([1], Res);
96 let NumMicroOps = UOps;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]97 }
98}
99
100// A folded store needs a cycle on port 4 for the store data, but it does not
101// need an extra port 2/3 cycle to recompute the address.
102def : WriteRes<WriteRMW, [BWPort4]>;
103
104// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]105defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
106defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
107defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]108def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]109
110def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
111
112// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]113defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]114
115// Loads, stores, and moves, not folded with other operations.
116def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
117def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
118def : WriteRes<WriteMove, [BWPort0156]>;
119
120// Idioms that clear a register, like xorps %xmm0, %xmm0.
121// These can often bypass execution ports completely.
122def : WriteRes<WriteZero, []>;
123
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]124// Treat misc copies as a move.
125def : InstRW<[WriteMove], (instrs COPY)>;
126
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]127// Branches don't produce values, so they have no latency, but they still
128// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]129defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]130
131// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]132def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
133def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
134def : WriteRes<WriteFMove, [BWPort5]>;
135
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]136defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
137defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
138defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
139defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
140defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
141defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
142defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
143defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
144defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
145defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]146
147// FMA Scheduling helper class.
148// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
149
150// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]151def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
152def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
153def : WriteRes<WriteVecMove, [BWPort015]>;
154
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]155defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
156defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
157defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
158defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
159defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
160defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
161defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]162
163// Vector bitwise operations.
164// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]165defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]166
167// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]168defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
169defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
170defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]171
172// Strings instructions.
173// Packed Compare Implicit Length Strings, Return Mask
174// String instructions.
175def : WriteRes<WritePCmpIStrM, [BWPort0]> {
176 let Latency = 10;
177 let ResourceCycles = [3];
178}
179def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
180 let Latency = 10;
181 let ResourceCycles = [3, 1];
182}
183// Packed Compare Explicit Length Strings, Return Mask
184def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort16, BWPort5]> {
185 let Latency = 10;
186 let ResourceCycles = [3, 2, 4];
187}
188def : WriteRes<WritePCmpEStrMLd, [BWPort05, BWPort16, BWPort23]> {
189 let Latency = 10;
190 let ResourceCycles = [6, 2, 1];
191}
192 // Packed Compare Implicit Length Strings, Return Index
193def : WriteRes<WritePCmpIStrI, [BWPort0]> {
194 let Latency = 11;
195 let ResourceCycles = [3];
196}
197def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
198 let Latency = 11;
199 let ResourceCycles = [3, 1];
200}
201// Packed Compare Explicit Length Strings, Return Index
202def : WriteRes<WritePCmpEStrI, [BWPort05, BWPort16]> {
203 let Latency = 11;
204 let ResourceCycles = [6, 2];
205}
206def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort16, BWPort5, BWPort23]> {
207 let Latency = 11;
208 let ResourceCycles = [3, 2, 2, 1];
209}
210
211// AES instructions.
212def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
213 let Latency = 7;
214 let ResourceCycles = [1];
215}
216def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
217 let Latency = 7;
218 let ResourceCycles = [1, 1];
219}
220def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
221 let Latency = 14;
222 let ResourceCycles = [2];
223}
224def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
225 let Latency = 14;
226 let ResourceCycles = [2, 1];
227}
228def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5]> { // Key Generation.
229 let Latency = 10;
230 let ResourceCycles = [2, 8];
231}
232def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23]> {
233 let Latency = 10;
234 let ResourceCycles = [2, 7, 1];
235}
236
237// Carry-less multiplication instructions.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]238defm : BWWriteResPair<WriteCLMul, [BWPort0, BWPort5], 7, [2, 1]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]239
240// Catch-all for expensive system instructions.
241def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
242
243// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]244defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
245defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
246defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]247
248// Old microcoded instructions that nobody use.
249def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
250
251// Fence instructions.
252def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
253
254// Nop, not very useful expect it provides a model for nops!
255def : WriteRes<WriteNop, []>;
256
257////////////////////////////////////////////////////////////////////////////////
258// Horizontal add/sub instructions.
259////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]260
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]261defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
262defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]263
264// Remaining instrs.
265
266def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
267 let Latency = 1;
268 let NumMicroOps = 1;
269 let ResourceCycles = [1];
270}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]271def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
272 "MMX_MOVD64grr",
273 "MMX_PMOVMSKBrr",
274 "MMX_PSLLDri",
275 "MMX_PSLLDrr",
276 "MMX_PSLLQri",
277 "MMX_PSLLQrr",
278 "MMX_PSLLWri",
279 "MMX_PSLLWrr",
280 "MMX_PSRADri",
281 "MMX_PSRADrr",
282 "MMX_PSRAWri",
283 "MMX_PSRAWrr",
284 "MMX_PSRLDri",
285 "MMX_PSRLDrr",
286 "MMX_PSRLQri",
287 "MMX_PSRLQrr",
288 "MMX_PSRLWri",
289 "MMX_PSRLWrr",
290 "MOVPDI2DIrr",
291 "MOVPQIto64rr",
292 "PSLLDri",
293 "PSLLQri",
294 "PSLLWri",
295 "PSRADri",
296 "PSRAWri",
297 "PSRLDri",
298 "PSRLQri",
299 "PSRLWri",
300 "VMOVPDI2DIrr",
301 "VMOVPQIto64rr",
302 "VPSLLDYri",
303 "VPSLLDri",
304 "VPSLLQYri",
305 "VPSLLQri",
306 "VPSLLVQYrr",
307 "VPSLLVQrr",
308 "VPSLLWYri",
309 "VPSLLWri",
310 "VPSRADYri",
311 "VPSRADri",
312 "VPSRAWYri",
313 "VPSRAWri",
314 "VPSRLDYri",
315 "VPSRLDri",
316 "VPSRLQYri",
317 "VPSRLQri",
318 "VPSRLVQYrr",
319 "VPSRLVQrr",
320 "VPSRLWYri",
321 "VPSRLWri",
322 "VTESTPDYrr",
323 "VTESTPDrr",
324 "VTESTPSYrr",
325 "VTESTPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]326
327def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
328 let Latency = 1;
329 let NumMicroOps = 1;
330 let ResourceCycles = [1];
331}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]332def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
333 "COM_FST0r",
334 "UCOM_FPr",
335 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]336
337def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
338 let Latency = 1;
339 let NumMicroOps = 1;
340 let ResourceCycles = [1];
341}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]342def: InstRW<[BWWriteResGroup3], (instregex "ANDNPDrr",
343 "ANDNPSrr",
344 "ANDPDrr",
345 "ANDPSrr",
346 "INSERTPSrr",
347 "MMX_MOVD64rr",
348 "MMX_MOVD64to64rr",
349 "MMX_MOVQ2DQrr",
350 "MMX_PALIGNRrri",
351 "MMX_PSHUFBrr",
352 "MMX_PSHUFWri",
353 "MMX_PUNPCKHBWirr",
354 "MMX_PUNPCKHDQirr",
355 "MMX_PUNPCKHWDirr",
356 "MMX_PUNPCKLBWirr",
357 "MMX_PUNPCKLDQirr",
358 "MMX_PUNPCKLWDirr",
359 "MOV64toPQIrr",
360 "MOVAPDrr",
361 "MOVAPSrr",
362 "MOVDDUPrr",
363 "MOVDI2PDIrr",
364 "MOVHLPSrr",
365 "MOVLHPSrr",
366 "MOVSDrr",
367 "MOVSHDUPrr",
368 "MOVSLDUPrr",
369 "MOVSSrr",
370 "MOVUPDrr",
371 "MOVUPSrr",
372 "ORPDrr",
373 "ORPSrr",
374 "PACKSSDWrr",
375 "PACKSSWBrr",
376 "PACKUSDWrr",
377 "PACKUSWBrr",
378 "PALIGNRrri",
379 "PBLENDWrri",
380 "PMOVSXBDrr",
381 "PMOVSXBQrr",
382 "PMOVSXBWrr",
383 "PMOVSXDQrr",
384 "PMOVSXWDrr",
385 "PMOVSXWQrr",
386 "PMOVZXBDrr",
387 "PMOVZXBQrr",
388 "PMOVZXBWrr",
389 "PMOVZXDQrr",
390 "PMOVZXWDrr",
391 "PMOVZXWQrr",
392 "PSHUFBrr",
393 "PSHUFDri",
394 "PSHUFHWri",
395 "PSHUFLWri",
396 "PSLLDQri",
397 "PSRLDQri",
398 "PUNPCKHBWrr",
399 "PUNPCKHDQrr",
400 "PUNPCKHQDQrr",
401 "PUNPCKHWDrr",
402 "PUNPCKLBWrr",
403 "PUNPCKLDQrr",
404 "PUNPCKLQDQrr",
405 "PUNPCKLWDrr",
406 "SHUFPDrri",
407 "SHUFPSrri",
408 "UNPCKHPDrr",
409 "UNPCKHPSrr",
410 "UNPCKLPDrr",
411 "UNPCKLPSrr",
412 "VANDNPDYrr",
413 "VANDNPDrr",
414 "VANDNPSYrr",
415 "VANDNPSrr",
416 "VANDPDYrr",
417 "VANDPDrr",
418 "VANDPSYrr",
419 "VANDPSrr",
420 "VBROADCASTSSrr",
421 "VINSERTPSrr",
422 "VMOV64toPQIrr",
423 "VMOVAPDYrr",
424 "VMOVAPDrr",
425 "VMOVAPSYrr",
426 "VMOVAPSrr",
427 "VMOVDDUPYrr",
428 "VMOVDDUPrr",
429 "VMOVDI2PDIrr",
430 "VMOVHLPSrr",
431 "VMOVLHPSrr",
432 "VMOVSDrr",
433 "VMOVSHDUPYrr",
434 "VMOVSHDUPrr",
435 "VMOVSLDUPYrr",
436 "VMOVSLDUPrr",
437 "VMOVSSrr",
438 "VMOVUPDYrr",
439 "VMOVUPDrr",
440 "VMOVUPSYrr",
441 "VMOVUPSrr",
442 "VORPDYrr",
443 "VORPDrr",
444 "VORPSYrr",
445 "VORPSrr",
446 "VPACKSSDWYrr",
447 "VPACKSSDWrr",
448 "VPACKSSWBYrr",
449 "VPACKSSWBrr",
450 "VPACKUSDWYrr",
451 "VPACKUSDWrr",
452 "VPACKUSWBYrr",
453 "VPACKUSWBrr",
454 "VPALIGNRYrri",
455 "VPALIGNRrri",
456 "VPBLENDWYrri",
457 "VPBLENDWrri",
458 "VPBROADCASTDrr",
459 "VPBROADCASTQrr",
460 "VPERMILPDYri",
461 "VPERMILPDYrr",
462 "VPERMILPDri",
463 "VPERMILPDrr",
464 "VPERMILPSYri",
465 "VPERMILPSYrr",
466 "VPERMILPSri",
467 "VPERMILPSrr",
468 "VPMOVSXBDrr",
469 "VPMOVSXBQrr",
470 "VPMOVSXBWrr",
471 "VPMOVSXDQrr",
472 "VPMOVSXWDrr",
473 "VPMOVSXWQrr",
474 "VPMOVZXBDrr",
475 "VPMOVZXBQrr",
476 "VPMOVZXBWrr",
477 "VPMOVZXDQrr",
478 "VPMOVZXWDrr",
479 "VPMOVZXWQrr",
480 "VPSHUFBYrr",
481 "VPSHUFBrr",
482 "VPSHUFDYri",
483 "VPSHUFDri",
484 "VPSHUFHWYri",
485 "VPSHUFHWri",
486 "VPSHUFLWYri",
487 "VPSHUFLWri",
488 "VPSLLDQYri",
489 "VPSLLDQri",
490 "VPSRLDQYri",
491 "VPSRLDQri",
492 "VPUNPCKHBWYrr",
493 "VPUNPCKHBWrr",
494 "VPUNPCKHDQYrr",
495 "VPUNPCKHDQrr",
496 "VPUNPCKHQDQYrr",
497 "VPUNPCKHQDQrr",
498 "VPUNPCKHWDYrr",
499 "VPUNPCKHWDrr",
500 "VPUNPCKLBWYrr",
501 "VPUNPCKLBWrr",
502 "VPUNPCKLDQYrr",
503 "VPUNPCKLDQrr",
504 "VPUNPCKLQDQYrr",
505 "VPUNPCKLQDQrr",
506 "VPUNPCKLWDYrr",
507 "VPUNPCKLWDrr",
508 "VSHUFPDYrri",
509 "VSHUFPDrri",
510 "VSHUFPSYrri",
511 "VSHUFPSrri",
512 "VUNPCKHPDYrr",
513 "VUNPCKHPDrr",
514 "VUNPCKHPSYrr",
515 "VUNPCKHPSrr",
516 "VUNPCKLPDYrr",
517 "VUNPCKLPDrr",
518 "VUNPCKLPSYrr",
519 "VUNPCKLPSrr",
520 "VXORPDYrr",
521 "VXORPDrr",
522 "VXORPSYrr",
523 "VXORPSrr",
524 "XORPDrr",
525 "XORPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]526
527def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
528 let Latency = 1;
529 let NumMicroOps = 1;
530 let ResourceCycles = [1];
531}
532def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
533
534def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
535 let Latency = 1;
536 let NumMicroOps = 1;
537 let ResourceCycles = [1];
538}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]539def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
540 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]541
542def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
543 let Latency = 1;
544 let NumMicroOps = 1;
545 let ResourceCycles = [1];
546}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]547def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
548 "ADC(16|32|64)i",
549 "ADC(8|16|32|64)rr",
550 "ADCX(32|64)rr",
551 "ADOX(32|64)rr",
552 "BT(16|32|64)ri8",
553 "BT(16|32|64)rr",
554 "BTC(16|32|64)ri8",
555 "BTC(16|32|64)rr",
556 "BTR(16|32|64)ri8",
557 "BTR(16|32|64)rr",
558 "BTS(16|32|64)ri8",
559 "BTS(16|32|64)rr",
560 "CDQ",
561 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
562 "CQO",
563 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
564 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
565 "JMP_1",
566 "JMP_4",
567 "RORX(32|64)ri",
568 "SAR(8|16|32|64)r1",
569 "SAR(8|16|32|64)ri",
570 "SARX(32|64)rr",
571 "SBB(16|32|64)ri",
572 "SBB(16|32|64)i",
573 "SBB(8|16|32|64)rr",
574 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
575 "SHL(8|16|32|64)r1",
576 "SHL(8|16|32|64)ri",
577 "SHLX(32|64)rr",
578 "SHR(8|16|32|64)r1",
579 "SHR(8|16|32|64)ri",
580 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]581
582def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
583 let Latency = 1;
584 let NumMicroOps = 1;
585 let ResourceCycles = [1];
586}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]587def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
588 "BLSI(32|64)rr",
589 "BLSMSK(32|64)rr",
590 "BLSR(32|64)rr",
591 "BZHI(32|64)rr",
592 "LEA(16|32|64)(_32)?r",
593 "MMX_PABSBrr",
594 "MMX_PABSDrr",
595 "MMX_PABSWrr",
596 "MMX_PADDBirr",
597 "MMX_PADDDirr",
598 "MMX_PADDQirr",
599 "MMX_PADDSBirr",
600 "MMX_PADDSWirr",
601 "MMX_PADDUSBirr",
602 "MMX_PADDUSWirr",
603 "MMX_PADDWirr",
604 "MMX_PAVGBirr",
605 "MMX_PAVGWirr",
606 "MMX_PCMPEQBirr",
607 "MMX_PCMPEQDirr",
608 "MMX_PCMPEQWirr",
609 "MMX_PCMPGTBirr",
610 "MMX_PCMPGTDirr",
611 "MMX_PCMPGTWirr",
612 "MMX_PMAXSWirr",
613 "MMX_PMAXUBirr",
614 "MMX_PMINSWirr",
615 "MMX_PMINUBirr",
616 "MMX_PSIGNBrr",
617 "MMX_PSIGNDrr",
618 "MMX_PSIGNWrr",
619 "MMX_PSUBBirr",
620 "MMX_PSUBDirr",
621 "MMX_PSUBQirr",
622 "MMX_PSUBSBirr",
623 "MMX_PSUBSWirr",
624 "MMX_PSUBUSBirr",
625 "MMX_PSUBUSWirr",
626 "MMX_PSUBWirr",
627 "PABSBrr",
628 "PABSDrr",
629 "PABSWrr",
630 "PADDBrr",
631 "PADDDrr",
632 "PADDQrr",
633 "PADDSBrr",
634 "PADDSWrr",
635 "PADDUSBrr",
636 "PADDUSWrr",
637 "PADDWrr",
638 "PAVGBrr",
639 "PAVGWrr",
640 "PCMPEQBrr",
641 "PCMPEQDrr",
642 "PCMPEQQrr",
643 "PCMPEQWrr",
644 "PCMPGTBrr",
645 "PCMPGTDrr",
646 "PCMPGTWrr",
647 "PMAXSBrr",
648 "PMAXSDrr",
649 "PMAXSWrr",
650 "PMAXUBrr",
651 "PMAXUDrr",
652 "PMAXUWrr",
653 "PMINSBrr",
654 "PMINSDrr",
655 "PMINSWrr",
656 "PMINUBrr",
657 "PMINUDrr",
658 "PMINUWrr",
659 "PSIGNBrr",
660 "PSIGNDrr",
661 "PSIGNWrr",
662 "PSUBBrr",
663 "PSUBDrr",
664 "PSUBQrr",
665 "PSUBSBrr",
666 "PSUBSWrr",
667 "PSUBUSBrr",
668 "PSUBUSWrr",
669 "PSUBWrr",
670 "VPABSBYrr",
671 "VPABSBrr",
672 "VPABSDYrr",
673 "VPABSDrr",
674 "VPABSWYrr",
675 "VPABSWrr",
676 "VPADDBYrr",
677 "VPADDBrr",
678 "VPADDDYrr",
679 "VPADDDrr",
680 "VPADDQYrr",
681 "VPADDQrr",
682 "VPADDSBYrr",
683 "VPADDSBrr",
684 "VPADDSWYrr",
685 "VPADDSWrr",
686 "VPADDUSBYrr",
687 "VPADDUSBrr",
688 "VPADDUSWYrr",
689 "VPADDUSWrr",
690 "VPADDWYrr",
691 "VPADDWrr",
692 "VPAVGBYrr",
693 "VPAVGBrr",
694 "VPAVGWYrr",
695 "VPAVGWrr",
696 "VPCMPEQBYrr",
697 "VPCMPEQBrr",
698 "VPCMPEQDYrr",
699 "VPCMPEQDrr",
700 "VPCMPEQQYrr",
701 "VPCMPEQQrr",
702 "VPCMPEQWYrr",
703 "VPCMPEQWrr",
704 "VPCMPGTBYrr",
705 "VPCMPGTBrr",
706 "VPCMPGTDYrr",
707 "VPCMPGTDrr",
708 "VPCMPGTWYrr",
709 "VPCMPGTWrr",
710 "VPMAXSBYrr",
711 "VPMAXSBrr",
712 "VPMAXSDYrr",
713 "VPMAXSDrr",
714 "VPMAXSWYrr",
715 "VPMAXSWrr",
716 "VPMAXUBYrr",
717 "VPMAXUBrr",
718 "VPMAXUDYrr",
719 "VPMAXUDrr",
720 "VPMAXUWYrr",
721 "VPMAXUWrr",
722 "VPMINSBYrr",
723 "VPMINSBrr",
724 "VPMINSDYrr",
725 "VPMINSDrr",
726 "VPMINSWYrr",
727 "VPMINSWrr",
728 "VPMINUBYrr",
729 "VPMINUBrr",
730 "VPMINUDYrr",
731 "VPMINUDrr",
732 "VPMINUWYrr",
733 "VPMINUWrr",
734 "VPSIGNBYrr",
735 "VPSIGNBrr",
736 "VPSIGNDYrr",
737 "VPSIGNDrr",
738 "VPSIGNWYrr",
739 "VPSIGNWrr",
740 "VPSUBBYrr",
741 "VPSUBBrr",
742 "VPSUBDYrr",
743 "VPSUBDrr",
744 "VPSUBQYrr",
745 "VPSUBQrr",
746 "VPSUBSBYrr",
747 "VPSUBSBrr",
748 "VPSUBSWYrr",
749 "VPSUBSWrr",
750 "VPSUBUSBYrr",
751 "VPSUBUSBrr",
752 "VPSUBUSWYrr",
753 "VPSUBUSWrr",
754 "VPSUBWYrr",
755 "VPSUBWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]756
757def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
758 let Latency = 1;
759 let NumMicroOps = 1;
760 let ResourceCycles = [1];
761}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]762def: InstRW<[BWWriteResGroup8], (instregex "BLENDPDrri",
763 "BLENDPSrri",
764 "MMX_MOVQ64rr",
765 "MMX_PANDNirr",
766 "MMX_PANDirr",
767 "MMX_PORirr",
768 "MMX_PXORirr",
769 "MOVDQArr",
770 "MOVDQUrr",
771 "MOVPQI2QIrr",
772 "PANDNrr",
773 "PANDrr",
774 "PORrr",
775 "PXORrr",
776 "VBLENDPDYrri",
777 "VBLENDPDrri",
778 "VBLENDPSYrri",
779 "VBLENDPSrri",
780 "VMOVDQAYrr",
781 "VMOVDQArr",
782 "VMOVDQUYrr",
783 "VMOVDQUrr",
784 "VMOVPQI2QIrr",
785 "VMOVZPQILo2PQIrr",
786 "VPANDNYrr",
787 "VPANDNrr",
788 "VPANDYrr",
789 "VPANDrr",
790 "VPBLENDDYrri",
791 "VPBLENDDrri",
792 "VPORYrr",
793 "VPORrr",
794 "VPXORYrr",
795 "VPXORrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]796
797def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
798 let Latency = 1;
799 let NumMicroOps = 1;
800 let ResourceCycles = [1];
801}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]802def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]803def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
804 "ADD(8|16|32|64)rr",
805 "ADD(8|16|32|64)i",
806 "AND(8|16|32|64)ri",
807 "AND(8|16|32|64)rr",
808 "AND(8|16|32|64)i",
809 "CBW",
810 "CLC",
811 "CMC",
812 "CMP(8|16|32|64)ri",
813 "CMP(8|16|32|64)rr",
814 "CMP(8|16|32|64)i",
815 "DEC(8|16|32|64)r",
816 "INC(8|16|32|64)r",
817 "LAHF",
818 "MOV(8|16|32|64)rr",
819 "MOV(8|16|32|64)ri",
820 "MOVSX(16|32|64)rr16",
821 "MOVSX(16|32|64)rr32",
822 "MOVSX(16|32|64)rr8",
823 "MOVZX(16|32|64)rr16",
824 "MOVZX(16|32|64)rr8",
825 "NEG(8|16|32|64)r",
826 "NOOP",
827 "NOT(8|16|32|64)r",
828 "OR(8|16|32|64)ri",
829 "OR(8|16|32|64)rr",
830 "OR(8|16|32|64)i",
831 "SAHF",
832 "SGDT64m",
833 "SIDT64m",
834 "SLDT64m",
835 "SMSW16m",
836 "STC",
837 "STRm",
838 "SUB(8|16|32|64)ri",
839 "SUB(8|16|32|64)rr",
840 "SUB(8|16|32|64)i",
841 "SYSCALL",
842 "TEST(8|16|32|64)rr",
843 "TEST(8|16|32|64)i",
844 "TEST(8|16|32|64)ri",
845 "XCHG(16|32|64)rr",
846 "XOR(8|16|32|64)ri",
847 "XOR(8|16|32|64)rr",
848 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]849
850def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
851 let Latency = 1;
852 let NumMicroOps = 2;
853 let ResourceCycles = [1,1];
854}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]855def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
856 "MMX_MOVD64from64rm",
857 "MMX_MOVD64mr",
858 "MMX_MOVNTQmr",
859 "MMX_MOVQ64mr",
860 "MOV(16|32|64)mr",
861 "MOV8mi",
862 "MOV8mr",
863 "MOVAPDmr",
864 "MOVAPSmr",
865 "MOVDQAmr",
866 "MOVDQUmr",
867 "MOVHPDmr",
868 "MOVHPSmr",
869 "MOVLPDmr",
870 "MOVLPSmr",
871 "MOVNTDQmr",
872 "MOVNTI_64mr",
873 "MOVNTImr",
874 "MOVNTPDmr",
875 "MOVNTPSmr",
876 "MOVPDI2DImr",
877 "MOVPQI2QImr",
878 "MOVPQIto64mr",
879 "MOVSDmr",
880 "MOVSSmr",
881 "MOVUPDmr",
882 "MOVUPSmr",
883 "ST_FP32m",
884 "ST_FP64m",
885 "ST_FP80m",
886 "VEXTRACTF128mr",
887 "VEXTRACTI128mr",
888 "VMOVAPDYmr",
889 "VMOVAPDmr",
890 "VMOVAPSYmr",
891 "VMOVAPSmr",
892 "VMOVDQAYmr",
893 "VMOVDQAmr",
894 "VMOVDQUYmr",
895 "VMOVDQUmr",
896 "VMOVHPDmr",
897 "VMOVHPSmr",
898 "VMOVLPDmr",
899 "VMOVLPSmr",
900 "VMOVNTDQYmr",
901 "VMOVNTDQmr",
902 "VMOVNTPDYmr",
903 "VMOVNTPDmr",
904 "VMOVNTPSYmr",
905 "VMOVNTPSmr",
906 "VMOVPDI2DImr",
907 "VMOVPQI2QImr",
908 "VMOVPQIto64mr",
909 "VMOVSDmr",
910 "VMOVSSmr",
911 "VMOVUPDYmr",
912 "VMOVUPDmr",
913 "VMOVUPSYmr",
914 "VMOVUPSmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]915
916def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
917 let Latency = 2;
918 let NumMicroOps = 2;
919 let ResourceCycles = [2];
920}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]921def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
922 "BLENDVPSrr0",
923 "MMX_PINSRWrr",
924 "PBLENDVBrr0",
925 "PINSRBrr",
926 "PINSRDrr",
927 "PINSRQrr",
928 "PINSRWrr",
929 "VBLENDVPDYrr",
930 "VBLENDVPDrr",
931 "VBLENDVPSYrr",
932 "VBLENDVPSrr",
933 "VPBLENDVBYrr",
934 "VPBLENDVBrr",
935 "VPINSRBrr",
936 "VPINSRDrr",
937 "VPINSRQrr",
938 "VPINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]939
940def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
941 let Latency = 2;
942 let NumMicroOps = 2;
943 let ResourceCycles = [2];
944}
945def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
946
947def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
948 let Latency = 2;
949 let NumMicroOps = 2;
950 let ResourceCycles = [2];
951}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]952def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
953 "ROL(8|16|32|64)ri",
954 "ROR(8|16|32|64)r1",
955 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]956
957def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
958 let Latency = 2;
959 let NumMicroOps = 2;
960 let ResourceCycles = [2];
961}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]962def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
963 "MFENCE",
964 "WAIT",
965 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]966
967def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
968 let Latency = 2;
969 let NumMicroOps = 2;
970 let ResourceCycles = [1,1];
971}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]972def: InstRW<[BWWriteResGroup15], (instregex "CVTPS2PDrr",
973 "CVTSS2SDrr",
974 "EXTRACTPSrr",
975 "MMX_PEXTRWrr",
976 "PEXTRBrr",
977 "PEXTRDrr",
978 "PEXTRQrr",
979 "PEXTRWrr",
980 "PSLLDrr",
981 "PSLLQrr",
982 "PSLLWrr",
983 "PSRADrr",
984 "PSRAWrr",
985 "PSRLDrr",
986 "PSRLQrr",
987 "PSRLWrr",
988 "PTESTrr",
989 "VCVTPH2PSYrr",
990 "VCVTPH2PSrr",
991 "VCVTPS2PDrr",
992 "VCVTSS2SDrr",
993 "VEXTRACTPSrr",
994 "VPEXTRBrr",
995 "VPEXTRDrr",
996 "VPEXTRQrr",
997 "VPEXTRWrr",
998 "VPSLLDrr",
999 "VPSLLQrr",
1000 "VPSLLWrr",
1001 "VPSRADrr",
1002 "VPSRAWrr",
1003 "VPSRLDrr",
1004 "VPSRLQrr",
1005 "VPSRLWrr",
1006 "VPTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1007
1008def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
1009 let Latency = 2;
1010 let NumMicroOps = 2;
1011 let ResourceCycles = [1,1];
1012}
1013def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
1014
1015def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
1016 let Latency = 2;
1017 let NumMicroOps = 2;
1018 let ResourceCycles = [1,1];
1019}
1020def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
1021
1022def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
1023 let Latency = 2;
1024 let NumMicroOps = 2;
1025 let ResourceCycles = [1,1];
1026}
1027def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
1028
1029def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
1030 let Latency = 2;
1031 let NumMicroOps = 2;
1032 let ResourceCycles = [1,1];
1033}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1034def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
1035 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1036
1037def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
1038 let Latency = 2;
1039 let NumMicroOps = 2;
1040 let ResourceCycles = [1,1];
1041}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1042def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]1043def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1044def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
1045 "ADC8ri",
1046 "CMOV(A|BE)(16|32|64)rr",
1047 "SBB8i8",
1048 "SBB8ri",
1049 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1050
1051def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
1052 let Latency = 2;
1053 let NumMicroOps = 3;
1054 let ResourceCycles = [1,1,1];
1055}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1056def: InstRW<[BWWriteResGroup21], (instregex "EXTRACTPSmr",
1057 "PEXTRBmr",
1058 "PEXTRDmr",
1059 "PEXTRQmr",
1060 "PEXTRWmr",
1061 "STMXCSR",
1062 "VEXTRACTPSmr",
1063 "VPEXTRBmr",
1064 "VPEXTRDmr",
1065 "VPEXTRQmr",
1066 "VPEXTRWmr",
1067 "VSTMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1068
1069def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
1070 let Latency = 2;
1071 let NumMicroOps = 3;
1072 let ResourceCycles = [1,1,1];
1073}
1074def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
1075
1076def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
1077 let Latency = 2;
1078 let NumMicroOps = 3;
1079 let ResourceCycles = [1,1,1];
1080}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1081def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1082
1083def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
1084 let Latency = 2;
1085 let NumMicroOps = 3;
1086 let ResourceCycles = [1,1,1];
1087}
1088def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
1089
1090def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1091 let Latency = 2;
1092 let NumMicroOps = 3;
1093 let ResourceCycles = [1,1,1];
1094}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1095def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1096def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
1097 "PUSH64i8",
1098 "STOSB",
1099 "STOSL",
1100 "STOSQ",
1101 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1102
1103def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
1104 let Latency = 3;
1105 let NumMicroOps = 1;
1106 let ResourceCycles = [1];
1107}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1108def: InstRW<[BWWriteResGroup26], (instregex "MOVMSKPDrr",
1109 "MOVMSKPSrr",
1110 "PMOVMSKBrr",
1111 "VMOVMSKPDYrr",
1112 "VMOVMSKPDrr",
1113 "VMOVMSKPSYrr",
1114 "VMOVMSKPSrr",
1115 "VPMOVMSKBYrr",
1116 "VPMOVMSKBrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1117
1118def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
1119 let Latency = 3;
1120 let NumMicroOps = 1;
1121 let ResourceCycles = [1];
1122}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1123def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1124def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
1125def: InstRW<[BWWriteResGroup27], (instregex "ADDPDrr",
1126 "ADDPSrr",
1127 "ADDSDrr",
1128 "ADDSSrr",
1129 "ADDSUBPDrr",
1130 "ADDSUBPSrr",
1131 "ADD_FPrST0",
1132 "ADD_FST0r",
1133 "ADD_FrST0",
1134 "BSF(16|32|64)rr",
1135 "BSR(16|32|64)rr",
1136 "CMPPDrri",
1137 "CMPPSrri",
1138 "CMPSDrr",
1139 "CMPSSrr",
1140 "COMISDrr",
1141 "COMISSrr",
1142 "CVTDQ2PSrr",
1143 "CVTPS2DQrr",
1144 "CVTTPS2DQrr",
1145 "LZCNT(16|32|64)rr",
1146 "MAX(C?)PDrr",
1147 "MAX(C?)PSrr",
1148 "MAX(C?)SDrr",
1149 "MAX(C?)SSrr",
1150 "MIN(C?)PDrr",
1151 "MIN(C?)PSrr",
1152 "MIN(C?)SDrr",
1153 "MIN(C?)SSrr",
1154 "MMX_CVTPI2PSirr",
1155 "PDEP(32|64)rr",
1156 "PEXT(32|64)rr",
1157 "POPCNT(16|32|64)rr",
1158 "SHLD(16|32|64)rri8",
1159 "SHRD(16|32|64)rri8",
1160 "SUBPDrr",
1161 "SUBPSrr",
1162 "SUBR_FPrST0",
1163 "SUBR_FST0r",
1164 "SUBR_FrST0",
1165 "SUBSDrr",
1166 "SUBSSrr",
1167 "SUB_FPrST0",
1168 "SUB_FST0r",
1169 "SUB_FrST0",
1170 "TZCNT(16|32|64)rr",
1171 "UCOMISDrr",
1172 "UCOMISSrr",
1173 "VADDPDYrr",
1174 "VADDPDrr",
1175 "VADDPSYrr",
1176 "VADDPSrr",
1177 "VADDSDrr",
1178 "VADDSSrr",
1179 "VADDSUBPDYrr",
1180 "VADDSUBPDrr",
1181 "VADDSUBPSYrr",
1182 "VADDSUBPSrr",
1183 "VCMPPDYrri",
1184 "VCMPPDrri",
1185 "VCMPPSYrri",
1186 "VCMPPSrri",
1187 "VCMPSDrr",
1188 "VCMPSSrr",
1189 "VCOMISDrr",
1190 "VCOMISSrr",
1191 "VCVTDQ2PSYrr",
1192 "VCVTDQ2PSrr",
1193 "VCVTPS2DQYrr",
1194 "VCVTPS2DQrr",
1195 "VCVTTPS2DQYrr",
1196 "VCVTTPS2DQrr",
1197 "VMAX(C?)PDYrr",
1198 "VMAX(C?)PDrr",
1199 "VMAX(C?)PSYrr",
1200 "VMAX(C?)PSrr",
1201 "VMAX(C?)SDrr",
1202 "VMAX(C?)SSrr",
1203 "VMIN(C?)PDYrr",
1204 "VMIN(C?)PDrr",
1205 "VMIN(C?)PSYrr",
1206 "VMIN(C?)PSrr",
1207 "VMIN(C?)SDrr",
1208 "VMIN(C?)SSrr",
1209 "VSUBPDYrr",
1210 "VSUBPDrr",
1211 "VSUBPSYrr",
1212 "VSUBPSrr",
1213 "VSUBSDrr",
1214 "VSUBSSrr",
1215 "VUCOMISDrr",
1216 "VUCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1217
1218def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
1219 let Latency = 3;
1220 let NumMicroOps = 2;
1221 let ResourceCycles = [1,1];
1222}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1223def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1224
1225def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
1226 let Latency = 3;
1227 let NumMicroOps = 1;
1228 let ResourceCycles = [1];
1229}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1230def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
1231 "VBROADCASTSSYrr",
1232 "VEXTRACTF128rr",
1233 "VEXTRACTI128rr",
1234 "VINSERTF128rr",
1235 "VINSERTI128rr",
1236 "VPBROADCASTBYrr",
1237 "VPBROADCASTBrr",
1238 "VPBROADCASTDYrr",
1239 "VPBROADCASTQYrr",
1240 "VPBROADCASTWYrr",
1241 "VPBROADCASTWrr",
1242 "VPERM2F128rr",
1243 "VPERM2I128rr",
1244 "VPERMDYrr",
1245 "VPERMPDYri",
1246 "VPERMPSYrr",
1247 "VPERMQYri",
1248 "VPMOVSXBDYrr",
1249 "VPMOVSXBQYrr",
1250 "VPMOVSXBWYrr",
1251 "VPMOVSXDQYrr",
1252 "VPMOVSXWDYrr",
1253 "VPMOVSXWQYrr",
1254 "VPMOVZXBDYrr",
1255 "VPMOVZXBQYrr",
1256 "VPMOVZXBWYrr",
1257 "VPMOVZXDQYrr",
1258 "VPMOVZXWDYrr",
1259 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1260
1261def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
1262 let Latency = 3;
1263 let NumMicroOps = 1;
1264 let ResourceCycles = [1];
1265}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1266def: InstRW<[BWWriteResGroup29], (instregex "MULPDrr",
1267 "MULPSrr",
1268 "MULSDrr",
1269 "MULSSrr",
1270 "VMULPDYrr",
1271 "VMULPDrr",
1272 "VMULPSYrr",
1273 "VMULPSrr",
1274 "VMULSDrr",
1275 "VMULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1276
1277def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
1278 let Latency = 3;
1279 let NumMicroOps = 3;
1280 let ResourceCycles = [3];
1281}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1282def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
1283 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1284
1285def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
1286 let Latency = 3;
1287 let NumMicroOps = 3;
1288 let ResourceCycles = [2,1];
1289}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1290def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVDYrr",
1291 "VPSLLVDrr",
1292 "VPSRAVDYrr",
1293 "VPSRAVDrr",
1294 "VPSRLVDYrr",
1295 "VPSRLVDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1296
1297def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
1298 let Latency = 3;
1299 let NumMicroOps = 3;
1300 let ResourceCycles = [2,1];
1301}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1302def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
1303 "MMX_PHADDSWrr",
1304 "MMX_PHADDWrr",
1305 "MMX_PHSUBDrr",
1306 "MMX_PHSUBSWrr",
1307 "MMX_PHSUBWrr",
1308 "PHADDDrr",
1309 "PHADDSWrr",
1310 "PHADDWrr",
1311 "PHSUBDrr",
1312 "PHSUBSWrr",
1313 "PHSUBWrr",
1314 "VPHADDDYrr",
1315 "VPHADDDrr",
1316 "VPHADDSWYrr",
1317 "VPHADDSWrr",
1318 "VPHADDWYrr",
1319 "VPHADDWrr",
1320 "VPHSUBDYrr",
1321 "VPHSUBDrr",
1322 "VPHSUBSWYrr",
1323 "VPHSUBSWrr",
1324 "VPHSUBWYrr",
1325 "VPHSUBWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1326
1327def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
1328 let Latency = 3;
1329 let NumMicroOps = 3;
1330 let ResourceCycles = [2,1];
1331}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1332def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
1333 "MMX_PACKSSWBirr",
1334 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1335
1336def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
1337 let Latency = 3;
1338 let NumMicroOps = 3;
1339 let ResourceCycles = [1,2];
1340}
1341def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1342
1343def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1344 let Latency = 3;
1345 let NumMicroOps = 3;
1346 let ResourceCycles = [1,2];
1347}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1348def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1349 "RCL(8|16|32|64)ri",
1350 "RCR(8|16|32|64)r1",
1351 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1352
1353def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1354 let Latency = 3;
1355 let NumMicroOps = 3;
1356 let ResourceCycles = [2,1];
1357}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1358def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1359 "ROR(8|16|32|64)rCL",
1360 "SAR(8|16|32|64)rCL",
1361 "SHL(8|16|32|64)rCL",
1362 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1363
1364def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1365 let Latency = 3;
1366 let NumMicroOps = 4;
1367 let ResourceCycles = [1,1,1,1];
1368}
1369def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1370
1371def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1372 let Latency = 3;
1373 let NumMicroOps = 4;
1374 let ResourceCycles = [1,1,1,1];
1375}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1376def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1377 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1378
1379def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1380 let Latency = 4;
1381 let NumMicroOps = 2;
1382 let ResourceCycles = [1,1];
1383}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1384def: InstRW<[BWWriteResGroup39], (instregex "CVTSD2SI64rr",
1385 "CVTSD2SIrr",
1386 "CVTSS2SI64rr",
1387 "CVTSS2SIrr",
1388 "CVTTSD2SI64rr",
1389 "CVTTSD2SIrr",
1390 "CVTTSS2SI64rr",
1391 "CVTTSS2SIrr",
1392 "VCVTSD2SI64rr",
1393 "VCVTSD2SIrr",
1394 "VCVTSS2SI64rr",
1395 "VCVTSS2SIrr",
1396 "VCVTTSD2SI64rr",
1397 "VCVTTSD2SIrr",
1398 "VCVTTSS2SI64rr",
1399 "VCVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1400
1401def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1402 let Latency = 4;
1403 let NumMicroOps = 2;
1404 let ResourceCycles = [1,1];
1405}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1406def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1407 "VPSLLDYrr",
1408 "VPSLLQYrr",
1409 "VPSLLWYrr",
1410 "VPSRADYrr",
1411 "VPSRAWYrr",
1412 "VPSRLDYrr",
1413 "VPSRLQYrr",
1414 "VPSRLWYrr",
1415 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1416
1417def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1418 let Latency = 4;
1419 let NumMicroOps = 2;
1420 let ResourceCycles = [1,1];
1421}
1422def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1423
1424def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1425 let Latency = 4;
1426 let NumMicroOps = 2;
1427 let ResourceCycles = [1,1];
1428}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1429def: InstRW<[BWWriteResGroup42], (instrs IMUL32r, IMUL64r, MUL32r, MUL64r)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1430def: InstRW<[BWWriteResGroup42], (instrs MULX64rr)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1431def: InstRW<[BWWriteResGroup42], (instregex "CVTDQ2PDrr",
1432 "CVTPD2DQrr",
1433 "CVTPD2PSrr",
1434 "CVTSD2SSrr",
1435 "CVTSI642SDrr",
1436 "CVTSI2SDrr",
1437 "CVTSI2SSrr",
1438 "CVTTPD2DQrr",
1439 "MMX_CVTPD2PIirr",
1440 "MMX_CVTPI2PDirr",
1441 "MMX_CVTPS2PIirr",
1442 "MMX_CVTTPD2PIirr",
1443 "MMX_CVTTPS2PIirr",
1444 "VCVTDQ2PDrr",
1445 "VCVTPD2DQrr",
1446 "VCVTPD2PSrr",
1447 "VCVTPS2PHrr",
1448 "VCVTSD2SSrr",
1449 "VCVTSI642SDrr",
1450 "VCVTSI2SDrr",
1451 "VCVTSI2SSrr",
1452 "VCVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1453
1454def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1455 let Latency = 4;
1456 let NumMicroOps = 4;
1457}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1458def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1459
1460def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1461 let Latency = 4;
1462 let NumMicroOps = 3;
1463 let ResourceCycles = [1,1,1];
1464}
1465def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1466
1467def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1468 let Latency = 4;
1469 let NumMicroOps = 3;
1470 let ResourceCycles = [1,1,1];
1471}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1472def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1473 "ISTT_FP32m",
1474 "ISTT_FP64m",
1475 "IST_F16m",
1476 "IST_F32m",
1477 "IST_FP16m",
1478 "IST_FP32m",
1479 "IST_FP64m",
1480 "VCVTPS2PHYmr",
1481 "VCVTPS2PHmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1482
1483def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1484 let Latency = 4;
1485 let NumMicroOps = 4;
1486 let ResourceCycles = [4];
1487}
1488def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1489
1490def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1491 let Latency = 4;
1492 let NumMicroOps = 4;
1493 let ResourceCycles = [1,3];
1494}
1495def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1496
1497def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1498 let Latency = 5;
1499 let NumMicroOps = 1;
1500 let ResourceCycles = [1];
1501}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1502def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1503 "MMX_PMADDWDirr",
1504 "MMX_PMULHRSWrr",
1505 "MMX_PMULHUWirr",
1506 "MMX_PMULHWirr",
1507 "MMX_PMULLWirr",
1508 "MMX_PMULUDQirr",
1509 "MMX_PSADBWirr",
1510 "MUL_FPrST0",
1511 "MUL_FST0r",
1512 "MUL_FrST0",
1513 "PCLMULQDQrr",
1514 "PCMPGTQrr",
1515 "PHMINPOSUWrr",
1516 "PMADDUBSWrr",
1517 "PMADDWDrr",
1518 "PMULDQrr",
1519 "PMULHRSWrr",
1520 "PMULHUWrr",
1521 "PMULHWrr",
1522 "PMULLWrr",
1523 "PMULUDQrr",
1524 "PSADBWrr",
1525 "RCPPSr",
1526 "RCPSSr",
1527 "RSQRTPSr",
1528 "RSQRTSSr",
1529 "VPCLMULQDQrr",
1530 "VPCMPGTQYrr",
1531 "VPCMPGTQrr",
1532 "VPHMINPOSUWrr",
1533 "VPMADDUBSWYrr",
1534 "VPMADDUBSWrr",
1535 "VPMADDWDYrr",
1536 "VPMADDWDrr",
1537 "VPMULDQYrr",
1538 "VPMULDQrr",
1539 "VPMULHRSWYrr",
1540 "VPMULHRSWrr",
1541 "VPMULHUWYrr",
1542 "VPMULHUWrr",
1543 "VPMULHWYrr",
1544 "VPMULHWrr",
1545 "VPMULLWYrr",
1546 "VPMULLWrr",
1547 "VPMULUDQYrr",
1548 "VPMULUDQrr",
1549 "VPSADBWYrr",
1550 "VPSADBWrr",
1551 "VRCPPSr",
1552 "VRCPSSr",
1553 "VRSQRTPSr",
1554 "VRSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1555
1556def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1557 let Latency = 5;
1558 let NumMicroOps = 1;
1559 let ResourceCycles = [1];
1560}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1561def: InstRW<[BWWriteResGroup48],
1562 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1563 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1564
1565def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1566 let Latency = 5;
1567 let NumMicroOps = 1;
1568 let ResourceCycles = [1];
1569}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1570def: InstRW<[BWWriteResGroup49], (instregex "LDDQUrm",
1571 "MMX_MOVD64rm",
1572 "MMX_MOVD64to64rm",
1573 "MMX_MOVQ64rm",
1574 "MOV(16|32|64)rm",
1575 "MOV64toPQIrm",
1576 "MOV8rm",
1577 "MOVAPDrm",
1578 "MOVAPSrm",
1579 "MOVDDUPrm",
1580 "MOVDI2PDIrm",
1581 "MOVDQArm",
1582 "MOVDQUrm",
1583 "MOVNTDQArm",
1584 "MOVQI2PQIrm",
1585 "MOVSDrm",
1586 "MOVSHDUPrm",
1587 "MOVSLDUPrm",
1588 "MOVSSrm",
1589 "MOVSX(16|32|64)rm16",
1590 "MOVSX(16|32|64)rm32",
1591 "MOVSX(16|32|64)rm8",
1592 "MOVUPDrm",
1593 "MOVUPSrm",
1594 "MOVZX(16|32|64)rm16",
1595 "MOVZX(16|32|64)rm8",
1596 "PREFETCHNTA",
1597 "PREFETCHT0",
1598 "PREFETCHT1",
1599 "PREFETCHT2",
1600 "VBROADCASTSSrm",
1601 "VLDDQUrm",
1602 "VMOV64toPQIrm",
1603 "VMOVAPDrm",
1604 "VMOVAPSrm",
1605 "VMOVDDUPrm",
1606 "VMOVDI2PDIrm",
1607 "VMOVDQArm",
1608 "VMOVDQUrm",
1609 "VMOVNTDQArm",
1610 "VMOVQI2PQIrm",
1611 "VMOVSDrm",
1612 "VMOVSHDUPrm",
1613 "VMOVSLDUPrm",
1614 "VMOVSSrm",
1615 "VMOVUPDrm",
1616 "VMOVUPSrm",
1617 "VPBROADCASTDrm",
1618 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1619
1620def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1621 let Latency = 5;
1622 let NumMicroOps = 3;
1623 let ResourceCycles = [1,2];
1624}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1625def: InstRW<[BWWriteResGroup50], (instregex "CVTSI642SSrr",
1626 "HADDPDrr",
1627 "HADDPSrr",
1628 "HSUBPDrr",
1629 "HSUBPSrr",
1630 "VCVTSI642SSrr",
1631 "VHADDPDYrr",
1632 "VHADDPDrr",
1633 "VHADDPSYrr",
1634 "VHADDPSrr",
1635 "VHSUBPDYrr",
1636 "VHSUBPDrr",
1637 "VHSUBPSYrr",
1638 "VHSUBPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1639
1640def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1641 let Latency = 5;
1642 let NumMicroOps = 3;
1643 let ResourceCycles = [1,1,1];
1644}
1645def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1646
1647def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1648 let Latency = 5;
1649 let NumMicroOps = 3;
1650 let ResourceCycles = [1,1,1];
1651}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1652def: InstRW<[BWWriteResGroup52], (instrs MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1653
1654def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1655 let Latency = 5;
1656 let NumMicroOps = 4;
1657 let ResourceCycles = [1,1,1,1];
1658}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1659def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPDYmr",
1660 "VMASKMOVPDmr",
1661 "VMASKMOVPSYmr",
1662 "VMASKMOVPSmr",
1663 "VPMASKMOVDYmr",
1664 "VPMASKMOVDmr",
1665 "VPMASKMOVQYmr",
1666 "VPMASKMOVQmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1667
1668def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1669 let Latency = 5;
1670 let NumMicroOps = 5;
1671 let ResourceCycles = [1,4];
1672}
1673def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1674
1675def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1676 let Latency = 5;
1677 let NumMicroOps = 5;
1678 let ResourceCycles = [1,4];
1679}
1680def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1681
1682def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1683 let Latency = 5;
1684 let NumMicroOps = 5;
1685 let ResourceCycles = [2,3];
1686}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1687def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1688
1689def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1690 let Latency = 5;
1691 let NumMicroOps = 6;
1692 let ResourceCycles = [1,1,4];
1693}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1694def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1695
1696def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1697 let Latency = 6;
1698 let NumMicroOps = 1;
1699 let ResourceCycles = [1];
1700}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1701def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1702 "LD_F64m",
1703 "LD_F80m",
1704 "VBROADCASTF128",
1705 "VBROADCASTI128",
1706 "VBROADCASTSDYrm",
1707 "VBROADCASTSSYrm",
1708 "VLDDQUYrm",
1709 "VMOVAPDYrm",
1710 "VMOVAPSYrm",
1711 "VMOVDDUPYrm",
1712 "VMOVDQAYrm",
1713 "VMOVDQUYrm",
1714 "VMOVNTDQAYrm",
1715 "VMOVSHDUPYrm",
1716 "VMOVSLDUPYrm",
1717 "VMOVUPDYrm",
1718 "VMOVUPSYrm",
1719 "VPBROADCASTDYrm",
1720 "VPBROADCASTQYrm",
1721 "ROUNDPDr",
1722 "ROUNDPSr",
1723 "ROUNDSDr",
1724 "ROUNDSSr",
1725 "VROUNDPDr",
1726 "VROUNDPSr",
1727 "VROUNDSDr",
1728 "VROUNDSSr",
1729 "VROUNDYPDr",
1730 "VROUNDYPSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1731
1732def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1733 let Latency = 6;
1734 let NumMicroOps = 2;
1735 let ResourceCycles = [1,1];
1736}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1737def: InstRW<[BWWriteResGroup59], (instregex "CVTPS2PDrm",
1738 "CVTSS2SDrm",
1739 "MMX_PSLLDrm",
1740 "MMX_PSLLQrm",
1741 "MMX_PSLLWrm",
1742 "MMX_PSRADrm",
1743 "MMX_PSRAWrm",
1744 "MMX_PSRLDrm",
1745 "MMX_PSRLQrm",
1746 "MMX_PSRLWrm",
1747 "VCVTPH2PSYrm",
1748 "VCVTPH2PSrm",
1749 "VCVTPS2PDrm",
1750 "VCVTSS2SDrm",
1751 "VPSLLVQrm",
1752 "VPSRLVQrm",
1753 "VTESTPDrm",
1754 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1755
1756def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1757 let Latency = 6;
1758 let NumMicroOps = 2;
1759 let ResourceCycles = [1,1];
1760}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1761def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1762 "VCVTPD2DQYrr",
1763 "VCVTPD2PSYrr",
1764 "VCVTPS2PHYrr",
1765 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1766
1767def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1768 let Latency = 6;
1769 let NumMicroOps = 2;
1770 let ResourceCycles = [1,1];
1771}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1772def: InstRW<[BWWriteResGroup61], (instregex "ANDNPDrm",
1773 "ANDNPSrm",
1774 "ANDPDrm",
1775 "ANDPSrm",
1776 "INSERTPSrm",
1777 "MMX_PALIGNRrmi",
1778 "MMX_PINSRWrm",
1779 "MMX_PSHUFBrm",
1780 "MMX_PSHUFWmi",
1781 "MMX_PUNPCKHBWirm",
1782 "MMX_PUNPCKHDQirm",
1783 "MMX_PUNPCKHWDirm",
1784 "MMX_PUNPCKLBWirm",
1785 "MMX_PUNPCKLDQirm",
1786 "MMX_PUNPCKLWDirm",
1787 "MOVHPDrm",
1788 "MOVHPSrm",
1789 "MOVLPDrm",
1790 "MOVLPSrm",
1791 "ORPDrm",
1792 "ORPSrm",
1793 "PACKSSDWrm",
1794 "PACKSSWBrm",
1795 "PACKUSDWrm",
1796 "PACKUSWBrm",
1797 "PALIGNRrmi",
1798 "PBLENDWrmi",
1799 "PINSRBrm",
1800 "PINSRDrm",
1801 "PINSRQrm",
1802 "PINSRWrm",
1803 "PMOVSXBDrm",
1804 "PMOVSXBQrm",
1805 "PMOVSXBWrm",
1806 "PMOVSXDQrm",
1807 "PMOVSXWDrm",
1808 "PMOVSXWQrm",
1809 "PMOVZXBDrm",
1810 "PMOVZXBQrm",
1811 "PMOVZXBWrm",
1812 "PMOVZXDQrm",
1813 "PMOVZXWDrm",
1814 "PMOVZXWQrm",
1815 "PSHUFBrm",
1816 "PSHUFDmi",
1817 "PSHUFHWmi",
1818 "PSHUFLWmi",
1819 "PUNPCKHBWrm",
1820 "PUNPCKHDQrm",
1821 "PUNPCKHQDQrm",
1822 "PUNPCKHWDrm",
1823 "PUNPCKLBWrm",
1824 "PUNPCKLDQrm",
1825 "PUNPCKLQDQrm",
1826 "PUNPCKLWDrm",
1827 "SHUFPDrmi",
1828 "SHUFPSrmi",
1829 "UNPCKHPDrm",
1830 "UNPCKHPSrm",
1831 "UNPCKLPDrm",
1832 "UNPCKLPSrm",
1833 "VANDNPDrm",
1834 "VANDNPSrm",
1835 "VANDPDrm",
1836 "VANDPSrm",
1837 "VINSERTPSrm",
1838 "VMOVHPDrm",
1839 "VMOVHPSrm",
1840 "VMOVLPDrm",
1841 "VMOVLPSrm",
1842 "VORPDrm",
1843 "VORPSrm",
1844 "VPACKSSDWrm",
1845 "VPACKSSWBrm",
1846 "VPACKUSDWrm",
1847 "VPACKUSWBrm",
1848 "VPALIGNRrmi",
1849 "VPBLENDWrmi",
1850 "VPERMILPDmi",
1851 "VPERMILPDrm",
1852 "VPERMILPSmi",
1853 "VPERMILPSrm",
1854 "VPINSRBrm",
1855 "VPINSRDrm",
1856 "VPINSRQrm",
1857 "VPINSRWrm",
1858 "VPMOVSXBDrm",
1859 "VPMOVSXBQrm",
1860 "VPMOVSXBWrm",
1861 "VPMOVSXDQrm",
1862 "VPMOVSXWDrm",
1863 "VPMOVSXWQrm",
1864 "VPMOVZXBDrm",
1865 "VPMOVZXBQrm",
1866 "VPMOVZXBWrm",
1867 "VPMOVZXDQrm",
1868 "VPMOVZXWDrm",
1869 "VPMOVZXWQrm",
1870 "VPSHUFBrm",
1871 "VPSHUFDmi",
1872 "VPSHUFHWmi",
1873 "VPSHUFLWmi",
1874 "VPUNPCKHBWrm",
1875 "VPUNPCKHDQrm",
1876 "VPUNPCKHQDQrm",
1877 "VPUNPCKHWDrm",
1878 "VPUNPCKLBWrm",
1879 "VPUNPCKLDQrm",
1880 "VPUNPCKLQDQrm",
1881 "VPUNPCKLWDrm",
1882 "VSHUFPDrmi",
1883 "VSHUFPSrmi",
1884 "VUNPCKHPDrm",
1885 "VUNPCKHPSrm",
1886 "VUNPCKLPDrm",
1887 "VUNPCKLPSrm",
1888 "VXORPDrm",
1889 "VXORPSrm",
1890 "XORPDrm",
1891 "XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1892
1893def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1894 let Latency = 6;
1895 let NumMicroOps = 2;
1896 let ResourceCycles = [1,1];
1897}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1898def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1899 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1900
1901def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1902 let Latency = 6;
1903 let NumMicroOps = 2;
1904 let ResourceCycles = [1,1];
1905}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1906def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1907 "ADCX(32|64)rm",
1908 "ADOX(32|64)rm",
1909 "BT(16|32|64)mi8",
1910 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1911 "RORX(32|64)mi",
1912 "SARX(32|64)rm",
1913 "SBB(8|16|32|64)rm",
1914 "SHLX(32|64)rm",
1915 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1916
1917def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1918 let Latency = 6;
1919 let NumMicroOps = 2;
1920 let ResourceCycles = [1,1];
1921}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]1922def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1923 "BLSI(32|64)rm",
1924 "BLSMSK(32|64)rm",
1925 "BLSR(32|64)rm",
1926 "BZHI(32|64)rm",
1927 "MMX_PABSBrm",
1928 "MMX_PABSDrm",
1929 "MMX_PABSWrm",
1930 "MMX_PADDBirm",
1931 "MMX_PADDDirm",
1932 "MMX_PADDQirm",
1933 "MMX_PADDSBirm",
1934 "MMX_PADDSWirm",
1935 "MMX_PADDUSBirm",
1936 "MMX_PADDUSWirm",
1937 "MMX_PADDWirm",
1938 "MMX_PAVGBirm",
1939 "MMX_PAVGWirm",
1940 "MMX_PCMPEQBirm",
1941 "MMX_PCMPEQDirm",
1942 "MMX_PCMPEQWirm",
1943 "MMX_PCMPGTBirm",
1944 "MMX_PCMPGTDirm",
1945 "MMX_PCMPGTWirm",
1946 "MMX_PMAXSWirm",
1947 "MMX_PMAXUBirm",
1948 "MMX_PMINSWirm",
1949 "MMX_PMINUBirm",
1950 "MMX_PSIGNBrm",
1951 "MMX_PSIGNDrm",
1952 "MMX_PSIGNWrm",
1953 "MMX_PSUBBirm",
1954 "MMX_PSUBDirm",
1955 "MMX_PSUBQirm",
1956 "MMX_PSUBSBirm",
1957 "MMX_PSUBSWirm",
1958 "MMX_PSUBUSBirm",
1959 "MMX_PSUBUSWirm",
1960 "MMX_PSUBWirm",
1961 "MOVBE(16|32|64)rm",
1962 "PABSBrm",
1963 "PABSDrm",
1964 "PABSWrm",
1965 "PADDBrm",
1966 "PADDDrm",
1967 "PADDQrm",
1968 "PADDSBrm",
1969 "PADDSWrm",
1970 "PADDUSBrm",
1971 "PADDUSWrm",
1972 "PADDWrm",
1973 "PAVGBrm",
1974 "PAVGWrm",
1975 "PCMPEQBrm",
1976 "PCMPEQDrm",
1977 "PCMPEQQrm",
1978 "PCMPEQWrm",
1979 "PCMPGTBrm",
1980 "PCMPGTDrm",
1981 "PCMPGTWrm",
1982 "PMAXSBrm",
1983 "PMAXSDrm",
1984 "PMAXSWrm",
1985 "PMAXUBrm",
1986 "PMAXUDrm",
1987 "PMAXUWrm",
1988 "PMINSBrm",
1989 "PMINSDrm",
1990 "PMINSWrm",
1991 "PMINUBrm",
1992 "PMINUDrm",
1993 "PMINUWrm",
1994 "PSIGNBrm",
1995 "PSIGNDrm",
1996 "PSIGNWrm",
1997 "PSUBBrm",
1998 "PSUBDrm",
1999 "PSUBQrm",
2000 "PSUBSBrm",
2001 "PSUBSWrm",
2002 "PSUBUSBrm",
2003 "PSUBUSWrm",
2004 "PSUBWrm",
2005 "VPABSBrm",
2006 "VPABSDrm",
2007 "VPABSWrm",
2008 "VPADDBrm",
2009 "VPADDDrm",
2010 "VPADDQrm",
2011 "VPADDSBrm",
2012 "VPADDSWrm",
2013 "VPADDUSBrm",
2014 "VPADDUSWrm",
2015 "VPADDWrm",
2016 "VPAVGBrm",
2017 "VPAVGWrm",
2018 "VPCMPEQBrm",
2019 "VPCMPEQDrm",
2020 "VPCMPEQQrm",
2021 "VPCMPEQWrm",
2022 "VPCMPGTBrm",
2023 "VPCMPGTDrm",
2024 "VPCMPGTWrm",
2025 "VPMAXSBrm",
2026 "VPMAXSDrm",
2027 "VPMAXSWrm",
2028 "VPMAXUBrm",
2029 "VPMAXUDrm",
2030 "VPMAXUWrm",
2031 "VPMINSBrm",
2032 "VPMINSDrm",
2033 "VPMINSWrm",
2034 "VPMINUBrm",
2035 "VPMINUDrm",
2036 "VPMINUWrm",
2037 "VPSIGNBrm",
2038 "VPSIGNDrm",
2039 "VPSIGNWrm",
2040 "VPSUBBrm",
2041 "VPSUBDrm",
2042 "VPSUBQrm",
2043 "VPSUBSBrm",
2044 "VPSUBSWrm",
2045 "VPSUBUSBrm",
2046 "VPSUBUSWrm",
2047 "VPSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2048
2049def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
2050 let Latency = 6;
2051 let NumMicroOps = 2;
2052 let ResourceCycles = [1,1];
2053}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2054def: InstRW<[BWWriteResGroup65], (instregex "BLENDPDrmi",
2055 "BLENDPSrmi",
2056 "MMX_PANDNirm",
2057 "MMX_PANDirm",
2058 "MMX_PORirm",
2059 "MMX_PXORirm",
2060 "PANDNrm",
2061 "PANDrm",
2062 "PORrm",
2063 "PXORrm",
2064 "VBLENDPDrmi",
2065 "VBLENDPSrmi",
2066 "VINSERTF128rm",
2067 "VINSERTI128rm",
2068 "VPANDNrm",
2069 "VPANDrm",
2070 "VPBLENDDrmi",
2071 "VPORrm",
2072 "VPXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2073
2074def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
2075 let Latency = 6;
2076 let NumMicroOps = 2;
2077 let ResourceCycles = [1,1];
2078}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2079def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2080def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
2081 "AND(8|16|32|64)rm",
2082 "CMP(8|16|32|64)mi",
2083 "CMP(8|16|32|64)mr",
2084 "CMP(8|16|32|64)rm",
2085 "OR(8|16|32|64)rm",
2086 "POP(16|32|64)rmr",
2087 "SUB(8|16|32|64)rm",
2088 "TEST(8|16|32|64)mr",
2089 "TEST(8|16|32|64)mi",
2090 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2091
2092def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2093 let Latency = 6;
2094 let NumMicroOps = 4;
2095 let ResourceCycles = [1,1,2];
2096}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2097def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
2098 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2099
2100def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
2101 let Latency = 6;
2102 let NumMicroOps = 4;
2103 let ResourceCycles = [1,1,1,1];
2104}
2105def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
2106
2107def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
2108 let Latency = 6;
2109 let NumMicroOps = 4;
2110 let ResourceCycles = [1,1,1,1];
2111}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2112def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
2113 "BTR(16|32|64)mi8",
2114 "BTS(16|32|64)mi8",
2115 "SAR(8|16|32|64)m1",
2116 "SAR(8|16|32|64)mi",
2117 "SHL(8|16|32|64)m1",
2118 "SHL(8|16|32|64)mi",
2119 "SHR(8|16|32|64)m1",
2120 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2121
2122def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2123 let Latency = 6;
2124 let NumMicroOps = 4;
2125 let ResourceCycles = [1,1,1,1];
2126}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2127def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
2128 "ADD(8|16|32|64)mr",
2129 "AND(8|16|32|64)mi",
2130 "AND(8|16|32|64)mr",
2131 "DEC(8|16|32|64)m",
2132 "INC(8|16|32|64)m",
2133 "NEG(8|16|32|64)m",
2134 "NOT(8|16|32|64)m",
2135 "OR(8|16|32|64)mi",
2136 "OR(8|16|32|64)mr",
2137 "POP(16|32|64)rmm",
2138 "PUSH(16|32|64)rmm",
2139 "SUB(8|16|32|64)mi",
2140 "SUB(8|16|32|64)mr",
2141 "XOR(8|16|32|64)mi",
2142 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2143
2144def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
2145 let Latency = 6;
2146 let NumMicroOps = 6;
2147 let ResourceCycles = [1,5];
2148}
2149def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
2150
2151def BWWriteResGroup72 : SchedWriteRes<[BWPort5]> {
2152 let Latency = 7;
2153 let NumMicroOps = 1;
2154 let ResourceCycles = [1];
2155}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2156def: InstRW<[BWWriteResGroup72], (instregex "AESDECLASTrr",
2157 "AESDECrr",
2158 "AESENCLASTrr",
2159 "AESENCrr",
2160 "VAESDECLASTrr",
2161 "VAESDECrr",
2162 "VAESENCLASTrr",
2163 "VAESENCrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2164
2165def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
2166 let Latency = 7;
2167 let NumMicroOps = 2;
2168 let ResourceCycles = [1,1];
2169}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2170def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
2171 "VPSLLQYrm",
2172 "VPSLLVQYrm",
2173 "VPSLLWYrm",
2174 "VPSRADYrm",
2175 "VPSRAWYrm",
2176 "VPSRLDYrm",
2177 "VPSRLQYrm",
2178 "VPSRLVQYrm",
2179 "VPSRLWYrm",
2180 "VTESTPDYrm",
2181 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2182
2183def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
2184 let Latency = 7;
2185 let NumMicroOps = 2;
2186 let ResourceCycles = [1,1];
2187}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2188def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
2189 "FCOM64m",
2190 "FCOMP32m",
2191 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2192
2193def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
2194 let Latency = 7;
2195 let NumMicroOps = 2;
2196 let ResourceCycles = [1,1];
2197}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2198def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
2199 "VANDNPSYrm",
2200 "VANDPDYrm",
2201 "VANDPSYrm",
2202 "VORPDYrm",
2203 "VORPSYrm",
2204 "VPACKSSDWYrm",
2205 "VPACKSSWBYrm",
2206 "VPACKUSDWYrm",
2207 "VPACKUSWBYrm",
2208 "VPALIGNRYrmi",
2209 "VPBLENDWYrmi",
2210 "VPERMILPDYmi",
2211 "VPERMILPDYrm",
2212 "VPERMILPSYmi",
2213 "VPERMILPSYrm",
2214 "VPSHUFBYrm",
2215 "VPSHUFDYmi",
2216 "VPSHUFHWYmi",
2217 "VPSHUFLWYmi",
2218 "VPUNPCKHBWYrm",
2219 "VPUNPCKHDQYrm",
2220 "VPUNPCKHQDQYrm",
2221 "VPUNPCKHWDYrm",
2222 "VPUNPCKLBWYrm",
2223 "VPUNPCKLDQYrm",
2224 "VPUNPCKLQDQYrm",
2225 "VPUNPCKLWDYrm",
2226 "VSHUFPDYrmi",
2227 "VSHUFPSYrmi",
2228 "VUNPCKHPDYrm",
2229 "VUNPCKHPSYrm",
2230 "VUNPCKLPDYrm",
2231 "VUNPCKLPSYrm",
2232 "VXORPDYrm",
2233 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2234
2235def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
2236 let Latency = 7;
2237 let NumMicroOps = 2;
2238 let ResourceCycles = [1,1];
2239}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2240def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
2241 "VPABSDYrm",
2242 "VPABSWYrm",
2243 "VPADDBYrm",
2244 "VPADDDYrm",
2245 "VPADDQYrm",
2246 "VPADDSBYrm",
2247 "VPADDSWYrm",
2248 "VPADDUSBYrm",
2249 "VPADDUSWYrm",
2250 "VPADDWYrm",
2251 "VPAVGBYrm",
2252 "VPAVGWYrm",
2253 "VPCMPEQBYrm",
2254 "VPCMPEQDYrm",
2255 "VPCMPEQQYrm",
2256 "VPCMPEQWYrm",
2257 "VPCMPGTBYrm",
2258 "VPCMPGTDYrm",
2259 "VPCMPGTWYrm",
2260 "VPMAXSBYrm",
2261 "VPMAXSDYrm",
2262 "VPMAXSWYrm",
2263 "VPMAXUBYrm",
2264 "VPMAXUDYrm",
2265 "VPMAXUWYrm",
2266 "VPMINSBYrm",
2267 "VPMINSDYrm",
2268 "VPMINSWYrm",
2269 "VPMINUBYrm",
2270 "VPMINUDYrm",
2271 "VPMINUWYrm",
2272 "VPSIGNBYrm",
2273 "VPSIGNDYrm",
2274 "VPSIGNWYrm",
2275 "VPSUBBYrm",
2276 "VPSUBDYrm",
2277 "VPSUBQYrm",
2278 "VPSUBSBYrm",
2279 "VPSUBSWYrm",
2280 "VPSUBUSBYrm",
2281 "VPSUBUSWYrm",
2282 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2283
2284def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
2285 let Latency = 7;
2286 let NumMicroOps = 2;
2287 let ResourceCycles = [1,1];
2288}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2289def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
2290 "VBLENDPSYrmi",
2291 "VPANDNYrm",
2292 "VPANDYrm",
2293 "VPBLENDDYrmi",
2294 "VPORYrm",
2295 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2296
2297def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
2298 let Latency = 7;
2299 let NumMicroOps = 3;
2300 let ResourceCycles = [1,2];
2301}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2302def: InstRW<[BWWriteResGroup78], (instregex "MPSADBWrri",
2303 "VMPSADBWYrri",
2304 "VMPSADBWrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2305
2306def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
2307 let Latency = 7;
2308 let NumMicroOps = 3;
2309 let ResourceCycles = [2,1];
2310}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2311def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
2312 "BLENDVPSrm0",
2313 "MMX_PACKSSDWirm",
2314 "MMX_PACKSSWBirm",
2315 "MMX_PACKUSWBirm",
2316 "PBLENDVBrm0",
2317 "VBLENDVPDrm",
2318 "VBLENDVPSrm",
2319 "VMASKMOVPDrm",
2320 "VMASKMOVPSrm",
2321 "VPBLENDVBrm",
2322 "VPMASKMOVDrm",
2323 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2324
2325def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
2326 let Latency = 7;
2327 let NumMicroOps = 3;
2328 let ResourceCycles = [1,2];
2329}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2330def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
2331 "SCASB",
2332 "SCASL",
2333 "SCASQ",
2334 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2335
2336def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2337 let Latency = 7;
2338 let NumMicroOps = 3;
2339 let ResourceCycles = [1,1,1];
2340}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2341def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
2342 "PSLLQrm",
2343 "PSLLWrm",
2344 "PSRADrm",
2345 "PSRAWrm",
2346 "PSRLDrm",
2347 "PSRLQrm",
2348 "PSRLWrm",
2349 "PTESTrm",
2350 "VPSLLDrm",
2351 "VPSLLQrm",
2352 "VPSLLWrm",
2353 "VPSRADrm",
2354 "VPSRAWrm",
2355 "VPSRLDrm",
2356 "VPSRLQrm",
2357 "VPSRLWrm",
2358 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2359
2360def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
2361 let Latency = 7;
2362 let NumMicroOps = 3;
2363 let ResourceCycles = [1,1,1];
2364}
2365def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
2366
2367def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
2368 let Latency = 7;
2369 let NumMicroOps = 3;
2370 let ResourceCycles = [1,1,1];
2371}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2372def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2373
2374def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2375 let Latency = 7;
2376 let NumMicroOps = 3;
2377 let ResourceCycles = [1,1,1];
2378}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2379def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
2380 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2381
2382def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
2383 let Latency = 7;
2384 let NumMicroOps = 3;
2385 let ResourceCycles = [1,1,1];
2386}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]2387def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2388
2389def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2390 let Latency = 7;
2391 let NumMicroOps = 3;
2392 let ResourceCycles = [1,1,1];
2393}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]2394def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2395
2396def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
2397 let Latency = 7;
2398 let NumMicroOps = 5;
2399 let ResourceCycles = [1,1,1,2];
2400}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2401def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
2402 "ROL(8|16|32|64)mi",
2403 "ROR(8|16|32|64)m1",
2404 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2405
2406def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2407 let Latency = 7;
2408 let NumMicroOps = 5;
2409 let ResourceCycles = [1,1,1,2];
2410}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2411def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2412
2413def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2414 let Latency = 7;
2415 let NumMicroOps = 5;
2416 let ResourceCycles = [1,1,1,1,1];
2417}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2418def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
2419 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2420
2421def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
2422 let Latency = 7;
2423 let NumMicroOps = 7;
2424 let ResourceCycles = [2,2,1,2];
2425}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2426def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2427
2428def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
2429 let Latency = 8;
2430 let NumMicroOps = 2;
2431 let ResourceCycles = [1,1];
2432}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2433def: InstRW<[BWWriteResGroup91], (instrs IMUL64m, MUL64m)>;
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2434def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2435def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
2436def: InstRW<[BWWriteResGroup91], (instregex "ADDPDrm",
2437 "ADDPSrm",
2438 "ADDSDrm",
2439 "ADDSSrm",
2440 "ADDSUBPDrm",
2441 "ADDSUBPSrm",
2442 "BSF(16|32|64)rm",
2443 "BSR(16|32|64)rm",
2444 "CMPPDrmi",
2445 "CMPPSrmi",
2446 "CMPSDrm",
2447 "CMPSSrm",
2448 "COMISDrm",
2449 "COMISSrm",
2450 "CVTDQ2PSrm",
2451 "CVTPS2DQrm",
2452 "CVTTPS2DQrm",
2453 "LZCNT(16|32|64)rm",
2454 "MAX(C?)PDrm",
2455 "MAX(C?)PSrm",
2456 "MAX(C?)SDrm",
2457 "MAX(C?)SSrm",
2458 "MIN(C?)PDrm",
2459 "MIN(C?)PSrm",
2460 "MIN(C?)SDrm",
2461 "MIN(C?)SSrm",
2462 "MMX_CVTPI2PSirm",
2463 "MMX_CVTPS2PIirm",
2464 "MMX_CVTTPS2PIirm",
2465 "PDEP(32|64)rm",
2466 "PEXT(32|64)rm",
2467 "POPCNT(16|32|64)rm",
2468 "SUBPDrm",
2469 "SUBPSrm",
2470 "SUBSDrm",
2471 "SUBSSrm",
2472 "TZCNT(16|32|64)rm",
2473 "UCOMISDrm",
2474 "UCOMISSrm",
2475 "VADDPDrm",
2476 "VADDPSrm",
2477 "VADDSDrm",
2478 "VADDSSrm",
2479 "VADDSUBPDrm",
2480 "VADDSUBPSrm",
2481 "VCMPPDrmi",
2482 "VCMPPSrmi",
2483 "VCMPSDrm",
2484 "VCMPSSrm",
2485 "VCOMISDrm",
2486 "VCOMISSrm",
2487 "VCVTDQ2PSrm",
2488 "VCVTPS2DQrm",
2489 "VCVTTPS2DQrm",
2490 "VMAX(C?)PDrm",
2491 "VMAX(C?)PSrm",
2492 "VMAX(C?)SDrm",
2493 "VMAX(C?)SSrm",
2494 "VMIN(C?)PDrm",
2495 "VMIN(C?)PSrm",
2496 "VMIN(C?)SDrm",
2497 "VMIN(C?)SSrm",
2498 "VSUBPDrm",
2499 "VSUBPSrm",
2500 "VSUBSDrm",
2501 "VSUBSSrm",
2502 "VUCOMISDrm",
2503 "VUCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2504
2505def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2506 let Latency = 8;
2507 let NumMicroOps = 3;
2508 let ResourceCycles = [1,1,1];
2509}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2510def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2511
2512def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2513 let Latency = 8;
2514 let NumMicroOps = 5;
2515}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2516def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2517
2518def BWWriteResGroup91_32 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2519 let Latency = 8;
2520 let NumMicroOps = 3;
2521 let ResourceCycles = [1,1,1];
2522}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2523def: InstRW<[BWWriteResGroup91_32], (instrs IMUL32m, MUL32m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2524
2525def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
2526 let Latency = 8;
2527 let NumMicroOps = 2;
2528 let ResourceCycles = [1,1];
2529}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2530def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
2531 "VPMOVSXBQYrm",
2532 "VPMOVSXBWYrm",
2533 "VPMOVSXDQYrm",
2534 "VPMOVSXWDYrm",
2535 "VPMOVSXWQYrm",
2536 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2537
2538def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
2539 let Latency = 8;
2540 let NumMicroOps = 2;
2541 let ResourceCycles = [1,1];
2542}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2543def: InstRW<[BWWriteResGroup93], (instregex "MULPDrm",
2544 "MULPSrm",
2545 "MULSDrm",
2546 "MULSSrm",
2547 "VMULPDrm",
2548 "VMULPSrm",
2549 "VMULSDrm",
2550 "VMULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2551
2552def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
2553 let Latency = 8;
2554 let NumMicroOps = 3;
2555 let ResourceCycles = [2,1];
2556}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2557def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
2558 "VBLENDVPSYrm",
2559 "VMASKMOVPDYrm",
2560 "VMASKMOVPSYrm",
2561 "VPBLENDVBYrm",
2562 "VPMASKMOVDYrm",
2563 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2564
2565def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2566 let Latency = 8;
2567 let NumMicroOps = 4;
2568 let ResourceCycles = [2,1,1];
2569}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2570def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
2571 "VPSRAVDrm",
2572 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2573
2574def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2575 let Latency = 8;
2576 let NumMicroOps = 4;
2577 let ResourceCycles = [2,1,1];
2578}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2579def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
2580 "MMX_PHADDSWrm",
2581 "MMX_PHADDWrm",
2582 "MMX_PHSUBDrm",
2583 "MMX_PHSUBSWrm",
2584 "MMX_PHSUBWrm",
2585 "PHADDDrm",
2586 "PHADDSWrm",
2587 "PHADDWrm",
2588 "PHSUBDrm",
2589 "PHSUBSWrm",
2590 "PHSUBWrm",
2591 "VPHADDDrm",
2592 "VPHADDSWrm",
2593 "VPHADDWrm",
2594 "VPHSUBDrm",
2595 "VPHSUBSWrm",
2596 "VPHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2597
2598def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2599 let Latency = 8;
2600 let NumMicroOps = 5;
2601 let ResourceCycles = [1,1,1,2];
2602}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2603def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2604 "RCL(8|16|32|64)mi",
2605 "RCR(8|16|32|64)m1",
2606 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2607
2608def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2609 let Latency = 8;
2610 let NumMicroOps = 5;
2611 let ResourceCycles = [1,1,2,1];
2612}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2613def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2614
2615def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2616 let Latency = 8;
2617 let NumMicroOps = 6;
2618 let ResourceCycles = [1,1,1,3];
2619}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2620def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2621 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2622
2623def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2624 let Latency = 8;
2625 let NumMicroOps = 6;
2626 let ResourceCycles = [1,1,1,2,1];
2627}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2628def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2629 "CMPXCHG(8|16|32|64)rm",
2630 "ROL(8|16|32|64)mCL",
2631 "SAR(8|16|32|64)mCL",
2632 "SBB(8|16|32|64)mi",
2633 "SBB(8|16|32|64)mr",
2634 "SHL(8|16|32|64)mCL",
2635 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2636
2637def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2638 let Latency = 9;
2639 let NumMicroOps = 2;
2640 let ResourceCycles = [1,1];
2641}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2642def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2643 "ADD_F64m",
2644 "ILD_F16m",
2645 "ILD_F32m",
2646 "ILD_F64m",
2647 "SUBR_F32m",
2648 "SUBR_F64m",
2649 "SUB_F32m",
2650 "SUB_F64m",
2651 "VADDPDYrm",
2652 "VADDPSYrm",
2653 "VADDSUBPDYrm",
2654 "VADDSUBPSYrm",
2655 "VCMPPDYrmi",
2656 "VCMPPSYrmi",
2657 "VCVTDQ2PSYrm",
2658 "VCVTPS2DQYrm",
2659 "VCVTTPS2DQYrm",
2660 "VMAX(C?)PDYrm",
2661 "VMAX(C?)PSYrm",
2662 "VMIN(C?)PDYrm",
2663 "VMIN(C?)PSYrm",
2664 "VSUBPDYrm",
2665 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2666
2667def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2668 let Latency = 9;
2669 let NumMicroOps = 2;
2670 let ResourceCycles = [1,1];
2671}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2672def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2673 "VPERM2I128rm",
2674 "VPERMDYrm",
2675 "VPERMPDYmi",
2676 "VPERMPSYrm",
2677 "VPERMQYmi",
2678 "VPMOVZXBDYrm",
2679 "VPMOVZXBQYrm",
2680 "VPMOVZXBWYrm",
2681 "VPMOVZXDQYrm",
2682 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2683
2684def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2685 let Latency = 9;
2686 let NumMicroOps = 2;
2687 let ResourceCycles = [1,1];
2688}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2689def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2690 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2691
2692def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2693 let Latency = 9;
2694 let NumMicroOps = 3;
2695 let ResourceCycles = [1,1,1];
2696}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2697def: InstRW<[BWWriteResGroup104], (instregex "DPPDrri",
2698 "VDPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2699
2700def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2701 let Latency = 9;
2702 let NumMicroOps = 3;
2703 let ResourceCycles = [1,1,1];
2704}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2705def: InstRW<[BWWriteResGroup105], (instregex "CVTSD2SI64rm",
2706 "CVTSD2SIrm",
2707 "CVTSS2SI64rm",
2708 "CVTSS2SIrm",
2709 "CVTTSD2SI64rm",
2710 "CVTTSD2SIrm",
2711 "CVTTSS2SIrm",
2712 "VCVTSD2SI64rm",
2713 "VCVTSD2SIrm",
2714 "VCVTSS2SI64rm",
2715 "VCVTSS2SIrm",
2716 "VCVTTSD2SI64rm",
2717 "VCVTTSD2SIrm",
2718 "VCVTTSS2SI64rm",
2719 "VCVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2720
2721def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2722 let Latency = 9;
2723 let NumMicroOps = 3;
2724 let ResourceCycles = [1,1,1];
2725}
2726def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2727
2728def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2729 let Latency = 9;
2730 let NumMicroOps = 3;
2731 let ResourceCycles = [1,1,1];
2732}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2733def: InstRW<[BWWriteResGroup107], (instrs MULX64rm)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2734def: InstRW<[BWWriteResGroup107], (instregex "CVTDQ2PDrm",
2735 "CVTPD2DQrm",
2736 "CVTPD2PSrm",
2737 "CVTSD2SSrm",
2738 "CVTTPD2DQrm",
2739 "MMX_CVTPD2PIirm",
2740 "MMX_CVTPI2PDirm",
2741 "MMX_CVTTPD2PIirm",
2742 "VCVTDQ2PDrm",
2743 "VCVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2744
2745def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2746 let Latency = 9;
2747 let NumMicroOps = 3;
2748 let ResourceCycles = [1,1,1];
2749}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2750def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTBYrm",
2751 "VPBROADCASTBrm",
2752 "VPBROADCASTWYrm",
2753 "VPBROADCASTWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2754
2755def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2756 let Latency = 9;
2757 let NumMicroOps = 4;
2758 let ResourceCycles = [2,1,1];
2759}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2760def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2761 "VPSRAVDYrm",
2762 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2763
2764def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2765 let Latency = 9;
2766 let NumMicroOps = 4;
2767 let ResourceCycles = [2,1,1];
2768}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2769def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2770 "VPHADDSWYrm",
2771 "VPHADDWYrm",
2772 "VPHSUBDYrm",
2773 "VPHSUBSWYrm",
2774 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2775
2776def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2777 let Latency = 9;
2778 let NumMicroOps = 4;
2779 let ResourceCycles = [1,1,1,1];
2780}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2781def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2782 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2783
2784def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2785 let Latency = 9;
2786 let NumMicroOps = 5;
2787 let ResourceCycles = [1,1,3];
2788}
2789def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2790
2791def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2792 let Latency = 9;
2793 let NumMicroOps = 5;
2794 let ResourceCycles = [1,2,1,1];
2795}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2796def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2797 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2798
2799def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2800 let Latency = 10;
2801 let NumMicroOps = 2;
2802 let ResourceCycles = [2];
2803}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2804def: InstRW<[BWWriteResGroup114], (instregex "PMULLDrr",
2805 "VPMULLDYrr",
2806 "VPMULLDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2807
2808def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2809 let Latency = 10;
2810 let NumMicroOps = 2;
2811 let ResourceCycles = [1,1];
2812}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2813def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2814 "MMX_PMADDWDirm",
2815 "MMX_PMULHRSWrm",
2816 "MMX_PMULHUWirm",
2817 "MMX_PMULHWirm",
2818 "MMX_PMULLWirm",
2819 "MMX_PMULUDQirm",
2820 "MMX_PSADBWirm",
2821 "PCLMULQDQrm",
2822 "PCMPGTQrm",
2823 "PHMINPOSUWrm",
2824 "PMADDUBSWrm",
2825 "PMADDWDrm",
2826 "PMULDQrm",
2827 "PMULHRSWrm",
2828 "PMULHUWrm",
2829 "PMULHWrm",
2830 "PMULLWrm",
2831 "PMULUDQrm",
2832 "PSADBWrm",
2833 "RCPPSm",
2834 "RCPSSm",
2835 "RSQRTPSm",
2836 "RSQRTSSm",
2837 "VPCLMULQDQrm",
2838 "VPCMPGTQrm",
2839 "VPHMINPOSUWrm",
2840 "VPMADDUBSWrm",
2841 "VPMADDWDrm",
2842 "VPMULDQrm",
2843 "VPMULHRSWrm",
2844 "VPMULHUWrm",
2845 "VPMULHWrm",
2846 "VPMULLWrm",
2847 "VPMULUDQrm",
2848 "VPSADBWrm",
2849 "VRCPPSm",
2850 "VRCPSSm",
2851 "VRSQRTPSm",
2852 "VRSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2853
2854def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2855 let Latency = 10;
2856 let NumMicroOps = 2;
2857 let ResourceCycles = [1,1];
2858}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2859def: InstRW<[BWWriteResGroup116],
2860 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2861 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2862
2863def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2864 let Latency = 10;
2865 let NumMicroOps = 3;
2866 let ResourceCycles = [2,1];
2867}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2868def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2869 "FICOM32m",
2870 "FICOMP16m",
2871 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2872
2873def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2874 let Latency = 10;
2875 let NumMicroOps = 3;
2876 let ResourceCycles = [1,1,1];
2877}
2878def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2879
2880def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2881 let Latency = 10;
2882 let NumMicroOps = 4;
2883 let ResourceCycles = [1,2,1];
2884}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2885def: InstRW<[BWWriteResGroup119], (instregex "HADDPDrm",
2886 "HADDPSrm",
2887 "HSUBPDrm",
2888 "HSUBPSrm",
2889 "VHADDPDrm",
2890 "VHADDPSrm",
2891 "VHSUBPDrm",
2892 "VHSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2893
2894def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2895 let Latency = 10;
2896 let NumMicroOps = 4;
2897 let ResourceCycles = [1,1,1,1];
2898}
2899def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2900
2901def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
2902 let Latency = 10;
2903 let NumMicroOps = 4;
2904 let ResourceCycles = [1,1,1,1];
2905}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2906def: InstRW<[BWWriteResGroup121], (instrs MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2907
2908def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2909 let Latency = 11;
2910 let NumMicroOps = 1;
2911 let ResourceCycles = [1];
2912}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2913def: InstRW<[BWWriteResGroup122], (instregex "DIVPSrr",
2914 "DIVSSrr",
2915 "VDIVPSrr",
2916 "VDIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2917
2918def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2919 let Latency = 11;
2920 let NumMicroOps = 2;
2921 let ResourceCycles = [1,1];
2922}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2923def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2924 "MUL_F64m",
2925 "VPCMPGTQYrm",
2926 "VPMADDUBSWYrm",
2927 "VPMADDWDYrm",
2928 "VPMULDQYrm",
2929 "VPMULHRSWYrm",
2930 "VPMULHUWYrm",
2931 "VPMULHWYrm",
2932 "VPMULLWYrm",
2933 "VPMULUDQYrm",
2934 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2935
2936def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2937 let Latency = 11;
2938 let NumMicroOps = 2;
2939 let ResourceCycles = [1,1];
2940}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2941def: InstRW<[BWWriteResGroup124],
2942 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2943
2944def BWWriteResGroup125 : SchedWriteRes<[BWPort0]> {
2945 let Latency = 11;
2946 let NumMicroOps = 3;
2947 let ResourceCycles = [3];
2948}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2949def: InstRW<[BWWriteResGroup125], (instregex "PCMPISTRIrr",
2950 "PCMPISTRM128rr",
2951 "VPCMPISTRIrr",
2952 "VPCMPISTRM128rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2953
2954def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2955 let Latency = 11;
2956 let NumMicroOps = 3;
2957 let ResourceCycles = [2,1];
2958}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2959def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2960 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2961
2962def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2963 let Latency = 11;
2964 let NumMicroOps = 3;
2965 let ResourceCycles = [2,1];
2966}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2967def: InstRW<[BWWriteResGroup127], (instregex "ROUNDPDm",
2968 "ROUNDPSm",
2969 "ROUNDSDm",
2970 "ROUNDSSm",
2971 "VROUNDPDm",
2972 "VROUNDPSm",
2973 "VROUNDSDm",
2974 "VROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2975
2976def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2977 let Latency = 11;
2978 let NumMicroOps = 3;
2979 let ResourceCycles = [1,1,1];
2980}
2981def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2982
2983def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2984 let Latency = 11;
2985 let NumMicroOps = 4;
2986 let ResourceCycles = [1,2,1];
2987}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2988def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2989 "VHADDPSYrm",
2990 "VHSUBPDYrm",
2991 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2992
2993def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2994 let Latency = 11;
2995 let NumMicroOps = 6;
2996 let ResourceCycles = [1,1,1,1,2];
2997}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]2998def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2999 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3000
3001def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
3002 let Latency = 11;
3003 let NumMicroOps = 7;
3004 let ResourceCycles = [2,2,3];
3005}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3006def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
3007 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3008
3009def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
3010 let Latency = 11;
3011 let NumMicroOps = 9;
3012 let ResourceCycles = [1,4,1,3];
3013}
3014def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
3015
3016def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
3017 let Latency = 11;
3018 let NumMicroOps = 11;
3019 let ResourceCycles = [2,9];
3020}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3021def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
3022def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3023
3024def BWWriteResGroup134 : SchedWriteRes<[BWPort5,BWPort23]> {
3025 let Latency = 12;
3026 let NumMicroOps = 2;
3027 let ResourceCycles = [1,1];
3028}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3029def: InstRW<[BWWriteResGroup134], (instregex "AESDECLASTrm",
3030 "AESDECrm",
3031 "AESENCLASTrm",
3032 "AESENCrm",
3033 "VAESDECLASTrm",
3034 "VAESDECrm",
3035 "VAESENCLASTrm",
3036 "VAESENCrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3037
3038def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
3039 let Latency = 12;
3040 let NumMicroOps = 3;
3041 let ResourceCycles = [2,1];
3042}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3043def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
3044 "ADD_FI32m",
3045 "SUBR_FI16m",
3046 "SUBR_FI32m",
3047 "SUB_FI16m",
3048 "SUB_FI32m",
3049 "VROUNDYPDm",
3050 "VROUNDYPSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3051
3052def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
3053 let Latency = 12;
3054 let NumMicroOps = 4;
3055 let ResourceCycles = [1,2,1];
3056}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3057def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3058
3059def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
3060 let Latency = 13;
3061 let NumMicroOps = 1;
3062 let ResourceCycles = [1];
3063}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3064def: InstRW<[BWWriteResGroup137], (instregex "SQRTPSr",
3065 "SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3066
3067def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
3068 let Latency = 13;
3069 let NumMicroOps = 4;
3070 let ResourceCycles = [1,2,1];
3071}
3072def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
3073
3074def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
3075 let Latency = 14;
3076 let NumMicroOps = 1;
3077 let ResourceCycles = [1];
3078}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3079def: InstRW<[BWWriteResGroup139], (instregex "DIVPDrr",
3080 "DIVSDrr",
3081 "VDIVPDrr",
3082 "VDIVSDrr",
3083 "VSQRTPSr",
3084 "VSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3085
3086def BWWriteResGroup140 : SchedWriteRes<[BWPort5]> {
3087 let Latency = 14;
3088 let NumMicroOps = 2;
3089 let ResourceCycles = [2];
3090}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3091def: InstRW<[BWWriteResGroup140], (instregex "(V?)AESIMCrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3092
3093def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3094 let Latency = 14;
3095 let NumMicroOps = 3;
3096 let ResourceCycles = [1,1,1];
3097}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3098def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
3099 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3100
3101def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
3102 let Latency = 14;
3103 let NumMicroOps = 4;
3104 let ResourceCycles = [2,1,1];
3105}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3106def: InstRW<[BWWriteResGroup142], (instregex "DPPSrri",
3107 "VDPPSYrri",
3108 "VDPPSrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3109
3110def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3111 let Latency = 14;
3112 let NumMicroOps = 4;
3113 let ResourceCycles = [1,1,1,1];
3114}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3115def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3116
3117def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
3118 let Latency = 14;
3119 let NumMicroOps = 8;
3120 let ResourceCycles = [2,2,1,3];
3121}
3122def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
3123
3124def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
3125 let Latency = 14;
3126 let NumMicroOps = 10;
3127 let ResourceCycles = [2,3,1,4];
3128}
3129def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
3130
3131def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
3132 let Latency = 14;
3133 let NumMicroOps = 12;
3134 let ResourceCycles = [2,1,4,5];
3135}
3136def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
3137
3138def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
3139 let Latency = 15;
3140 let NumMicroOps = 1;
3141 let ResourceCycles = [1];
3142}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3143def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
3144 "DIVR_FST0r",
3145 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3146
3147def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
3148 let Latency = 15;
3149 let NumMicroOps = 3;
3150 let ResourceCycles = [2,1];
3151}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3152def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3153
3154def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3155 let Latency = 15;
3156 let NumMicroOps = 10;
3157 let ResourceCycles = [1,1,1,4,1,2];
3158}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3159def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3160
3161def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
3162 let Latency = 16;
3163 let NumMicroOps = 2;
3164 let ResourceCycles = [1,1];
3165}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3166def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
3167 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3168
3169def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
3170 let Latency = 16;
3171 let NumMicroOps = 3;
3172 let ResourceCycles = [2,1];
3173}
3174def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
3175
3176def BWWriteResGroup152 : SchedWriteRes<[BWPort0,BWPort23]> {
3177 let Latency = 16;
3178 let NumMicroOps = 4;
3179 let ResourceCycles = [3,1];
3180}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3181def: InstRW<[BWWriteResGroup152], (instregex "(V?)PCMPISTRIrm",
3182 "(V?)PCMPISTRM128rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3183
3184def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3185 let Latency = 16;
3186 let NumMicroOps = 14;
3187 let ResourceCycles = [1,1,1,4,2,5];
3188}
3189def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
3190
3191def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
3192 let Latency = 16;
3193 let NumMicroOps = 16;
3194 let ResourceCycles = [16];
3195}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3196def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3197
3198def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
3199 let Latency = 17;
3200 let NumMicroOps = 3;
3201 let ResourceCycles = [2,1];
3202}
3203def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
3204
3205def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3206 let Latency = 17;
3207 let NumMicroOps = 4;
3208 let ResourceCycles = [2,1,1];
3209}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3210def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
3211 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3212
3213def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
3214 let Latency = 18;
3215 let NumMicroOps = 2;
3216 let ResourceCycles = [1,1];
3217}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3218def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm",
3219 "SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3220
3221def BWWriteResGroup158 : SchedWriteRes<[BWPort0,BWPort5,BWPort0156]> {
3222 let Latency = 18;
3223 let NumMicroOps = 8;
3224 let ResourceCycles = [4,3,1];
3225}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3226def: InstRW<[BWWriteResGroup158], (instregex "(V?)PCMPESTRIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3227
3228def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
3229 let Latency = 18;
3230 let NumMicroOps = 8;
3231 let ResourceCycles = [1,1,1,5];
3232}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3233def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3234def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3235
3236def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3237 let Latency = 18;
3238 let NumMicroOps = 11;
3239 let ResourceCycles = [2,1,1,3,1,3];
3240}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3241def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3242
3243def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
3244 let Latency = 19;
3245 let NumMicroOps = 2;
3246 let ResourceCycles = [1,1];
3247}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3248def: InstRW<[BWWriteResGroup161], (instregex "DIVPDrm",
3249 "DIVSDrm",
3250 "VDIVPDrm",
3251 "VDIVSDrm",
3252 "VSQRTPSm",
3253 "VSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3254
3255def BWWriteResGroup162 : SchedWriteRes<[BWPort5,BWPort23]> {
3256 let Latency = 19;
3257 let NumMicroOps = 3;
3258 let ResourceCycles = [2,1];
3259}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3260def: InstRW<[BWWriteResGroup162], (instregex "(V?)AESIMCrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3261
3262def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3263 let Latency = 19;
3264 let NumMicroOps = 5;
3265 let ResourceCycles = [2,1,1,1];
3266}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3267def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3268
3269def BWWriteResGroup164 : SchedWriteRes<[BWPort0,BWPort5,BWPort015,BWPort0156]> {
3270 let Latency = 19;
3271 let NumMicroOps = 9;
3272 let ResourceCycles = [4,3,1,1];
3273}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3274def: InstRW<[BWWriteResGroup164], (instregex "(V?)PCMPESTRM128rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3275
3276def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
3277 let Latency = 20;
3278 let NumMicroOps = 1;
3279 let ResourceCycles = [1];
3280}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3281def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
3282 "DIV_FST0r",
3283 "DIV_FrST0",
3284 "SQRTPDr",
3285 "SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3286
3287def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3288 let Latency = 20;
3289 let NumMicroOps = 5;
3290 let ResourceCycles = [2,1,1,1];
3291}
3292def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
3293
3294def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3295 let Latency = 20;
3296 let NumMicroOps = 8;
3297 let ResourceCycles = [1,1,1,1,1,1,2];
3298}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3299def: InstRW<[BWWriteResGroup167], (instregex "INSB",
3300 "INSL",
3301 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3302
3303def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
3304 let Latency = 21;
3305 let NumMicroOps = 1;
3306 let ResourceCycles = [1];
3307}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3308def: InstRW<[BWWriteResGroup168], (instregex "VSQRTPDr",
3309 "VSQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3310
3311def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
3312 let Latency = 21;
3313 let NumMicroOps = 2;
3314 let ResourceCycles = [1,1];
3315}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3316def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
3317 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3318
3319def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
3320 let Latency = 21;
3321 let NumMicroOps = 3;
3322 let ResourceCycles = [2,1];
3323}
3324def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
3325
3326def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3327 let Latency = 21;
3328 let NumMicroOps = 19;
3329 let ResourceCycles = [2,1,4,1,1,4,6];
3330}
3331def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
3332
3333def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
3334 let Latency = 22;
3335 let NumMicroOps = 18;
3336 let ResourceCycles = [1,1,16];
3337}
3338def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
3339
3340def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
3341 let Latency = 23;
3342 let NumMicroOps = 3;
3343 let ResourceCycles = [2,1];
3344}
3345def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
3346
3347def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3348 let Latency = 23;
3349 let NumMicroOps = 4;
3350 let ResourceCycles = [2,1,1];
3351}
3352def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
3353
3354def BWWriteResGroup175 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort0156]> {
3355 let Latency = 23;
3356 let NumMicroOps = 9;
3357 let ResourceCycles = [4,3,1,1];
3358}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3359def: InstRW<[BWWriteResGroup175], (instregex "(V?)PCMPESTRIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3360
3361def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
3362 let Latency = 23;
3363 let NumMicroOps = 19;
3364 let ResourceCycles = [3,1,15];
3365}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3366def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3367
3368def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3369 let Latency = 24;
3370 let NumMicroOps = 3;
3371 let ResourceCycles = [1,1,1];
3372}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3373def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
3374 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3375
3376def BWWriteResGroup178 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015,BWPort0156]> {
3377 let Latency = 24;
3378 let NumMicroOps = 10;
3379 let ResourceCycles = [4,3,1,1,1];
3380}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3381def: InstRW<[BWWriteResGroup178], (instregex "(V?)PCMPESTRM128rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3382
3383def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
3384 let Latency = 25;
3385 let NumMicroOps = 2;
3386 let ResourceCycles = [1,1];
3387}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3388def: InstRW<[BWWriteResGroup179], (instregex "SQRTPDm",
3389 "SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3390
3391def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
3392 let Latency = 26;
3393 let NumMicroOps = 2;
3394 let ResourceCycles = [1,1];
3395}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3396def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
3397 "DIVR_F64m",
3398 "VSQRTPDm",
3399 "VSQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3400
3401def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3402 let Latency = 27;
3403 let NumMicroOps = 4;
3404 let ResourceCycles = [2,1,1];
3405}
3406def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
3407
3408def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3409 let Latency = 29;
3410 let NumMicroOps = 3;
3411 let ResourceCycles = [1,1,1];
3412}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3413def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
3414 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3415
3416def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3417 let Latency = 29;
3418 let NumMicroOps = 4;
3419 let ResourceCycles = [2,1,1];
3420}
3421def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
3422
3423def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3424 let Latency = 22;
3425 let NumMicroOps = 7;
3426 let ResourceCycles = [1,3,2,1];
3427}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3428def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3429
3430def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3431 let Latency = 23;
3432 let NumMicroOps = 9;
3433 let ResourceCycles = [1,3,4,1];
3434}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3435def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3436
3437def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3438 let Latency = 24;
3439 let NumMicroOps = 9;
3440 let ResourceCycles = [1,5,2,1];
3441}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3442def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3443
3444def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3445 let Latency = 25;
3446 let NumMicroOps = 7;
3447 let ResourceCycles = [1,3,2,1];
3448}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3449def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
3450 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3451
3452def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3453 let Latency = 26;
3454 let NumMicroOps = 9;
3455 let ResourceCycles = [1,5,2,1];
3456}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3457def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3458
3459def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3460 let Latency = 26;
3461 let NumMicroOps = 14;
3462 let ResourceCycles = [1,4,8,1];
3463}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3464def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3465
3466def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3467 let Latency = 27;
3468 let NumMicroOps = 9;
3469 let ResourceCycles = [1,5,2,1];
3470}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3471def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3472
3473def BWWriteResGroup184 : SchedWriteRes<[BWPort0,BWPort5,BWPort015]> {
3474 let Latency = 29;
3475 let NumMicroOps = 11;
3476 let ResourceCycles = [2,7,2];
3477}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3478def: InstRW<[BWWriteResGroup184], (instregex "(V?)AESKEYGENASSIST128rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3479
3480def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
3481 let Latency = 29;
3482 let NumMicroOps = 27;
3483 let ResourceCycles = [1,5,1,1,19];
3484}
3485def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
3486
3487def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
3488 let Latency = 30;
3489 let NumMicroOps = 28;
3490 let ResourceCycles = [1,6,1,1,19];
3491}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3492def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3493
3494def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
3495 let Latency = 31;
3496 let NumMicroOps = 31;
3497 let ResourceCycles = [8,1,21,1];
3498}
3499def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
3500
3501def BWWriteResGroup188 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015]> {
3502 let Latency = 33;
3503 let NumMicroOps = 11;
3504 let ResourceCycles = [2,7,1,1];
3505}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3506def: InstRW<[BWWriteResGroup188], (instregex "(V?)AESKEYGENASSIST128rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3507
3508def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
3509 let Latency = 34;
3510 let NumMicroOps = 3;
3511 let ResourceCycles = [2,1];
3512}
3513def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
3514
3515def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
3516 let Latency = 34;
3517 let NumMicroOps = 8;
3518 let ResourceCycles = [2,2,2,1,1];
3519}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3520def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3521
3522def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
3523 let Latency = 34;
3524 let NumMicroOps = 23;
3525 let ResourceCycles = [1,5,3,4,10];
3526}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3527def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
3528 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3529
3530def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
3531 let Latency = 35;
3532 let NumMicroOps = 8;
3533 let ResourceCycles = [2,2,2,1,1];
3534}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3535def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3536
3537def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3538 let Latency = 35;
3539 let NumMicroOps = 23;
3540 let ResourceCycles = [1,5,2,1,4,10];
3541}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame^]3542def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
3543 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3544
3545def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3546 let Latency = 40;
3547 let NumMicroOps = 4;
3548 let ResourceCycles = [2,1,1];
3549}
3550def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
3551
3552def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
3553 let Latency = 42;
3554 let NumMicroOps = 22;
3555 let ResourceCycles = [2,20];
3556}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3557def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3558
3559def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
3560 let Latency = 60;
3561 let NumMicroOps = 64;
3562 let ResourceCycles = [2,2,8,1,10,2,39];
3563}
3564def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3565
3566def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
3567 let Latency = 63;
3568 let NumMicroOps = 88;
3569 let ResourceCycles = [4,4,31,1,2,1,45];
3570}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3571def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3572
3573def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
3574 let Latency = 63;
3575 let NumMicroOps = 90;
3576 let ResourceCycles = [4,2,33,1,2,1,47];
3577}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3578def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3579
3580def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
3581 let Latency = 75;
3582 let NumMicroOps = 15;
3583 let ResourceCycles = [6,3,6];
3584}
3585def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
3586
3587def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
3588 let Latency = 80;
3589 let NumMicroOps = 32;
3590 let ResourceCycles = [7,7,3,3,1,11];
3591}
3592def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
3593
3594def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
3595 let Latency = 115;
3596 let NumMicroOps = 100;
3597 let ResourceCycles = [9,9,11,8,1,11,21,30];
3598}
3599def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3600
3601} // SchedModel
3602