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gerrit-public.fairphone.software / toolchain / llvm-project / 8743f8ca245d94e91889f376c236aed81b61ffa3 / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 18202fa69879a424b77246145c437ac223ab3f3b [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]37#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]38#include <cctype>
39using namespace llvm;
40
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]41static cl::opt<bool> JumpIsExpensiveOverride(
42 "jump-is-expensive", cl::init(false),
43 cl::desc("Do not create extra branches to split comparison logic."),
44 cl::Hidden);
45
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]46/// InitLibcallNames - Set default libcall names.
47///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]48static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]49 Names[RTLIB::SHL_I16] = "__ashlhi3";
50 Names[RTLIB::SHL_I32] = "__ashlsi3";
51 Names[RTLIB::SHL_I64] = "__ashldi3";
52 Names[RTLIB::SHL_I128] = "__ashlti3";
53 Names[RTLIB::SRL_I16] = "__lshrhi3";
54 Names[RTLIB::SRL_I32] = "__lshrsi3";
55 Names[RTLIB::SRL_I64] = "__lshrdi3";
56 Names[RTLIB::SRL_I128] = "__lshrti3";
57 Names[RTLIB::SRA_I16] = "__ashrhi3";
58 Names[RTLIB::SRA_I32] = "__ashrsi3";
59 Names[RTLIB::SRA_I64] = "__ashrdi3";
60 Names[RTLIB::SRA_I128] = "__ashrti3";
61 Names[RTLIB::MUL_I8] = "__mulqi3";
62 Names[RTLIB::MUL_I16] = "__mulhi3";
63 Names[RTLIB::MUL_I32] = "__mulsi3";
64 Names[RTLIB::MUL_I64] = "__muldi3";
65 Names[RTLIB::MUL_I128] = "__multi3";
66 Names[RTLIB::MULO_I32] = "__mulosi4";
67 Names[RTLIB::MULO_I64] = "__mulodi4";
68 Names[RTLIB::MULO_I128] = "__muloti4";
69 Names[RTLIB::SDIV_I8] = "__divqi3";
70 Names[RTLIB::SDIV_I16] = "__divhi3";
71 Names[RTLIB::SDIV_I32] = "__divsi3";
72 Names[RTLIB::SDIV_I64] = "__divdi3";
73 Names[RTLIB::SDIV_I128] = "__divti3";
74 Names[RTLIB::UDIV_I8] = "__udivqi3";
75 Names[RTLIB::UDIV_I16] = "__udivhi3";
76 Names[RTLIB::UDIV_I32] = "__udivsi3";
77 Names[RTLIB::UDIV_I64] = "__udivdi3";
78 Names[RTLIB::UDIV_I128] = "__udivti3";
79 Names[RTLIB::SREM_I8] = "__modqi3";
80 Names[RTLIB::SREM_I16] = "__modhi3";
81 Names[RTLIB::SREM_I32] = "__modsi3";
82 Names[RTLIB::SREM_I64] = "__moddi3";
83 Names[RTLIB::SREM_I128] = "__modti3";
84 Names[RTLIB::UREM_I8] = "__umodqi3";
85 Names[RTLIB::UREM_I16] = "__umodhi3";
86 Names[RTLIB::UREM_I32] = "__umodsi3";
87 Names[RTLIB::UREM_I64] = "__umoddi3";
88 Names[RTLIB::UREM_I128] = "__umodti3";
89
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]90 Names[RTLIB::NEG_I32] = "__negsi2";
91 Names[RTLIB::NEG_I64] = "__negdi2";
92 Names[RTLIB::ADD_F32] = "__addsf3";
93 Names[RTLIB::ADD_F64] = "__adddf3";
94 Names[RTLIB::ADD_F80] = "__addxf3";
95 Names[RTLIB::ADD_F128] = "__addtf3";
96 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
97 Names[RTLIB::SUB_F32] = "__subsf3";
98 Names[RTLIB::SUB_F64] = "__subdf3";
99 Names[RTLIB::SUB_F80] = "__subxf3";
100 Names[RTLIB::SUB_F128] = "__subtf3";
101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102 Names[RTLIB::MUL_F32] = "__mulsf3";
103 Names[RTLIB::MUL_F64] = "__muldf3";
104 Names[RTLIB::MUL_F80] = "__mulxf3";
105 Names[RTLIB::MUL_F128] = "__multf3";
106 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
107 Names[RTLIB::DIV_F32] = "__divsf3";
108 Names[RTLIB::DIV_F64] = "__divdf3";
109 Names[RTLIB::DIV_F80] = "__divxf3";
110 Names[RTLIB::DIV_F128] = "__divtf3";
111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
112 Names[RTLIB::REM_F32] = "fmodf";
113 Names[RTLIB::REM_F64] = "fmod";
114 Names[RTLIB::REM_F80] = "fmodl";
115 Names[RTLIB::REM_F128] = "fmodl";
116 Names[RTLIB::REM_PPCF128] = "fmodl";
117 Names[RTLIB::FMA_F32] = "fmaf";
118 Names[RTLIB::FMA_F64] = "fma";
119 Names[RTLIB::FMA_F80] = "fmal";
120 Names[RTLIB::FMA_F128] = "fmal";
121 Names[RTLIB::FMA_PPCF128] = "fmal";
122 Names[RTLIB::POWI_F32] = "__powisf2";
123 Names[RTLIB::POWI_F64] = "__powidf2";
124 Names[RTLIB::POWI_F80] = "__powixf2";
125 Names[RTLIB::POWI_F128] = "__powitf2";
126 Names[RTLIB::POWI_PPCF128] = "__powitf2";
127 Names[RTLIB::SQRT_F32] = "sqrtf";
128 Names[RTLIB::SQRT_F64] = "sqrt";
129 Names[RTLIB::SQRT_F80] = "sqrtl";
130 Names[RTLIB::SQRT_F128] = "sqrtl";
131 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
132 Names[RTLIB::LOG_F32] = "logf";
133 Names[RTLIB::LOG_F64] = "log";
134 Names[RTLIB::LOG_F80] = "logl";
135 Names[RTLIB::LOG_F128] = "logl";
136 Names[RTLIB::LOG_PPCF128] = "logl";
137 Names[RTLIB::LOG2_F32] = "log2f";
138 Names[RTLIB::LOG2_F64] = "log2";
139 Names[RTLIB::LOG2_F80] = "log2l";
140 Names[RTLIB::LOG2_F128] = "log2l";
141 Names[RTLIB::LOG2_PPCF128] = "log2l";
142 Names[RTLIB::LOG10_F32] = "log10f";
143 Names[RTLIB::LOG10_F64] = "log10";
144 Names[RTLIB::LOG10_F80] = "log10l";
145 Names[RTLIB::LOG10_F128] = "log10l";
146 Names[RTLIB::LOG10_PPCF128] = "log10l";
147 Names[RTLIB::EXP_F32] = "expf";
148 Names[RTLIB::EXP_F64] = "exp";
149 Names[RTLIB::EXP_F80] = "expl";
150 Names[RTLIB::EXP_F128] = "expl";
151 Names[RTLIB::EXP_PPCF128] = "expl";
152 Names[RTLIB::EXP2_F32] = "exp2f";
153 Names[RTLIB::EXP2_F64] = "exp2";
154 Names[RTLIB::EXP2_F80] = "exp2l";
155 Names[RTLIB::EXP2_F128] = "exp2l";
156 Names[RTLIB::EXP2_PPCF128] = "exp2l";
157 Names[RTLIB::SIN_F32] = "sinf";
158 Names[RTLIB::SIN_F64] = "sin";
159 Names[RTLIB::SIN_F80] = "sinl";
160 Names[RTLIB::SIN_F128] = "sinl";
161 Names[RTLIB::SIN_PPCF128] = "sinl";
162 Names[RTLIB::COS_F32] = "cosf";
163 Names[RTLIB::COS_F64] = "cos";
164 Names[RTLIB::COS_F80] = "cosl";
165 Names[RTLIB::COS_F128] = "cosl";
166 Names[RTLIB::COS_PPCF128] = "cosl";
167 Names[RTLIB::POW_F32] = "powf";
168 Names[RTLIB::POW_F64] = "pow";
169 Names[RTLIB::POW_F80] = "powl";
170 Names[RTLIB::POW_F128] = "powl";
171 Names[RTLIB::POW_PPCF128] = "powl";
172 Names[RTLIB::CEIL_F32] = "ceilf";
173 Names[RTLIB::CEIL_F64] = "ceil";
174 Names[RTLIB::CEIL_F80] = "ceill";
175 Names[RTLIB::CEIL_F128] = "ceill";
176 Names[RTLIB::CEIL_PPCF128] = "ceill";
177 Names[RTLIB::TRUNC_F32] = "truncf";
178 Names[RTLIB::TRUNC_F64] = "trunc";
179 Names[RTLIB::TRUNC_F80] = "truncl";
180 Names[RTLIB::TRUNC_F128] = "truncl";
181 Names[RTLIB::TRUNC_PPCF128] = "truncl";
182 Names[RTLIB::RINT_F32] = "rintf";
183 Names[RTLIB::RINT_F64] = "rint";
184 Names[RTLIB::RINT_F80] = "rintl";
185 Names[RTLIB::RINT_F128] = "rintl";
186 Names[RTLIB::RINT_PPCF128] = "rintl";
187 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
188 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
189 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
190 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
191 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]192 Names[RTLIB::ROUND_F32] = "roundf";
193 Names[RTLIB::ROUND_F64] = "round";
194 Names[RTLIB::ROUND_F80] = "roundl";
195 Names[RTLIB::ROUND_F128] = "roundl";
196 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]197 Names[RTLIB::FLOOR_F32] = "floorf";
198 Names[RTLIB::FLOOR_F64] = "floor";
199 Names[RTLIB::FLOOR_F80] = "floorl";
200 Names[RTLIB::FLOOR_F128] = "floorl";
201 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]202 Names[RTLIB::FMIN_F32] = "fminf";
203 Names[RTLIB::FMIN_F64] = "fmin";
204 Names[RTLIB::FMIN_F80] = "fminl";
205 Names[RTLIB::FMIN_F128] = "fminl";
206 Names[RTLIB::FMIN_PPCF128] = "fminl";
207 Names[RTLIB::FMAX_F32] = "fmaxf";
208 Names[RTLIB::FMAX_F64] = "fmax";
209 Names[RTLIB::FMAX_F80] = "fmaxl";
210 Names[RTLIB::FMAX_F128] = "fmaxl";
211 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]212 Names[RTLIB::ROUND_F32] = "roundf";
213 Names[RTLIB::ROUND_F64] = "round";
214 Names[RTLIB::ROUND_F80] = "roundl";
215 Names[RTLIB::ROUND_F128] = "roundl";
216 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]217 Names[RTLIB::COPYSIGN_F32] = "copysignf";
218 Names[RTLIB::COPYSIGN_F64] = "copysign";
219 Names[RTLIB::COPYSIGN_F80] = "copysignl";
220 Names[RTLIB::COPYSIGN_F128] = "copysignl";
221 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]222 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
223 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]224 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
225 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
226 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]227 if (TT.isOSDarwin()) {
228 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
229 // of the gnueabi-style __gnu_*_ieee.
230 // FIXME: What about other targets?
231 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
232 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
233 } else {
234 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
235 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
236 }
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]237 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
238 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
239 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
240 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]241 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
242 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
243 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]244 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]245 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
246 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]247 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]248 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
249 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
250 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]251 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
252 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
253 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
254 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
255 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
256 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
257 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
258 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
259 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]260 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]261 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
262 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]263 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
264 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
265 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]266 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
267 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
268 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
269 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
270 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
271 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
272 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
273 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
274 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
275 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
276 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
277 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
278 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
279 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
280 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
281 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]282 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]283 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
284 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
285 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
286 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
287 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
288 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
289 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
290 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
291 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
292 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
293 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
294 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
295 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
296 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]297 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]298 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
299 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
300 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
301 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
302 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
303 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
304 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
305 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
306 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
307 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
308 Names[RTLIB::OEQ_F32] = "__eqsf2";
309 Names[RTLIB::OEQ_F64] = "__eqdf2";
310 Names[RTLIB::OEQ_F128] = "__eqtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]311 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]312 Names[RTLIB::UNE_F32] = "__nesf2";
313 Names[RTLIB::UNE_F64] = "__nedf2";
314 Names[RTLIB::UNE_F128] = "__netf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]315 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]316 Names[RTLIB::OGE_F32] = "__gesf2";
317 Names[RTLIB::OGE_F64] = "__gedf2";
318 Names[RTLIB::OGE_F128] = "__getf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]319 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]320 Names[RTLIB::OLT_F32] = "__ltsf2";
321 Names[RTLIB::OLT_F64] = "__ltdf2";
322 Names[RTLIB::OLT_F128] = "__lttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]323 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]324 Names[RTLIB::OLE_F32] = "__lesf2";
325 Names[RTLIB::OLE_F64] = "__ledf2";
326 Names[RTLIB::OLE_F128] = "__letf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]327 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]328 Names[RTLIB::OGT_F32] = "__gtsf2";
329 Names[RTLIB::OGT_F64] = "__gtdf2";
330 Names[RTLIB::OGT_F128] = "__gttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]331 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]332 Names[RTLIB::UO_F32] = "__unordsf2";
333 Names[RTLIB::UO_F64] = "__unorddf2";
334 Names[RTLIB::UO_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]335 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]336 Names[RTLIB::O_F32] = "__unordsf2";
337 Names[RTLIB::O_F64] = "__unorddf2";
338 Names[RTLIB::O_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]339 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]340 Names[RTLIB::MEMCPY] = "memcpy";
341 Names[RTLIB::MEMMOVE] = "memmove";
342 Names[RTLIB::MEMSET] = "memset";
343 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
344 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
345 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
346 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
347 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]348 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]349 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
350 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
351 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
352 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]353 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]354 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
355 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
356 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
357 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]358 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]359 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
360 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
361 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
362 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]363 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]364 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
365 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
366 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
367 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]368 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]369 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
370 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
371 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
372 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]373 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]374 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
375 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
376 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
377 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]378 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]379 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
380 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
381 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
382 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]383 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]384 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
385 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
386 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
387 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
388 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
389 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
390 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
391 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
392 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
393 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
394 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
395 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
396 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
397 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
398 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
399 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
400 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
401 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
402 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
403 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]404
405 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
406 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1";
407 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2";
408 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4";
409 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8";
410 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16";
411
412 Names[RTLIB::ATOMIC_STORE] = "__atomic_store";
413 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1";
414 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2";
415 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4";
416 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8";
417 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16";
418
419 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange";
420 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1";
421 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2";
422 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4";
423 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8";
424 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16";
425
426 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange";
427 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1";
428 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2";
429 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4";
430 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8";
431 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16";
432
433 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1";
434 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2";
435 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4";
436 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8";
437 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16";
438 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1";
439 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2";
440 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4";
441 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8";
442 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16";
443 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1";
444 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2";
445 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4";
446 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8";
447 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16";
448 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1";
449 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2";
450 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4";
451 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8";
452 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16";
453 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1";
454 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2";
455 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4";
456 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8";
457 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16";
458 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1";
459 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2";
460 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4";
461 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8";
462 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16";
463
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]464 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]465 Names[RTLIB::SINCOS_F32] = "sincosf";
466 Names[RTLIB::SINCOS_F64] = "sincos";
467 Names[RTLIB::SINCOS_F80] = "sincosl";
468 Names[RTLIB::SINCOS_F128] = "sincosl";
469 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]470 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]471
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]472 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]473 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]474 }
Sanjoy Dasdf9ae702016-03-24 20:23:29 +0000[diff] [blame]475
476 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]477}
478
479/// InitLibcallCallingConvs - Set default libcall CallingConvs.
480///
481static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
482 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
483 CCs[i] = CallingConv::C;
484 }
485}
486
487/// getFPEXT - Return the FPEXT_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]490 if (OpVT == MVT::f16) {
491 if (RetVT == MVT::f32)
492 return FPEXT_F16_F32;
493 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]494 if (RetVT == MVT::f64)
495 return FPEXT_F32_F64;
496 if (RetVT == MVT::f128)
497 return FPEXT_F32_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]498 if (RetVT == MVT::ppcf128)
499 return FPEXT_F32_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]500 } else if (OpVT == MVT::f64) {
501 if (RetVT == MVT::f128)
502 return FPEXT_F64_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]503 else if (RetVT == MVT::ppcf128)
504 return FPEXT_F64_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]505 }
506
507 return UNKNOWN_LIBCALL;
508}
509
510/// getFPROUND - Return the FPROUND_*_* value for the given types, or
511/// UNKNOWN_LIBCALL if there is none.
512RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]513 if (RetVT == MVT::f16) {
514 if (OpVT == MVT::f32)
515 return FPROUND_F32_F16;
516 if (OpVT == MVT::f64)
517 return FPROUND_F64_F16;
518 if (OpVT == MVT::f80)
519 return FPROUND_F80_F16;
520 if (OpVT == MVT::f128)
521 return FPROUND_F128_F16;
522 if (OpVT == MVT::ppcf128)
523 return FPROUND_PPCF128_F16;
524 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]525 if (OpVT == MVT::f64)
526 return FPROUND_F64_F32;
527 if (OpVT == MVT::f80)
528 return FPROUND_F80_F32;
529 if (OpVT == MVT::f128)
530 return FPROUND_F128_F32;
531 if (OpVT == MVT::ppcf128)
532 return FPROUND_PPCF128_F32;
533 } else if (RetVT == MVT::f64) {
534 if (OpVT == MVT::f80)
535 return FPROUND_F80_F64;
536 if (OpVT == MVT::f128)
537 return FPROUND_F128_F64;
538 if (OpVT == MVT::ppcf128)
539 return FPROUND_PPCF128_F64;
540 }
541
542 return UNKNOWN_LIBCALL;
543}
544
545/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
546/// UNKNOWN_LIBCALL if there is none.
547RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
548 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]549 if (RetVT == MVT::i32)
550 return FPTOSINT_F32_I32;
551 if (RetVT == MVT::i64)
552 return FPTOSINT_F32_I64;
553 if (RetVT == MVT::i128)
554 return FPTOSINT_F32_I128;
555 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]556 if (RetVT == MVT::i32)
557 return FPTOSINT_F64_I32;
558 if (RetVT == MVT::i64)
559 return FPTOSINT_F64_I64;
560 if (RetVT == MVT::i128)
561 return FPTOSINT_F64_I128;
562 } else if (OpVT == MVT::f80) {
563 if (RetVT == MVT::i32)
564 return FPTOSINT_F80_I32;
565 if (RetVT == MVT::i64)
566 return FPTOSINT_F80_I64;
567 if (RetVT == MVT::i128)
568 return FPTOSINT_F80_I128;
569 } else if (OpVT == MVT::f128) {
570 if (RetVT == MVT::i32)
571 return FPTOSINT_F128_I32;
572 if (RetVT == MVT::i64)
573 return FPTOSINT_F128_I64;
574 if (RetVT == MVT::i128)
575 return FPTOSINT_F128_I128;
576 } else if (OpVT == MVT::ppcf128) {
577 if (RetVT == MVT::i32)
578 return FPTOSINT_PPCF128_I32;
579 if (RetVT == MVT::i64)
580 return FPTOSINT_PPCF128_I64;
581 if (RetVT == MVT::i128)
582 return FPTOSINT_PPCF128_I128;
583 }
584 return UNKNOWN_LIBCALL;
585}
586
587/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
588/// UNKNOWN_LIBCALL if there is none.
589RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
590 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]591 if (RetVT == MVT::i32)
592 return FPTOUINT_F32_I32;
593 if (RetVT == MVT::i64)
594 return FPTOUINT_F32_I64;
595 if (RetVT == MVT::i128)
596 return FPTOUINT_F32_I128;
597 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]598 if (RetVT == MVT::i32)
599 return FPTOUINT_F64_I32;
600 if (RetVT == MVT::i64)
601 return FPTOUINT_F64_I64;
602 if (RetVT == MVT::i128)
603 return FPTOUINT_F64_I128;
604 } else if (OpVT == MVT::f80) {
605 if (RetVT == MVT::i32)
606 return FPTOUINT_F80_I32;
607 if (RetVT == MVT::i64)
608 return FPTOUINT_F80_I64;
609 if (RetVT == MVT::i128)
610 return FPTOUINT_F80_I128;
611 } else if (OpVT == MVT::f128) {
612 if (RetVT == MVT::i32)
613 return FPTOUINT_F128_I32;
614 if (RetVT == MVT::i64)
615 return FPTOUINT_F128_I64;
616 if (RetVT == MVT::i128)
617 return FPTOUINT_F128_I128;
618 } else if (OpVT == MVT::ppcf128) {
619 if (RetVT == MVT::i32)
620 return FPTOUINT_PPCF128_I32;
621 if (RetVT == MVT::i64)
622 return FPTOUINT_PPCF128_I64;
623 if (RetVT == MVT::i128)
624 return FPTOUINT_PPCF128_I128;
625 }
626 return UNKNOWN_LIBCALL;
627}
628
629/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
630/// UNKNOWN_LIBCALL if there is none.
631RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
632 if (OpVT == MVT::i32) {
633 if (RetVT == MVT::f32)
634 return SINTTOFP_I32_F32;
635 if (RetVT == MVT::f64)
636 return SINTTOFP_I32_F64;
637 if (RetVT == MVT::f80)
638 return SINTTOFP_I32_F80;
639 if (RetVT == MVT::f128)
640 return SINTTOFP_I32_F128;
641 if (RetVT == MVT::ppcf128)
642 return SINTTOFP_I32_PPCF128;
643 } else if (OpVT == MVT::i64) {
644 if (RetVT == MVT::f32)
645 return SINTTOFP_I64_F32;
646 if (RetVT == MVT::f64)
647 return SINTTOFP_I64_F64;
648 if (RetVT == MVT::f80)
649 return SINTTOFP_I64_F80;
650 if (RetVT == MVT::f128)
651 return SINTTOFP_I64_F128;
652 if (RetVT == MVT::ppcf128)
653 return SINTTOFP_I64_PPCF128;
654 } else if (OpVT == MVT::i128) {
655 if (RetVT == MVT::f32)
656 return SINTTOFP_I128_F32;
657 if (RetVT == MVT::f64)
658 return SINTTOFP_I128_F64;
659 if (RetVT == MVT::f80)
660 return SINTTOFP_I128_F80;
661 if (RetVT == MVT::f128)
662 return SINTTOFP_I128_F128;
663 if (RetVT == MVT::ppcf128)
664 return SINTTOFP_I128_PPCF128;
665 }
666 return UNKNOWN_LIBCALL;
667}
668
669/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
670/// UNKNOWN_LIBCALL if there is none.
671RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
672 if (OpVT == MVT::i32) {
673 if (RetVT == MVT::f32)
674 return UINTTOFP_I32_F32;
675 if (RetVT == MVT::f64)
676 return UINTTOFP_I32_F64;
677 if (RetVT == MVT::f80)
678 return UINTTOFP_I32_F80;
679 if (RetVT == MVT::f128)
680 return UINTTOFP_I32_F128;
681 if (RetVT == MVT::ppcf128)
682 return UINTTOFP_I32_PPCF128;
683 } else if (OpVT == MVT::i64) {
684 if (RetVT == MVT::f32)
685 return UINTTOFP_I64_F32;
686 if (RetVT == MVT::f64)
687 return UINTTOFP_I64_F64;
688 if (RetVT == MVT::f80)
689 return UINTTOFP_I64_F80;
690 if (RetVT == MVT::f128)
691 return UINTTOFP_I64_F128;
692 if (RetVT == MVT::ppcf128)
693 return UINTTOFP_I64_PPCF128;
694 } else if (OpVT == MVT::i128) {
695 if (RetVT == MVT::f32)
696 return UINTTOFP_I128_F32;
697 if (RetVT == MVT::f64)
698 return UINTTOFP_I128_F64;
699 if (RetVT == MVT::f80)
700 return UINTTOFP_I128_F80;
701 if (RetVT == MVT::f128)
702 return UINTTOFP_I128_F128;
703 if (RetVT == MVT::ppcf128)
704 return UINTTOFP_I128_PPCF128;
705 }
706 return UNKNOWN_LIBCALL;
707}
708
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]709RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]710#define OP_TO_LIBCALL(Name, Enum) \
711 case Name: \
712 switch (VT.SimpleTy) { \
713 default: \
714 return UNKNOWN_LIBCALL; \
715 case MVT::i8: \
716 return Enum##_1; \
717 case MVT::i16: \
718 return Enum##_2; \
719 case MVT::i32: \
720 return Enum##_4; \
721 case MVT::i64: \
722 return Enum##_8; \
723 case MVT::i128: \
724 return Enum##_16; \
725 }
726
727 switch (Opc) {
728 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
729 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
730 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
731 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
732 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
733 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
734 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
735 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
736 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
737 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
738 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
739 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
740 }
741
742#undef OP_TO_LIBCALL
743
744 return UNKNOWN_LIBCALL;
745}
746
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]747/// InitCmpLibcallCCs - Set default comparison libcall CC.
748///
749static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
750 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
751 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
752 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
753 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]754 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]755 CCs[RTLIB::UNE_F32] = ISD::SETNE;
756 CCs[RTLIB::UNE_F64] = ISD::SETNE;
757 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]758 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]759 CCs[RTLIB::OGE_F32] = ISD::SETGE;
760 CCs[RTLIB::OGE_F64] = ISD::SETGE;
761 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]762 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]763 CCs[RTLIB::OLT_F32] = ISD::SETLT;
764 CCs[RTLIB::OLT_F64] = ISD::SETLT;
765 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]766 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]767 CCs[RTLIB::OLE_F32] = ISD::SETLE;
768 CCs[RTLIB::OLE_F64] = ISD::SETLE;
769 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]770 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]771 CCs[RTLIB::OGT_F32] = ISD::SETGT;
772 CCs[RTLIB::OGT_F64] = ISD::SETGT;
773 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]774 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]775 CCs[RTLIB::UO_F32] = ISD::SETNE;
776 CCs[RTLIB::UO_F64] = ISD::SETNE;
777 CCs[RTLIB::UO_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]778 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]779 CCs[RTLIB::O_F32] = ISD::SETEQ;
780 CCs[RTLIB::O_F64] = ISD::SETEQ;
781 CCs[RTLIB::O_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]782 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]783}
784
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]785/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]786TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]787 initActions();
788
789 // Perform these initializations only once.
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]790 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
791 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
792 = MaxStoresPerMemmoveOptSize = 4;
793 UseUnderscoreSetJmp = false;
794 UseUnderscoreLongJmp = false;
795 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]796 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]797 HasExtractBitsInsn = false;
Matt Arsenaultbf0db912015-01-13 20:53:23 +0000[diff] [blame]798 FsqrtIsCheap = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]799 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]800 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]801 MaskAndBranchFoldingIsLegal = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]802 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]803 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]804 StackPointerRegisterToSaveRestore = 0;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]805 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]806 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]807 BooleanVectorContents = UndefinedBooleanContent;
808 SchedPreferenceInfo = Sched::ILP;
809 JumpBufSize = 0;
810 JumpBufAlignment = 0;
811 MinFunctionAlignment = 0;
812 PrefFunctionAlignment = 0;
813 PrefLoopAlignment = 0;
Matt Arsenaultd8fed1b2015-11-11 18:44:33 +0000[diff] [blame]814 GatherAllAliasesMaxDepth = 6;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]815 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]816 MinimumJumpTableEntries = 4;
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]817 // TODO: the default will be switched to 0 in the next commit, along
818 // with the Target-specific changes necessary.
819 MaxAtomicSizeInBitsSupported = 1024;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]820
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]821 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
822
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]823 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]824 InitCmpLibcallCCs(CmpLibcallCCs);
825 InitLibcallCallingConvs(LibcallCallingConvs);
826}
827
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]828void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]829 // All operations default to being supported.
830 memset(OpActions, 0, sizeof(OpActions));
831 memset(LoadExtActions, 0, sizeof(LoadExtActions));
832 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
833 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
834 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Craig Topper00230802016-04-08 07:10:46 +0000[diff] [blame]835 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
836 std::fill(std::begin(TargetDAGCombineArray),
837 std::end(TargetDAGCombineArray), 0);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]838
839 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]840 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]841 // Default all indexed load / store to expand.
842 for (unsigned IM = (unsigned)ISD::PRE_INC;
843 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]844 setIndexedLoadAction(IM, VT, Expand);
845 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]846 }
847
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]848 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]849 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]850
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]851 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]852 setOperationAction(ISD::FGETSIGN, VT, Expand);
853 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
854 setOperationAction(ISD::FMINNUM, VT, Expand);
855 setOperationAction(ISD::FMAXNUM, VT, Expand);
James Molloy01cdecc2015-08-11 09:13:05 +0000[diff] [blame]856 setOperationAction(ISD::FMINNAN, VT, Expand);
857 setOperationAction(ISD::FMAXNAN, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]858 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]859 setOperationAction(ISD::SMIN, VT, Expand);
860 setOperationAction(ISD::SMAX, VT, Expand);
861 setOperationAction(ISD::UMIN, VT, Expand);
862 setOperationAction(ISD::UMAX, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]863
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]864 // Overflow operations default to expand
865 setOperationAction(ISD::SADDO, VT, Expand);
866 setOperationAction(ISD::SSUBO, VT, Expand);
867 setOperationAction(ISD::UADDO, VT, Expand);
868 setOperationAction(ISD::USUBO, VT, Expand);
869 setOperationAction(ISD::SMULO, VT, Expand);
870 setOperationAction(ISD::UMULO, VT, Expand);
Hal Finkelcd8664c2015-12-11 23:11:52 +0000[diff] [blame]871
James Molloy90111f72015-11-12 12:29:09 +0000[diff] [blame]872 setOperationAction(ISD::BITREVERSE, VT, Expand);
873
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]874 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]875 setOperationAction(ISD::FROUND, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]876
877 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]878 if (VT.isVector()) {
879 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
880 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]883 }
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]884
885 // For most targets @llvm.get.dynamic.area.offest just returns 0.
886 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]887 }
888
889 // Most targets ignore the @llvm.prefetch intrinsic.
890 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
891
Ahmed Bougachaf9c19da2015-08-28 01:49:59 +0000[diff] [blame]892 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
893 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
894
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]895 // ConstantFP nodes default to expand. Targets can either change this to
896 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
897 // to optimize expansions for certain constants.
898 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
899 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
900 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
901 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
902 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
903
904 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]905 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
906 setOperationAction(ISD::FLOG , VT, Expand);
907 setOperationAction(ISD::FLOG2, VT, Expand);
908 setOperationAction(ISD::FLOG10, VT, Expand);
909 setOperationAction(ISD::FEXP , VT, Expand);
910 setOperationAction(ISD::FEXP2, VT, Expand);
911 setOperationAction(ISD::FFLOOR, VT, Expand);
912 setOperationAction(ISD::FMINNUM, VT, Expand);
913 setOperationAction(ISD::FMAXNUM, VT, Expand);
914 setOperationAction(ISD::FNEARBYINT, VT, Expand);
915 setOperationAction(ISD::FCEIL, VT, Expand);
916 setOperationAction(ISD::FRINT, VT, Expand);
917 setOperationAction(ISD::FTRUNC, VT, Expand);
918 setOperationAction(ISD::FROUND, VT, Expand);
919 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]920
921 // Default ISD::TRAP to expand (which turns it into abort).
922 setOperationAction(ISD::TRAP, MVT::Other, Expand);
923
924 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
925 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
926 //
927 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]928}
929
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]930MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
931 EVT) const {
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]932 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]933}
934
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]935EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
936 const DataLayout &DL) const {
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]937 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
938 if (LHSTy.isVector())
939 return LHSTy;
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]940 return getScalarShiftAmountTy(DL, LHSTy);
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]941}
942
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]943/// canOpTrap - Returns true if the operation can trap for the value type.
944/// VT must be a legal type.
945bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
946 assert(isTypeLegal(VT));
947 switch (Op) {
948 default:
949 return false;
950 case ISD::FDIV:
951 case ISD::FREM:
952 case ISD::SDIV:
953 case ISD::UDIV:
954 case ISD::SREM:
955 case ISD::UREM:
956 return true;
957 }
958}
959
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]960void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
961 // If the command-line option was specified, ignore this request.
962 if (!JumpIsExpensiveOverride.getNumOccurrences())
963 JumpIsExpensive = isExpensive;
964}
965
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]966TargetLoweringBase::LegalizeKind
967TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
968 // If this is a simple type, use the ComputeRegisterProp mechanism.
969 if (VT.isSimple()) {
970 MVT SVT = VT.getSimpleVT();
971 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
972 MVT NVT = TransformToType[SVT.SimpleTy];
973 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
974
975 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
976 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
977 "Promote may not follow Expand or Promote");
978
979 if (LA == TypeSplitVector)
980 return LegalizeKind(LA,
981 EVT::getVectorVT(Context, SVT.getVectorElementType(),
982 SVT.getVectorNumElements() / 2));
983 if (LA == TypeScalarizeVector)
984 return LegalizeKind(LA, SVT.getVectorElementType());
985 return LegalizeKind(LA, NVT);
986 }
987
988 // Handle Extended Scalar Types.
989 if (!VT.isVector()) {
990 assert(VT.isInteger() && "Float types must be simple");
991 unsigned BitSize = VT.getSizeInBits();
992 // First promote to a power-of-two size, then expand if necessary.
993 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
994 EVT NVT = VT.getRoundIntegerType(Context);
995 assert(NVT != VT && "Unable to round integer VT");
996 LegalizeKind NextStep = getTypeConversion(Context, NVT);
997 // Avoid multi-step promotion.
998 if (NextStep.first == TypePromoteInteger)
999 return NextStep;
1000 // Return rounded integer type.
1001 return LegalizeKind(TypePromoteInteger, NVT);
1002 }
1003
1004 return LegalizeKind(TypeExpandInteger,
1005 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1006 }
1007
1008 // Handle vector types.
1009 unsigned NumElts = VT.getVectorNumElements();
1010 EVT EltVT = VT.getVectorElementType();
1011
1012 // Vectors with only one element are always scalarized.
1013 if (NumElts == 1)
1014 return LegalizeKind(TypeScalarizeVector, EltVT);
1015
1016 // Try to widen vector elements until the element type is a power of two and
1017 // promote it to a legal type later on, for example:
1018 // <3 x i8> -> <4 x i8> -> <4 x i32>
1019 if (EltVT.isInteger()) {
1020 // Vectors with a number of elements that is not a power of two are always
1021 // widened, for example <3 x i8> -> <4 x i8>.
1022 if (!VT.isPow2VectorType()) {
1023 NumElts = (unsigned)NextPowerOf2(NumElts);
1024 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1025 return LegalizeKind(TypeWidenVector, NVT);
1026 }
1027
1028 // Examine the element type.
1029 LegalizeKind LK = getTypeConversion(Context, EltVT);
1030
1031 // If type is to be expanded, split the vector.
1032 // <4 x i140> -> <2 x i140>
1033 if (LK.first == TypeExpandInteger)
1034 return LegalizeKind(TypeSplitVector,
1035 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1036
1037 // Promote the integer element types until a legal vector type is found
1038 // or until the element integer type is too big. If a legal type was not
1039 // found, fallback to the usual mechanism of widening/splitting the
1040 // vector.
1041 EVT OldEltVT = EltVT;
1042 while (1) {
1043 // Increase the bitwidth of the element to the next pow-of-two
1044 // (which is greater than 8 bits).
1045 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1046 .getRoundIntegerType(Context);
1047
1048 // Stop trying when getting a non-simple element type.
1049 // Note that vector elements may be greater than legal vector element
1050 // types. Example: X86 XMM registers hold 64bit element on 32bit
1051 // systems.
1052 if (!EltVT.isSimple())
1053 break;
1054
1055 // Build a new vector type and check if it is legal.
1056 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1057 // Found a legal promoted vector type.
1058 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1059 return LegalizeKind(TypePromoteInteger,
1060 EVT::getVectorVT(Context, EltVT, NumElts));
1061 }
1062
1063 // Reset the type to the unexpanded type if we did not find a legal vector
1064 // type with a promoted vector element type.
1065 EltVT = OldEltVT;
1066 }
1067
1068 // Try to widen the vector until a legal type is found.
1069 // If there is no wider legal type, split the vector.
1070 while (1) {
1071 // Round up to the next power of 2.
1072 NumElts = (unsigned)NextPowerOf2(NumElts);
1073
1074 // If there is no simple vector type with this many elements then there
1075 // cannot be a larger legal vector type. Note that this assumes that
1076 // there are no skipped intermediate vector types in the simple types.
1077 if (!EltVT.isSimple())
1078 break;
1079 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1080 if (LargerVector == MVT())
1081 break;
1082
1083 // If this type is legal then widen the vector.
1084 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1085 return LegalizeKind(TypeWidenVector, LargerVector);
1086 }
1087
1088 // Widen odd vectors to next power of two.
1089 if (!VT.isPow2VectorType()) {
1090 EVT NVT = VT.getPow2VectorType(Context);
1091 return LegalizeKind(TypeWidenVector, NVT);
1092 }
1093
1094 // Vectors with illegal element types are expanded.
1095 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1096 return LegalizeKind(TypeSplitVector, NVT);
1097}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1098
1099static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1100 unsigned &NumIntermediates,
1101 MVT &RegisterVT,
1102 TargetLoweringBase *TLI) {
1103 // Figure out the right, legal destination reg to copy into.
1104 unsigned NumElts = VT.getVectorNumElements();
1105 MVT EltTy = VT.getVectorElementType();
1106
1107 unsigned NumVectorRegs = 1;
1108
1109 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1110 // could break down into LHS/RHS like LegalizeDAG does.
1111 if (!isPowerOf2_32(NumElts)) {
1112 NumVectorRegs = NumElts;
1113 NumElts = 1;
1114 }
1115
1116 // Divide the input until we get to a supported size. This will always
1117 // end with a scalar if the target doesn't support vectors.
1118 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1119 NumElts >>= 1;
1120 NumVectorRegs <<= 1;
1121 }
1122
1123 NumIntermediates = NumVectorRegs;
1124
1125 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1126 if (!TLI->isTypeLegal(NewVT))
1127 NewVT = EltTy;
1128 IntermediateVT = NewVT;
1129
1130 unsigned NewVTSize = NewVT.getSizeInBits();
1131
1132 // Convert sizes such as i33 to i64.
1133 if (!isPowerOf2_32(NewVTSize))
1134 NewVTSize = NextPowerOf2(NewVTSize);
1135
1136 MVT DestVT = TLI->getRegisterType(NewVT);
1137 RegisterVT = DestVT;
1138 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1139 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1140
1141 // Otherwise, promotion or legal types use the same number of registers as
1142 // the vector decimated to the appropriate level.
1143 return NumVectorRegs;
1144}
1145
1146/// isLegalRC - Return true if the value types that can be represented by the
1147/// specified register class are all legal.
1148bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
1149 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1150 I != E; ++I) {
1151 if (isTypeLegal(*I))
1152 return true;
1153 }
1154 return false;
1155}
1156
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1157/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1158/// sequence of memory operands that is recognized by PrologEpilogInserter.
1159MachineBasicBlock*
1160TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
1161 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1162 MachineFunction &MF = *MI->getParent()->getParent();
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1163 MachineFrameInfo &MFI = *MF.getFrameInfo();
1164
1165 // We're handling multiple types of operands here:
1166 // PATCHPOINT MetaArgs - live-in, read only, direct
1167 // STATEPOINT Deopt Spill - live-through, read only, indirect
1168 // STATEPOINT Deopt Alloca - live-through, read only, direct
1169 // (We're currently conservative and mark the deopt slots read/write in
1170 // practice.)
1171 // STATEPOINT GC Spill - live-through, read/write, indirect
1172 // STATEPOINT GC Alloca - live-through, read/write, direct
1173 // The live-in vs live-through is handled already (the live through ones are
1174 // all stack slots), but we need to handle the different type of stackmap
1175 // operands and memory effects here.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1176
1177 // MI changes inside this loop as we grow operands.
1178 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1179 MachineOperand &MO = MI->getOperand(OperIdx);
1180 if (!MO.isFI())
1181 continue;
1182
1183 // foldMemoryOperand builds a new MI after replacing a single FI operand
1184 // with the canonical set of five x86 addressing-mode operands.
1185 int FI = MO.getIndex();
1186 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1187
1188 // Copy operands before the frame-index.
1189 for (unsigned i = 0; i < OperIdx; ++i)
1190 MIB.addOperand(MI->getOperand(i));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1191 // Add frame index operands recognized by stackmaps.cpp
1192 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1193 // indirect-mem-ref tag, size, #FI, offset.
1194 // Used for spills inserted by StatepointLowering. This codepath is not
1195 // used for patchpoints/stackmaps at all, for these spilling is done via
1196 // foldMemoryOperand callback only.
1197 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1198 MIB.addImm(StackMaps::IndirectMemRefOp);
1199 MIB.addImm(MFI.getObjectSize(FI));
1200 MIB.addOperand(MI->getOperand(OperIdx));
1201 MIB.addImm(0);
1202 } else {
1203 // direct-mem-ref tag, #FI, offset.
1204 // Used by patchpoint, and direct alloca arguments to statepoints
1205 MIB.addImm(StackMaps::DirectMemRefOp);
1206 MIB.addOperand(MI->getOperand(OperIdx));
1207 MIB.addImm(0);
1208 }
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1209 // Copy the operands after the frame index.
1210 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1211 MIB.addOperand(MI->getOperand(i));
1212
1213 // Inherit previous memory operands.
1214 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1215 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1216
1217 // Add a new memory operand for this FI.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1218 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1219
1220 unsigned Flags = MachineMemOperand::MOLoad;
1221 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1222 Flags |= MachineMemOperand::MOStore;
1223 Flags |= MachineMemOperand::MOVolatile;
1224 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1225 MachineMemOperand *MMO = MF.getMachineMemOperand(
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]1226 MachinePointerInfo::getFixedStack(MF, FI), Flags,
Mehdi Aminibd7287e2015-07-16 06:11:10 +0000[diff] [blame]1227 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1228 MIB->addMemOperand(MF, MMO);
1229
1230 // Replace the instruction and update the operand index.
1231 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1232 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1233 MI->eraseFromParent();
1234 MI = MIB;
1235 }
1236 return MBB;
1237}
1238
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1239/// findRepresentativeClass - Return the largest legal super-reg register class
1240/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1241// This function is in TargetLowering because it uses RegClassForVT which would
1242// need to be moved to TargetRegisterInfo and would necessitate moving
1243// isTypeLegal over as well - a massive change that would just require
1244// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1245std::pair<const TargetRegisterClass *, uint8_t>
1246TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1247 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1248 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1249 if (!RC)
1250 return std::make_pair(RC, 0);
1251
1252 // Compute the set of all super-register classes.
1253 BitVector SuperRegRC(TRI->getNumRegClasses());
1254 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1255 SuperRegRC.setBitsInMask(RCI.getMask());
1256
1257 // Find the first legal register class with the largest spill size.
1258 const TargetRegisterClass *BestRC = RC;
1259 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1260 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1261 // We want the largest possible spill size.
1262 if (SuperRC->getSize() <= BestRC->getSize())
1263 continue;
1264 if (!isLegalRC(SuperRC))
1265 continue;
1266 BestRC = SuperRC;
1267 }
1268 return std::make_pair(BestRC, 1);
1269}
1270
1271/// computeRegisterProperties - Once all of the register classes are added,
1272/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1273void TargetLoweringBase::computeRegisterProperties(
1274 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1275 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1276 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1277
1278 // Everything defaults to needing one register.
1279 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1280 NumRegistersForVT[i] = 1;
1281 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1282 }
1283 // ...except isVoid, which doesn't need any registers.
1284 NumRegistersForVT[MVT::isVoid] = 0;
1285
1286 // Find the largest integer register class.
1287 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1288 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1289 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1290
1291 // Every integer value type larger than this largest register takes twice as
1292 // many registers to represent as the previous ValueType.
1293 for (unsigned ExpandedReg = LargestIntReg + 1;
1294 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1295 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1296 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1297 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1298 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1299 TypeExpandInteger);
1300 }
1301
1302 // Inspect all of the ValueType's smaller than the largest integer
1303 // register to see which ones need promotion.
1304 unsigned LegalIntReg = LargestIntReg;
1305 for (unsigned IntReg = LargestIntReg - 1;
1306 IntReg >= (unsigned)MVT::i1; --IntReg) {
1307 MVT IVT = (MVT::SimpleValueType)IntReg;
1308 if (isTypeLegal(IVT)) {
1309 LegalIntReg = IntReg;
1310 } else {
1311 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1312 (const MVT::SimpleValueType)LegalIntReg;
1313 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1314 }
1315 }
1316
1317 // ppcf128 type is really two f64's.
1318 if (!isTypeLegal(MVT::ppcf128)) {
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]1319 if (isTypeLegal(MVT::f64)) {
1320 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1321 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1322 TransformToType[MVT::ppcf128] = MVT::f64;
1323 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1324 } else {
1325 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1326 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1327 TransformToType[MVT::ppcf128] = MVT::i128;
1328 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1329 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1330 }
1331
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1332 // Decide how to handle f128. If the target does not have native f128 support,
1333 // expand it to i128 and we will be generating soft float library calls.
1334 if (!isTypeLegal(MVT::f128)) {
1335 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1336 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1337 TransformToType[MVT::f128] = MVT::i128;
1338 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1339 }
1340
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1341 // Decide how to handle f64. If the target does not have native f64 support,
1342 // expand it to i64 and we will be generating soft float library calls.
1343 if (!isTypeLegal(MVT::f64)) {
1344 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1345 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1346 TransformToType[MVT::f64] = MVT::i64;
1347 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1348 }
1349
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1350 // Decide how to handle f32. If the target does not have native f32 support,
1351 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1352 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1353 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1354 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1355 TransformToType[MVT::f32] = MVT::i32;
1356 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1357 }
1358
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1359 // Decide how to handle f16. If the target does not have native f16 support,
1360 // promote it to f32, because there are no f16 library calls (except for
1361 // conversions).
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1362 if (!isTypeLegal(MVT::f16)) {
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1363 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1364 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1365 TransformToType[MVT::f16] = MVT::f32;
1366 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1367 }
1368
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1369 // Loop over all of the vector value types to see which need transformations.
1370 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1371 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1372 MVT VT = (MVT::SimpleValueType) i;
1373 if (isTypeLegal(VT))
1374 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1375
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1376 MVT EltVT = VT.getVectorElementType();
1377 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1378 bool IsLegalWiderType = false;
1379 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1380 switch (PreferredAction) {
1381 case TypePromoteInteger: {
1382 // Try to promote the elements of integer vectors. If no legal
1383 // promotion was found, fall through to the widen-vector method.
1384 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1385 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1386 // Promote vectors of integers to vectors with the same number
1387 // of elements, with a wider element type.
1388 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1389 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1390 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1391 TransformToType[i] = SVT;
1392 RegisterTypeForVT[i] = SVT;
1393 NumRegistersForVT[i] = 1;
1394 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1395 IsLegalWiderType = true;
1396 break;
1397 }
1398 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1399 if (IsLegalWiderType)
1400 break;
1401 }
1402 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1403 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1404 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1405 MVT SVT = (MVT::SimpleValueType) nVT;
1406 if (SVT.getVectorElementType() == EltVT
1407 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1408 TransformToType[i] = SVT;
1409 RegisterTypeForVT[i] = SVT;
1410 NumRegistersForVT[i] = 1;
1411 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1412 IsLegalWiderType = true;
1413 break;
1414 }
1415 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1416 if (IsLegalWiderType)
1417 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1418 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1419 case TypeSplitVector:
1420 case TypeScalarizeVector: {
1421 MVT IntermediateVT;
1422 MVT RegisterVT;
1423 unsigned NumIntermediates;
1424 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1425 NumIntermediates, RegisterVT, this);
1426 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1427
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1428 MVT NVT = VT.getPow2VectorType();
1429 if (NVT == VT) {
1430 // Type is already a power of 2. The default action is to split.
1431 TransformToType[i] = MVT::Other;
1432 if (PreferredAction == TypeScalarizeVector)
1433 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1434 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1435 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1436 else
1437 // Set type action according to the number of elements.
1438 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1439 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1440 } else {
1441 TransformToType[i] = NVT;
1442 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1443 }
1444 break;
1445 }
1446 default:
1447 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1448 }
1449 }
1450
1451 // Determine the 'representative' register class for each value type.
1452 // An representative register class is the largest (meaning one which is
1453 // not a sub-register class / subreg register class) legal register class for
1454 // a group of value types. For example, on i386, i8, i16, and i32
1455 // representative would be GR32; while on x86_64 it's GR64.
1456 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1457 const TargetRegisterClass* RRC;
1458 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1459 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1460 RepRegClassForVT[i] = RRC;
1461 RepRegClassCostForVT[i] = Cost;
1462 }
1463}
1464
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1465EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1466 EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1467 assert(!VT.isVector() && "No default SetCC type for vectors!");
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1468 return getPointerTy(DL).SimpleTy;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1469}
1470
1471MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1472 return MVT::i32; // return the default value
1473}
1474
1475/// getVectorTypeBreakdown - Vector types are broken down into some number of
1476/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1477/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1478/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1479///
1480/// This method returns the number of registers needed, and the VT for each
1481/// register. It also returns the VT and quantity of the intermediate values
1482/// before they are promoted/expanded.
1483///
1484unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1485 EVT &IntermediateVT,
1486 unsigned &NumIntermediates,
1487 MVT &RegisterVT) const {
1488 unsigned NumElts = VT.getVectorNumElements();
1489
1490 // If there is a wider vector type with the same element type as this one,
1491 // or a promoted vector type that has the same number of elements which
1492 // are wider, then we should convert to that legal vector type.
1493 // This handles things like <2 x float> -> <4 x float> and
1494 // <4 x i1> -> <4 x i32>.
1495 LegalizeTypeAction TA = getTypeAction(Context, VT);
1496 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1497 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1498 if (isTypeLegal(RegisterEVT)) {
1499 IntermediateVT = RegisterEVT;
1500 RegisterVT = RegisterEVT.getSimpleVT();
1501 NumIntermediates = 1;
1502 return 1;
1503 }
1504 }
1505
1506 // Figure out the right, legal destination reg to copy into.
1507 EVT EltTy = VT.getVectorElementType();
1508
1509 unsigned NumVectorRegs = 1;
1510
1511 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1512 // could break down into LHS/RHS like LegalizeDAG does.
1513 if (!isPowerOf2_32(NumElts)) {
1514 NumVectorRegs = NumElts;
1515 NumElts = 1;
1516 }
1517
1518 // Divide the input until we get to a supported size. This will always
1519 // end with a scalar if the target doesn't support vectors.
1520 while (NumElts > 1 && !isTypeLegal(
1521 EVT::getVectorVT(Context, EltTy, NumElts))) {
1522 NumElts >>= 1;
1523 NumVectorRegs <<= 1;
1524 }
1525
1526 NumIntermediates = NumVectorRegs;
1527
1528 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1529 if (!isTypeLegal(NewVT))
1530 NewVT = EltTy;
1531 IntermediateVT = NewVT;
1532
1533 MVT DestVT = getRegisterType(Context, NewVT);
1534 RegisterVT = DestVT;
1535 unsigned NewVTSize = NewVT.getSizeInBits();
1536
1537 // Convert sizes such as i33 to i64.
1538 if (!isPowerOf2_32(NewVTSize))
1539 NewVTSize = NextPowerOf2(NewVTSize);
1540
1541 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1542 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1543
1544 // Otherwise, promotion or legal types use the same number of registers as
1545 // the vector decimated to the appropriate level.
1546 return NumVectorRegs;
1547}
1548
1549/// Get the EVTs and ArgFlags collections that represent the legalized return
1550/// type of the given function. This does not require a DAG or a return value,
1551/// and is suitable for use before any DAGs for the function are constructed.
1552/// TODO: Move this out of TargetLowering.cpp.
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1553void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1554 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1555 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1556 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1557 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1558 unsigned NumValues = ValueVTs.size();
1559 if (NumValues == 0) return;
1560
1561 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1562 EVT VT = ValueVTs[j];
1563 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1564
1565 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1566 ExtendKind = ISD::SIGN_EXTEND;
1567 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1568 ExtendKind = ISD::ZERO_EXTEND;
1569
1570 // FIXME: C calling convention requires the return type to be promoted to
1571 // at least 32-bit. But this is not necessary for non-C calling
1572 // conventions. The frontend should mark functions whose return values
1573 // require promoting with signext or zeroext attributes.
1574 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1575 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1576 if (VT.bitsLT(MinVT))
1577 VT = MinVT;
1578 }
1579
1580 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1581 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1582
1583 // 'inreg' on function refers to return value
1584 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1585 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1586 Flags.setInReg();
1587
1588 // Propagate extension type if any
1589 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1590 Flags.setSExt();
1591 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1592 Flags.setZExt();
1593
1594 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1595 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1596 }
1597}
1598
1599/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1600/// function arguments in the caller parameter area. This is the actual
1601/// alignment, not its logarithm.
Mehdi Amini5c183d52015-07-09 02:09:28 +0000[diff] [blame]1602unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1603 const DataLayout &DL) const {
1604 return DL.getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1605}
1606
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1607bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1608 const DataLayout &DL, EVT VT,
1609 unsigned AddrSpace,
1610 unsigned Alignment,
1611 bool *Fast) const {
1612 // Check if the specified alignment is sufficient based on the data layout.
1613 // TODO: While using the data layout works in practice, a better solution
1614 // would be to implement this check directly (make this a virtual function).
1615 // For example, the ABI alignment may change based on software platform while
1616 // this function should only be affected by hardware implementation.
1617 Type *Ty = VT.getTypeForEVT(Context);
1618 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1619 // Assume that an access that meets the ABI-specified alignment is fast.
1620 if (Fast != nullptr)
1621 *Fast = true;
1622 return true;
1623 }
1624
1625 // This is a misaligned access.
1626 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1627}
1628
1629
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1630//===----------------------------------------------------------------------===//
1631// TargetTransformInfo Helpers
1632//===----------------------------------------------------------------------===//
1633
1634int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1635 enum InstructionOpcodes {
1636#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1637#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1638#include "llvm/IR/Instruction.def"
1639 };
1640 switch (static_cast<InstructionOpcodes>(Opcode)) {
1641 case Ret: return 0;
1642 case Br: return 0;
1643 case Switch: return 0;
1644 case IndirectBr: return 0;
1645 case Invoke: return 0;
1646 case Resume: return 0;
1647 case Unreachable: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1648 case CleanupRet: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1649 case CatchRet: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1650 case CatchPad: return 0;
1651 case CatchSwitch: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1652 case CleanupPad: return 0;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1653 case Add: return ISD::ADD;
1654 case FAdd: return ISD::FADD;
1655 case Sub: return ISD::SUB;
1656 case FSub: return ISD::FSUB;
1657 case Mul: return ISD::MUL;
1658 case FMul: return ISD::FMUL;
1659 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1660 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1661 case FDiv: return ISD::FDIV;
1662 case URem: return ISD::UREM;
1663 case SRem: return ISD::SREM;
1664 case FRem: return ISD::FREM;
1665 case Shl: return ISD::SHL;
1666 case LShr: return ISD::SRL;
1667 case AShr: return ISD::SRA;
1668 case And: return ISD::AND;
1669 case Or: return ISD::OR;
1670 case Xor: return ISD::XOR;
1671 case Alloca: return 0;
1672 case Load: return ISD::LOAD;
1673 case Store: return ISD::STORE;
1674 case GetElementPtr: return 0;
1675 case Fence: return 0;
1676 case AtomicCmpXchg: return 0;
1677 case AtomicRMW: return 0;
1678 case Trunc: return ISD::TRUNCATE;
1679 case ZExt: return ISD::ZERO_EXTEND;
1680 case SExt: return ISD::SIGN_EXTEND;
1681 case FPToUI: return ISD::FP_TO_UINT;
1682 case FPToSI: return ISD::FP_TO_SINT;
1683 case UIToFP: return ISD::UINT_TO_FP;
1684 case SIToFP: return ISD::SINT_TO_FP;
1685 case FPTrunc: return ISD::FP_ROUND;
1686 case FPExt: return ISD::FP_EXTEND;
1687 case PtrToInt: return ISD::BITCAST;
1688 case IntToPtr: return ISD::BITCAST;
1689 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1690 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1691 case ICmp: return ISD::SETCC;
1692 case FCmp: return ISD::SETCC;
1693 case PHI: return 0;
1694 case Call: return 0;
1695 case Select: return ISD::SELECT;
1696 case UserOp1: return 0;
1697 case UserOp2: return 0;
1698 case VAArg: return 0;
1699 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1700 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1701 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1702 case ExtractValue: return ISD::MERGE_VALUES;
1703 case InsertValue: return ISD::MERGE_VALUES;
1704 case LandingPad: return 0;
1705 }
1706
1707 llvm_unreachable("Unknown instruction type encountered!");
1708}
1709
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1710std::pair<int, MVT>
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1711TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1712 Type *Ty) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1713 LLVMContext &C = Ty->getContext();
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1714 EVT MTy = getValueType(DL, Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1715
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1716 int Cost = 1;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1717 // We keep legalizing the type until we find a legal kind. We assume that
1718 // the only operation that costs anything is the split. After splitting
1719 // we need to handle two types.
1720 while (true) {
1721 LegalizeKind LK = getTypeConversion(C, MTy);
1722
1723 if (LK.first == TypeLegal)
1724 return std::make_pair(Cost, MTy.getSimpleVT());
1725
1726 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1727 Cost *= 2;
1728
Chih-Hung Hsiehed7d81e2015-12-03 22:02:40 +0000[diff] [blame]1729 // Do not loop with f128 type.
1730 if (MTy == LK.second)
1731 return std::make_pair(Cost, MTy.getSimpleVT());
1732
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1733 // Keep legalizing the type.
1734 MTy = LK.second;
1735 }
1736}
1737
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1738Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1739 if (!TM.getTargetTriple().isAndroid())
1740 return nullptr;
1741
1742 // Android provides a libc function to retrieve the address of the current
1743 // thread's unsafe stack pointer.
1744 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1745 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1746 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1747 StackPtrTy->getPointerTo(0), nullptr);
1748 return IRB.CreateCall(Fn);
1749}
1750
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1751//===----------------------------------------------------------------------===//
1752// Loop Strength Reduction hooks
1753//===----------------------------------------------------------------------===//
1754
1755/// isLegalAddressingMode - Return true if the addressing mode represented
1756/// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]1757bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1758 const AddrMode &AM, Type *Ty,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1759 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1760 // The default implementation of this implements a conservative RISCy, r+r and
1761 // r+i addr mode.
1762
1763 // Allows a sign-extended 16-bit immediate field.
1764 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1765 return false;
1766
1767 // No global is ever allowed as a base.
1768 if (AM.BaseGV)
1769 return false;
1770
1771 // Only support r+r,
1772 switch (AM.Scale) {
1773 case 0: // "r+i" or just "i", depending on HasBaseReg.
1774 break;
1775 case 1:
1776 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1777 return false;
1778 // Otherwise we have r+r or r+i.
1779 break;
1780 case 2:
1781 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1782 return false;
1783 // Allow 2*r as r+r.
1784 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1785 default: // Don't allow n * r
1786 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1787 }
1788
1789 return true;
1790}
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1791
1792//===----------------------------------------------------------------------===//
1793// Stack Protector
1794//===----------------------------------------------------------------------===//
1795
1796// For OpenBSD return its special guard variable. Otherwise return nullptr,
1797// so that SelectionDAG handle SSP.
1798Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1799 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1800 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1801 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1802 auto Guard = cast<GlobalValue>(M.getOrInsertGlobal("__guard_local", PtrTy));
1803 Guard->setVisibility(GlobalValue::HiddenVisibility);
1804 return Guard;
1805 }
1806 return nullptr;
1807}
1808
1809// Currently only support "standard" __stack_chk_guard.
1810// TODO: add LOAD_STACK_GUARD support.
1811void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1812 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext()));
1813}
1814
1815// Currently only support "standard" __stack_chk_guard.
1816// TODO: add LOAD_STACK_GUARD support.
1817Value *TargetLoweringBase::getSDStackGuard(const Module &M) const {
1818 return M.getGlobalVariable("__stack_chk_guard");
1819}