Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Bob Wilson | 359f8ba | 2010-09-08 23:39:54 +0000 | [diff] [blame] | 10 | // This file contains a pass that expands pseudo instructions into target |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 11 | // instructions to allow proper scheduling, if-conversion, and other late |
| 12 | // optimizations. This pass should be run after register allocation but before |
Bob Wilson | 359f8ba | 2010-09-08 23:39:54 +0000 | [diff] [blame] | 13 | // the post-regalloc scheduling pass. |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 14 | // |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 17 | #include "ARM.h" |
| 18 | #include "ARMBaseInstrInfo.h" |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 19 | #include "ARMBaseRegisterInfo.h" |
Tim Northover | 72360d2 | 2013-12-02 10:35:41 +0000 | [diff] [blame] | 20 | #include "ARMConstantPoolValue.h" |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 21 | #include "ARMMachineFunctionInfo.h" |
Eugene Zelenko | e6cf437 | 2017-01-26 23:40:06 +0000 | [diff] [blame] | 22 | #include "ARMSubtarget.h" |
Evan Cheng | a20cde3 | 2011-07-20 23:34:39 +0000 | [diff] [blame] | 23 | #include "MCTargetDesc/ARMAddressingModes.h" |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/LivePhysRegs.h" |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineFunctionPass.h" |
Eugene Zelenko | e6cf437 | 2017-01-26 23:40:06 +0000 | [diff] [blame] | 27 | |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 28 | using namespace llvm; |
| 29 | |
Chandler Carruth | 84e68b2 | 2014-04-22 02:41:26 +0000 | [diff] [blame] | 30 | #define DEBUG_TYPE "arm-pseudo" |
| 31 | |
Benjamin Kramer | 4938edb | 2011-08-19 01:42:18 +0000 | [diff] [blame] | 32 | static cl::opt<bool> |
Jakob Stoklund Olesen | 9c3badc | 2011-07-29 00:27:32 +0000 | [diff] [blame] | 33 | VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, |
| 34 | cl::desc("Verify machine code after expanding ARM pseudos")); |
| 35 | |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 36 | namespace { |
| 37 | class ARMExpandPseudo : public MachineFunctionPass { |
| 38 | public: |
| 39 | static char ID; |
Owen Anderson | a7aed18 | 2010-08-06 18:33:48 +0000 | [diff] [blame] | 40 | ARMExpandPseudo() : MachineFunctionPass(ID) {} |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 41 | |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 42 | const ARMBaseInstrInfo *TII; |
Evan Cheng | 2f736c9 | 2010-05-13 00:17:02 +0000 | [diff] [blame] | 43 | const TargetRegisterInfo *TRI; |
Evan Cheng | f478cf9 | 2010-11-12 23:03:38 +0000 | [diff] [blame] | 44 | const ARMSubtarget *STI; |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 45 | ARMFunctionInfo *AFI; |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 46 | |
Craig Topper | 6bc27bf | 2014-03-10 02:09:33 +0000 | [diff] [blame] | 47 | bool runOnMachineFunction(MachineFunction &Fn) override; |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 48 | |
Derek Schuff | 1dbf7a5 | 2016-04-04 17:09:25 +0000 | [diff] [blame] | 49 | MachineFunctionProperties getRequiredProperties() const override { |
| 50 | return MachineFunctionProperties().set( |
Matthias Braun | 1eb4736 | 2016-08-25 01:27:13 +0000 | [diff] [blame] | 51 | MachineFunctionProperties::Property::NoVRegs); |
Derek Schuff | 1dbf7a5 | 2016-04-04 17:09:25 +0000 | [diff] [blame] | 52 | } |
| 53 | |
Mehdi Amini | 117296c | 2016-10-01 02:56:57 +0000 | [diff] [blame] | 54 | StringRef getPassName() const override { |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 55 | return "ARM pseudo instruction expansion pass"; |
| 56 | } |
| 57 | |
| 58 | private: |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 59 | void TransferImpOps(MachineInstr &OldMI, |
| 60 | MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 61 | bool ExpandMI(MachineBasicBlock &MBB, |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 62 | MachineBasicBlock::iterator MBBI, |
| 63 | MachineBasicBlock::iterator &NextMBBI); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 64 | bool ExpandMBB(MachineBasicBlock &MBB); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 65 | void ExpandVLD(MachineBasicBlock::iterator &MBBI); |
| 66 | void ExpandVST(MachineBasicBlock::iterator &MBBI); |
| 67 | void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 68 | void ExpandVTBL(MachineBasicBlock::iterator &MBBI, |
Jim Grosbach | 4a5c887 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 69 | unsigned Opc, bool IsExt); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 70 | void ExpandMOV32BitImm(MachineBasicBlock &MBB, |
| 71 | MachineBasicBlock::iterator &MBBI); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 72 | bool ExpandCMP_SWAP(MachineBasicBlock &MBB, |
| 73 | MachineBasicBlock::iterator MBBI, unsigned LdrexOp, |
| 74 | unsigned StrexOp, unsigned UxtOp, |
| 75 | MachineBasicBlock::iterator &NextMBBI); |
| 76 | |
| 77 | bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, |
| 78 | MachineBasicBlock::iterator MBBI, |
| 79 | MachineBasicBlock::iterator &NextMBBI); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 80 | }; |
| 81 | char ARMExpandPseudo::ID = 0; |
Alexander Kornienko | f00654e | 2015-06-23 09:49:53 +0000 | [diff] [blame] | 82 | } |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 83 | |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 84 | /// TransferImpOps - Transfer implicit operands on the pseudo instruction to |
| 85 | /// the instructions created from the expansion. |
| 86 | void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, |
| 87 | MachineInstrBuilder &UseMI, |
| 88 | MachineInstrBuilder &DefMI) { |
Evan Cheng | 6cc775f | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 89 | const MCInstrDesc &Desc = OldMI.getDesc(); |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 90 | for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); |
| 91 | i != e; ++i) { |
| 92 | const MachineOperand &MO = OldMI.getOperand(i); |
| 93 | assert(MO.isReg() && MO.getReg()); |
| 94 | if (MO.isUse()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 95 | UseMI.add(MO); |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 96 | else |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 97 | DefMI.add(MO); |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 98 | } |
| 99 | } |
| 100 | |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 101 | namespace { |
| 102 | // Constants for register spacing in NEON load/store instructions. |
| 103 | // For quad-register load-lane and store-lane pseudo instructors, the |
| 104 | // spacing is initially assumed to be EvenDblSpc, and that is changed to |
| 105 | // OddDblSpc depending on the lane number operand. |
| 106 | enum NEONRegSpacing { |
| 107 | SingleSpc, |
| 108 | EvenDblSpc, |
| 109 | OddDblSpc |
| 110 | }; |
| 111 | |
| 112 | // Entries for NEON load/store information table. The table is sorted by |
| 113 | // PseudoOpc for fast binary-search lookups. |
| 114 | struct NEONLdStTableEntry { |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 115 | uint16_t PseudoOpc; |
| 116 | uint16_t RealOpc; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 117 | bool IsLoad; |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 118 | bool isUpdating; |
| 119 | bool hasWritebackOperand; |
Craig Topper | 980739a | 2012-09-20 06:14:08 +0000 | [diff] [blame] | 120 | uint8_t RegSpacing; // One of type NEONRegSpacing |
| 121 | uint8_t NumRegs; // D registers loaded or stored |
| 122 | uint8_t RegElts; // elements per D register; used for lane ops |
Jim Grosbach | 2f2e3c4 | 2011-10-21 18:54:25 +0000 | [diff] [blame] | 123 | // FIXME: Temporary flag to denote whether the real instruction takes |
| 124 | // a single register (like the encoding) or all of the registers in |
| 125 | // the list (like the asm syntax and the isel DAG). When all definitions |
| 126 | // are converted to take only the single encoded register, this will |
| 127 | // go away. |
| 128 | bool copyAllListRegs; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 129 | |
| 130 | // Comparison methods for binary search of the table. |
| 131 | bool operator<(const NEONLdStTableEntry &TE) const { |
| 132 | return PseudoOpc < TE.PseudoOpc; |
| 133 | } |
| 134 | friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { |
| 135 | return TE.PseudoOpc < PseudoOpc; |
| 136 | } |
Chandler Carruth | 88c54b8 | 2010-10-23 08:10:43 +0000 | [diff] [blame] | 137 | friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, |
| 138 | const NEONLdStTableEntry &TE) { |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 139 | return PseudoOpc < TE.PseudoOpc; |
| 140 | } |
| 141 | }; |
Alexander Kornienko | f00654e | 2015-06-23 09:49:53 +0000 | [diff] [blame] | 142 | } |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 143 | |
| 144 | static const NEONLdStTableEntry NEONLdStTable[] = { |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 145 | { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, |
| 146 | { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, |
| 147 | { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, |
| 148 | { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, |
| 149 | { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, |
| 150 | { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, |
Bob Wilson | dc44990 | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 151 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 152 | { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, |
Jiangning Liu | 4df2363 | 2014-01-16 09:16:13 +0000 | [diff] [blame] | 153 | { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 154 | { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, |
Jiangning Liu | 4df2363 | 2014-01-16 09:16:13 +0000 | [diff] [blame] | 155 | { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 156 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 157 | { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, |
| 158 | { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, |
| 159 | { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, |
| 160 | { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, |
| 161 | { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, |
| 162 | { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, |
| 163 | { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, |
| 164 | { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, |
| 165 | { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, |
| 166 | { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 167 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 168 | { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, |
Jim Grosbach | d146a02 | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 169 | { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, |
| 170 | { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 171 | { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, |
Jim Grosbach | d146a02 | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 172 | { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, |
| 173 | { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 174 | { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, |
Jim Grosbach | d146a02 | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 175 | { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, |
| 176 | { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 177 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 178 | { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, |
| 179 | { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, |
| 180 | { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, |
| 181 | { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, |
| 182 | { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, |
| 183 | { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, |
Bob Wilson | 77ab165 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 184 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 185 | { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, |
| 186 | { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, |
| 187 | { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, |
| 188 | { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, |
| 189 | { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, |
| 190 | { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, |
| 191 | { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, |
| 192 | { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, |
| 193 | { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, |
| 194 | { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 195 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 196 | { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, |
| 197 | { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, |
| 198 | { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, |
| 199 | { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, |
| 200 | { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, |
| 201 | { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 202 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 203 | { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, |
| 204 | { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, |
| 205 | { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, |
| 206 | { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, |
| 207 | { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, |
| 208 | { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, |
| 209 | { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, |
| 210 | { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, |
| 211 | { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 212 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 213 | { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, |
| 214 | { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, |
| 215 | { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, |
| 216 | { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, |
| 217 | { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, |
| 218 | { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, |
Bob Wilson | 431ac4ef | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 219 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 220 | { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, |
| 221 | { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, |
| 222 | { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, |
| 223 | { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, |
| 224 | { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, |
| 225 | { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, |
| 226 | { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, |
| 227 | { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, |
| 228 | { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, |
| 229 | { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 230 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 231 | { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, |
| 232 | { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, |
| 233 | { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, |
| 234 | { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, |
| 235 | { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, |
| 236 | { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 237 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 238 | { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, |
| 239 | { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, |
| 240 | { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, |
| 241 | { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, |
| 242 | { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, |
| 243 | { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, |
| 244 | { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, |
| 245 | { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, |
| 246 | { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 247 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 248 | { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, |
| 249 | { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, |
| 250 | { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, |
| 251 | { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, |
| 252 | { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, |
| 253 | { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, |
Bob Wilson | d80b29d | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 254 | |
Jim Grosbach | 5ee209c | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 255 | { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, |
| 256 | { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, |
| 257 | { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, |
Jim Grosbach | 98d032f | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 258 | { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, |
| 259 | { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, |
| 260 | { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 261 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 262 | { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, |
| 263 | { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, |
| 264 | { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, |
| 265 | { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, |
| 266 | { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, |
| 267 | { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, |
| 268 | { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, |
| 269 | { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, |
| 270 | { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, |
| 271 | { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 272 | |
Jim Grosbach | 8d24618 | 2011-12-14 19:35:22 +0000 | [diff] [blame] | 273 | { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, |
Jim Grosbach | 88ac761 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 274 | { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, |
| 275 | { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, |
Jim Grosbach | 8d24618 | 2011-12-14 19:35:22 +0000 | [diff] [blame] | 276 | { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, |
Jim Grosbach | 88ac761 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 277 | { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, |
| 278 | { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, |
Jim Grosbach | 8d24618 | 2011-12-14 19:35:22 +0000 | [diff] [blame] | 279 | { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, |
Jim Grosbach | 88ac761 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 280 | { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, |
| 281 | { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 282 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 283 | { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, |
| 284 | { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, |
| 285 | { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, |
| 286 | { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, |
| 287 | { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, |
| 288 | { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, |
| 289 | { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, |
| 290 | { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, |
| 291 | { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, |
| 292 | { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 293 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 294 | { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, |
| 295 | { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, |
| 296 | { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, |
| 297 | { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, |
| 298 | { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, |
| 299 | { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 300 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 301 | { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, |
| 302 | { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, |
| 303 | { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, |
| 304 | { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, |
| 305 | { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, |
| 306 | { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, |
| 307 | { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, |
| 308 | { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, |
| 309 | { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 310 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 311 | { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, |
| 312 | { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, |
| 313 | { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, |
| 314 | { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, |
| 315 | { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, |
| 316 | { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, |
| 317 | { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, |
| 318 | { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, |
| 319 | { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, |
| 320 | { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 321 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 322 | { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, |
| 323 | { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, |
| 324 | { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, |
| 325 | { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, |
| 326 | { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, |
| 327 | { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 328 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 329 | { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, |
| 330 | { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, |
| 331 | { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, |
| 332 | { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, |
| 333 | { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, |
| 334 | { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, |
| 335 | { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, |
| 336 | { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, |
| 337 | { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 338 | }; |
| 339 | |
| 340 | /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON |
| 341 | /// load or store pseudo instruction. |
| 342 | static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 343 | #ifndef NDEBUG |
| 344 | // Make sure the table is sorted. |
| 345 | static bool TableChecked = false; |
| 346 | if (!TableChecked) { |
Craig Topper | c177d9e | 2015-10-17 16:37:11 +0000 | [diff] [blame] | 347 | assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) && |
| 348 | "NEONLdStTable is not sorted!"); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 349 | TableChecked = true; |
| 350 | } |
| 351 | #endif |
| 352 | |
Craig Topper | a2d0635 | 2015-10-17 18:22:46 +0000 | [diff] [blame] | 353 | auto I = std::lower_bound(std::begin(NEONLdStTable), |
| 354 | std::end(NEONLdStTable), Opcode); |
Craig Topper | c177d9e | 2015-10-17 16:37:11 +0000 | [diff] [blame] | 355 | if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 356 | return I; |
Craig Topper | 062a2ba | 2014-04-25 05:30:21 +0000 | [diff] [blame] | 357 | return nullptr; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, |
| 361 | /// corresponding to the specified register spacing. Not all of the results |
| 362 | /// are necessarily valid, e.g., a Q register only has 2 D subregisters. |
| 363 | static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, |
| 364 | const TargetRegisterInfo *TRI, unsigned &D0, |
| 365 | unsigned &D1, unsigned &D2, unsigned &D3) { |
| 366 | if (RegSpc == SingleSpc) { |
| 367 | D0 = TRI->getSubReg(Reg, ARM::dsub_0); |
| 368 | D1 = TRI->getSubReg(Reg, ARM::dsub_1); |
| 369 | D2 = TRI->getSubReg(Reg, ARM::dsub_2); |
| 370 | D3 = TRI->getSubReg(Reg, ARM::dsub_3); |
| 371 | } else if (RegSpc == EvenDblSpc) { |
| 372 | D0 = TRI->getSubReg(Reg, ARM::dsub_0); |
| 373 | D1 = TRI->getSubReg(Reg, ARM::dsub_2); |
| 374 | D2 = TRI->getSubReg(Reg, ARM::dsub_4); |
| 375 | D3 = TRI->getSubReg(Reg, ARM::dsub_6); |
| 376 | } else { |
| 377 | assert(RegSpc == OddDblSpc && "unknown register spacing"); |
| 378 | D0 = TRI->getSubReg(Reg, ARM::dsub_1); |
| 379 | D1 = TRI->getSubReg(Reg, ARM::dsub_3); |
| 380 | D2 = TRI->getSubReg(Reg, ARM::dsub_5); |
| 381 | D3 = TRI->getSubReg(Reg, ARM::dsub_7); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 382 | } |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 383 | } |
| 384 | |
Bob Wilson | 5a1df80 | 2010-09-02 16:17:29 +0000 | [diff] [blame] | 385 | /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register |
| 386 | /// operands to real VLD instructions with D register operands. |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 387 | void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 388 | MachineInstr &MI = *MBBI; |
| 389 | MachineBasicBlock &MBB = *MI.getParent(); |
| 390 | |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 391 | const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); |
| 392 | assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); |
Craig Topper | 980739a | 2012-09-20 06:14:08 +0000 | [diff] [blame] | 393 | NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 394 | unsigned NumRegs = TableEntry->NumRegs; |
| 395 | |
| 396 | MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
| 397 | TII->get(TableEntry->RealOpc)); |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 398 | unsigned OpIdx = 0; |
| 399 | |
| 400 | bool DstIsDead = MI.getOperand(OpIdx).isDead(); |
| 401 | unsigned DstReg = MI.getOperand(OpIdx++).getReg(); |
| 402 | unsigned D0, D1, D2, D3; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 403 | GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); |
Jim Grosbach | 2f2e3c4 | 2011-10-21 18:54:25 +0000 | [diff] [blame] | 404 | MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); |
| 405 | if (NumRegs > 1 && TableEntry->copyAllListRegs) |
| 406 | MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); |
| 407 | if (NumRegs > 2 && TableEntry->copyAllListRegs) |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 408 | MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); |
Jim Grosbach | 2f2e3c4 | 2011-10-21 18:54:25 +0000 | [diff] [blame] | 409 | if (NumRegs > 3 && TableEntry->copyAllListRegs) |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 410 | MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 411 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 412 | if (TableEntry->isUpdating) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 413 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 4ccd5ce | 2010-09-09 00:15:32 +0000 | [diff] [blame] | 414 | |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 415 | // Copy the addrmode6 operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 416 | MIB.add(MI.getOperand(OpIdx++)); |
| 417 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 4ccd5ce | 2010-09-09 00:15:32 +0000 | [diff] [blame] | 418 | // Copy the am6offset operand. |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 419 | if (TableEntry->hasWritebackOperand) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 420 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 421 | |
Bob Wilson | 84971c8 | 2010-09-09 00:38:32 +0000 | [diff] [blame] | 422 | // For an instruction writing double-spaced subregs, the pseudo instruction |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 423 | // has an extra operand that is a use of the super-register. Record the |
| 424 | // operand index and skip over it. |
| 425 | unsigned SrcOpIdx = 0; |
| 426 | if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) |
| 427 | SrcOpIdx = OpIdx++; |
| 428 | |
| 429 | // Copy the predicate operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 430 | MIB.add(MI.getOperand(OpIdx++)); |
| 431 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 432 | |
| 433 | // Copy the super-register source operand used for double-spaced subregs over |
Bob Wilson | 84971c8 | 2010-09-09 00:38:32 +0000 | [diff] [blame] | 434 | // to the new instruction as an implicit operand. |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 435 | if (SrcOpIdx != 0) { |
| 436 | MachineOperand MO = MI.getOperand(SrcOpIdx); |
Bob Wilson | 84971c8 | 2010-09-09 00:38:32 +0000 | [diff] [blame] | 437 | MO.setImplicit(true); |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 438 | MIB.add(MO); |
Bob Wilson | 84971c8 | 2010-09-09 00:38:32 +0000 | [diff] [blame] | 439 | } |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 440 | // Add an implicit def for the super-register. |
| 441 | MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); |
Bob Wilson | 84971c8 | 2010-09-09 00:38:32 +0000 | [diff] [blame] | 442 | TransferImpOps(MI, MIB, MIB); |
Evan Cheng | 4079133 | 2011-04-19 00:04:03 +0000 | [diff] [blame] | 443 | |
| 444 | // Transfer memoperands. |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 445 | MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Evan Cheng | 4079133 | 2011-04-19 00:04:03 +0000 | [diff] [blame] | 446 | |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 447 | MI.eraseFromParent(); |
| 448 | } |
| 449 | |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 450 | /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register |
| 451 | /// operands to real VST instructions with D register operands. |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 452 | void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 453 | MachineInstr &MI = *MBBI; |
| 454 | MachineBasicBlock &MBB = *MI.getParent(); |
| 455 | |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 456 | const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); |
| 457 | assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); |
Craig Topper | 980739a | 2012-09-20 06:14:08 +0000 | [diff] [blame] | 458 | NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 459 | unsigned NumRegs = TableEntry->NumRegs; |
| 460 | |
| 461 | MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
| 462 | TII->get(TableEntry->RealOpc)); |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 463 | unsigned OpIdx = 0; |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 464 | if (TableEntry->isUpdating) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 465 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 4ccd5ce | 2010-09-09 00:15:32 +0000 | [diff] [blame] | 466 | |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 467 | // Copy the addrmode6 operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 468 | MIB.add(MI.getOperand(OpIdx++)); |
| 469 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 4ccd5ce | 2010-09-09 00:15:32 +0000 | [diff] [blame] | 470 | // Copy the am6offset operand. |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 471 | if (TableEntry->hasWritebackOperand) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 472 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 473 | |
| 474 | bool SrcIsKill = MI.getOperand(OpIdx).isKill(); |
Jakob Stoklund Olesen | a15a224 | 2012-06-15 17:46:54 +0000 | [diff] [blame] | 475 | bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 476 | unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 477 | unsigned D0, D1, D2, D3; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 478 | GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); |
Jakob Stoklund Olesen | a15a224 | 2012-06-15 17:46:54 +0000 | [diff] [blame] | 479 | MIB.addReg(D0, getUndefRegState(SrcIsUndef)); |
Jim Grosbach | 05df460 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 480 | if (NumRegs > 1 && TableEntry->copyAllListRegs) |
Jakob Stoklund Olesen | a15a224 | 2012-06-15 17:46:54 +0000 | [diff] [blame] | 481 | MIB.addReg(D1, getUndefRegState(SrcIsUndef)); |
Jim Grosbach | 05df460 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 482 | if (NumRegs > 2 && TableEntry->copyAllListRegs) |
Jakob Stoklund Olesen | a15a224 | 2012-06-15 17:46:54 +0000 | [diff] [blame] | 483 | MIB.addReg(D2, getUndefRegState(SrcIsUndef)); |
Jim Grosbach | 05df460 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 484 | if (NumRegs > 3 && TableEntry->copyAllListRegs) |
Jakob Stoklund Olesen | a15a224 | 2012-06-15 17:46:54 +0000 | [diff] [blame] | 485 | MIB.addReg(D3, getUndefRegState(SrcIsUndef)); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 486 | |
| 487 | // Copy the predicate operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 488 | MIB.add(MI.getOperand(OpIdx++)); |
| 489 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 490 | |
Jakob Stoklund Olesen | a15a224 | 2012-06-15 17:46:54 +0000 | [diff] [blame] | 491 | if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 492 | MIB->addRegisterKilled(SrcReg, TRI, true); |
Weiming Zhao | fe26fd2 | 2014-01-15 01:32:12 +0000 | [diff] [blame] | 493 | else if (!SrcIsUndef) |
| 494 | MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 495 | TransferImpOps(MI, MIB, MIB); |
Evan Cheng | 4079133 | 2011-04-19 00:04:03 +0000 | [diff] [blame] | 496 | |
| 497 | // Transfer memoperands. |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 498 | MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Evan Cheng | 4079133 | 2011-04-19 00:04:03 +0000 | [diff] [blame] | 499 | |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 500 | MI.eraseFromParent(); |
| 501 | } |
| 502 | |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 503 | /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ |
| 504 | /// register operands to real instructions with D register operands. |
| 505 | void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { |
| 506 | MachineInstr &MI = *MBBI; |
| 507 | MachineBasicBlock &MBB = *MI.getParent(); |
| 508 | |
| 509 | const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); |
| 510 | assert(TableEntry && "NEONLdStTable lookup failed"); |
Craig Topper | 980739a | 2012-09-20 06:14:08 +0000 | [diff] [blame] | 511 | NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 512 | unsigned NumRegs = TableEntry->NumRegs; |
| 513 | unsigned RegElts = TableEntry->RegElts; |
| 514 | |
| 515 | MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
| 516 | TII->get(TableEntry->RealOpc)); |
| 517 | unsigned OpIdx = 0; |
| 518 | // The lane operand is always the 3rd from last operand, before the 2 |
| 519 | // predicate operands. |
| 520 | unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); |
| 521 | |
| 522 | // Adjust the lane and spacing as needed for Q registers. |
| 523 | assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); |
| 524 | if (RegSpc == EvenDblSpc && Lane >= RegElts) { |
| 525 | RegSpc = OddDblSpc; |
| 526 | Lane -= RegElts; |
| 527 | } |
| 528 | assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); |
| 529 | |
Ted Kremenek | 3c4408c | 2011-01-23 17:05:06 +0000 | [diff] [blame] | 530 | unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; |
Bob Wilson | 62e9a05 | 2010-09-14 21:12:05 +0000 | [diff] [blame] | 531 | unsigned DstReg = 0; |
| 532 | bool DstIsDead = false; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 533 | if (TableEntry->IsLoad) { |
| 534 | DstIsDead = MI.getOperand(OpIdx).isDead(); |
| 535 | DstReg = MI.getOperand(OpIdx++).getReg(); |
| 536 | GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); |
Bob Wilson | dc44990 | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 537 | MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); |
| 538 | if (NumRegs > 1) |
| 539 | MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 540 | if (NumRegs > 2) |
| 541 | MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); |
| 542 | if (NumRegs > 3) |
| 543 | MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); |
| 544 | } |
| 545 | |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 546 | if (TableEntry->isUpdating) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 547 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 548 | |
| 549 | // Copy the addrmode6 operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 550 | MIB.add(MI.getOperand(OpIdx++)); |
| 551 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 552 | // Copy the am6offset operand. |
Jim Grosbach | e4c8e69 | 2011-10-31 19:11:23 +0000 | [diff] [blame] | 553 | if (TableEntry->hasWritebackOperand) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 554 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 555 | |
| 556 | // Grab the super-register source. |
| 557 | MachineOperand MO = MI.getOperand(OpIdx++); |
| 558 | if (!TableEntry->IsLoad) |
| 559 | GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); |
| 560 | |
| 561 | // Add the subregs as sources of the new instruction. |
| 562 | unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | |
| 563 | getKillRegState(MO.isKill())); |
Bob Wilson | dc44990 | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 564 | MIB.addReg(D0, SrcFlags); |
| 565 | if (NumRegs > 1) |
| 566 | MIB.addReg(D1, SrcFlags); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 567 | if (NumRegs > 2) |
| 568 | MIB.addReg(D2, SrcFlags); |
| 569 | if (NumRegs > 3) |
| 570 | MIB.addReg(D3, SrcFlags); |
| 571 | |
| 572 | // Add the lane number operand. |
| 573 | MIB.addImm(Lane); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 574 | OpIdx += 1; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 575 | |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 576 | // Copy the predicate operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 577 | MIB.add(MI.getOperand(OpIdx++)); |
| 578 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 579 | |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 580 | // Copy the super-register source to be an implicit source. |
| 581 | MO.setImplicit(true); |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 582 | MIB.add(MO); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 583 | if (TableEntry->IsLoad) |
| 584 | // Add an implicit def for the super-register. |
| 585 | MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); |
| 586 | TransferImpOps(MI, MIB, MIB); |
Jakob Stoklund Olesen | 465cdf3 | 2011-12-17 00:07:02 +0000 | [diff] [blame] | 587 | // Transfer memoperands. |
| 588 | MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 589 | MI.eraseFromParent(); |
| 590 | } |
| 591 | |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 592 | /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ |
| 593 | /// register operands to real instructions with D register operands. |
| 594 | void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, |
Jim Grosbach | 4a5c887 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 595 | unsigned Opc, bool IsExt) { |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 596 | MachineInstr &MI = *MBBI; |
| 597 | MachineBasicBlock &MBB = *MI.getParent(); |
| 598 | |
| 599 | MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); |
| 600 | unsigned OpIdx = 0; |
| 601 | |
| 602 | // Transfer the destination register operand. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 603 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 604 | if (IsExt) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 605 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 606 | |
| 607 | bool SrcIsKill = MI.getOperand(OpIdx).isKill(); |
| 608 | unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); |
| 609 | unsigned D0, D1, D2, D3; |
| 610 | GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); |
Jim Grosbach | 4a5c887 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 611 | MIB.addReg(D0); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 612 | |
| 613 | // Copy the other source register operand. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 614 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 615 | |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 616 | // Copy the predicate operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 617 | MIB.add(MI.getOperand(OpIdx++)); |
| 618 | MIB.add(MI.getOperand(OpIdx++)); |
Bob Wilson | 450c6cf | 2010-09-16 04:25:37 +0000 | [diff] [blame] | 619 | |
Weiming Zhao | fe26fd2 | 2014-01-15 01:32:12 +0000 | [diff] [blame] | 620 | // Add an implicit kill and use for the super-reg. |
| 621 | MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 622 | TransferImpOps(MI, MIB, MIB); |
| 623 | MI.eraseFromParent(); |
| 624 | } |
| 625 | |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 626 | static bool IsAnAddressOperand(const MachineOperand &MO) { |
| 627 | // This check is overly conservative. Unless we are certain that the machine |
| 628 | // operand is not a symbol reference, we return that it is a symbol reference. |
| 629 | // This is important as the load pair may not be split up Windows. |
| 630 | switch (MO.getType()) { |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 631 | case MachineOperand::MO_Register: |
| 632 | case MachineOperand::MO_Immediate: |
| 633 | case MachineOperand::MO_CImmediate: |
| 634 | case MachineOperand::MO_FPImmediate: |
| 635 | return false; |
| 636 | case MachineOperand::MO_MachineBasicBlock: |
| 637 | return true; |
| 638 | case MachineOperand::MO_FrameIndex: |
| 639 | return false; |
| 640 | case MachineOperand::MO_ConstantPoolIndex: |
| 641 | case MachineOperand::MO_TargetIndex: |
| 642 | case MachineOperand::MO_JumpTableIndex: |
| 643 | case MachineOperand::MO_ExternalSymbol: |
| 644 | case MachineOperand::MO_GlobalAddress: |
| 645 | case MachineOperand::MO_BlockAddress: |
| 646 | return true; |
| 647 | case MachineOperand::MO_RegisterMask: |
| 648 | case MachineOperand::MO_RegisterLiveOut: |
| 649 | return false; |
| 650 | case MachineOperand::MO_Metadata: |
| 651 | case MachineOperand::MO_MCSymbol: |
| 652 | return true; |
| 653 | case MachineOperand::MO_CFIIndex: |
| 654 | return false; |
Tim Northover | 6b3bd61 | 2016-07-29 20:32:59 +0000 | [diff] [blame] | 655 | case MachineOperand::MO_IntrinsicID: |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 656 | case MachineOperand::MO_Predicate: |
Tim Northover | 6b3bd61 | 2016-07-29 20:32:59 +0000 | [diff] [blame] | 657 | llvm_unreachable("should not exist post-isel"); |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 658 | } |
Saleem Abdulrasool | ef550a6 | 2014-04-30 05:12:41 +0000 | [diff] [blame] | 659 | llvm_unreachable("unhandled machine operand type"); |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 660 | } |
| 661 | |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 662 | void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, |
| 663 | MachineBasicBlock::iterator &MBBI) { |
| 664 | MachineInstr &MI = *MBBI; |
| 665 | unsigned Opcode = MI.getOpcode(); |
| 666 | unsigned PredReg = 0; |
Duncan P. N. Exon Smith | 6307eb5 | 2016-02-23 02:46:52 +0000 | [diff] [blame] | 667 | ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 668 | unsigned DstReg = MI.getOperand(0).getReg(); |
| 669 | bool DstIsDead = MI.getOperand(0).isDead(); |
| 670 | bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; |
| 671 | const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 672 | bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 673 | MachineInstrBuilder LO16, HI16; |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 674 | |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 675 | if (!STI->hasV6T2Ops() && |
| 676 | (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 677 | // FIXME Windows CE supports older ARM CPUs |
| 678 | assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); |
| 679 | |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 680 | // Expand into a movi + orr. |
| 681 | LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); |
| 682 | HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) |
| 683 | .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) |
| 684 | .addReg(DstReg); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 685 | |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 686 | assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); |
| 687 | unsigned ImmVal = (unsigned)MO.getImm(); |
| 688 | unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); |
| 689 | unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); |
| 690 | LO16 = LO16.addImm(SOImmValV1); |
| 691 | HI16 = HI16.addImm(SOImmValV2); |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 692 | LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
| 693 | HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 694 | LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); |
| 695 | HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 696 | TransferImpOps(MI, LO16, HI16); |
| 697 | MI.eraseFromParent(); |
| 698 | return; |
| 699 | } |
| 700 | |
| 701 | unsigned LO16Opc = 0; |
| 702 | unsigned HI16Opc = 0; |
| 703 | if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { |
| 704 | LO16Opc = ARM::t2MOVi16; |
| 705 | HI16Opc = ARM::t2MOVTi16; |
| 706 | } else { |
| 707 | LO16Opc = ARM::MOVi16; |
| 708 | HI16Opc = ARM::MOVTi16; |
| 709 | } |
| 710 | |
| 711 | LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); |
| 712 | HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) |
| 713 | .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) |
| 714 | .addReg(DstReg); |
| 715 | |
Saleem Abdulrasool | d6c0ba3 | 2014-05-01 04:19:56 +0000 | [diff] [blame] | 716 | switch (MO.getType()) { |
| 717 | case MachineOperand::MO_Immediate: { |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 718 | unsigned Imm = MO.getImm(); |
| 719 | unsigned Lo16 = Imm & 0xffff; |
| 720 | unsigned Hi16 = (Imm >> 16) & 0xffff; |
| 721 | LO16 = LO16.addImm(Lo16); |
| 722 | HI16 = HI16.addImm(Hi16); |
Saleem Abdulrasool | d6c0ba3 | 2014-05-01 04:19:56 +0000 | [diff] [blame] | 723 | break; |
| 724 | } |
| 725 | case MachineOperand::MO_ExternalSymbol: { |
| 726 | const char *ES = MO.getSymbolName(); |
| 727 | unsigned TF = MO.getTargetFlags(); |
| 728 | LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); |
| 729 | HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); |
| 730 | break; |
| 731 | } |
| 732 | default: { |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 733 | const GlobalValue *GV = MO.getGlobal(); |
| 734 | unsigned TF = MO.getTargetFlags(); |
| 735 | LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); |
| 736 | HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); |
Saleem Abdulrasool | d6c0ba3 | 2014-05-01 04:19:56 +0000 | [diff] [blame] | 737 | break; |
| 738 | } |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 739 | } |
| 740 | |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 741 | LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
| 742 | HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 743 | LO16.addImm(Pred).addReg(PredReg); |
| 744 | HI16.addImm(Pred).addReg(PredReg); |
| 745 | |
Saleem Abdulrasool | 8d60fdc | 2014-05-21 01:25:24 +0000 | [diff] [blame] | 746 | if (RequiresBundling) |
Duncan P. N. Exon Smith | c5b668d | 2016-02-22 20:49:58 +0000 | [diff] [blame] | 747 | finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); |
Saleem Abdulrasool | f822263 | 2014-04-30 04:54:58 +0000 | [diff] [blame] | 748 | |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 749 | TransferImpOps(MI, LO16, HI16); |
| 750 | MI.eraseFromParent(); |
| 751 | } |
| 752 | |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 753 | /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 754 | /// possible. This only gets used at -O0 so we don't care about efficiency of |
| 755 | /// the generated code. |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 756 | bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, |
| 757 | MachineBasicBlock::iterator MBBI, |
| 758 | unsigned LdrexOp, unsigned StrexOp, |
| 759 | unsigned UxtOp, |
| 760 | MachineBasicBlock::iterator &NextMBBI) { |
| 761 | bool IsThumb = STI->isThumb(); |
| 762 | MachineInstr &MI = *MBBI; |
| 763 | DebugLoc DL = MI.getDebugLoc(); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 764 | const MachineOperand &Dest = MI.getOperand(0); |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 765 | unsigned TempReg = MI.getOperand(1).getReg(); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 766 | // Duplicating undef operands into 2 instructions does not guarantee the same |
| 767 | // value on both; However undef should be replaced by xzr anyway. |
| 768 | assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); |
| 769 | unsigned AddrReg = MI.getOperand(2).getReg(); |
| 770 | unsigned DesiredReg = MI.getOperand(3).getReg(); |
| 771 | unsigned NewReg = MI.getOperand(4).getReg(); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 772 | |
| 773 | MachineFunction *MF = MBB.getParent(); |
| 774 | auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); |
| 775 | auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); |
| 776 | auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); |
| 777 | |
| 778 | MF->insert(++MBB.getIterator(), LoadCmpBB); |
| 779 | MF->insert(++LoadCmpBB->getIterator(), StoreBB); |
| 780 | MF->insert(++StoreBB->getIterator(), DoneBB); |
| 781 | |
| 782 | if (UxtOp) { |
| 783 | MachineInstrBuilder MIB = |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 784 | BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) |
| 785 | .addReg(DesiredReg, RegState::Kill); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 786 | if (!IsThumb) |
| 787 | MIB.addImm(0); |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 788 | MIB.add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 789 | } |
| 790 | |
| 791 | // .Lloadcmp: |
| 792 | // ldrex rDest, [rAddr] |
| 793 | // cmp rDest, rDesired |
| 794 | // bne .Ldone |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 795 | |
| 796 | MachineInstrBuilder MIB; |
| 797 | MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 798 | MIB.addReg(AddrReg); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 799 | if (LdrexOp == ARM::t2LDREX) |
| 800 | MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 801 | MIB.add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 802 | |
| 803 | unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 804 | BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) |
| 805 | .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 806 | .addReg(DesiredReg) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 807 | .add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 808 | unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; |
| 809 | BuildMI(LoadCmpBB, DL, TII->get(Bcc)) |
| 810 | .addMBB(DoneBB) |
| 811 | .addImm(ARMCC::NE) |
| 812 | .addReg(ARM::CPSR, RegState::Kill); |
| 813 | LoadCmpBB->addSuccessor(DoneBB); |
| 814 | LoadCmpBB->addSuccessor(StoreBB); |
| 815 | |
| 816 | // .Lstore: |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 817 | // strex rTempReg, rNew, [rAddr] |
| 818 | // cmp rTempReg, #0 |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 819 | // bne .Lloadcmp |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 820 | MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 821 | .addReg(NewReg) |
| 822 | .addReg(AddrReg); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 823 | if (StrexOp == ARM::t2STREX) |
| 824 | MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 825 | MIB.add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 826 | |
| 827 | unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 828 | BuildMI(StoreBB, DL, TII->get(CMPri)) |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 829 | .addReg(TempReg, RegState::Kill) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 830 | .addImm(0) |
| 831 | .add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 832 | BuildMI(StoreBB, DL, TII->get(Bcc)) |
| 833 | .addMBB(LoadCmpBB) |
| 834 | .addImm(ARMCC::NE) |
| 835 | .addReg(ARM::CPSR, RegState::Kill); |
| 836 | StoreBB->addSuccessor(LoadCmpBB); |
| 837 | StoreBB->addSuccessor(DoneBB); |
| 838 | |
| 839 | DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); |
| 840 | DoneBB->transferSuccessors(&MBB); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 841 | |
Ahmed Bougacha | b4af107 | 2016-04-27 20:32:54 +0000 | [diff] [blame] | 842 | MBB.addSuccessor(LoadCmpBB); |
| 843 | |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 844 | NextMBBI = MBB.end(); |
| 845 | MI.eraseFromParent(); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 846 | |
| 847 | // Recompute livein lists. |
| 848 | const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); |
| 849 | LivePhysRegs LiveRegs; |
| 850 | computeLiveIns(LiveRegs, MRI, *DoneBB); |
| 851 | computeLiveIns(LiveRegs, MRI, *StoreBB); |
| 852 | computeLiveIns(LiveRegs, MRI, *LoadCmpBB); |
| 853 | // Do an extra pass around the loop to get loop carried registers right. |
| 854 | StoreBB->clearLiveIns(); |
| 855 | computeLiveIns(LiveRegs, MRI, *StoreBB); |
| 856 | LoadCmpBB->clearLiveIns(); |
| 857 | computeLiveIns(LiveRegs, MRI, *LoadCmpBB); |
| 858 | |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 859 | return true; |
| 860 | } |
| 861 | |
| 862 | /// ARM's ldrexd/strexd take a consecutive register pair (represented as a |
| 863 | /// single GPRPair register), Thumb's take two separate registers so we need to |
| 864 | /// extract the subregs from the pair. |
| 865 | static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, |
| 866 | unsigned Flags, bool IsThumb, |
| 867 | const TargetRegisterInfo *TRI) { |
| 868 | if (IsThumb) { |
| 869 | unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); |
| 870 | unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); |
| 871 | MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead())); |
| 872 | MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); |
| 873 | } else |
| 874 | MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead())); |
| 875 | } |
| 876 | |
| 877 | /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. |
| 878 | bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, |
| 879 | MachineBasicBlock::iterator MBBI, |
| 880 | MachineBasicBlock::iterator &NextMBBI) { |
| 881 | bool IsThumb = STI->isThumb(); |
| 882 | MachineInstr &MI = *MBBI; |
| 883 | DebugLoc DL = MI.getDebugLoc(); |
| 884 | MachineOperand &Dest = MI.getOperand(0); |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 885 | unsigned TempReg = MI.getOperand(1).getReg(); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 886 | // Duplicating undef operands into 2 instructions does not guarantee the same |
| 887 | // value on both; However undef should be replaced by xzr anyway. |
| 888 | assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); |
| 889 | unsigned AddrReg = MI.getOperand(2).getReg(); |
| 890 | unsigned DesiredReg = MI.getOperand(3).getReg(); |
| 891 | MachineOperand New = MI.getOperand(4); |
| 892 | New.setIsKill(false); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 893 | |
| 894 | unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); |
| 895 | unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 896 | unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); |
| 897 | unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 898 | |
| 899 | MachineFunction *MF = MBB.getParent(); |
| 900 | auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); |
| 901 | auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); |
| 902 | auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); |
| 903 | |
| 904 | MF->insert(++MBB.getIterator(), LoadCmpBB); |
| 905 | MF->insert(++LoadCmpBB->getIterator(), StoreBB); |
| 906 | MF->insert(++StoreBB->getIterator(), DoneBB); |
| 907 | |
| 908 | // .Lloadcmp: |
| 909 | // ldrexd rDestLo, rDestHi, [rAddr] |
| 910 | // cmp rDestLo, rDesiredLo |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 911 | // sbcs rTempReg<dead>, rDestHi, rDesiredHi |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 912 | // bne .Ldone |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 913 | unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; |
| 914 | MachineInstrBuilder MIB; |
| 915 | MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); |
| 916 | addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 917 | MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 918 | |
| 919 | unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 920 | BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) |
| 921 | .addReg(DestLo, getKillRegState(Dest.isDead())) |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 922 | .addReg(DesiredLo) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 923 | .add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 924 | |
Oleg Ranevskyy | e2ae415 | 2016-12-01 22:58:35 +0000 | [diff] [blame] | 925 | BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) |
| 926 | .addReg(DestHi, getKillRegState(Dest.isDead())) |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 927 | .addReg(DesiredHi) |
Oleg Ranevskyy | e2ae415 | 2016-12-01 22:58:35 +0000 | [diff] [blame] | 928 | .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 929 | |
| 930 | unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; |
| 931 | BuildMI(LoadCmpBB, DL, TII->get(Bcc)) |
| 932 | .addMBB(DoneBB) |
| 933 | .addImm(ARMCC::NE) |
| 934 | .addReg(ARM::CPSR, RegState::Kill); |
| 935 | LoadCmpBB->addSuccessor(DoneBB); |
| 936 | LoadCmpBB->addSuccessor(StoreBB); |
| 937 | |
| 938 | // .Lstore: |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 939 | // strexd rTempReg, rNewLo, rNewHi, [rAddr] |
| 940 | // cmp rTempReg, #0 |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 941 | // bne .Lloadcmp |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 942 | unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 943 | MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 944 | addExclusiveRegPair(MIB, New, 0, IsThumb, TRI); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 945 | MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 946 | |
| 947 | unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 948 | BuildMI(StoreBB, DL, TII->get(CMPri)) |
Matthias Braun | a88587c | 2017-08-09 22:22:05 +0000 | [diff] [blame] | 949 | .addReg(TempReg, RegState::Kill) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 950 | .addImm(0) |
| 951 | .add(predOps(ARMCC::AL)); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 952 | BuildMI(StoreBB, DL, TII->get(Bcc)) |
| 953 | .addMBB(LoadCmpBB) |
| 954 | .addImm(ARMCC::NE) |
| 955 | .addReg(ARM::CPSR, RegState::Kill); |
| 956 | StoreBB->addSuccessor(LoadCmpBB); |
| 957 | StoreBB->addSuccessor(DoneBB); |
| 958 | |
| 959 | DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); |
| 960 | DoneBB->transferSuccessors(&MBB); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 961 | |
Ahmed Bougacha | b4af107 | 2016-04-27 20:32:54 +0000 | [diff] [blame] | 962 | MBB.addSuccessor(LoadCmpBB); |
| 963 | |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 964 | NextMBBI = MBB.end(); |
| 965 | MI.eraseFromParent(); |
Matthias Braun | 05eeadb | 2017-05-31 01:21:35 +0000 | [diff] [blame] | 966 | |
| 967 | // Recompute livein lists. |
| 968 | const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); |
| 969 | LivePhysRegs LiveRegs; |
| 970 | computeLiveIns(LiveRegs, MRI, *DoneBB); |
| 971 | computeLiveIns(LiveRegs, MRI, *StoreBB); |
| 972 | computeLiveIns(LiveRegs, MRI, *LoadCmpBB); |
| 973 | // Do an extra pass around the loop to get loop carried registers right. |
| 974 | StoreBB->clearLiveIns(); |
| 975 | computeLiveIns(LiveRegs, MRI, *StoreBB); |
| 976 | LoadCmpBB->clearLiveIns(); |
| 977 | computeLiveIns(LiveRegs, MRI, *LoadCmpBB); |
| 978 | |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 979 | return true; |
| 980 | } |
| 981 | |
| 982 | |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 983 | bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 984 | MachineBasicBlock::iterator MBBI, |
| 985 | MachineBasicBlock::iterator &NextMBBI) { |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 986 | MachineInstr &MI = *MBBI; |
| 987 | unsigned Opcode = MI.getOpcode(); |
| 988 | switch (Opcode) { |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 989 | default: |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 990 | return false; |
Quentin Colombet | 71a7148 | 2015-07-20 21:42:14 +0000 | [diff] [blame] | 991 | |
| 992 | case ARM::TCRETURNdi: |
| 993 | case ARM::TCRETURNri: { |
| 994 | MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); |
| 995 | assert(MBBI->isReturn() && |
| 996 | "Can only insert epilog into returning blocks"); |
| 997 | unsigned RetOpcode = MBBI->getOpcode(); |
| 998 | DebugLoc dl = MBBI->getDebugLoc(); |
| 999 | const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( |
| 1000 | MBB.getParent()->getSubtarget().getInstrInfo()); |
| 1001 | |
| 1002 | // Tail call return: adjust the stack pointer and jump to callee. |
| 1003 | MBBI = MBB.getLastNonDebugInstr(); |
| 1004 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
| 1005 | |
| 1006 | // Jump to label or value in register. |
| 1007 | if (RetOpcode == ARM::TCRETURNdi) { |
| 1008 | unsigned TCOpcode = |
| 1009 | STI->isThumb() |
| 1010 | ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) |
| 1011 | : ARM::TAILJMPd; |
| 1012 | MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); |
| 1013 | if (JumpTarget.isGlobal()) |
| 1014 | MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), |
| 1015 | JumpTarget.getTargetFlags()); |
| 1016 | else { |
| 1017 | assert(JumpTarget.isSymbol()); |
| 1018 | MIB.addExternalSymbol(JumpTarget.getSymbolName(), |
| 1019 | JumpTarget.getTargetFlags()); |
| 1020 | } |
| 1021 | |
| 1022 | // Add the default predicate in Thumb mode. |
| 1023 | if (STI->isThumb()) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1024 | MIB.add(predOps(ARMCC::AL)); |
Quentin Colombet | 71a7148 | 2015-07-20 21:42:14 +0000 | [diff] [blame] | 1025 | } else if (RetOpcode == ARM::TCRETURNri) { |
| 1026 | BuildMI(MBB, MBBI, dl, |
| 1027 | TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)) |
| 1028 | .addReg(JumpTarget.getReg(), RegState::Kill); |
| 1029 | } |
| 1030 | |
Duncan P. N. Exon Smith | 29c5249 | 2016-07-08 20:21:17 +0000 | [diff] [blame] | 1031 | auto NewMI = std::prev(MBBI); |
Quentin Colombet | 71a7148 | 2015-07-20 21:42:14 +0000 | [diff] [blame] | 1032 | for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) |
| 1033 | NewMI->addOperand(MBBI->getOperand(i)); |
| 1034 | |
| 1035 | // Delete the pseudo instruction TCRETURN. |
| 1036 | MBB.erase(MBBI); |
| 1037 | MBBI = NewMI; |
| 1038 | return true; |
| 1039 | } |
Jim Grosbach | bb0547d | 2011-03-11 23:09:50 +0000 | [diff] [blame] | 1040 | case ARM::VMOVScc: |
| 1041 | case ARM::VMOVDcc: { |
| 1042 | unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; |
| 1043 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), |
| 1044 | MI.getOperand(1).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1045 | .add(MI.getOperand(2)) |
| 1046 | .addImm(MI.getOperand(3).getImm()) // 'pred' |
| 1047 | .add(MI.getOperand(4)); |
Jim Grosbach | bb0547d | 2011-03-11 23:09:50 +0000 | [diff] [blame] | 1048 | |
| 1049 | MI.eraseFromParent(); |
| 1050 | return true; |
| 1051 | } |
Jim Grosbach | 4def704 | 2011-07-01 17:14:11 +0000 | [diff] [blame] | 1052 | case ARM::t2MOVCCr: |
Jim Grosbach | 62a7b47 | 2011-03-10 23:56:09 +0000 | [diff] [blame] | 1053 | case ARM::MOVCCr: { |
Jim Grosbach | 4def704 | 2011-07-01 17:14:11 +0000 | [diff] [blame] | 1054 | unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; |
| 1055 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), |
Jim Grosbach | 62a7b47 | 2011-03-10 23:56:09 +0000 | [diff] [blame] | 1056 | MI.getOperand(1).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1057 | .add(MI.getOperand(2)) |
| 1058 | .addImm(MI.getOperand(3).getImm()) // 'pred' |
| 1059 | .add(MI.getOperand(4)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1060 | .add(condCodeOp()); // 's' bit |
Jim Grosbach | 62a7b47 | 2011-03-10 23:56:09 +0000 | [diff] [blame] | 1061 | |
| 1062 | MI.eraseFromParent(); |
| 1063 | return true; |
| 1064 | } |
Owen Anderson | 0491270 | 2011-07-21 23:38:37 +0000 | [diff] [blame] | 1065 | case ARM::MOVCCsi: { |
| 1066 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), |
| 1067 | (MI.getOperand(1).getReg())) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1068 | .add(MI.getOperand(2)) |
| 1069 | .addImm(MI.getOperand(3).getImm()) |
| 1070 | .addImm(MI.getOperand(4).getImm()) // 'pred' |
| 1071 | .add(MI.getOperand(5)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1072 | .add(condCodeOp()); // 's' bit |
Owen Anderson | 0491270 | 2011-07-21 23:38:37 +0000 | [diff] [blame] | 1073 | |
| 1074 | MI.eraseFromParent(); |
| 1075 | return true; |
| 1076 | } |
Owen Anderson | b595ed0 | 2011-07-21 18:54:16 +0000 | [diff] [blame] | 1077 | case ARM::MOVCCsr: { |
Owen Anderson | 0491270 | 2011-07-21 23:38:37 +0000 | [diff] [blame] | 1078 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), |
Jim Grosbach | 62a7b47 | 2011-03-10 23:56:09 +0000 | [diff] [blame] | 1079 | (MI.getOperand(1).getReg())) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1080 | .add(MI.getOperand(2)) |
| 1081 | .add(MI.getOperand(3)) |
| 1082 | .addImm(MI.getOperand(4).getImm()) |
| 1083 | .addImm(MI.getOperand(5).getImm()) // 'pred' |
| 1084 | .add(MI.getOperand(6)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1085 | .add(condCodeOp()); // 's' bit |
Jim Grosbach | 62a7b47 | 2011-03-10 23:56:09 +0000 | [diff] [blame] | 1086 | |
| 1087 | MI.eraseFromParent(); |
| 1088 | return true; |
| 1089 | } |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 1090 | case ARM::t2MOVCCi16: |
Jim Grosbach | d025498 | 2011-03-11 01:09:28 +0000 | [diff] [blame] | 1091 | case ARM::MOVCCi16: { |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 1092 | unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; |
| 1093 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), |
Jim Grosbach | d025498 | 2011-03-11 01:09:28 +0000 | [diff] [blame] | 1094 | MI.getOperand(1).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1095 | .addImm(MI.getOperand(2).getImm()) |
| 1096 | .addImm(MI.getOperand(3).getImm()) // 'pred' |
| 1097 | .add(MI.getOperand(4)); |
Jim Grosbach | d025498 | 2011-03-11 01:09:28 +0000 | [diff] [blame] | 1098 | MI.eraseFromParent(); |
| 1099 | return true; |
| 1100 | } |
Jim Grosbach | 4def704 | 2011-07-01 17:14:11 +0000 | [diff] [blame] | 1101 | case ARM::t2MOVCCi: |
Jim Grosbach | d025498 | 2011-03-11 01:09:28 +0000 | [diff] [blame] | 1102 | case ARM::MOVCCi: { |
Jim Grosbach | 4def704 | 2011-07-01 17:14:11 +0000 | [diff] [blame] | 1103 | unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; |
| 1104 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), |
Jim Grosbach | d025498 | 2011-03-11 01:09:28 +0000 | [diff] [blame] | 1105 | MI.getOperand(1).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1106 | .addImm(MI.getOperand(2).getImm()) |
| 1107 | .addImm(MI.getOperand(3).getImm()) // 'pred' |
| 1108 | .add(MI.getOperand(4)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1109 | .add(condCodeOp()); // 's' bit |
Jim Grosbach | d025498 | 2011-03-11 01:09:28 +0000 | [diff] [blame] | 1110 | |
| 1111 | MI.eraseFromParent(); |
| 1112 | return true; |
| 1113 | } |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 1114 | case ARM::t2MVNCCi: |
Jim Grosbach | fa56bca | 2011-03-11 19:55:55 +0000 | [diff] [blame] | 1115 | case ARM::MVNCCi: { |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 1116 | unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; |
| 1117 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), |
Jim Grosbach | fa56bca | 2011-03-11 19:55:55 +0000 | [diff] [blame] | 1118 | MI.getOperand(1).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1119 | .addImm(MI.getOperand(2).getImm()) |
| 1120 | .addImm(MI.getOperand(3).getImm()) // 'pred' |
| 1121 | .add(MI.getOperand(4)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1122 | .add(condCodeOp()); // 's' bit |
Jim Grosbach | fa56bca | 2011-03-11 19:55:55 +0000 | [diff] [blame] | 1123 | |
| 1124 | MI.eraseFromParent(); |
| 1125 | return true; |
| 1126 | } |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 1127 | case ARM::t2MOVCClsl: |
| 1128 | case ARM::t2MOVCClsr: |
| 1129 | case ARM::t2MOVCCasr: |
| 1130 | case ARM::t2MOVCCror: { |
| 1131 | unsigned NewOpc; |
| 1132 | switch (Opcode) { |
| 1133 | case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; |
| 1134 | case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; |
| 1135 | case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; |
| 1136 | case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; |
| 1137 | default: llvm_unreachable("unexpeced conditional move"); |
| 1138 | } |
| 1139 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), |
| 1140 | MI.getOperand(1).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1141 | .add(MI.getOperand(2)) |
| 1142 | .addImm(MI.getOperand(3).getImm()) |
| 1143 | .addImm(MI.getOperand(4).getImm()) // 'pred' |
| 1144 | .add(MI.getOperand(5)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1145 | .add(condCodeOp()); // 's' bit |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 1146 | MI.eraseFromParent(); |
| 1147 | return true; |
| 1148 | } |
Chad Rosier | 1ec8e40 | 2012-11-06 23:05:24 +0000 | [diff] [blame] | 1149 | case ARM::Int_eh_sjlj_dispatchsetup: { |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1150 | MachineFunction &MF = *MI.getParent()->getParent(); |
| 1151 | const ARMBaseInstrInfo *AII = |
| 1152 | static_cast<const ARMBaseInstrInfo*>(TII); |
| 1153 | const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); |
| 1154 | // For functions using a base pointer, we rematerialize it (via the frame |
| 1155 | // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it |
| 1156 | // for us. Otherwise, expand to nothing. |
| 1157 | if (RI.hasBasePointer(MF)) { |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1158 | int32_t NumBytes = AFI->getFramePtrSpillOffset(); |
| 1159 | unsigned FramePtr = RI.getFrameRegister(MF); |
Eric Christopher | fc6de42 | 2014-08-05 02:39:49 +0000 | [diff] [blame] | 1160 | assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && |
| 1161 | "base pointer without frame pointer?"); |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1162 | |
| 1163 | if (AFI->isThumb2Function()) { |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1164 | emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, |
| 1165 | FramePtr, -NumBytes, ARMCC::AL, 0, *TII); |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1166 | } else if (AFI->isThumbFunction()) { |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1167 | emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, |
| 1168 | FramePtr, -NumBytes, *TII, RI); |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1169 | } else { |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1170 | emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, |
| 1171 | FramePtr, -NumBytes, ARMCC::AL, 0, |
| 1172 | *TII); |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1173 | } |
Jim Grosbach | cb6fc2b | 2010-10-20 00:02:50 +0000 | [diff] [blame] | 1174 | // If there's dynamic realignment, adjust for it. |
Jim Grosbach | 723159e | 2010-10-20 01:10:01 +0000 | [diff] [blame] | 1175 | if (RI.needsStackRealignment(MF)) { |
Matthias Braun | 941a705 | 2016-07-28 18:40:00 +0000 | [diff] [blame] | 1176 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
| 1177 | unsigned MaxAlign = MFI.getMaxAlignment(); |
Jim Grosbach | cb6fc2b | 2010-10-20 00:02:50 +0000 | [diff] [blame] | 1178 | assert (!AFI->isThumb1OnlyFunction()); |
| 1179 | // Emit bic r6, r6, MaxAlign |
Kristof Beyls | 933de7a | 2015-01-08 15:09:14 +0000 | [diff] [blame] | 1180 | assert(MaxAlign <= 256 && "The BIC instruction cannot encode " |
| 1181 | "immediates larger than 256 with all lower " |
| 1182 | "bits set."); |
Jim Grosbach | cb6fc2b | 2010-10-20 00:02:50 +0000 | [diff] [blame] | 1183 | unsigned bicOpc = AFI->isThumbFunction() ? |
| 1184 | ARM::t2BICri : ARM::BICri; |
Diana Picus | 8a73f55 | 2017-01-13 10:18:01 +0000 | [diff] [blame] | 1185 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) |
| 1186 | .addReg(ARM::R6, RegState::Kill) |
| 1187 | .addImm(MaxAlign - 1) |
| 1188 | .add(predOps(ARMCC::AL)) |
| 1189 | .add(condCodeOp()); |
Jim Grosbach | cb6fc2b | 2010-10-20 00:02:50 +0000 | [diff] [blame] | 1190 | } |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1191 | |
| 1192 | } |
| 1193 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1194 | return true; |
Jim Grosbach | bbdc5d2 | 2010-10-19 23:27:08 +0000 | [diff] [blame] | 1195 | } |
| 1196 | |
Jim Grosbach | 8b6a9c1 | 2010-10-14 22:57:13 +0000 | [diff] [blame] | 1197 | case ARM::MOVsrl_flag: |
| 1198 | case ARM::MOVsra_flag: { |
Robert Wilhelm | 2788d3e | 2013-09-28 13:42:22 +0000 | [diff] [blame] | 1199 | // These are just fancy MOVs instructions. |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1200 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), |
| 1201 | MI.getOperand(0).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1202 | .add(MI.getOperand(1)) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1203 | .addImm(ARM_AM::getSORegOpc( |
| 1204 | (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) |
| 1205 | .add(predOps(ARMCC::AL)) |
| 1206 | .addReg(ARM::CPSR, RegState::Define); |
Jim Grosbach | 8b6a9c1 | 2010-10-14 22:57:13 +0000 | [diff] [blame] | 1207 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1208 | return true; |
Jim Grosbach | 8b6a9c1 | 2010-10-14 22:57:13 +0000 | [diff] [blame] | 1209 | } |
| 1210 | case ARM::RRX: { |
| 1211 | // This encodes as "MOVs Rd, Rm, rrx |
| 1212 | MachineInstrBuilder MIB = |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1213 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), |
| 1214 | MI.getOperand(0).getReg()) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1215 | .add(MI.getOperand(1)) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1216 | .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)) |
| 1217 | .add(predOps(ARMCC::AL)) |
Diana Picus | bd66b7d | 2017-01-20 08:15:24 +0000 | [diff] [blame] | 1218 | .add(condCodeOp()); |
Jim Grosbach | 8b6a9c1 | 2010-10-14 22:57:13 +0000 | [diff] [blame] | 1219 | TransferImpOps(MI, MIB, MIB); |
| 1220 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1221 | return true; |
Jim Grosbach | 8b6a9c1 | 2010-10-14 22:57:13 +0000 | [diff] [blame] | 1222 | } |
Jim Grosbach | e4750ef | 2011-06-30 19:38:01 +0000 | [diff] [blame] | 1223 | case ARM::tTPsoft: |
Jason W Kim | c79c5f6 | 2010-12-08 23:14:44 +0000 | [diff] [blame] | 1224 | case ARM::TPsoft: { |
Saleem Abdulrasool | 5282eed | 2017-01-29 16:46:22 +0000 | [diff] [blame] | 1225 | const bool Thumb = Opcode == ARM::tTPsoft; |
| 1226 | |
Christian Pirker | c6308f5 | 2014-06-24 15:45:59 +0000 | [diff] [blame] | 1227 | MachineInstrBuilder MIB; |
Saleem Abdulrasool | 5282eed | 2017-01-29 16:46:22 +0000 | [diff] [blame] | 1228 | if (STI->genLongCalls()) { |
| 1229 | MachineFunction *MF = MBB.getParent(); |
| 1230 | MachineConstantPool *MCP = MF->getConstantPool(); |
| 1231 | unsigned PCLabelID = AFI->createPICLabelUId(); |
| 1232 | MachineConstantPoolValue *CPV = |
| 1233 | ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(), |
| 1234 | "__aeabi_read_tp", PCLabelID, 0); |
| 1235 | unsigned Reg = MI.getOperand(0).getReg(); |
Christian Pirker | c6308f5 | 2014-06-24 15:45:59 +0000 | [diff] [blame] | 1236 | MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
Saleem Abdulrasool | 5282eed | 2017-01-29 16:46:22 +0000 | [diff] [blame] | 1237 | TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) |
| 1238 | .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); |
| 1239 | if (!Thumb) |
| 1240 | MIB.addImm(0); |
| 1241 | MIB.add(predOps(ARMCC::AL)); |
| 1242 | |
| 1243 | MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
| 1244 | TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); |
| 1245 | if (Thumb) |
| 1246 | MIB.add(predOps(ARMCC::AL)); |
| 1247 | MIB.addReg(Reg, RegState::Kill); |
| 1248 | } else { |
| 1249 | MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
| 1250 | TII->get(Thumb ? ARM::tBL : ARM::BL)); |
| 1251 | if (Thumb) |
| 1252 | MIB.add(predOps(ARMCC::AL)); |
| 1253 | MIB.addExternalSymbol("__aeabi_read_tp", 0); |
| 1254 | } |
Jason W Kim | c79c5f6 | 2010-12-08 23:14:44 +0000 | [diff] [blame] | 1255 | |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 1256 | MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Jason W Kim | c79c5f6 | 2010-12-08 23:14:44 +0000 | [diff] [blame] | 1257 | TransferImpOps(MI, MIB, MIB); |
| 1258 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1259 | return true; |
Bill Wendling | f75412d | 2010-12-09 00:51:54 +0000 | [diff] [blame] | 1260 | } |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 1261 | case ARM::tLDRpci_pic: |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1262 | case ARM::t2LDRpci_pic: { |
| 1263 | unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) |
Owen Anderson | 4ebf471 | 2011-02-08 22:39:40 +0000 | [diff] [blame] | 1264 | ? ARM::tLDRpci : ARM::t2LDRpci; |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1265 | unsigned DstReg = MI.getOperand(0).getReg(); |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 1266 | bool DstIsDead = MI.getOperand(0).isDead(); |
| 1267 | MachineInstrBuilder MIB1 = |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1268 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1269 | .add(MI.getOperand(1)) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1270 | .add(predOps(ARMCC::AL)); |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 1271 | MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1272 | MachineInstrBuilder MIB2 = |
| 1273 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) |
| 1274 | .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) |
| 1275 | .addReg(DstReg) |
| 1276 | .add(MI.getOperand(2)); |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 1277 | TransferImpOps(MI, MIB1, MIB2); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1278 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1279 | return true; |
| 1280 | } |
| 1281 | |
Tim Northover | 72360d2 | 2013-12-02 10:35:41 +0000 | [diff] [blame] | 1282 | case ARM::LDRLIT_ga_abs: |
| 1283 | case ARM::LDRLIT_ga_pcrel: |
| 1284 | case ARM::LDRLIT_ga_pcrel_ldr: |
| 1285 | case ARM::tLDRLIT_ga_abs: |
| 1286 | case ARM::tLDRLIT_ga_pcrel: { |
| 1287 | unsigned DstReg = MI.getOperand(0).getReg(); |
| 1288 | bool DstIsDead = MI.getOperand(0).isDead(); |
| 1289 | const MachineOperand &MO1 = MI.getOperand(1); |
| 1290 | const GlobalValue *GV = MO1.getGlobal(); |
| 1291 | bool IsARM = |
| 1292 | Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; |
| 1293 | bool IsPIC = |
| 1294 | Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; |
| 1295 | unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; |
| 1296 | unsigned PICAddOpc = |
| 1297 | IsARM |
Tim Northover | 2ac7e4b | 2014-12-10 23:40:50 +0000 | [diff] [blame] | 1298 | ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) |
Tim Northover | 72360d2 | 2013-12-02 10:35:41 +0000 | [diff] [blame] | 1299 | : ARM::tPICADD; |
| 1300 | |
| 1301 | // We need a new const-pool entry to load from. |
| 1302 | MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); |
| 1303 | unsigned ARMPCLabelIndex = 0; |
| 1304 | MachineConstantPoolValue *CPV; |
| 1305 | |
| 1306 | if (IsPIC) { |
| 1307 | unsigned PCAdj = IsARM ? 8 : 4; |
| 1308 | ARMPCLabelIndex = AFI->createPICLabelUId(); |
| 1309 | CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, |
| 1310 | ARMCP::CPValue, PCAdj); |
| 1311 | } else |
| 1312 | CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); |
| 1313 | |
| 1314 | MachineInstrBuilder MIB = |
| 1315 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) |
| 1316 | .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); |
| 1317 | if (IsARM) |
| 1318 | MIB.addImm(0); |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1319 | MIB.add(predOps(ARMCC::AL)); |
Tim Northover | 72360d2 | 2013-12-02 10:35:41 +0000 | [diff] [blame] | 1320 | |
| 1321 | if (IsPIC) { |
| 1322 | MachineInstrBuilder MIB = |
| 1323 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) |
| 1324 | .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) |
| 1325 | .addReg(DstReg) |
| 1326 | .addImm(ARMPCLabelIndex); |
| 1327 | |
| 1328 | if (IsARM) |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1329 | MIB.add(predOps(ARMCC::AL)); |
Tim Northover | 72360d2 | 2013-12-02 10:35:41 +0000 | [diff] [blame] | 1330 | } |
| 1331 | |
| 1332 | MI.eraseFromParent(); |
| 1333 | return true; |
| 1334 | } |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1335 | case ARM::MOV_ga_pcrel: |
| 1336 | case ARM::MOV_ga_pcrel_ldr: |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1337 | case ARM::t2MOV_ga_pcrel: { |
| 1338 | // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1339 | unsigned LabelId = AFI->createPICLabelUId(); |
| 1340 | unsigned DstReg = MI.getOperand(0).getReg(); |
| 1341 | bool DstIsDead = MI.getOperand(0).isDead(); |
| 1342 | const MachineOperand &MO1 = MI.getOperand(1); |
| 1343 | const GlobalValue *GV = MO1.getGlobal(); |
| 1344 | unsigned TF = MO1.getTargetFlags(); |
Tim Northover | db962e2c | 2013-11-25 16:24:52 +0000 | [diff] [blame] | 1345 | bool isARM = Opcode != ARM::t2MOV_ga_pcrel; |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1346 | unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; |
Jim Grosbach | 06210a2 | 2011-07-13 17:25:55 +0000 | [diff] [blame] | 1347 | unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; |
Tim Northover | db962e2c | 2013-11-25 16:24:52 +0000 | [diff] [blame] | 1348 | unsigned LO16TF = TF | ARMII::MO_LO16; |
| 1349 | unsigned HI16TF = TF | ARMII::MO_HI16; |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1350 | unsigned PICAddOpc = isARM |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1351 | ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1352 | : ARM::tPICADD; |
| 1353 | MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
| 1354 | TII->get(LO16Opc), DstReg) |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1355 | .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1356 | .addImm(LabelId); |
Tim Northover | db962e2c | 2013-11-25 16:24:52 +0000 | [diff] [blame] | 1357 | |
| 1358 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1359 | .addReg(DstReg) |
| 1360 | .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) |
| 1361 | .addImm(LabelId); |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1362 | |
| 1363 | MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1364 | TII->get(PICAddOpc)) |
| 1365 | .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) |
| 1366 | .addReg(DstReg).addImm(LabelId); |
| 1367 | if (isARM) { |
Diana Picus | 4f8c3e1 | 2017-01-13 09:37:56 +0000 | [diff] [blame] | 1368 | MIB3.add(predOps(ARMCC::AL)); |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1369 | if (Opcode == ARM::MOV_ga_pcrel_ldr) |
Jakob Stoklund Olesen | 4fd0e4f | 2012-05-20 06:38:42 +0000 | [diff] [blame] | 1370 | MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1371 | } |
Evan Cheng | 2f2435d | 2011-01-21 18:55:51 +0000 | [diff] [blame] | 1372 | TransferImpOps(MI, MIB1, MIB3); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1373 | MI.eraseFromParent(); |
| 1374 | return true; |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1375 | } |
Evan Cheng | 7c1f56f | 2010-05-12 23:13:12 +0000 | [diff] [blame] | 1376 | |
Anton Korobeynikov | 48043d0 | 2010-08-30 22:50:36 +0000 | [diff] [blame] | 1377 | case ARM::MOVi32imm: |
Evan Cheng | 2bcb8da | 2010-11-13 02:25:14 +0000 | [diff] [blame] | 1378 | case ARM::MOVCCi32imm: |
| 1379 | case ARM::t2MOVi32imm: |
Evan Cheng | dfce83c | 2011-01-17 08:03:18 +0000 | [diff] [blame] | 1380 | case ARM::t2MOVCCi32imm: |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1381 | ExpandMOV32BitImm(MBB, MBBI); |
| 1382 | return true; |
Evan Cheng | 2f736c9 | 2010-05-13 00:17:02 +0000 | [diff] [blame] | 1383 | |
Tim Northover | d840745 | 2013-10-01 14:33:28 +0000 | [diff] [blame] | 1384 | case ARM::SUBS_PC_LR: { |
| 1385 | MachineInstrBuilder MIB = |
| 1386 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) |
| 1387 | .addReg(ARM::LR) |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1388 | .add(MI.getOperand(0)) |
| 1389 | .add(MI.getOperand(1)) |
| 1390 | .add(MI.getOperand(2)) |
Tim Northover | d840745 | 2013-10-01 14:33:28 +0000 | [diff] [blame] | 1391 | .addReg(ARM::CPSR, RegState::Undef); |
| 1392 | TransferImpOps(MI, MIB, MIB); |
| 1393 | MI.eraseFromParent(); |
| 1394 | return true; |
| 1395 | } |
Owen Anderson | d6c5a74 | 2011-03-29 16:45:53 +0000 | [diff] [blame] | 1396 | case ARM::VLDMQIA: { |
| 1397 | unsigned NewOpc = ARM::VLDMDIA; |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1398 | MachineInstrBuilder MIB = |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1399 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1400 | unsigned OpIdx = 0; |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1401 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1402 | // Grab the Q register destination. |
| 1403 | bool DstIsDead = MI.getOperand(OpIdx).isDead(); |
| 1404 | unsigned DstReg = MI.getOperand(OpIdx++).getReg(); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1405 | |
| 1406 | // Copy the source register. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1407 | MIB.add(MI.getOperand(OpIdx++)); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1408 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1409 | // Copy the predicate operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1410 | MIB.add(MI.getOperand(OpIdx++)); |
| 1411 | MIB.add(MI.getOperand(OpIdx++)); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1412 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1413 | // Add the destination operands (D subregs). |
| 1414 | unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); |
| 1415 | unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); |
| 1416 | MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) |
| 1417 | .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1418 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1419 | // Add an implicit def for the super-register. |
| 1420 | MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); |
| 1421 | TransferImpOps(MI, MIB, MIB); |
Jakob Stoklund Olesen | 465cdf3 | 2011-12-17 00:07:02 +0000 | [diff] [blame] | 1422 | MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1423 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1424 | return true; |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1425 | } |
| 1426 | |
Owen Anderson | d6c5a74 | 2011-03-29 16:45:53 +0000 | [diff] [blame] | 1427 | case ARM::VSTMQIA: { |
| 1428 | unsigned NewOpc = ARM::VSTMDIA; |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1429 | MachineInstrBuilder MIB = |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1430 | BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1431 | unsigned OpIdx = 0; |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1432 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1433 | // Grab the Q register source. |
| 1434 | bool SrcIsKill = MI.getOperand(OpIdx).isKill(); |
| 1435 | unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1436 | |
| 1437 | // Copy the destination register. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1438 | MIB.add(MI.getOperand(OpIdx++)); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1439 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1440 | // Copy the predicate operands. |
Diana Picus | 116bbab | 2017-01-13 09:58:52 +0000 | [diff] [blame] | 1441 | MIB.add(MI.getOperand(OpIdx++)); |
| 1442 | MIB.add(MI.getOperand(OpIdx++)); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1443 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1444 | // Add the source operands (D subregs). |
| 1445 | unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); |
| 1446 | unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); |
Matthias Braun | d6b108e | 2015-02-16 19:34:30 +0000 | [diff] [blame] | 1447 | MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) |
| 1448 | .addReg(D1, SrcIsKill ? RegState::Kill : 0); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1449 | |
Chris Lattner | 1d0c257 | 2011-04-29 05:24:29 +0000 | [diff] [blame] | 1450 | if (SrcIsKill) // Add an implicit kill for the Q register. |
| 1451 | MIB->addRegisterKilled(SrcReg, TRI, true); |
Bill Wendling | a68e3a5 | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 1452 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1453 | TransferImpOps(MI, MIB, MIB); |
Jakob Stoklund Olesen | 465cdf3 | 2011-12-17 00:07:02 +0000 | [diff] [blame] | 1454 | MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1455 | MI.eraseFromParent(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1456 | return true; |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1457 | } |
| 1458 | |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 1459 | case ARM::VLD2q8Pseudo: |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 1460 | case ARM::VLD2q16Pseudo: |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 1461 | case ARM::VLD2q32Pseudo: |
Jim Grosbach | d146a02 | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 1462 | case ARM::VLD2q8PseudoWB_fixed: |
| 1463 | case ARM::VLD2q16PseudoWB_fixed: |
| 1464 | case ARM::VLD2q32PseudoWB_fixed: |
Jim Grosbach | d146a02 | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 1465 | case ARM::VLD2q8PseudoWB_register: |
| 1466 | case ARM::VLD2q16PseudoWB_register: |
| 1467 | case ARM::VLD2q32PseudoWB_register: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1468 | case ARM::VLD3d8Pseudo: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1469 | case ARM::VLD3d16Pseudo: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1470 | case ARM::VLD3d32Pseudo: |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 1471 | case ARM::VLD1d64TPseudo: |
Jiangning Liu | 4df2363 | 2014-01-16 09:16:13 +0000 | [diff] [blame] | 1472 | case ARM::VLD1d64TPseudoWB_fixed: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1473 | case ARM::VLD3d8Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1474 | case ARM::VLD3d16Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1475 | case ARM::VLD3d32Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1476 | case ARM::VLD3q8Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1477 | case ARM::VLD3q16Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1478 | case ARM::VLD3q32Pseudo_UPD: |
Bob Wilson | a609b89 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1479 | case ARM::VLD3q8oddPseudo: |
| 1480 | case ARM::VLD3q16oddPseudo: |
| 1481 | case ARM::VLD3q32oddPseudo: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1482 | case ARM::VLD3q8oddPseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1483 | case ARM::VLD3q16oddPseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1484 | case ARM::VLD3q32oddPseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1485 | case ARM::VLD4d8Pseudo: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1486 | case ARM::VLD4d16Pseudo: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1487 | case ARM::VLD4d32Pseudo: |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 1488 | case ARM::VLD1d64QPseudo: |
Jiangning Liu | 4df2363 | 2014-01-16 09:16:13 +0000 | [diff] [blame] | 1489 | case ARM::VLD1d64QPseudoWB_fixed: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1490 | case ARM::VLD4d8Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1491 | case ARM::VLD4d16Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1492 | case ARM::VLD4d32Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1493 | case ARM::VLD4q8Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1494 | case ARM::VLD4q16Pseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1495 | case ARM::VLD4q32Pseudo_UPD: |
Bob Wilson | a609b89 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1496 | case ARM::VLD4q8oddPseudo: |
| 1497 | case ARM::VLD4q16oddPseudo: |
| 1498 | case ARM::VLD4q32oddPseudo: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1499 | case ARM::VLD4q8oddPseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1500 | case ARM::VLD4q16oddPseudo_UPD: |
Bob Wilson | 35fafca | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 1501 | case ARM::VLD4q32oddPseudo_UPD: |
Bob Wilson | 77ab165 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1502 | case ARM::VLD3DUPd8Pseudo: |
| 1503 | case ARM::VLD3DUPd16Pseudo: |
| 1504 | case ARM::VLD3DUPd32Pseudo: |
| 1505 | case ARM::VLD3DUPd8Pseudo_UPD: |
| 1506 | case ARM::VLD3DUPd16Pseudo_UPD: |
| 1507 | case ARM::VLD3DUPd32Pseudo_UPD: |
Bob Wilson | 431ac4ef | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1508 | case ARM::VLD4DUPd8Pseudo: |
| 1509 | case ARM::VLD4DUPd16Pseudo: |
| 1510 | case ARM::VLD4DUPd32Pseudo: |
| 1511 | case ARM::VLD4DUPd8Pseudo_UPD: |
| 1512 | case ARM::VLD4DUPd16Pseudo_UPD: |
| 1513 | case ARM::VLD4DUPd32Pseudo_UPD: |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1514 | ExpandVLD(MBBI); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1515 | return true; |
Bob Wilson | 75a6408 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 1516 | |
Bob Wilson | 950882b | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1517 | case ARM::VST2q8Pseudo: |
Bob Wilson | 950882b | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1518 | case ARM::VST2q16Pseudo: |
Bob Wilson | 950882b | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1519 | case ARM::VST2q32Pseudo: |
Jim Grosbach | 88ac761 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1520 | case ARM::VST2q8PseudoWB_fixed: |
| 1521 | case ARM::VST2q16PseudoWB_fixed: |
| 1522 | case ARM::VST2q32PseudoWB_fixed: |
Jim Grosbach | 88ac761 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1523 | case ARM::VST2q8PseudoWB_register: |
| 1524 | case ARM::VST2q16PseudoWB_register: |
| 1525 | case ARM::VST2q32PseudoWB_register: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1526 | case ARM::VST3d8Pseudo: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1527 | case ARM::VST3d16Pseudo: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1528 | case ARM::VST3d32Pseudo: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1529 | case ARM::VST1d64TPseudo: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1530 | case ARM::VST3d8Pseudo_UPD: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1531 | case ARM::VST3d16Pseudo_UPD: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1532 | case ARM::VST3d32Pseudo_UPD: |
Jim Grosbach | 98d032f | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 1533 | case ARM::VST1d64TPseudoWB_fixed: |
| 1534 | case ARM::VST1d64TPseudoWB_register: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1535 | case ARM::VST3q8Pseudo_UPD: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1536 | case ARM::VST3q16Pseudo_UPD: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1537 | case ARM::VST3q32Pseudo_UPD: |
Bob Wilson | a609b89 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1538 | case ARM::VST3q8oddPseudo: |
| 1539 | case ARM::VST3q16oddPseudo: |
| 1540 | case ARM::VST3q32oddPseudo: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1541 | case ARM::VST3q8oddPseudo_UPD: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1542 | case ARM::VST3q16oddPseudo_UPD: |
Bob Wilson | 97919e9 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1543 | case ARM::VST3q32oddPseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1544 | case ARM::VST4d8Pseudo: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1545 | case ARM::VST4d16Pseudo: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1546 | case ARM::VST4d32Pseudo: |
Bob Wilson | 4cec449 | 2010-08-26 05:33:30 +0000 | [diff] [blame] | 1547 | case ARM::VST1d64QPseudo: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1548 | case ARM::VST4d8Pseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1549 | case ARM::VST4d16Pseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1550 | case ARM::VST4d32Pseudo_UPD: |
Jim Grosbach | 5ee209c | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 1551 | case ARM::VST1d64QPseudoWB_fixed: |
| 1552 | case ARM::VST1d64QPseudoWB_register: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1553 | case ARM::VST4q8Pseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1554 | case ARM::VST4q16Pseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1555 | case ARM::VST4q32Pseudo_UPD: |
Bob Wilson | a609b89 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1556 | case ARM::VST4q8oddPseudo: |
| 1557 | case ARM::VST4q16oddPseudo: |
| 1558 | case ARM::VST4q32oddPseudo: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1559 | case ARM::VST4q8oddPseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1560 | case ARM::VST4q16oddPseudo_UPD: |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1561 | case ARM::VST4q32oddPseudo_UPD: |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1562 | ExpandVST(MBBI); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1563 | return true; |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1564 | |
Bob Wilson | dc44990 | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 1565 | case ARM::VLD1LNq8Pseudo: |
| 1566 | case ARM::VLD1LNq16Pseudo: |
| 1567 | case ARM::VLD1LNq32Pseudo: |
| 1568 | case ARM::VLD1LNq8Pseudo_UPD: |
| 1569 | case ARM::VLD1LNq16Pseudo_UPD: |
| 1570 | case ARM::VLD1LNq32Pseudo_UPD: |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1571 | case ARM::VLD2LNd8Pseudo: |
| 1572 | case ARM::VLD2LNd16Pseudo: |
| 1573 | case ARM::VLD2LNd32Pseudo: |
| 1574 | case ARM::VLD2LNq16Pseudo: |
| 1575 | case ARM::VLD2LNq32Pseudo: |
| 1576 | case ARM::VLD2LNd8Pseudo_UPD: |
| 1577 | case ARM::VLD2LNd16Pseudo_UPD: |
| 1578 | case ARM::VLD2LNd32Pseudo_UPD: |
| 1579 | case ARM::VLD2LNq16Pseudo_UPD: |
| 1580 | case ARM::VLD2LNq32Pseudo_UPD: |
| 1581 | case ARM::VLD3LNd8Pseudo: |
| 1582 | case ARM::VLD3LNd16Pseudo: |
| 1583 | case ARM::VLD3LNd32Pseudo: |
| 1584 | case ARM::VLD3LNq16Pseudo: |
| 1585 | case ARM::VLD3LNq32Pseudo: |
| 1586 | case ARM::VLD3LNd8Pseudo_UPD: |
| 1587 | case ARM::VLD3LNd16Pseudo_UPD: |
| 1588 | case ARM::VLD3LNd32Pseudo_UPD: |
| 1589 | case ARM::VLD3LNq16Pseudo_UPD: |
| 1590 | case ARM::VLD3LNq32Pseudo_UPD: |
| 1591 | case ARM::VLD4LNd8Pseudo: |
| 1592 | case ARM::VLD4LNd16Pseudo: |
| 1593 | case ARM::VLD4LNd32Pseudo: |
| 1594 | case ARM::VLD4LNq16Pseudo: |
| 1595 | case ARM::VLD4LNq32Pseudo: |
| 1596 | case ARM::VLD4LNd8Pseudo_UPD: |
| 1597 | case ARM::VLD4LNd16Pseudo_UPD: |
| 1598 | case ARM::VLD4LNd32Pseudo_UPD: |
| 1599 | case ARM::VLD4LNq16Pseudo_UPD: |
| 1600 | case ARM::VLD4LNq32Pseudo_UPD: |
Bob Wilson | d80b29d | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1601 | case ARM::VST1LNq8Pseudo: |
| 1602 | case ARM::VST1LNq16Pseudo: |
| 1603 | case ARM::VST1LNq32Pseudo: |
| 1604 | case ARM::VST1LNq8Pseudo_UPD: |
| 1605 | case ARM::VST1LNq16Pseudo_UPD: |
| 1606 | case ARM::VST1LNq32Pseudo_UPD: |
Bob Wilson | d5c57a5 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1607 | case ARM::VST2LNd8Pseudo: |
| 1608 | case ARM::VST2LNd16Pseudo: |
| 1609 | case ARM::VST2LNd32Pseudo: |
| 1610 | case ARM::VST2LNq16Pseudo: |
| 1611 | case ARM::VST2LNq32Pseudo: |
| 1612 | case ARM::VST2LNd8Pseudo_UPD: |
| 1613 | case ARM::VST2LNd16Pseudo_UPD: |
| 1614 | case ARM::VST2LNd32Pseudo_UPD: |
| 1615 | case ARM::VST2LNq16Pseudo_UPD: |
| 1616 | case ARM::VST2LNq32Pseudo_UPD: |
| 1617 | case ARM::VST3LNd8Pseudo: |
| 1618 | case ARM::VST3LNd16Pseudo: |
| 1619 | case ARM::VST3LNd32Pseudo: |
| 1620 | case ARM::VST3LNq16Pseudo: |
| 1621 | case ARM::VST3LNq32Pseudo: |
| 1622 | case ARM::VST3LNd8Pseudo_UPD: |
| 1623 | case ARM::VST3LNd16Pseudo_UPD: |
| 1624 | case ARM::VST3LNd32Pseudo_UPD: |
| 1625 | case ARM::VST3LNq16Pseudo_UPD: |
| 1626 | case ARM::VST3LNq32Pseudo_UPD: |
| 1627 | case ARM::VST4LNd8Pseudo: |
| 1628 | case ARM::VST4LNd16Pseudo: |
| 1629 | case ARM::VST4LNd32Pseudo: |
| 1630 | case ARM::VST4LNq16Pseudo: |
| 1631 | case ARM::VST4LNq32Pseudo: |
| 1632 | case ARM::VST4LNd8Pseudo_UPD: |
| 1633 | case ARM::VST4LNd16Pseudo_UPD: |
| 1634 | case ARM::VST4LNd32Pseudo_UPD: |
| 1635 | case ARM::VST4LNq16Pseudo_UPD: |
| 1636 | case ARM::VST4LNq32Pseudo_UPD: |
| 1637 | ExpandLaneOp(MBBI); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1638 | return true; |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 1639 | |
Jim Grosbach | 4a5c887 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 1640 | case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; |
| 1641 | case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; |
Jim Grosbach | 4a5c887 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 1642 | case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; |
| 1643 | case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 1644 | |
| 1645 | case ARM::CMP_SWAP_8: |
| 1646 | if (STI->isThumb()) |
| 1647 | return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, |
| 1648 | ARM::tUXTB, NextMBBI); |
| 1649 | else |
| 1650 | return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, |
| 1651 | ARM::UXTB, NextMBBI); |
| 1652 | case ARM::CMP_SWAP_16: |
| 1653 | if (STI->isThumb()) |
| 1654 | return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, |
| 1655 | ARM::tUXTH, NextMBBI); |
| 1656 | else |
| 1657 | return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, |
| 1658 | ARM::UXTH, NextMBBI); |
| 1659 | case ARM::CMP_SWAP_32: |
| 1660 | if (STI->isThumb()) |
| 1661 | return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, |
| 1662 | NextMBBI); |
| 1663 | else |
| 1664 | return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); |
| 1665 | |
| 1666 | case ARM::CMP_SWAP_64: |
| 1667 | return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1668 | } |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1669 | } |
| 1670 | |
| 1671 | bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { |
| 1672 | bool Modified = false; |
| 1673 | |
| 1674 | MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); |
| 1675 | while (MBBI != E) { |
Benjamin Kramer | b6d0bd4 | 2014-03-02 12:27:27 +0000 | [diff] [blame] | 1676 | MachineBasicBlock::iterator NMBBI = std::next(MBBI); |
Tim Northover | b629c77 | 2016-04-18 21:48:55 +0000 | [diff] [blame] | 1677 | Modified |= ExpandMI(MBB, MBBI, NMBBI); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1678 | MBBI = NMBBI; |
| 1679 | } |
| 1680 | |
| 1681 | return Modified; |
| 1682 | } |
| 1683 | |
| 1684 | bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { |
Eric Christopher | 1b21f00 | 2015-01-29 00:19:33 +0000 | [diff] [blame] | 1685 | STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); |
| 1686 | TII = STI->getInstrInfo(); |
| 1687 | TRI = STI->getRegisterInfo(); |
Evan Cheng | b8b0ad8 | 2011-01-20 08:34:58 +0000 | [diff] [blame] | 1688 | AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1689 | |
| 1690 | bool Modified = false; |
Javed Absar | e9599e3 | 2017-07-20 12:35:37 +0000 | [diff] [blame] | 1691 | for (MachineBasicBlock &MBB : MF) |
| 1692 | Modified |= ExpandMBB(MBB); |
Jakob Stoklund Olesen | 9c3badc | 2011-07-29 00:27:32 +0000 | [diff] [blame] | 1693 | if (VerifyARMPseudo) |
| 1694 | MF.verify(this, "After expanding ARM pseudo instructions."); |
Evan Cheng | 207b246 | 2009-11-06 23:52:48 +0000 | [diff] [blame] | 1695 | return Modified; |
| 1696 | } |
| 1697 | |
| 1698 | /// createARMExpandPseudoPass - returns an instance of the pseudo instruction |
| 1699 | /// expansion pass. |
| 1700 | FunctionPass *llvm::createARMExpandPseudoPass() { |
| 1701 | return new ARMExpandPseudo(); |
| 1702 | } |