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Jia Liub22310f2012-02-18 12:03:15 +00001//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
Evan Cheng207b2462009-11-06 23:52:48 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Bob Wilson359f8ba2010-09-08 23:39:54 +000010// This file contains a pass that expands pseudo instructions into target
Evan Cheng207b2462009-11-06 23:52:48 +000011// instructions to allow proper scheduling, if-conversion, and other late
12// optimizations. This pass should be run after register allocation but before
Bob Wilson359f8ba2010-09-08 23:39:54 +000013// the post-regalloc scheduling pass.
Evan Cheng207b2462009-11-06 23:52:48 +000014//
15//===----------------------------------------------------------------------===//
16
Evan Cheng207b2462009-11-06 23:52:48 +000017#include "ARM.h"
18#include "ARMBaseInstrInfo.h"
Jim Grosbachbbdc5d22010-10-19 23:27:08 +000019#include "ARMBaseRegisterInfo.h"
Tim Northover72360d22013-12-02 10:35:41 +000020#include "ARMConstantPoolValue.h"
Jim Grosbachbbdc5d22010-10-19 23:27:08 +000021#include "ARMMachineFunctionInfo.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000022#include "ARMSubtarget.h"
Evan Chenga20cde32011-07-20 23:34:39 +000023#include "MCTargetDesc/ARMAddressingModes.h"
Tim Northoverb629c772016-04-18 21:48:55 +000024#include "llvm/CodeGen/LivePhysRegs.h"
Jim Grosbachbbdc5d22010-10-19 23:27:08 +000025#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Cheng207b2462009-11-06 23:52:48 +000026#include "llvm/CodeGen/MachineFunctionPass.h"
Eugene Zelenkoe6cf4372017-01-26 23:40:06 +000027
Evan Cheng207b2462009-11-06 23:52:48 +000028using namespace llvm;
29
Chandler Carruth84e68b22014-04-22 02:41:26 +000030#define DEBUG_TYPE "arm-pseudo"
31
Benjamin Kramer4938edb2011-08-19 01:42:18 +000032static cl::opt<bool>
Jakob Stoklund Olesen9c3badc2011-07-29 00:27:32 +000033VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
35
Evan Cheng207b2462009-11-06 23:52:48 +000036namespace {
37 class ARMExpandPseudo : public MachineFunctionPass {
38 public:
39 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +000040 ARMExpandPseudo() : MachineFunctionPass(ID) {}
Evan Cheng207b2462009-11-06 23:52:48 +000041
Jim Grosbachbbdc5d22010-10-19 23:27:08 +000042 const ARMBaseInstrInfo *TII;
Evan Cheng2f736c92010-05-13 00:17:02 +000043 const TargetRegisterInfo *TRI;
Evan Chengf478cf92010-11-12 23:03:38 +000044 const ARMSubtarget *STI;
Evan Chengb8b0ad82011-01-20 08:34:58 +000045 ARMFunctionInfo *AFI;
Evan Cheng207b2462009-11-06 23:52:48 +000046
Craig Topper6bc27bf2014-03-10 02:09:33 +000047 bool runOnMachineFunction(MachineFunction &Fn) override;
Evan Cheng207b2462009-11-06 23:52:48 +000048
Derek Schuff1dbf7a52016-04-04 17:09:25 +000049 MachineFunctionProperties getRequiredProperties() const override {
50 return MachineFunctionProperties().set(
Matthias Braun1eb47362016-08-25 01:27:13 +000051 MachineFunctionProperties::Property::NoVRegs);
Derek Schuff1dbf7a52016-04-04 17:09:25 +000052 }
53
Mehdi Amini117296c2016-10-01 02:56:57 +000054 StringRef getPassName() const override {
Evan Cheng207b2462009-11-06 23:52:48 +000055 return "ARM pseudo instruction expansion pass";
56 }
57
58 private:
Evan Cheng7c1f56f2010-05-12 23:13:12 +000059 void TransferImpOps(MachineInstr &OldMI,
60 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
Evan Chengb8b0ad82011-01-20 08:34:58 +000061 bool ExpandMI(MachineBasicBlock &MBB,
Tim Northoverb629c772016-04-18 21:48:55 +000062 MachineBasicBlock::iterator MBBI,
63 MachineBasicBlock::iterator &NextMBBI);
Evan Cheng207b2462009-11-06 23:52:48 +000064 bool ExpandMBB(MachineBasicBlock &MBB);
Bob Wilsond5c57a52010-09-13 23:01:35 +000065 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
66 void ExpandVST(MachineBasicBlock::iterator &MBBI);
67 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
Bob Wilsonc597fd3b2010-09-13 23:55:10 +000068 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
Jim Grosbach4a5c8872011-12-15 22:27:11 +000069 unsigned Opc, bool IsExt);
Evan Chengb8b0ad82011-01-20 08:34:58 +000070 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator &MBBI);
Tim Northoverb629c772016-04-18 21:48:55 +000072 bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
74 unsigned StrexOp, unsigned UxtOp,
75 MachineBasicBlock::iterator &NextMBBI);
76
77 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator MBBI,
79 MachineBasicBlock::iterator &NextMBBI);
Evan Cheng207b2462009-11-06 23:52:48 +000080 };
81 char ARMExpandPseudo::ID = 0;
Alexander Kornienkof00654e2015-06-23 09:49:53 +000082}
Evan Cheng207b2462009-11-06 23:52:48 +000083
Evan Cheng7c1f56f2010-05-12 23:13:12 +000084/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
85/// the instructions created from the expansion.
86void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
87 MachineInstrBuilder &UseMI,
88 MachineInstrBuilder &DefMI) {
Evan Cheng6cc775f2011-06-28 19:10:37 +000089 const MCInstrDesc &Desc = OldMI.getDesc();
Evan Cheng7c1f56f2010-05-12 23:13:12 +000090 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
91 i != e; ++i) {
92 const MachineOperand &MO = OldMI.getOperand(i);
93 assert(MO.isReg() && MO.getReg());
94 if (MO.isUse())
Diana Picus116bbab2017-01-13 09:58:52 +000095 UseMI.add(MO);
Evan Cheng7c1f56f2010-05-12 23:13:12 +000096 else
Diana Picus116bbab2017-01-13 09:58:52 +000097 DefMI.add(MO);
Evan Cheng7c1f56f2010-05-12 23:13:12 +000098 }
99}
100
Bob Wilsond5c57a52010-09-13 23:01:35 +0000101namespace {
102 // Constants for register spacing in NEON load/store instructions.
103 // For quad-register load-lane and store-lane pseudo instructors, the
104 // spacing is initially assumed to be EvenDblSpc, and that is changed to
105 // OddDblSpc depending on the lane number operand.
106 enum NEONRegSpacing {
107 SingleSpc,
108 EvenDblSpc,
109 OddDblSpc
110 };
111
112 // Entries for NEON load/store information table. The table is sorted by
113 // PseudoOpc for fast binary-search lookups.
114 struct NEONLdStTableEntry {
Craig Topperca658c22012-03-11 07:16:55 +0000115 uint16_t PseudoOpc;
116 uint16_t RealOpc;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000117 bool IsLoad;
Jim Grosbache4c8e692011-10-31 19:11:23 +0000118 bool isUpdating;
119 bool hasWritebackOperand;
Craig Topper980739a2012-09-20 06:14:08 +0000120 uint8_t RegSpacing; // One of type NEONRegSpacing
121 uint8_t NumRegs; // D registers loaded or stored
122 uint8_t RegElts; // elements per D register; used for lane ops
Jim Grosbach2f2e3c42011-10-21 18:54:25 +0000123 // FIXME: Temporary flag to denote whether the real instruction takes
124 // a single register (like the encoding) or all of the registers in
125 // the list (like the asm syntax and the isel DAG). When all definitions
126 // are converted to take only the single encoded register, this will
127 // go away.
128 bool copyAllListRegs;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000129
130 // Comparison methods for binary search of the table.
131 bool operator<(const NEONLdStTableEntry &TE) const {
132 return PseudoOpc < TE.PseudoOpc;
133 }
134 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
135 return TE.PseudoOpc < PseudoOpc;
136 }
Chandler Carruth88c54b82010-10-23 08:10:43 +0000137 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
138 const NEONLdStTableEntry &TE) {
Bob Wilsond5c57a52010-09-13 23:01:35 +0000139 return PseudoOpc < TE.PseudoOpc;
140 }
141 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000142}
Bob Wilsond5c57a52010-09-13 23:01:35 +0000143
144static const NEONLdStTableEntry NEONLdStTable[] = {
Jim Grosbache4c8e692011-10-31 19:11:23 +0000145{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
146{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
147{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
148{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
149{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
150{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
Bob Wilsondc449902010-11-01 22:04:05 +0000151
Jim Grosbache4c8e692011-10-31 19:11:23 +0000152{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
Jiangning Liu4df23632014-01-16 09:16:13 +0000153{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
Jim Grosbache4c8e692011-10-31 19:11:23 +0000154{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
Jiangning Liu4df23632014-01-16 09:16:13 +0000155{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000156
Jim Grosbache4c8e692011-10-31 19:11:23 +0000157{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
158{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
159{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
160{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
161{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
162{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
163{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
164{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
165{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
166{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000167
Jim Grosbache4c8e692011-10-31 19:11:23 +0000168{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
Jim Grosbachd146a022011-12-09 21:28:25 +0000169{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
170{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
Jim Grosbache4c8e692011-10-31 19:11:23 +0000171{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
Jim Grosbachd146a022011-12-09 21:28:25 +0000172{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
173{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
Jim Grosbache4c8e692011-10-31 19:11:23 +0000174{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
Jim Grosbachd146a022011-12-09 21:28:25 +0000175{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
176{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000177
Jim Grosbache4c8e692011-10-31 19:11:23 +0000178{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
179{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
180{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
181{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
182{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
183{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
Bob Wilson77ab1652010-11-29 19:35:29 +0000184
Jim Grosbache4c8e692011-10-31 19:11:23 +0000185{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
186{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
187{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
188{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
189{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
190{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
191{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
192{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
193{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
194{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000195
Jim Grosbache4c8e692011-10-31 19:11:23 +0000196{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
197{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
198{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
199{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
200{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
201{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000202
Jim Grosbache4c8e692011-10-31 19:11:23 +0000203{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
204{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
205{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
206{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
207{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
208{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
209{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
210{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
211{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000212
Jim Grosbache4c8e692011-10-31 19:11:23 +0000213{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
214{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
215{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
216{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
217{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
218{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000219
Jim Grosbache4c8e692011-10-31 19:11:23 +0000220{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
221{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
222{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
223{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
224{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
225{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
226{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
227{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
228{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
229{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000230
Jim Grosbache4c8e692011-10-31 19:11:23 +0000231{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
232{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
233{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
234{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
235{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
236{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000237
Jim Grosbache4c8e692011-10-31 19:11:23 +0000238{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
239{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
240{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
241{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
242{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
243{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
244{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
245{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
246{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000247
Jim Grosbache4c8e692011-10-31 19:11:23 +0000248{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
249{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
250{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
251{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
252{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
253{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
Bob Wilsond80b29d2010-11-02 21:18:25 +0000254
Jim Grosbach5ee209c2011-11-29 22:58:48 +0000255{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
256{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
257{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
Jim Grosbach98d032f2011-11-29 22:38:04 +0000258{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
259{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
260{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000261
Jim Grosbache4c8e692011-10-31 19:11:23 +0000262{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
263{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
264{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
265{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
266{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
267{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
268{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
269{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
270{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
271{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000272
Jim Grosbach8d246182011-12-14 19:35:22 +0000273{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
Jim Grosbach88ac7612011-12-14 21:32:11 +0000274{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
275{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
Jim Grosbach8d246182011-12-14 19:35:22 +0000276{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
Jim Grosbach88ac7612011-12-14 21:32:11 +0000277{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
278{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
Jim Grosbach8d246182011-12-14 19:35:22 +0000279{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
Jim Grosbach88ac7612011-12-14 21:32:11 +0000280{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
281{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000282
Jim Grosbache4c8e692011-10-31 19:11:23 +0000283{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
284{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
285{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
286{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
287{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
288{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
289{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
290{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
291{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
292{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000293
Jim Grosbache4c8e692011-10-31 19:11:23 +0000294{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
295{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
296{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
297{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
298{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
299{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000300
Jim Grosbache4c8e692011-10-31 19:11:23 +0000301{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
302{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
303{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
304{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
305{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
306{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
307{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
308{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
309{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000310
Jim Grosbache4c8e692011-10-31 19:11:23 +0000311{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
312{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
313{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
314{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
315{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
316{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
317{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
318{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
319{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
320{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000321
Jim Grosbache4c8e692011-10-31 19:11:23 +0000322{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
323{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
324{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
325{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
326{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
327{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
Bob Wilsond5c57a52010-09-13 23:01:35 +0000328
Jim Grosbache4c8e692011-10-31 19:11:23 +0000329{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
330{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
331{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
332{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
333{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
334{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
335{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
336{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
337{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
Bob Wilsond5c57a52010-09-13 23:01:35 +0000338};
339
340/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
341/// load or store pseudo instruction.
342static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
Bob Wilsond5c57a52010-09-13 23:01:35 +0000343#ifndef NDEBUG
344 // Make sure the table is sorted.
345 static bool TableChecked = false;
346 if (!TableChecked) {
Craig Topperc177d9e2015-10-17 16:37:11 +0000347 assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
348 "NEONLdStTable is not sorted!");
Bob Wilsond5c57a52010-09-13 23:01:35 +0000349 TableChecked = true;
350 }
351#endif
352
Craig Toppera2d06352015-10-17 18:22:46 +0000353 auto I = std::lower_bound(std::begin(NEONLdStTable),
354 std::end(NEONLdStTable), Opcode);
Craig Topperc177d9e2015-10-17 16:37:11 +0000355 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
Bob Wilsond5c57a52010-09-13 23:01:35 +0000356 return I;
Craig Topper062a2ba2014-04-25 05:30:21 +0000357 return nullptr;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000358}
359
360/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
361/// corresponding to the specified register spacing. Not all of the results
362/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
363static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
364 const TargetRegisterInfo *TRI, unsigned &D0,
365 unsigned &D1, unsigned &D2, unsigned &D3) {
366 if (RegSpc == SingleSpc) {
367 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
368 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
369 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
370 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
371 } else if (RegSpc == EvenDblSpc) {
372 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
373 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
374 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
375 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
376 } else {
377 assert(RegSpc == OddDblSpc && "unknown register spacing");
378 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
379 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
380 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
381 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000382 }
Bob Wilsond5c57a52010-09-13 23:01:35 +0000383}
384
Bob Wilson5a1df802010-09-02 16:17:29 +0000385/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
386/// operands to real VLD instructions with D register operands.
Bob Wilsond5c57a52010-09-13 23:01:35 +0000387void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
Bob Wilson75a64082010-09-02 16:00:54 +0000388 MachineInstr &MI = *MBBI;
389 MachineBasicBlock &MBB = *MI.getParent();
390
Bob Wilsond5c57a52010-09-13 23:01:35 +0000391 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
392 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
Craig Topper980739a2012-09-20 06:14:08 +0000393 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000394 unsigned NumRegs = TableEntry->NumRegs;
395
396 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
397 TII->get(TableEntry->RealOpc));
Bob Wilson75a64082010-09-02 16:00:54 +0000398 unsigned OpIdx = 0;
399
400 bool DstIsDead = MI.getOperand(OpIdx).isDead();
401 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
402 unsigned D0, D1, D2, D3;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000403 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
Jim Grosbach2f2e3c42011-10-21 18:54:25 +0000404 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
405 if (NumRegs > 1 && TableEntry->copyAllListRegs)
406 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
407 if (NumRegs > 2 && TableEntry->copyAllListRegs)
Bob Wilson35fafca2010-09-03 18:16:02 +0000408 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
Jim Grosbach2f2e3c42011-10-21 18:54:25 +0000409 if (NumRegs > 3 && TableEntry->copyAllListRegs)
Bob Wilson35fafca2010-09-03 18:16:02 +0000410 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
Bob Wilson75a64082010-09-02 16:00:54 +0000411
Jim Grosbache4c8e692011-10-31 19:11:23 +0000412 if (TableEntry->isUpdating)
Diana Picus116bbab2017-01-13 09:58:52 +0000413 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson4ccd5ce2010-09-09 00:15:32 +0000414
Bob Wilson75a64082010-09-02 16:00:54 +0000415 // Copy the addrmode6 operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000416 MIB.add(MI.getOperand(OpIdx++));
417 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson4ccd5ce2010-09-09 00:15:32 +0000418 // Copy the am6offset operand.
Jim Grosbache4c8e692011-10-31 19:11:23 +0000419 if (TableEntry->hasWritebackOperand)
Diana Picus116bbab2017-01-13 09:58:52 +0000420 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson75a64082010-09-02 16:00:54 +0000421
Bob Wilson84971c82010-09-09 00:38:32 +0000422 // For an instruction writing double-spaced subregs, the pseudo instruction
Bob Wilson450c6cf2010-09-16 04:25:37 +0000423 // has an extra operand that is a use of the super-register. Record the
424 // operand index and skip over it.
425 unsigned SrcOpIdx = 0;
426 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
427 SrcOpIdx = OpIdx++;
428
429 // Copy the predicate operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000430 MIB.add(MI.getOperand(OpIdx++));
431 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson450c6cf2010-09-16 04:25:37 +0000432
433 // Copy the super-register source operand used for double-spaced subregs over
Bob Wilson84971c82010-09-09 00:38:32 +0000434 // to the new instruction as an implicit operand.
Bob Wilson450c6cf2010-09-16 04:25:37 +0000435 if (SrcOpIdx != 0) {
436 MachineOperand MO = MI.getOperand(SrcOpIdx);
Bob Wilson84971c82010-09-09 00:38:32 +0000437 MO.setImplicit(true);
Diana Picus116bbab2017-01-13 09:58:52 +0000438 MIB.add(MO);
Bob Wilson84971c82010-09-09 00:38:32 +0000439 }
Bob Wilson35fafca2010-09-03 18:16:02 +0000440 // Add an implicit def for the super-register.
441 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
Bob Wilson84971c82010-09-09 00:38:32 +0000442 TransferImpOps(MI, MIB, MIB);
Evan Cheng40791332011-04-19 00:04:03 +0000443
444 // Transfer memoperands.
Chris Lattner1d0c2572011-04-29 05:24:29 +0000445 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Evan Cheng40791332011-04-19 00:04:03 +0000446
Bob Wilson75a64082010-09-02 16:00:54 +0000447 MI.eraseFromParent();
448}
449
Bob Wilson97919e92010-08-26 18:51:29 +0000450/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
451/// operands to real VST instructions with D register operands.
Bob Wilsond5c57a52010-09-13 23:01:35 +0000452void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
Bob Wilson9392b0e2010-08-25 23:27:42 +0000453 MachineInstr &MI = *MBBI;
454 MachineBasicBlock &MBB = *MI.getParent();
455
Bob Wilsond5c57a52010-09-13 23:01:35 +0000456 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
457 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
Craig Topper980739a2012-09-20 06:14:08 +0000458 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000459 unsigned NumRegs = TableEntry->NumRegs;
460
461 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
462 TII->get(TableEntry->RealOpc));
Bob Wilson9392b0e2010-08-25 23:27:42 +0000463 unsigned OpIdx = 0;
Jim Grosbache4c8e692011-10-31 19:11:23 +0000464 if (TableEntry->isUpdating)
Diana Picus116bbab2017-01-13 09:58:52 +0000465 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson4ccd5ce2010-09-09 00:15:32 +0000466
Bob Wilson9392b0e2010-08-25 23:27:42 +0000467 // Copy the addrmode6 operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000468 MIB.add(MI.getOperand(OpIdx++));
469 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson4ccd5ce2010-09-09 00:15:32 +0000470 // Copy the am6offset operand.
Jim Grosbache4c8e692011-10-31 19:11:23 +0000471 if (TableEntry->hasWritebackOperand)
Diana Picus116bbab2017-01-13 09:58:52 +0000472 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson9392b0e2010-08-25 23:27:42 +0000473
474 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
Jakob Stoklund Olesena15a2242012-06-15 17:46:54 +0000475 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
Bob Wilson450c6cf2010-09-16 04:25:37 +0000476 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
Bob Wilson9392b0e2010-08-25 23:27:42 +0000477 unsigned D0, D1, D2, D3;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000478 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
Jakob Stoklund Olesena15a2242012-06-15 17:46:54 +0000479 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
Jim Grosbach05df4602011-10-31 21:50:31 +0000480 if (NumRegs > 1 && TableEntry->copyAllListRegs)
Jakob Stoklund Olesena15a2242012-06-15 17:46:54 +0000481 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
Jim Grosbach05df4602011-10-31 21:50:31 +0000482 if (NumRegs > 2 && TableEntry->copyAllListRegs)
Jakob Stoklund Olesena15a2242012-06-15 17:46:54 +0000483 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
Jim Grosbach05df4602011-10-31 21:50:31 +0000484 if (NumRegs > 3 && TableEntry->copyAllListRegs)
Jakob Stoklund Olesena15a2242012-06-15 17:46:54 +0000485 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
Bob Wilson450c6cf2010-09-16 04:25:37 +0000486
487 // Copy the predicate operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000488 MIB.add(MI.getOperand(OpIdx++));
489 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson450c6cf2010-09-16 04:25:37 +0000490
Jakob Stoklund Olesena15a2242012-06-15 17:46:54 +0000491 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
Chris Lattner1d0c2572011-04-29 05:24:29 +0000492 MIB->addRegisterKilled(SrcReg, TRI, true);
Weiming Zhaofe26fd22014-01-15 01:32:12 +0000493 else if (!SrcIsUndef)
494 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000495 TransferImpOps(MI, MIB, MIB);
Evan Cheng40791332011-04-19 00:04:03 +0000496
497 // Transfer memoperands.
Chris Lattner1d0c2572011-04-29 05:24:29 +0000498 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Evan Cheng40791332011-04-19 00:04:03 +0000499
Bob Wilson9392b0e2010-08-25 23:27:42 +0000500 MI.eraseFromParent();
501}
502
Bob Wilsond5c57a52010-09-13 23:01:35 +0000503/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
504/// register operands to real instructions with D register operands.
505void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
506 MachineInstr &MI = *MBBI;
507 MachineBasicBlock &MBB = *MI.getParent();
508
509 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
510 assert(TableEntry && "NEONLdStTable lookup failed");
Craig Topper980739a2012-09-20 06:14:08 +0000511 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000512 unsigned NumRegs = TableEntry->NumRegs;
513 unsigned RegElts = TableEntry->RegElts;
514
515 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
516 TII->get(TableEntry->RealOpc));
517 unsigned OpIdx = 0;
518 // The lane operand is always the 3rd from last operand, before the 2
519 // predicate operands.
520 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
521
522 // Adjust the lane and spacing as needed for Q registers.
523 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
524 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
525 RegSpc = OddDblSpc;
526 Lane -= RegElts;
527 }
528 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
529
Ted Kremenek3c4408c2011-01-23 17:05:06 +0000530 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
Bob Wilson62e9a052010-09-14 21:12:05 +0000531 unsigned DstReg = 0;
532 bool DstIsDead = false;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000533 if (TableEntry->IsLoad) {
534 DstIsDead = MI.getOperand(OpIdx).isDead();
535 DstReg = MI.getOperand(OpIdx++).getReg();
536 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
Bob Wilsondc449902010-11-01 22:04:05 +0000537 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
538 if (NumRegs > 1)
539 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
Bob Wilsond5c57a52010-09-13 23:01:35 +0000540 if (NumRegs > 2)
541 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
542 if (NumRegs > 3)
543 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
544 }
545
Jim Grosbache4c8e692011-10-31 19:11:23 +0000546 if (TableEntry->isUpdating)
Diana Picus116bbab2017-01-13 09:58:52 +0000547 MIB.add(MI.getOperand(OpIdx++));
Bob Wilsond5c57a52010-09-13 23:01:35 +0000548
549 // Copy the addrmode6 operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000550 MIB.add(MI.getOperand(OpIdx++));
551 MIB.add(MI.getOperand(OpIdx++));
Bob Wilsond5c57a52010-09-13 23:01:35 +0000552 // Copy the am6offset operand.
Jim Grosbache4c8e692011-10-31 19:11:23 +0000553 if (TableEntry->hasWritebackOperand)
Diana Picus116bbab2017-01-13 09:58:52 +0000554 MIB.add(MI.getOperand(OpIdx++));
Bob Wilsond5c57a52010-09-13 23:01:35 +0000555
556 // Grab the super-register source.
557 MachineOperand MO = MI.getOperand(OpIdx++);
558 if (!TableEntry->IsLoad)
559 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
560
561 // Add the subregs as sources of the new instruction.
562 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
563 getKillRegState(MO.isKill()));
Bob Wilsondc449902010-11-01 22:04:05 +0000564 MIB.addReg(D0, SrcFlags);
565 if (NumRegs > 1)
566 MIB.addReg(D1, SrcFlags);
Bob Wilsond5c57a52010-09-13 23:01:35 +0000567 if (NumRegs > 2)
568 MIB.addReg(D2, SrcFlags);
569 if (NumRegs > 3)
570 MIB.addReg(D3, SrcFlags);
571
572 // Add the lane number operand.
573 MIB.addImm(Lane);
Bob Wilson450c6cf2010-09-16 04:25:37 +0000574 OpIdx += 1;
Bob Wilsond5c57a52010-09-13 23:01:35 +0000575
Bob Wilson450c6cf2010-09-16 04:25:37 +0000576 // Copy the predicate operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000577 MIB.add(MI.getOperand(OpIdx++));
578 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson450c6cf2010-09-16 04:25:37 +0000579
Bob Wilsond5c57a52010-09-13 23:01:35 +0000580 // Copy the super-register source to be an implicit source.
581 MO.setImplicit(true);
Diana Picus116bbab2017-01-13 09:58:52 +0000582 MIB.add(MO);
Bob Wilsond5c57a52010-09-13 23:01:35 +0000583 if (TableEntry->IsLoad)
584 // Add an implicit def for the super-register.
585 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
586 TransferImpOps(MI, MIB, MIB);
Jakob Stoklund Olesen465cdf32011-12-17 00:07:02 +0000587 // Transfer memoperands.
588 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Bob Wilsond5c57a52010-09-13 23:01:35 +0000589 MI.eraseFromParent();
590}
591
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000592/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
593/// register operands to real instructions with D register operands.
594void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
Jim Grosbach4a5c8872011-12-15 22:27:11 +0000595 unsigned Opc, bool IsExt) {
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000596 MachineInstr &MI = *MBBI;
597 MachineBasicBlock &MBB = *MI.getParent();
598
599 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
600 unsigned OpIdx = 0;
601
602 // Transfer the destination register operand.
Diana Picus116bbab2017-01-13 09:58:52 +0000603 MIB.add(MI.getOperand(OpIdx++));
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000604 if (IsExt)
Diana Picus116bbab2017-01-13 09:58:52 +0000605 MIB.add(MI.getOperand(OpIdx++));
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000606
607 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
608 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
609 unsigned D0, D1, D2, D3;
610 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
Jim Grosbach4a5c8872011-12-15 22:27:11 +0000611 MIB.addReg(D0);
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000612
613 // Copy the other source register operand.
Diana Picus116bbab2017-01-13 09:58:52 +0000614 MIB.add(MI.getOperand(OpIdx++));
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000615
Bob Wilson450c6cf2010-09-16 04:25:37 +0000616 // Copy the predicate operands.
Diana Picus116bbab2017-01-13 09:58:52 +0000617 MIB.add(MI.getOperand(OpIdx++));
618 MIB.add(MI.getOperand(OpIdx++));
Bob Wilson450c6cf2010-09-16 04:25:37 +0000619
Weiming Zhaofe26fd22014-01-15 01:32:12 +0000620 // Add an implicit kill and use for the super-reg.
621 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
Bob Wilsonc597fd3b2010-09-13 23:55:10 +0000622 TransferImpOps(MI, MIB, MIB);
623 MI.eraseFromParent();
624}
625
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000626static bool IsAnAddressOperand(const MachineOperand &MO) {
627 // This check is overly conservative. Unless we are certain that the machine
628 // operand is not a symbol reference, we return that it is a symbol reference.
629 // This is important as the load pair may not be split up Windows.
630 switch (MO.getType()) {
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000631 case MachineOperand::MO_Register:
632 case MachineOperand::MO_Immediate:
633 case MachineOperand::MO_CImmediate:
634 case MachineOperand::MO_FPImmediate:
635 return false;
636 case MachineOperand::MO_MachineBasicBlock:
637 return true;
638 case MachineOperand::MO_FrameIndex:
639 return false;
640 case MachineOperand::MO_ConstantPoolIndex:
641 case MachineOperand::MO_TargetIndex:
642 case MachineOperand::MO_JumpTableIndex:
643 case MachineOperand::MO_ExternalSymbol:
644 case MachineOperand::MO_GlobalAddress:
645 case MachineOperand::MO_BlockAddress:
646 return true;
647 case MachineOperand::MO_RegisterMask:
648 case MachineOperand::MO_RegisterLiveOut:
649 return false;
650 case MachineOperand::MO_Metadata:
651 case MachineOperand::MO_MCSymbol:
652 return true;
653 case MachineOperand::MO_CFIIndex:
654 return false;
Tim Northover6b3bd612016-07-29 20:32:59 +0000655 case MachineOperand::MO_IntrinsicID:
Tim Northoverde3aea0412016-08-17 20:25:25 +0000656 case MachineOperand::MO_Predicate:
Tim Northover6b3bd612016-07-29 20:32:59 +0000657 llvm_unreachable("should not exist post-isel");
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000658 }
Saleem Abdulrasoolef550a62014-04-30 05:12:41 +0000659 llvm_unreachable("unhandled machine operand type");
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000660}
661
Evan Chengb8b0ad82011-01-20 08:34:58 +0000662void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
663 MachineBasicBlock::iterator &MBBI) {
664 MachineInstr &MI = *MBBI;
665 unsigned Opcode = MI.getOpcode();
666 unsigned PredReg = 0;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000667 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
Evan Chengb8b0ad82011-01-20 08:34:58 +0000668 unsigned DstReg = MI.getOperand(0).getReg();
669 bool DstIsDead = MI.getOperand(0).isDead();
670 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
671 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000672 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
Evan Chengb8b0ad82011-01-20 08:34:58 +0000673 MachineInstrBuilder LO16, HI16;
Evan Cheng207b2462009-11-06 23:52:48 +0000674
Evan Chengb8b0ad82011-01-20 08:34:58 +0000675 if (!STI->hasV6T2Ops() &&
676 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000677 // FIXME Windows CE supports older ARM CPUs
678 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
679
Evan Chengb8b0ad82011-01-20 08:34:58 +0000680 // Expand into a movi + orr.
681 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
682 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
683 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
684 .addReg(DstReg);
Evan Cheng207b2462009-11-06 23:52:48 +0000685
Evan Chengb8b0ad82011-01-20 08:34:58 +0000686 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
687 unsigned ImmVal = (unsigned)MO.getImm();
688 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
689 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
690 LO16 = LO16.addImm(SOImmValV1);
691 HI16 = HI16.addImm(SOImmValV2);
Chris Lattner1d0c2572011-04-29 05:24:29 +0000692 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
693 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Diana Picusbd66b7d2017-01-20 08:15:24 +0000694 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
695 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
Evan Chengb8b0ad82011-01-20 08:34:58 +0000696 TransferImpOps(MI, LO16, HI16);
697 MI.eraseFromParent();
698 return;
699 }
700
701 unsigned LO16Opc = 0;
702 unsigned HI16Opc = 0;
703 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
704 LO16Opc = ARM::t2MOVi16;
705 HI16Opc = ARM::t2MOVTi16;
706 } else {
707 LO16Opc = ARM::MOVi16;
708 HI16Opc = ARM::MOVTi16;
709 }
710
711 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
712 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
713 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
714 .addReg(DstReg);
715
Saleem Abdulrasoold6c0ba32014-05-01 04:19:56 +0000716 switch (MO.getType()) {
717 case MachineOperand::MO_Immediate: {
Evan Chengb8b0ad82011-01-20 08:34:58 +0000718 unsigned Imm = MO.getImm();
719 unsigned Lo16 = Imm & 0xffff;
720 unsigned Hi16 = (Imm >> 16) & 0xffff;
721 LO16 = LO16.addImm(Lo16);
722 HI16 = HI16.addImm(Hi16);
Saleem Abdulrasoold6c0ba32014-05-01 04:19:56 +0000723 break;
724 }
725 case MachineOperand::MO_ExternalSymbol: {
726 const char *ES = MO.getSymbolName();
727 unsigned TF = MO.getTargetFlags();
728 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
729 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
730 break;
731 }
732 default: {
Evan Chengb8b0ad82011-01-20 08:34:58 +0000733 const GlobalValue *GV = MO.getGlobal();
734 unsigned TF = MO.getTargetFlags();
735 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
736 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
Saleem Abdulrasoold6c0ba32014-05-01 04:19:56 +0000737 break;
738 }
Evan Chengb8b0ad82011-01-20 08:34:58 +0000739 }
740
Chris Lattner1d0c2572011-04-29 05:24:29 +0000741 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
742 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Evan Chengb8b0ad82011-01-20 08:34:58 +0000743 LO16.addImm(Pred).addReg(PredReg);
744 HI16.addImm(Pred).addReg(PredReg);
745
Saleem Abdulrasool8d60fdc2014-05-21 01:25:24 +0000746 if (RequiresBundling)
Duncan P. N. Exon Smithc5b668d2016-02-22 20:49:58 +0000747 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
Saleem Abdulrasoolf8222632014-04-30 04:54:58 +0000748
Evan Chengb8b0ad82011-01-20 08:34:58 +0000749 TransferImpOps(MI, LO16, HI16);
750 MI.eraseFromParent();
751}
752
Tim Northoverb629c772016-04-18 21:48:55 +0000753/// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
Matthias Braun05eeadb2017-05-31 01:21:35 +0000754/// possible. This only gets used at -O0 so we don't care about efficiency of
755/// the generated code.
Tim Northoverb629c772016-04-18 21:48:55 +0000756bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
757 MachineBasicBlock::iterator MBBI,
758 unsigned LdrexOp, unsigned StrexOp,
759 unsigned UxtOp,
760 MachineBasicBlock::iterator &NextMBBI) {
761 bool IsThumb = STI->isThumb();
762 MachineInstr &MI = *MBBI;
763 DebugLoc DL = MI.getDebugLoc();
Matthias Braun05eeadb2017-05-31 01:21:35 +0000764 const MachineOperand &Dest = MI.getOperand(0);
Matthias Brauna88587c2017-08-09 22:22:05 +0000765 unsigned TempReg = MI.getOperand(1).getReg();
Matthias Braun05eeadb2017-05-31 01:21:35 +0000766 // Duplicating undef operands into 2 instructions does not guarantee the same
767 // value on both; However undef should be replaced by xzr anyway.
768 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
769 unsigned AddrReg = MI.getOperand(2).getReg();
770 unsigned DesiredReg = MI.getOperand(3).getReg();
771 unsigned NewReg = MI.getOperand(4).getReg();
Tim Northoverb629c772016-04-18 21:48:55 +0000772
773 MachineFunction *MF = MBB.getParent();
774 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
775 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
776 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
777
778 MF->insert(++MBB.getIterator(), LoadCmpBB);
779 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
780 MF->insert(++StoreBB->getIterator(), DoneBB);
781
782 if (UxtOp) {
783 MachineInstrBuilder MIB =
Matthias Braun05eeadb2017-05-31 01:21:35 +0000784 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
785 .addReg(DesiredReg, RegState::Kill);
Tim Northoverb629c772016-04-18 21:48:55 +0000786 if (!IsThumb)
787 MIB.addImm(0);
Diana Picus4f8c3e12017-01-13 09:37:56 +0000788 MIB.add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000789 }
790
791 // .Lloadcmp:
792 // ldrex rDest, [rAddr]
793 // cmp rDest, rDesired
794 // bne .Ldone
Tim Northoverb629c772016-04-18 21:48:55 +0000795
796 MachineInstrBuilder MIB;
797 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
Matthias Braun05eeadb2017-05-31 01:21:35 +0000798 MIB.addReg(AddrReg);
Tim Northoverb629c772016-04-18 21:48:55 +0000799 if (LdrexOp == ARM::t2LDREX)
800 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
Diana Picus4f8c3e12017-01-13 09:37:56 +0000801 MIB.add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000802
803 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
Diana Picus4f8c3e12017-01-13 09:37:56 +0000804 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
805 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
Matthias Braun05eeadb2017-05-31 01:21:35 +0000806 .addReg(DesiredReg)
Diana Picus4f8c3e12017-01-13 09:37:56 +0000807 .add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000808 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
809 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
810 .addMBB(DoneBB)
811 .addImm(ARMCC::NE)
812 .addReg(ARM::CPSR, RegState::Kill);
813 LoadCmpBB->addSuccessor(DoneBB);
814 LoadCmpBB->addSuccessor(StoreBB);
815
816 // .Lstore:
Matthias Brauna88587c2017-08-09 22:22:05 +0000817 // strex rTempReg, rNew, [rAddr]
818 // cmp rTempReg, #0
Tim Northoverb629c772016-04-18 21:48:55 +0000819 // bne .Lloadcmp
Matthias Brauna88587c2017-08-09 22:22:05 +0000820 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
Matthias Braun05eeadb2017-05-31 01:21:35 +0000821 .addReg(NewReg)
822 .addReg(AddrReg);
Tim Northoverb629c772016-04-18 21:48:55 +0000823 if (StrexOp == ARM::t2STREX)
824 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
Diana Picus4f8c3e12017-01-13 09:37:56 +0000825 MIB.add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000826
827 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
Diana Picus4f8c3e12017-01-13 09:37:56 +0000828 BuildMI(StoreBB, DL, TII->get(CMPri))
Matthias Brauna88587c2017-08-09 22:22:05 +0000829 .addReg(TempReg, RegState::Kill)
Diana Picus4f8c3e12017-01-13 09:37:56 +0000830 .addImm(0)
831 .add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000832 BuildMI(StoreBB, DL, TII->get(Bcc))
833 .addMBB(LoadCmpBB)
834 .addImm(ARMCC::NE)
835 .addReg(ARM::CPSR, RegState::Kill);
836 StoreBB->addSuccessor(LoadCmpBB);
837 StoreBB->addSuccessor(DoneBB);
838
839 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
840 DoneBB->transferSuccessors(&MBB);
Tim Northoverb629c772016-04-18 21:48:55 +0000841
Ahmed Bougachab4af1072016-04-27 20:32:54 +0000842 MBB.addSuccessor(LoadCmpBB);
843
Tim Northoverb629c772016-04-18 21:48:55 +0000844 NextMBBI = MBB.end();
845 MI.eraseFromParent();
Matthias Braun05eeadb2017-05-31 01:21:35 +0000846
847 // Recompute livein lists.
848 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
849 LivePhysRegs LiveRegs;
850 computeLiveIns(LiveRegs, MRI, *DoneBB);
851 computeLiveIns(LiveRegs, MRI, *StoreBB);
852 computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
853 // Do an extra pass around the loop to get loop carried registers right.
854 StoreBB->clearLiveIns();
855 computeLiveIns(LiveRegs, MRI, *StoreBB);
856 LoadCmpBB->clearLiveIns();
857 computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
858
Tim Northoverb629c772016-04-18 21:48:55 +0000859 return true;
860}
861
862/// ARM's ldrexd/strexd take a consecutive register pair (represented as a
863/// single GPRPair register), Thumb's take two separate registers so we need to
864/// extract the subregs from the pair.
865static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
866 unsigned Flags, bool IsThumb,
867 const TargetRegisterInfo *TRI) {
868 if (IsThumb) {
869 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
870 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
871 MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead()));
872 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead()));
873 } else
874 MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead()));
875}
876
877/// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
878bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
879 MachineBasicBlock::iterator MBBI,
880 MachineBasicBlock::iterator &NextMBBI) {
881 bool IsThumb = STI->isThumb();
882 MachineInstr &MI = *MBBI;
883 DebugLoc DL = MI.getDebugLoc();
884 MachineOperand &Dest = MI.getOperand(0);
Matthias Brauna88587c2017-08-09 22:22:05 +0000885 unsigned TempReg = MI.getOperand(1).getReg();
Matthias Braun05eeadb2017-05-31 01:21:35 +0000886 // Duplicating undef operands into 2 instructions does not guarantee the same
887 // value on both; However undef should be replaced by xzr anyway.
888 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
889 unsigned AddrReg = MI.getOperand(2).getReg();
890 unsigned DesiredReg = MI.getOperand(3).getReg();
891 MachineOperand New = MI.getOperand(4);
892 New.setIsKill(false);
Tim Northoverb629c772016-04-18 21:48:55 +0000893
894 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
895 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
Matthias Braun05eeadb2017-05-31 01:21:35 +0000896 unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
897 unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
Tim Northoverb629c772016-04-18 21:48:55 +0000898
899 MachineFunction *MF = MBB.getParent();
900 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
901 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
902 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
903
904 MF->insert(++MBB.getIterator(), LoadCmpBB);
905 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
906 MF->insert(++StoreBB->getIterator(), DoneBB);
907
908 // .Lloadcmp:
909 // ldrexd rDestLo, rDestHi, [rAddr]
910 // cmp rDestLo, rDesiredLo
Matthias Brauna88587c2017-08-09 22:22:05 +0000911 // sbcs rTempReg<dead>, rDestHi, rDesiredHi
Tim Northoverb629c772016-04-18 21:48:55 +0000912 // bne .Ldone
Tim Northoverb629c772016-04-18 21:48:55 +0000913 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
914 MachineInstrBuilder MIB;
915 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
916 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
Matthias Braun05eeadb2017-05-31 01:21:35 +0000917 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000918
919 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
Diana Picus4f8c3e12017-01-13 09:37:56 +0000920 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
921 .addReg(DestLo, getKillRegState(Dest.isDead()))
Matthias Braun05eeadb2017-05-31 01:21:35 +0000922 .addReg(DesiredLo)
Diana Picus4f8c3e12017-01-13 09:37:56 +0000923 .add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000924
Oleg Ranevskyye2ae4152016-12-01 22:58:35 +0000925 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
926 .addReg(DestHi, getKillRegState(Dest.isDead()))
Matthias Braun05eeadb2017-05-31 01:21:35 +0000927 .addReg(DesiredHi)
Oleg Ranevskyye2ae4152016-12-01 22:58:35 +0000928 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
Tim Northoverb629c772016-04-18 21:48:55 +0000929
930 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
931 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
932 .addMBB(DoneBB)
933 .addImm(ARMCC::NE)
934 .addReg(ARM::CPSR, RegState::Kill);
935 LoadCmpBB->addSuccessor(DoneBB);
936 LoadCmpBB->addSuccessor(StoreBB);
937
938 // .Lstore:
Matthias Brauna88587c2017-08-09 22:22:05 +0000939 // strexd rTempReg, rNewLo, rNewHi, [rAddr]
940 // cmp rTempReg, #0
Tim Northoverb629c772016-04-18 21:48:55 +0000941 // bne .Lloadcmp
Tim Northoverb629c772016-04-18 21:48:55 +0000942 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
Matthias Brauna88587c2017-08-09 22:22:05 +0000943 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
Tim Northoverb629c772016-04-18 21:48:55 +0000944 addExclusiveRegPair(MIB, New, 0, IsThumb, TRI);
Matthias Braun05eeadb2017-05-31 01:21:35 +0000945 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000946
947 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
Diana Picus4f8c3e12017-01-13 09:37:56 +0000948 BuildMI(StoreBB, DL, TII->get(CMPri))
Matthias Brauna88587c2017-08-09 22:22:05 +0000949 .addReg(TempReg, RegState::Kill)
Diana Picus4f8c3e12017-01-13 09:37:56 +0000950 .addImm(0)
951 .add(predOps(ARMCC::AL));
Tim Northoverb629c772016-04-18 21:48:55 +0000952 BuildMI(StoreBB, DL, TII->get(Bcc))
953 .addMBB(LoadCmpBB)
954 .addImm(ARMCC::NE)
955 .addReg(ARM::CPSR, RegState::Kill);
956 StoreBB->addSuccessor(LoadCmpBB);
957 StoreBB->addSuccessor(DoneBB);
958
959 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
960 DoneBB->transferSuccessors(&MBB);
Tim Northoverb629c772016-04-18 21:48:55 +0000961
Ahmed Bougachab4af1072016-04-27 20:32:54 +0000962 MBB.addSuccessor(LoadCmpBB);
963
Tim Northoverb629c772016-04-18 21:48:55 +0000964 NextMBBI = MBB.end();
965 MI.eraseFromParent();
Matthias Braun05eeadb2017-05-31 01:21:35 +0000966
967 // Recompute livein lists.
968 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
969 LivePhysRegs LiveRegs;
970 computeLiveIns(LiveRegs, MRI, *DoneBB);
971 computeLiveIns(LiveRegs, MRI, *StoreBB);
972 computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
973 // Do an extra pass around the loop to get loop carried registers right.
974 StoreBB->clearLiveIns();
975 computeLiveIns(LiveRegs, MRI, *StoreBB);
976 LoadCmpBB->clearLiveIns();
977 computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
978
Tim Northoverb629c772016-04-18 21:48:55 +0000979 return true;
980}
981
982
Evan Chengb8b0ad82011-01-20 08:34:58 +0000983bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
Tim Northoverb629c772016-04-18 21:48:55 +0000984 MachineBasicBlock::iterator MBBI,
985 MachineBasicBlock::iterator &NextMBBI) {
Evan Chengb8b0ad82011-01-20 08:34:58 +0000986 MachineInstr &MI = *MBBI;
987 unsigned Opcode = MI.getOpcode();
988 switch (Opcode) {
Bob Wilson9392b0e2010-08-25 23:27:42 +0000989 default:
Evan Chengb8b0ad82011-01-20 08:34:58 +0000990 return false;
Quentin Colombet71a71482015-07-20 21:42:14 +0000991
992 case ARM::TCRETURNdi:
993 case ARM::TCRETURNri: {
994 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
995 assert(MBBI->isReturn() &&
996 "Can only insert epilog into returning blocks");
997 unsigned RetOpcode = MBBI->getOpcode();
998 DebugLoc dl = MBBI->getDebugLoc();
999 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1000 MBB.getParent()->getSubtarget().getInstrInfo());
1001
1002 // Tail call return: adjust the stack pointer and jump to callee.
1003 MBBI = MBB.getLastNonDebugInstr();
1004 MachineOperand &JumpTarget = MBBI->getOperand(0);
1005
1006 // Jump to label or value in register.
1007 if (RetOpcode == ARM::TCRETURNdi) {
1008 unsigned TCOpcode =
1009 STI->isThumb()
1010 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1011 : ARM::TAILJMPd;
1012 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1013 if (JumpTarget.isGlobal())
1014 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1015 JumpTarget.getTargetFlags());
1016 else {
1017 assert(JumpTarget.isSymbol());
1018 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1019 JumpTarget.getTargetFlags());
1020 }
1021
1022 // Add the default predicate in Thumb mode.
1023 if (STI->isThumb())
Diana Picusbd66b7d2017-01-20 08:15:24 +00001024 MIB.add(predOps(ARMCC::AL));
Quentin Colombet71a71482015-07-20 21:42:14 +00001025 } else if (RetOpcode == ARM::TCRETURNri) {
1026 BuildMI(MBB, MBBI, dl,
1027 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
1028 .addReg(JumpTarget.getReg(), RegState::Kill);
1029 }
1030
Duncan P. N. Exon Smith29c52492016-07-08 20:21:17 +00001031 auto NewMI = std::prev(MBBI);
Quentin Colombet71a71482015-07-20 21:42:14 +00001032 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1033 NewMI->addOperand(MBBI->getOperand(i));
1034
1035 // Delete the pseudo instruction TCRETURN.
1036 MBB.erase(MBBI);
1037 MBBI = NewMI;
1038 return true;
1039 }
Jim Grosbachbb0547d2011-03-11 23:09:50 +00001040 case ARM::VMOVScc:
1041 case ARM::VMOVDcc: {
1042 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1043 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1044 MI.getOperand(1).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001045 .add(MI.getOperand(2))
1046 .addImm(MI.getOperand(3).getImm()) // 'pred'
1047 .add(MI.getOperand(4));
Jim Grosbachbb0547d2011-03-11 23:09:50 +00001048
1049 MI.eraseFromParent();
1050 return true;
1051 }
Jim Grosbach4def7042011-07-01 17:14:11 +00001052 case ARM::t2MOVCCr:
Jim Grosbach62a7b472011-03-10 23:56:09 +00001053 case ARM::MOVCCr: {
Jim Grosbach4def7042011-07-01 17:14:11 +00001054 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1055 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
Jim Grosbach62a7b472011-03-10 23:56:09 +00001056 MI.getOperand(1).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001057 .add(MI.getOperand(2))
1058 .addImm(MI.getOperand(3).getImm()) // 'pred'
1059 .add(MI.getOperand(4))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001060 .add(condCodeOp()); // 's' bit
Jim Grosbach62a7b472011-03-10 23:56:09 +00001061
1062 MI.eraseFromParent();
1063 return true;
1064 }
Owen Anderson04912702011-07-21 23:38:37 +00001065 case ARM::MOVCCsi: {
1066 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1067 (MI.getOperand(1).getReg()))
Diana Picus116bbab2017-01-13 09:58:52 +00001068 .add(MI.getOperand(2))
1069 .addImm(MI.getOperand(3).getImm())
1070 .addImm(MI.getOperand(4).getImm()) // 'pred'
1071 .add(MI.getOperand(5))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001072 .add(condCodeOp()); // 's' bit
Owen Anderson04912702011-07-21 23:38:37 +00001073
1074 MI.eraseFromParent();
1075 return true;
1076 }
Owen Andersonb595ed02011-07-21 18:54:16 +00001077 case ARM::MOVCCsr: {
Owen Anderson04912702011-07-21 23:38:37 +00001078 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
Jim Grosbach62a7b472011-03-10 23:56:09 +00001079 (MI.getOperand(1).getReg()))
Diana Picus116bbab2017-01-13 09:58:52 +00001080 .add(MI.getOperand(2))
1081 .add(MI.getOperand(3))
1082 .addImm(MI.getOperand(4).getImm())
1083 .addImm(MI.getOperand(5).getImm()) // 'pred'
1084 .add(MI.getOperand(6))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001085 .add(condCodeOp()); // 's' bit
Jim Grosbach62a7b472011-03-10 23:56:09 +00001086
1087 MI.eraseFromParent();
1088 return true;
1089 }
Tim Northover42180442013-08-22 09:57:11 +00001090 case ARM::t2MOVCCi16:
Jim Grosbachd0254982011-03-11 01:09:28 +00001091 case ARM::MOVCCi16: {
Tim Northover42180442013-08-22 09:57:11 +00001092 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1093 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
Jim Grosbachd0254982011-03-11 01:09:28 +00001094 MI.getOperand(1).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001095 .addImm(MI.getOperand(2).getImm())
1096 .addImm(MI.getOperand(3).getImm()) // 'pred'
1097 .add(MI.getOperand(4));
Jim Grosbachd0254982011-03-11 01:09:28 +00001098 MI.eraseFromParent();
1099 return true;
1100 }
Jim Grosbach4def7042011-07-01 17:14:11 +00001101 case ARM::t2MOVCCi:
Jim Grosbachd0254982011-03-11 01:09:28 +00001102 case ARM::MOVCCi: {
Jim Grosbach4def7042011-07-01 17:14:11 +00001103 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1104 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
Jim Grosbachd0254982011-03-11 01:09:28 +00001105 MI.getOperand(1).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001106 .addImm(MI.getOperand(2).getImm())
1107 .addImm(MI.getOperand(3).getImm()) // 'pred'
1108 .add(MI.getOperand(4))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001109 .add(condCodeOp()); // 's' bit
Jim Grosbachd0254982011-03-11 01:09:28 +00001110
1111 MI.eraseFromParent();
1112 return true;
1113 }
Tim Northover42180442013-08-22 09:57:11 +00001114 case ARM::t2MVNCCi:
Jim Grosbachfa56bca2011-03-11 19:55:55 +00001115 case ARM::MVNCCi: {
Tim Northover42180442013-08-22 09:57:11 +00001116 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1117 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
Jim Grosbachfa56bca2011-03-11 19:55:55 +00001118 MI.getOperand(1).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001119 .addImm(MI.getOperand(2).getImm())
1120 .addImm(MI.getOperand(3).getImm()) // 'pred'
1121 .add(MI.getOperand(4))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001122 .add(condCodeOp()); // 's' bit
Jim Grosbachfa56bca2011-03-11 19:55:55 +00001123
1124 MI.eraseFromParent();
1125 return true;
1126 }
Tim Northover42180442013-08-22 09:57:11 +00001127 case ARM::t2MOVCClsl:
1128 case ARM::t2MOVCClsr:
1129 case ARM::t2MOVCCasr:
1130 case ARM::t2MOVCCror: {
1131 unsigned NewOpc;
1132 switch (Opcode) {
1133 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1134 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1135 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1136 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1137 default: llvm_unreachable("unexpeced conditional move");
1138 }
1139 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1140 MI.getOperand(1).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001141 .add(MI.getOperand(2))
1142 .addImm(MI.getOperand(3).getImm())
1143 .addImm(MI.getOperand(4).getImm()) // 'pred'
1144 .add(MI.getOperand(5))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001145 .add(condCodeOp()); // 's' bit
Tim Northover42180442013-08-22 09:57:11 +00001146 MI.eraseFromParent();
1147 return true;
1148 }
Chad Rosier1ec8e402012-11-06 23:05:24 +00001149 case ARM::Int_eh_sjlj_dispatchsetup: {
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001150 MachineFunction &MF = *MI.getParent()->getParent();
1151 const ARMBaseInstrInfo *AII =
1152 static_cast<const ARMBaseInstrInfo*>(TII);
1153 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1154 // For functions using a base pointer, we rematerialize it (via the frame
1155 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1156 // for us. Otherwise, expand to nothing.
1157 if (RI.hasBasePointer(MF)) {
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001158 int32_t NumBytes = AFI->getFramePtrSpillOffset();
1159 unsigned FramePtr = RI.getFrameRegister(MF);
Eric Christopherfc6de422014-08-05 02:39:49 +00001160 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1161 "base pointer without frame pointer?");
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001162
1163 if (AFI->isThumb2Function()) {
Craig Topperf6e7e122012-03-27 07:21:54 +00001164 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1165 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001166 } else if (AFI->isThumbFunction()) {
Craig Topperf6e7e122012-03-27 07:21:54 +00001167 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1168 FramePtr, -NumBytes, *TII, RI);
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001169 } else {
Craig Topperf6e7e122012-03-27 07:21:54 +00001170 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1171 FramePtr, -NumBytes, ARMCC::AL, 0,
1172 *TII);
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001173 }
Jim Grosbachcb6fc2b2010-10-20 00:02:50 +00001174 // If there's dynamic realignment, adjust for it.
Jim Grosbach723159e2010-10-20 01:10:01 +00001175 if (RI.needsStackRealignment(MF)) {
Matthias Braun941a7052016-07-28 18:40:00 +00001176 MachineFrameInfo &MFI = MF.getFrameInfo();
1177 unsigned MaxAlign = MFI.getMaxAlignment();
Jim Grosbachcb6fc2b2010-10-20 00:02:50 +00001178 assert (!AFI->isThumb1OnlyFunction());
1179 // Emit bic r6, r6, MaxAlign
Kristof Beyls933de7a2015-01-08 15:09:14 +00001180 assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1181 "immediates larger than 256 with all lower "
1182 "bits set.");
Jim Grosbachcb6fc2b2010-10-20 00:02:50 +00001183 unsigned bicOpc = AFI->isThumbFunction() ?
1184 ARM::t2BICri : ARM::BICri;
Diana Picus8a73f552017-01-13 10:18:01 +00001185 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1186 .addReg(ARM::R6, RegState::Kill)
1187 .addImm(MaxAlign - 1)
1188 .add(predOps(ARMCC::AL))
1189 .add(condCodeOp());
Jim Grosbachcb6fc2b2010-10-20 00:02:50 +00001190 }
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001191
1192 }
1193 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001194 return true;
Jim Grosbachbbdc5d22010-10-19 23:27:08 +00001195 }
1196
Jim Grosbach8b6a9c12010-10-14 22:57:13 +00001197 case ARM::MOVsrl_flag:
1198 case ARM::MOVsra_flag: {
Robert Wilhelm2788d3e2013-09-28 13:42:22 +00001199 // These are just fancy MOVs instructions.
Diana Picus4f8c3e12017-01-13 09:37:56 +00001200 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1201 MI.getOperand(0).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001202 .add(MI.getOperand(1))
Diana Picus4f8c3e12017-01-13 09:37:56 +00001203 .addImm(ARM_AM::getSORegOpc(
1204 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1205 .add(predOps(ARMCC::AL))
1206 .addReg(ARM::CPSR, RegState::Define);
Jim Grosbach8b6a9c12010-10-14 22:57:13 +00001207 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001208 return true;
Jim Grosbach8b6a9c12010-10-14 22:57:13 +00001209 }
1210 case ARM::RRX: {
1211 // This encodes as "MOVs Rd, Rm, rrx
1212 MachineInstrBuilder MIB =
Diana Picus4f8c3e12017-01-13 09:37:56 +00001213 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1214 MI.getOperand(0).getReg())
Diana Picus116bbab2017-01-13 09:58:52 +00001215 .add(MI.getOperand(1))
Diana Picus4f8c3e12017-01-13 09:37:56 +00001216 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1217 .add(predOps(ARMCC::AL))
Diana Picusbd66b7d2017-01-20 08:15:24 +00001218 .add(condCodeOp());
Jim Grosbach8b6a9c12010-10-14 22:57:13 +00001219 TransferImpOps(MI, MIB, MIB);
1220 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001221 return true;
Jim Grosbach8b6a9c12010-10-14 22:57:13 +00001222 }
Jim Grosbache4750ef2011-06-30 19:38:01 +00001223 case ARM::tTPsoft:
Jason W Kimc79c5f62010-12-08 23:14:44 +00001224 case ARM::TPsoft: {
Saleem Abdulrasool5282eed2017-01-29 16:46:22 +00001225 const bool Thumb = Opcode == ARM::tTPsoft;
1226
Christian Pirkerc6308f52014-06-24 15:45:59 +00001227 MachineInstrBuilder MIB;
Saleem Abdulrasool5282eed2017-01-29 16:46:22 +00001228 if (STI->genLongCalls()) {
1229 MachineFunction *MF = MBB.getParent();
1230 MachineConstantPool *MCP = MF->getConstantPool();
1231 unsigned PCLabelID = AFI->createPICLabelUId();
1232 MachineConstantPoolValue *CPV =
1233 ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
1234 "__aeabi_read_tp", PCLabelID, 0);
1235 unsigned Reg = MI.getOperand(0).getReg();
Christian Pirkerc6308f52014-06-24 15:45:59 +00001236 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
Saleem Abdulrasool5282eed2017-01-29 16:46:22 +00001237 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1238 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1239 if (!Thumb)
1240 MIB.addImm(0);
1241 MIB.add(predOps(ARMCC::AL));
1242
1243 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1244 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1245 if (Thumb)
1246 MIB.add(predOps(ARMCC::AL));
1247 MIB.addReg(Reg, RegState::Kill);
1248 } else {
1249 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1250 TII->get(Thumb ? ARM::tBL : ARM::BL));
1251 if (Thumb)
1252 MIB.add(predOps(ARMCC::AL));
1253 MIB.addExternalSymbol("__aeabi_read_tp", 0);
1254 }
Jason W Kimc79c5f62010-12-08 23:14:44 +00001255
Chris Lattner1d0c2572011-04-29 05:24:29 +00001256 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Jason W Kimc79c5f62010-12-08 23:14:44 +00001257 TransferImpOps(MI, MIB, MIB);
1258 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001259 return true;
Bill Wendlingf75412d2010-12-09 00:51:54 +00001260 }
Bob Wilsonc597fd3b2010-09-13 23:55:10 +00001261 case ARM::tLDRpci_pic:
Evan Cheng207b2462009-11-06 23:52:48 +00001262 case ARM::t2LDRpci_pic: {
1263 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
Owen Anderson4ebf4712011-02-08 22:39:40 +00001264 ? ARM::tLDRpci : ARM::t2LDRpci;
Evan Cheng207b2462009-11-06 23:52:48 +00001265 unsigned DstReg = MI.getOperand(0).getReg();
Evan Cheng7c1f56f2010-05-12 23:13:12 +00001266 bool DstIsDead = MI.getOperand(0).isDead();
1267 MachineInstrBuilder MIB1 =
Diana Picus4f8c3e12017-01-13 09:37:56 +00001268 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
Diana Picus116bbab2017-01-13 09:58:52 +00001269 .add(MI.getOperand(1))
Diana Picus4f8c3e12017-01-13 09:37:56 +00001270 .add(predOps(ARMCC::AL));
Chris Lattner1d0c2572011-04-29 05:24:29 +00001271 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Diana Picus116bbab2017-01-13 09:58:52 +00001272 MachineInstrBuilder MIB2 =
1273 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1274 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1275 .addReg(DstReg)
1276 .add(MI.getOperand(2));
Evan Cheng7c1f56f2010-05-12 23:13:12 +00001277 TransferImpOps(MI, MIB1, MIB2);
Evan Cheng207b2462009-11-06 23:52:48 +00001278 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001279 return true;
1280 }
1281
Tim Northover72360d22013-12-02 10:35:41 +00001282 case ARM::LDRLIT_ga_abs:
1283 case ARM::LDRLIT_ga_pcrel:
1284 case ARM::LDRLIT_ga_pcrel_ldr:
1285 case ARM::tLDRLIT_ga_abs:
1286 case ARM::tLDRLIT_ga_pcrel: {
1287 unsigned DstReg = MI.getOperand(0).getReg();
1288 bool DstIsDead = MI.getOperand(0).isDead();
1289 const MachineOperand &MO1 = MI.getOperand(1);
1290 const GlobalValue *GV = MO1.getGlobal();
1291 bool IsARM =
1292 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1293 bool IsPIC =
1294 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1295 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1296 unsigned PICAddOpc =
1297 IsARM
Tim Northover2ac7e4b2014-12-10 23:40:50 +00001298 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
Tim Northover72360d22013-12-02 10:35:41 +00001299 : ARM::tPICADD;
1300
1301 // We need a new const-pool entry to load from.
1302 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1303 unsigned ARMPCLabelIndex = 0;
1304 MachineConstantPoolValue *CPV;
1305
1306 if (IsPIC) {
1307 unsigned PCAdj = IsARM ? 8 : 4;
1308 ARMPCLabelIndex = AFI->createPICLabelUId();
1309 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
1310 ARMCP::CPValue, PCAdj);
1311 } else
1312 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1313
1314 MachineInstrBuilder MIB =
1315 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1316 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1317 if (IsARM)
1318 MIB.addImm(0);
Diana Picus4f8c3e12017-01-13 09:37:56 +00001319 MIB.add(predOps(ARMCC::AL));
Tim Northover72360d22013-12-02 10:35:41 +00001320
1321 if (IsPIC) {
1322 MachineInstrBuilder MIB =
1323 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1324 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1325 .addReg(DstReg)
1326 .addImm(ARMPCLabelIndex);
1327
1328 if (IsARM)
Diana Picus4f8c3e12017-01-13 09:37:56 +00001329 MIB.add(predOps(ARMCC::AL));
Tim Northover72360d22013-12-02 10:35:41 +00001330 }
1331
1332 MI.eraseFromParent();
1333 return true;
1334 }
Evan Cheng2f2435d2011-01-21 18:55:51 +00001335 case ARM::MOV_ga_pcrel:
1336 case ARM::MOV_ga_pcrel_ldr:
Evan Cheng2f2435d2011-01-21 18:55:51 +00001337 case ARM::t2MOV_ga_pcrel: {
1338 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
Evan Chengb8b0ad82011-01-20 08:34:58 +00001339 unsigned LabelId = AFI->createPICLabelUId();
1340 unsigned DstReg = MI.getOperand(0).getReg();
1341 bool DstIsDead = MI.getOperand(0).isDead();
1342 const MachineOperand &MO1 = MI.getOperand(1);
1343 const GlobalValue *GV = MO1.getGlobal();
1344 unsigned TF = MO1.getTargetFlags();
Tim Northoverdb962e2c2013-11-25 16:24:52 +00001345 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
Evan Cheng2f2435d2011-01-21 18:55:51 +00001346 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
Jim Grosbach06210a22011-07-13 17:25:55 +00001347 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
Tim Northoverdb962e2c2013-11-25 16:24:52 +00001348 unsigned LO16TF = TF | ARMII::MO_LO16;
1349 unsigned HI16TF = TF | ARMII::MO_HI16;
Evan Chengb8b0ad82011-01-20 08:34:58 +00001350 unsigned PICAddOpc = isARM
Evan Cheng2f2435d2011-01-21 18:55:51 +00001351 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
Evan Chengb8b0ad82011-01-20 08:34:58 +00001352 : ARM::tPICADD;
1353 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1354 TII->get(LO16Opc), DstReg)
Evan Cheng2f2435d2011-01-21 18:55:51 +00001355 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
Evan Chengb8b0ad82011-01-20 08:34:58 +00001356 .addImm(LabelId);
Tim Northoverdb962e2c2013-11-25 16:24:52 +00001357
1358 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
Evan Cheng2f2435d2011-01-21 18:55:51 +00001359 .addReg(DstReg)
1360 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1361 .addImm(LabelId);
Evan Cheng2f2435d2011-01-21 18:55:51 +00001362
1363 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
Evan Chengb8b0ad82011-01-20 08:34:58 +00001364 TII->get(PICAddOpc))
1365 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1366 .addReg(DstReg).addImm(LabelId);
1367 if (isARM) {
Diana Picus4f8c3e12017-01-13 09:37:56 +00001368 MIB3.add(predOps(ARMCC::AL));
Evan Cheng2f2435d2011-01-21 18:55:51 +00001369 if (Opcode == ARM::MOV_ga_pcrel_ldr)
Jakob Stoklund Olesen4fd0e4f2012-05-20 06:38:42 +00001370 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Evan Chengb8b0ad82011-01-20 08:34:58 +00001371 }
Evan Cheng2f2435d2011-01-21 18:55:51 +00001372 TransferImpOps(MI, MIB1, MIB3);
Evan Chengb8b0ad82011-01-20 08:34:58 +00001373 MI.eraseFromParent();
1374 return true;
Evan Cheng207b2462009-11-06 23:52:48 +00001375 }
Evan Cheng7c1f56f2010-05-12 23:13:12 +00001376
Anton Korobeynikov48043d02010-08-30 22:50:36 +00001377 case ARM::MOVi32imm:
Evan Cheng2bcb8da2010-11-13 02:25:14 +00001378 case ARM::MOVCCi32imm:
1379 case ARM::t2MOVi32imm:
Evan Chengdfce83c2011-01-17 08:03:18 +00001380 case ARM::t2MOVCCi32imm:
Evan Chengb8b0ad82011-01-20 08:34:58 +00001381 ExpandMOV32BitImm(MBB, MBBI);
1382 return true;
Evan Cheng2f736c92010-05-13 00:17:02 +00001383
Tim Northoverd8407452013-10-01 14:33:28 +00001384 case ARM::SUBS_PC_LR: {
1385 MachineInstrBuilder MIB =
1386 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1387 .addReg(ARM::LR)
Diana Picus116bbab2017-01-13 09:58:52 +00001388 .add(MI.getOperand(0))
1389 .add(MI.getOperand(1))
1390 .add(MI.getOperand(2))
Tim Northoverd8407452013-10-01 14:33:28 +00001391 .addReg(ARM::CPSR, RegState::Undef);
1392 TransferImpOps(MI, MIB, MIB);
1393 MI.eraseFromParent();
1394 return true;
1395 }
Owen Andersond6c5a742011-03-29 16:45:53 +00001396 case ARM::VLDMQIA: {
1397 unsigned NewOpc = ARM::VLDMDIA;
Bob Wilson6b853c32010-09-16 00:31:02 +00001398 MachineInstrBuilder MIB =
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001399 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
Bob Wilson6b853c32010-09-16 00:31:02 +00001400 unsigned OpIdx = 0;
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001401
Bob Wilson6b853c32010-09-16 00:31:02 +00001402 // Grab the Q register destination.
1403 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1404 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001405
1406 // Copy the source register.
Diana Picus116bbab2017-01-13 09:58:52 +00001407 MIB.add(MI.getOperand(OpIdx++));
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001408
Bob Wilson6b853c32010-09-16 00:31:02 +00001409 // Copy the predicate operands.
Diana Picus116bbab2017-01-13 09:58:52 +00001410 MIB.add(MI.getOperand(OpIdx++));
1411 MIB.add(MI.getOperand(OpIdx++));
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001412
Bob Wilson6b853c32010-09-16 00:31:02 +00001413 // Add the destination operands (D subregs).
1414 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1415 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1416 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1417 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001418
Bob Wilson6b853c32010-09-16 00:31:02 +00001419 // Add an implicit def for the super-register.
1420 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1421 TransferImpOps(MI, MIB, MIB);
Jakob Stoklund Olesen465cdf32011-12-17 00:07:02 +00001422 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Bob Wilson6b853c32010-09-16 00:31:02 +00001423 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001424 return true;
Bob Wilson6b853c32010-09-16 00:31:02 +00001425 }
1426
Owen Andersond6c5a742011-03-29 16:45:53 +00001427 case ARM::VSTMQIA: {
1428 unsigned NewOpc = ARM::VSTMDIA;
Bob Wilson6b853c32010-09-16 00:31:02 +00001429 MachineInstrBuilder MIB =
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001430 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
Bob Wilson6b853c32010-09-16 00:31:02 +00001431 unsigned OpIdx = 0;
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001432
Bob Wilson6b853c32010-09-16 00:31:02 +00001433 // Grab the Q register source.
1434 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1435 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001436
1437 // Copy the destination register.
Diana Picus116bbab2017-01-13 09:58:52 +00001438 MIB.add(MI.getOperand(OpIdx++));
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001439
Bob Wilson6b853c32010-09-16 00:31:02 +00001440 // Copy the predicate operands.
Diana Picus116bbab2017-01-13 09:58:52 +00001441 MIB.add(MI.getOperand(OpIdx++));
1442 MIB.add(MI.getOperand(OpIdx++));
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001443
Bob Wilson6b853c32010-09-16 00:31:02 +00001444 // Add the source operands (D subregs).
1445 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1446 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
Matthias Braund6b108e2015-02-16 19:34:30 +00001447 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1448 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001449
Chris Lattner1d0c2572011-04-29 05:24:29 +00001450 if (SrcIsKill) // Add an implicit kill for the Q register.
1451 MIB->addRegisterKilled(SrcReg, TRI, true);
Bill Wendlinga68e3a52010-11-16 01:16:36 +00001452
Bob Wilson6b853c32010-09-16 00:31:02 +00001453 TransferImpOps(MI, MIB, MIB);
Jakob Stoklund Olesen465cdf32011-12-17 00:07:02 +00001454 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Bob Wilson6b853c32010-09-16 00:31:02 +00001455 MI.eraseFromParent();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001456 return true;
Bob Wilson6b853c32010-09-16 00:31:02 +00001457 }
1458
Bob Wilson75a64082010-09-02 16:00:54 +00001459 case ARM::VLD2q8Pseudo:
Bob Wilson75a64082010-09-02 16:00:54 +00001460 case ARM::VLD2q16Pseudo:
Bob Wilson75a64082010-09-02 16:00:54 +00001461 case ARM::VLD2q32Pseudo:
Jim Grosbachd146a022011-12-09 21:28:25 +00001462 case ARM::VLD2q8PseudoWB_fixed:
1463 case ARM::VLD2q16PseudoWB_fixed:
1464 case ARM::VLD2q32PseudoWB_fixed:
Jim Grosbachd146a022011-12-09 21:28:25 +00001465 case ARM::VLD2q8PseudoWB_register:
1466 case ARM::VLD2q16PseudoWB_register:
1467 case ARM::VLD2q32PseudoWB_register:
Bob Wilson35fafca2010-09-03 18:16:02 +00001468 case ARM::VLD3d8Pseudo:
Bob Wilson35fafca2010-09-03 18:16:02 +00001469 case ARM::VLD3d16Pseudo:
Bob Wilson35fafca2010-09-03 18:16:02 +00001470 case ARM::VLD3d32Pseudo:
Bob Wilson75a64082010-09-02 16:00:54 +00001471 case ARM::VLD1d64TPseudo:
Jiangning Liu4df23632014-01-16 09:16:13 +00001472 case ARM::VLD1d64TPseudoWB_fixed:
Bob Wilson35fafca2010-09-03 18:16:02 +00001473 case ARM::VLD3d8Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001474 case ARM::VLD3d16Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001475 case ARM::VLD3d32Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001476 case ARM::VLD3q8Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001477 case ARM::VLD3q16Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001478 case ARM::VLD3q32Pseudo_UPD:
Bob Wilsona609b892011-02-07 17:43:15 +00001479 case ARM::VLD3q8oddPseudo:
1480 case ARM::VLD3q16oddPseudo:
1481 case ARM::VLD3q32oddPseudo:
Bob Wilson35fafca2010-09-03 18:16:02 +00001482 case ARM::VLD3q8oddPseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001483 case ARM::VLD3q16oddPseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001484 case ARM::VLD3q32oddPseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001485 case ARM::VLD4d8Pseudo:
Bob Wilson35fafca2010-09-03 18:16:02 +00001486 case ARM::VLD4d16Pseudo:
Bob Wilson35fafca2010-09-03 18:16:02 +00001487 case ARM::VLD4d32Pseudo:
Bob Wilson75a64082010-09-02 16:00:54 +00001488 case ARM::VLD1d64QPseudo:
Jiangning Liu4df23632014-01-16 09:16:13 +00001489 case ARM::VLD1d64QPseudoWB_fixed:
Bob Wilson35fafca2010-09-03 18:16:02 +00001490 case ARM::VLD4d8Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001491 case ARM::VLD4d16Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001492 case ARM::VLD4d32Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001493 case ARM::VLD4q8Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001494 case ARM::VLD4q16Pseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001495 case ARM::VLD4q32Pseudo_UPD:
Bob Wilsona609b892011-02-07 17:43:15 +00001496 case ARM::VLD4q8oddPseudo:
1497 case ARM::VLD4q16oddPseudo:
1498 case ARM::VLD4q32oddPseudo:
Bob Wilson35fafca2010-09-03 18:16:02 +00001499 case ARM::VLD4q8oddPseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001500 case ARM::VLD4q16oddPseudo_UPD:
Bob Wilson35fafca2010-09-03 18:16:02 +00001501 case ARM::VLD4q32oddPseudo_UPD:
Bob Wilson77ab1652010-11-29 19:35:29 +00001502 case ARM::VLD3DUPd8Pseudo:
1503 case ARM::VLD3DUPd16Pseudo:
1504 case ARM::VLD3DUPd32Pseudo:
1505 case ARM::VLD3DUPd8Pseudo_UPD:
1506 case ARM::VLD3DUPd16Pseudo_UPD:
1507 case ARM::VLD3DUPd32Pseudo_UPD:
Bob Wilson431ac4ef2010-11-30 00:00:35 +00001508 case ARM::VLD4DUPd8Pseudo:
1509 case ARM::VLD4DUPd16Pseudo:
1510 case ARM::VLD4DUPd32Pseudo:
1511 case ARM::VLD4DUPd8Pseudo_UPD:
1512 case ARM::VLD4DUPd16Pseudo_UPD:
1513 case ARM::VLD4DUPd32Pseudo_UPD:
Bob Wilsond5c57a52010-09-13 23:01:35 +00001514 ExpandVLD(MBBI);
Evan Chengb8b0ad82011-01-20 08:34:58 +00001515 return true;
Bob Wilson75a64082010-09-02 16:00:54 +00001516
Bob Wilson950882b2010-08-28 05:12:57 +00001517 case ARM::VST2q8Pseudo:
Bob Wilson950882b2010-08-28 05:12:57 +00001518 case ARM::VST2q16Pseudo:
Bob Wilson950882b2010-08-28 05:12:57 +00001519 case ARM::VST2q32Pseudo:
Jim Grosbach88ac7612011-12-14 21:32:11 +00001520 case ARM::VST2q8PseudoWB_fixed:
1521 case ARM::VST2q16PseudoWB_fixed:
1522 case ARM::VST2q32PseudoWB_fixed:
Jim Grosbach88ac7612011-12-14 21:32:11 +00001523 case ARM::VST2q8PseudoWB_register:
1524 case ARM::VST2q16PseudoWB_register:
1525 case ARM::VST2q32PseudoWB_register:
Bob Wilson97919e92010-08-26 18:51:29 +00001526 case ARM::VST3d8Pseudo:
Bob Wilson97919e92010-08-26 18:51:29 +00001527 case ARM::VST3d16Pseudo:
Bob Wilson97919e92010-08-26 18:51:29 +00001528 case ARM::VST3d32Pseudo:
Bob Wilson97919e92010-08-26 18:51:29 +00001529 case ARM::VST1d64TPseudo:
Bob Wilson97919e92010-08-26 18:51:29 +00001530 case ARM::VST3d8Pseudo_UPD:
Bob Wilson97919e92010-08-26 18:51:29 +00001531 case ARM::VST3d16Pseudo_UPD:
Bob Wilson97919e92010-08-26 18:51:29 +00001532 case ARM::VST3d32Pseudo_UPD:
Jim Grosbach98d032f2011-11-29 22:38:04 +00001533 case ARM::VST1d64TPseudoWB_fixed:
1534 case ARM::VST1d64TPseudoWB_register:
Bob Wilson97919e92010-08-26 18:51:29 +00001535 case ARM::VST3q8Pseudo_UPD:
Bob Wilson97919e92010-08-26 18:51:29 +00001536 case ARM::VST3q16Pseudo_UPD:
Bob Wilson97919e92010-08-26 18:51:29 +00001537 case ARM::VST3q32Pseudo_UPD:
Bob Wilsona609b892011-02-07 17:43:15 +00001538 case ARM::VST3q8oddPseudo:
1539 case ARM::VST3q16oddPseudo:
1540 case ARM::VST3q32oddPseudo:
Bob Wilson97919e92010-08-26 18:51:29 +00001541 case ARM::VST3q8oddPseudo_UPD:
Bob Wilson97919e92010-08-26 18:51:29 +00001542 case ARM::VST3q16oddPseudo_UPD:
Bob Wilson97919e92010-08-26 18:51:29 +00001543 case ARM::VST3q32oddPseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001544 case ARM::VST4d8Pseudo:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001545 case ARM::VST4d16Pseudo:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001546 case ARM::VST4d32Pseudo:
Bob Wilson4cec4492010-08-26 05:33:30 +00001547 case ARM::VST1d64QPseudo:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001548 case ARM::VST4d8Pseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001549 case ARM::VST4d16Pseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001550 case ARM::VST4d32Pseudo_UPD:
Jim Grosbach5ee209c2011-11-29 22:58:48 +00001551 case ARM::VST1d64QPseudoWB_fixed:
1552 case ARM::VST1d64QPseudoWB_register:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001553 case ARM::VST4q8Pseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001554 case ARM::VST4q16Pseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001555 case ARM::VST4q32Pseudo_UPD:
Bob Wilsona609b892011-02-07 17:43:15 +00001556 case ARM::VST4q8oddPseudo:
1557 case ARM::VST4q16oddPseudo:
1558 case ARM::VST4q32oddPseudo:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001559 case ARM::VST4q8oddPseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001560 case ARM::VST4q16oddPseudo_UPD:
Bob Wilson9392b0e2010-08-25 23:27:42 +00001561 case ARM::VST4q32oddPseudo_UPD:
Bob Wilsond5c57a52010-09-13 23:01:35 +00001562 ExpandVST(MBBI);
Evan Chengb8b0ad82011-01-20 08:34:58 +00001563 return true;
Bob Wilsond5c57a52010-09-13 23:01:35 +00001564
Bob Wilsondc449902010-11-01 22:04:05 +00001565 case ARM::VLD1LNq8Pseudo:
1566 case ARM::VLD1LNq16Pseudo:
1567 case ARM::VLD1LNq32Pseudo:
1568 case ARM::VLD1LNq8Pseudo_UPD:
1569 case ARM::VLD1LNq16Pseudo_UPD:
1570 case ARM::VLD1LNq32Pseudo_UPD:
Bob Wilsond5c57a52010-09-13 23:01:35 +00001571 case ARM::VLD2LNd8Pseudo:
1572 case ARM::VLD2LNd16Pseudo:
1573 case ARM::VLD2LNd32Pseudo:
1574 case ARM::VLD2LNq16Pseudo:
1575 case ARM::VLD2LNq32Pseudo:
1576 case ARM::VLD2LNd8Pseudo_UPD:
1577 case ARM::VLD2LNd16Pseudo_UPD:
1578 case ARM::VLD2LNd32Pseudo_UPD:
1579 case ARM::VLD2LNq16Pseudo_UPD:
1580 case ARM::VLD2LNq32Pseudo_UPD:
1581 case ARM::VLD3LNd8Pseudo:
1582 case ARM::VLD3LNd16Pseudo:
1583 case ARM::VLD3LNd32Pseudo:
1584 case ARM::VLD3LNq16Pseudo:
1585 case ARM::VLD3LNq32Pseudo:
1586 case ARM::VLD3LNd8Pseudo_UPD:
1587 case ARM::VLD3LNd16Pseudo_UPD:
1588 case ARM::VLD3LNd32Pseudo_UPD:
1589 case ARM::VLD3LNq16Pseudo_UPD:
1590 case ARM::VLD3LNq32Pseudo_UPD:
1591 case ARM::VLD4LNd8Pseudo:
1592 case ARM::VLD4LNd16Pseudo:
1593 case ARM::VLD4LNd32Pseudo:
1594 case ARM::VLD4LNq16Pseudo:
1595 case ARM::VLD4LNq32Pseudo:
1596 case ARM::VLD4LNd8Pseudo_UPD:
1597 case ARM::VLD4LNd16Pseudo_UPD:
1598 case ARM::VLD4LNd32Pseudo_UPD:
1599 case ARM::VLD4LNq16Pseudo_UPD:
1600 case ARM::VLD4LNq32Pseudo_UPD:
Bob Wilsond80b29d2010-11-02 21:18:25 +00001601 case ARM::VST1LNq8Pseudo:
1602 case ARM::VST1LNq16Pseudo:
1603 case ARM::VST1LNq32Pseudo:
1604 case ARM::VST1LNq8Pseudo_UPD:
1605 case ARM::VST1LNq16Pseudo_UPD:
1606 case ARM::VST1LNq32Pseudo_UPD:
Bob Wilsond5c57a52010-09-13 23:01:35 +00001607 case ARM::VST2LNd8Pseudo:
1608 case ARM::VST2LNd16Pseudo:
1609 case ARM::VST2LNd32Pseudo:
1610 case ARM::VST2LNq16Pseudo:
1611 case ARM::VST2LNq32Pseudo:
1612 case ARM::VST2LNd8Pseudo_UPD:
1613 case ARM::VST2LNd16Pseudo_UPD:
1614 case ARM::VST2LNd32Pseudo_UPD:
1615 case ARM::VST2LNq16Pseudo_UPD:
1616 case ARM::VST2LNq32Pseudo_UPD:
1617 case ARM::VST3LNd8Pseudo:
1618 case ARM::VST3LNd16Pseudo:
1619 case ARM::VST3LNd32Pseudo:
1620 case ARM::VST3LNq16Pseudo:
1621 case ARM::VST3LNq32Pseudo:
1622 case ARM::VST3LNd8Pseudo_UPD:
1623 case ARM::VST3LNd16Pseudo_UPD:
1624 case ARM::VST3LNd32Pseudo_UPD:
1625 case ARM::VST3LNq16Pseudo_UPD:
1626 case ARM::VST3LNq32Pseudo_UPD:
1627 case ARM::VST4LNd8Pseudo:
1628 case ARM::VST4LNd16Pseudo:
1629 case ARM::VST4LNd32Pseudo:
1630 case ARM::VST4LNq16Pseudo:
1631 case ARM::VST4LNq32Pseudo:
1632 case ARM::VST4LNd8Pseudo_UPD:
1633 case ARM::VST4LNd16Pseudo_UPD:
1634 case ARM::VST4LNd32Pseudo_UPD:
1635 case ARM::VST4LNq16Pseudo_UPD:
1636 case ARM::VST4LNq32Pseudo_UPD:
1637 ExpandLaneOp(MBBI);
Evan Chengb8b0ad82011-01-20 08:34:58 +00001638 return true;
Bob Wilsonc597fd3b2010-09-13 23:55:10 +00001639
Jim Grosbach4a5c8872011-12-15 22:27:11 +00001640 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1641 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
Jim Grosbach4a5c8872011-12-15 22:27:11 +00001642 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1643 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
Tim Northoverb629c772016-04-18 21:48:55 +00001644
1645 case ARM::CMP_SWAP_8:
1646 if (STI->isThumb())
1647 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1648 ARM::tUXTB, NextMBBI);
1649 else
1650 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1651 ARM::UXTB, NextMBBI);
1652 case ARM::CMP_SWAP_16:
1653 if (STI->isThumb())
1654 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1655 ARM::tUXTH, NextMBBI);
1656 else
1657 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1658 ARM::UXTH, NextMBBI);
1659 case ARM::CMP_SWAP_32:
1660 if (STI->isThumb())
1661 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1662 NextMBBI);
1663 else
1664 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1665
1666 case ARM::CMP_SWAP_64:
1667 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
Evan Chengb8b0ad82011-01-20 08:34:58 +00001668 }
Evan Chengb8b0ad82011-01-20 08:34:58 +00001669}
1670
1671bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1672 bool Modified = false;
1673
1674 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1675 while (MBBI != E) {
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00001676 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
Tim Northoverb629c772016-04-18 21:48:55 +00001677 Modified |= ExpandMI(MBB, MBBI, NMBBI);
Evan Cheng207b2462009-11-06 23:52:48 +00001678 MBBI = NMBBI;
1679 }
1680
1681 return Modified;
1682}
1683
1684bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
Eric Christopher1b21f002015-01-29 00:19:33 +00001685 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1686 TII = STI->getInstrInfo();
1687 TRI = STI->getRegisterInfo();
Evan Chengb8b0ad82011-01-20 08:34:58 +00001688 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng207b2462009-11-06 23:52:48 +00001689
1690 bool Modified = false;
Javed Absare9599e32017-07-20 12:35:37 +00001691 for (MachineBasicBlock &MBB : MF)
1692 Modified |= ExpandMBB(MBB);
Jakob Stoklund Olesen9c3badc2011-07-29 00:27:32 +00001693 if (VerifyARMPseudo)
1694 MF.verify(this, "After expanding ARM pseudo instructions.");
Evan Cheng207b2462009-11-06 23:52:48 +00001695 return Modified;
1696}
1697
1698/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1699/// expansion pass.
1700FunctionPass *llvm::createARMExpandPseudoPass() {
1701 return new ARMExpandPseudo();
1702}