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Valery Pykhtine330cfa2016-09-20 10:41:16 +00001//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// VOP3 Classes
12//===----------------------------------------------------------------------===//
13
14class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
Sam Kolton4685b70a2017-07-18 14:23:26 +000015 dag src0 = !if(P.HasOMod,
16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
17 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
18
Valery Pykhtine330cfa2016-09-20 10:41:16 +000019 list<dag> ret3 = [(set P.DstVT:$vdst,
Sam Kolton4685b70a2017-07-18 14:23:26 +000020 (node (P.Src0VT src0),
Valery Pykhtine330cfa2016-09-20 10:41:16 +000021 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
22 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
23
24 list<dag> ret2 = [(set P.DstVT:$vdst,
Sam Kolton4685b70a2017-07-18 14:23:26 +000025 (node (P.Src0VT src0),
Valery Pykhtine330cfa2016-09-20 10:41:16 +000026 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
27
28 list<dag> ret1 = [(set P.DstVT:$vdst,
Sam Kolton4685b70a2017-07-18 14:23:26 +000029 (node (P.Src0VT src0)))];
Valery Pykhtine330cfa2016-09-20 10:41:16 +000030
31 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
32 !if(!eq(P.NumSrcArgs, 2), ret2,
33 ret1));
34}
35
Matt Arsenault9be7b0d2017-02-27 18:49:11 +000036class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
37 list<dag> ret3 = [(set P.DstVT:$vdst,
38 (node (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
39 (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
40 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
41 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))];
42
43 list<dag> ret2 = [(set P.DstVT:$vdst,
44 (node !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
45 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
46 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))];
47
48 list<dag> ret1 = [(set P.DstVT:$vdst,
49 (node (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
50
51 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
52 !if(!eq(P.NumSrcArgs, 2), ret2,
53 ret1));
54}
55
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +000056class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
57 list<dag> ret3 = [(set P.DstVT:$vdst,
58 (node (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
59 (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
60 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
61 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
62
63 list<dag> ret2 = [(set P.DstVT:$vdst,
64 (node !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
65 (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
66 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
67
68 list<dag> ret1 = [(set P.DstVT:$vdst,
69 (node (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
70
71 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
72 !if(!eq(P.NumSrcArgs, 2), ret2,
73 ret1));
74}
75
76class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
77 list<dag> ret3 = [(set P.DstVT:$vdst,
78 (node (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
79 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
80 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
81 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
82
83 list<dag> ret2 = [(set P.DstVT:$vdst,
84 (node !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
85 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
86 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
87
88 list<dag> ret1 = [(set P.DstVT:$vdst,
89 (node (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
90
91 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
92 !if(!eq(P.NumSrcArgs, 2), ret2,
93 ret1));
94}
95
Valery Pykhtine330cfa2016-09-20 10:41:16 +000096class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
97 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
98 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
99 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
100 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
101 !if(!eq(P.NumSrcArgs, 2), ret2,
102 ret1));
103}
104
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000105class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> {
106 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))];
107 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
108 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
109 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
110 !if(!eq(P.NumSrcArgs, 2), ret2,
111 ret1));
112}
113
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000114class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
Valery Pykhtin355103f2016-09-23 09:08:07 +0000115 VOP3_Pseudo<OpName, P,
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000116 !if(P.HasOpSel,
117 !if(P.HasModifiers,
118 getVOP3OpSelModPat<P, node>.ret,
119 getVOP3OpSelPat<P, node>.ret),
120 !if(P.HasModifiers,
121 getVOP3ModPat<P, node>.ret,
122 !if(P.HasIntClamp,
123 getVOP3ClampPat<P, node>.ret,
124 getVOP3Pat<P, node>.ret))),
125 VOP3Only, 0, P.HasOpSel> {
126
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000127 let IntClamp = P.HasIntClamp;
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000128 let AsmMatchConverter =
129 !if(P.HasOpSel,
130 "cvtVOP3OpSel",
131 !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
132 "cvtVOP3",
133 ""));
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000134}
135
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000136// Special case for v_div_fmas_{f32|f64}, since it seems to be the
137// only VOP instruction that implicitly reads VCC.
138let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
139def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
140 let Outs64 = (outs DstRC.RegClass:$vdst);
141}
142def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
143 let Outs64 = (outs DstRC.RegClass:$vdst);
144}
145}
146
147class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
148 list<dag> ret =
149 [(set P.DstVT:$vdst,
150 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
151 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
152 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
153 (i1 VCC)))];
154}
155
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000156class VOP3Features<bit Clamp, bit OpSel> {
157 bit HasClamp = Clamp;
158 bit HasOpSel = OpSel;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000159}
160
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000161def VOP3_REGULAR : VOP3Features<0, 0>;
162def VOP3_CLAMP : VOP3Features<1, 0>;
163def VOP3_OPSEL : VOP3Features<1, 1>;
164
165class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> {
166
167 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp);
168 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel);
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000169
170 // FIXME: Hack to stop printing _e64
171 let Outs64 = (outs DstRC.RegClass:$vdst);
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000172 let Asm64 =
173 " " # !if(Features.HasOpSel,
174 getAsmVOP3OpSel<NumSrcArgs,
175 HasIntClamp,
176 HasSrc0FloatMods,
177 HasSrc1FloatMods,
178 HasSrc2FloatMods>.ret,
179 !if(Features.HasClamp,
180 getAsm64<HasDst, NumSrcArgs, HasIntClamp,
181 HasModifiers, HasOMod, DstVT>.ret,
182 P.Asm64));
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000183}
184
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000185class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
Matt Arsenault3b99f122017-01-19 06:04:12 +0000186 // v_div_scale_{f32|f64} do not support input modifiers.
187 let HasModifiers = 0;
Sam Kolton4685b70a2017-07-18 14:23:26 +0000188 let HasOMod = 0;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000189 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
Matt Arsenault3b99f122017-01-19 06:04:12 +0000190 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000191}
192
193def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
194 // FIXME: Hack to stop printing _e64
195 let DstRC = RegisterOperand<VGPR_32>;
196}
197
198def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
199 // FIXME: Hack to stop printing _e64
200 let DstRC = RegisterOperand<VReg_64>;
201}
202
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000203def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000204 let HasClamp = 1;
205
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000206 // FIXME: Hack to stop printing _e64
207 let DstRC = RegisterOperand<VReg_64>;
208
209 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000210 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000211}
212
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000213//===----------------------------------------------------------------------===//
Dmitry Preobrazhensky50805a02017-08-07 13:14:12 +0000214// VOP3 INTERP
215//===----------------------------------------------------------------------===//
216
217class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
218 let AsmMatchConverter = "cvtVOP3Interp";
219}
220
221def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
222 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
223 Attr:$attr, AttrChan:$attrchan,
224 clampmod:$clamp, omod:$omod);
225
226 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
227}
228
229def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
230 let Ins64 = (ins InterpSlot:$src0,
231 Attr:$attr, AttrChan:$attrchan,
232 clampmod:$clamp, omod:$omod);
233
234 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
235
236 let HasClamp = 1;
237}
238
239class getInterp16Asm <bit HasSrc2, bit HasOMod> {
240 string src2 = !if(HasSrc2, ", $src2_modifiers", "");
241 string omod = !if(HasOMod, "$omod", "");
242 string ret =
243 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
244}
245
246class getInterp16Ins <bit HasSrc2, bit HasOMod,
247 Operand Src0Mod, Operand Src2Mod> {
248 dag ret = !if(HasSrc2,
249 !if(HasOMod,
250 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
251 Attr:$attr, AttrChan:$attrchan,
252 Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
253 highmod:$high, clampmod:$clamp, omod:$omod),
254 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
255 Attr:$attr, AttrChan:$attrchan,
256 Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
257 highmod:$high, clampmod:$clamp)
258 ),
259 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
260 Attr:$attr, AttrChan:$attrchan,
261 highmod:$high, clampmod:$clamp, omod:$omod)
262 );
263}
264
265class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
266
267 let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
268 let HasHigh = 1;
269
270 let Outs64 = (outs VGPR_32:$vdst);
271 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
272 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
273}
274
275//===----------------------------------------------------------------------===//
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000276// VOP3 Instructions
277//===----------------------------------------------------------------------===//
278
279let isCommutable = 1 in {
280
281def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
282def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000283def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
284def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000285def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
286def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
287def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
288
289let SchedRW = [WriteDoubleAdd] in {
290def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
291def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
292def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>;
293def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum, 1>;
294} // End SchedRW = [WriteDoubleAdd]
295
296let SchedRW = [WriteQuarterRate32] in {
297def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>;
298def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
299def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
300def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
301} // End SchedRW = [WriteQuarterRate32]
302
303let Uses = [VCC, EXEC] in {
304// v_div_fmas_f32:
305// result = src0 * src1 + src2
306// if (vcc)
307// result *= 2^32
308//
Valery Pykhtin355103f2016-09-23 09:08:07 +0000309def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000310 getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> {
311 let SchedRW = [WriteFloatFMA];
312}
313// v_div_fmas_f64:
314// result = src0 * src1 + src2
315// if (vcc)
316// result *= 2^64
317//
Valery Pykhtin355103f2016-09-23 09:08:07 +0000318def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000319 getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> {
320 let SchedRW = [WriteDouble];
321}
322} // End Uses = [VCC, EXEC]
323
324} // End isCommutable = 1
325
326def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
327def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
328def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
329def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
330def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
331def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
332def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
Stanislav Mekhanoshin1a61ab812017-06-09 19:03:00 +0000333def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>;
334def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000335def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
336def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
337def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
338def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
339def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
340def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
341def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
342def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
343def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000344def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
345def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
346def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
347def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000348def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
349def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
350
351let SchedRW = [WriteDoubleAdd] in {
352def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
353def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
354} // End SchedRW = [WriteDoubleAdd]
355
Valery Pykhtin355103f2016-09-23 09:08:07 +0000356def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000357 let SchedRW = [WriteFloatFMA, WriteSALU];
Matt Arsenault81da1142016-11-15 00:05:42 +0000358 let hasExtraSrcRegAllocReq = 1;
Matt Arsenault3b99f122017-01-19 06:04:12 +0000359 let AsmMatchConverter = "";
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000360}
361
362// Double precision division pre-scale.
Valery Pykhtin355103f2016-09-23 09:08:07 +0000363def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000364 let SchedRW = [WriteDouble, WriteSALU];
Matt Arsenault81da1142016-11-15 00:05:42 +0000365 let hasExtraSrcRegAllocReq = 1;
Matt Arsenault3b99f122017-01-19 06:04:12 +0000366 let AsmMatchConverter = "";
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000367}
368
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000369def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
Mark Searlese5c78322017-06-08 18:21:19 +0000370
371let Constraints = "@earlyclobber $vdst" in {
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000372def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
Mark Searlese5c78322017-06-08 18:21:19 +0000373} // End Constraints = "@earlyclobber $vdst"
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000374
375def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
376 let SchedRW = [WriteDouble];
377}
378
379// These instructions only exist on SI and CI
380let SubtargetPredicate = isSICI in {
381def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
382def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
383def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
384def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
385} // End SubtargetPredicate = isSICI
386
387let SubtargetPredicate = isVI in {
388def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
389def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
390def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
391} // End SubtargetPredicate = isVI
392
393
394let SubtargetPredicate = isCIVI in {
395
Mark Searlese5c78322017-06-08 18:21:19 +0000396let Constraints = "@earlyclobber $vdst" in {
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000397def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
398def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>;
Mark Searlese5c78322017-06-08 18:21:19 +0000399} // End Constraints = "@earlyclobber $vdst"
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000400
401let isCommutable = 1 in {
Matt Arsenault4709ab92017-11-08 00:48:25 +0000402let SchedRW = [WriteDouble, WriteSALU] in {
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000403def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
404def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
Matt Arsenault4709ab92017-11-08 00:48:25 +0000405} // End SchedRW = [WriteDouble, WriteSALU]
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000406} // End isCommutable = 1
407
408} // End SubtargetPredicate = isCIVI
409
410
Sam Koltonf7659d712017-05-23 10:08:55 +0000411let SubtargetPredicate = Has16BitInsts in {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000412
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +0000413let renamedInGFX9 = 1 in {
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000414def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
415}
416let SubtargetPredicate = isGFX9 in {
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000417def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000418}
Stanislav Mekhanoshinca5d2ef2017-06-03 00:16:44 +0000419
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000420let isCommutable = 1 in {
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000421
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +0000422let renamedInGFX9 = 1 in {
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000423def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000424def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
425def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000426def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
427}
428
429let SubtargetPredicate = isGFX9 in {
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000430def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
431def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
432def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
433def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000434} // End SubtargetPredicate = isGFX9
Dmitry Preobrazhensky50805a02017-08-07 13:14:12 +0000435
436def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
437def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
438def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
439
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000440} // End isCommutable = 1
Sam Koltonf7659d712017-05-23 10:08:55 +0000441} // End SubtargetPredicate = Has16BitInsts
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000442
Sam Koltonf7659d712017-05-23 10:08:55 +0000443let SubtargetPredicate = isVI in {
Dmitry Preobrazhensky50805a02017-08-07 13:14:12 +0000444def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
445def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
446def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
447
Dmitry Preobrazhensky14104e02017-04-12 17:10:07 +0000448def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000449} // End SubtargetPredicate = isVI
450
Sam Koltonf7659d712017-05-23 10:08:55 +0000451let Predicates = [Has16BitInsts] in {
Tom Stellard115a6152016-11-10 16:02:37 +0000452
Matt Arsenault10268f92017-02-27 22:40:39 +0000453multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
454 Instruction inst, SDPatternOperator op3> {
Matt Arsenault90c75932017-10-03 00:06:41 +0000455def : GCNPat <
Tom Stellard115a6152016-11-10 16:02:37 +0000456 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000457 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
Tom Stellard115a6152016-11-10 16:02:37 +0000458>;
459
Matt Arsenault90c75932017-10-03 00:06:41 +0000460def : GCNPat<
Tom Stellard115a6152016-11-10 16:02:37 +0000461 (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000462 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
Tom Stellard115a6152016-11-10 16:02:37 +0000463>;
464
Matt Arsenault90c75932017-10-03 00:06:41 +0000465def : GCNPat<
Tom Stellard115a6152016-11-10 16:02:37 +0000466 (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
467 (REG_SEQUENCE VReg_64,
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000468 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)), sub0,
Tom Stellard115a6152016-11-10 16:02:37 +0000469 (V_MOV_B32_e32 (i32 0)), sub1)
470>;
471}
472
Matt Arsenault10268f92017-02-27 22:40:39 +0000473defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
474defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
Tom Stellard115a6152016-11-10 16:02:37 +0000475
Sam Koltonf7659d712017-05-23 10:08:55 +0000476} // End Predicates = [Has16BitInsts]
Tom Stellard115a6152016-11-10 16:02:37 +0000477
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000478let SubtargetPredicate = isGFX9 in {
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000479def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
Matt Arsenaultc9f25172017-02-27 21:04:41 +0000480def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
481def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
482def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
483def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
484def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
485def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
Matt Arsenault10268f92017-02-27 22:40:39 +0000486
Matt Arsenault03612632017-02-28 20:27:30 +0000487def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000488
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000489def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>;
490def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>;
491def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000492
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000493def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>;
494def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>;
495def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000496
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000497def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>;
498def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>;
499def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>;
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000500
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000501def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
502def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000503
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000504def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
505def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000506
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000507def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
508def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +0000509
510def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
511def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000512} // End SubtargetPredicate = isGFX9
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000513
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000514//===----------------------------------------------------------------------===//
515// Integer Clamp Patterns
516//===----------------------------------------------------------------------===//
517
518class getClampPat<VOPProfile P, SDPatternOperator node> {
519 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
520 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
521 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
522 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
523 !if(!eq(P.NumSrcArgs, 2), ret2,
524 ret1));
525}
526
527class getClampRes<VOPProfile P, Instruction inst> {
528 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
529 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
530 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
531 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
532 !if(!eq(P.NumSrcArgs, 2), ret2,
533 ret1));
534}
535
Matt Arsenault90c75932017-10-03 00:06:41 +0000536class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat<
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000537 getClampPat<inst.Pfl, node>.ret,
538 getClampRes<inst.Pfl, inst>.ret
539>;
540
541def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>;
542def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>;
543
544def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>;
545def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>;
546def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>;
547
548def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>;
549def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>;
550
551def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>;
552def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000553
554//===----------------------------------------------------------------------===//
555// Target
556//===----------------------------------------------------------------------===//
557
558//===----------------------------------------------------------------------===//
559// SI
560//===----------------------------------------------------------------------===//
561
562let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
563
564multiclass VOP3_Real_si<bits<9> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000565 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
566 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000567}
568
569multiclass VOP3be_Real_si<bits<9> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000570 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
571 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000572}
573
574} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
575
576defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>;
577defm V_MAD_F32 : VOP3_Real_si <0x141>;
578defm V_MAD_I32_I24 : VOP3_Real_si <0x142>;
579defm V_MAD_U32_U24 : VOP3_Real_si <0x143>;
580defm V_CUBEID_F32 : VOP3_Real_si <0x144>;
581defm V_CUBESC_F32 : VOP3_Real_si <0x145>;
582defm V_CUBETC_F32 : VOP3_Real_si <0x146>;
583defm V_CUBEMA_F32 : VOP3_Real_si <0x147>;
584defm V_BFE_U32 : VOP3_Real_si <0x148>;
585defm V_BFE_I32 : VOP3_Real_si <0x149>;
586defm V_BFI_B32 : VOP3_Real_si <0x14a>;
587defm V_FMA_F32 : VOP3_Real_si <0x14b>;
588defm V_FMA_F64 : VOP3_Real_si <0x14c>;
589defm V_LERP_U8 : VOP3_Real_si <0x14d>;
590defm V_ALIGNBIT_B32 : VOP3_Real_si <0x14e>;
591defm V_ALIGNBYTE_B32 : VOP3_Real_si <0x14f>;
592defm V_MULLIT_F32 : VOP3_Real_si <0x150>;
593defm V_MIN3_F32 : VOP3_Real_si <0x151>;
594defm V_MIN3_I32 : VOP3_Real_si <0x152>;
595defm V_MIN3_U32 : VOP3_Real_si <0x153>;
596defm V_MAX3_F32 : VOP3_Real_si <0x154>;
597defm V_MAX3_I32 : VOP3_Real_si <0x155>;
598defm V_MAX3_U32 : VOP3_Real_si <0x156>;
599defm V_MED3_F32 : VOP3_Real_si <0x157>;
600defm V_MED3_I32 : VOP3_Real_si <0x158>;
601defm V_MED3_U32 : VOP3_Real_si <0x159>;
602defm V_SAD_U8 : VOP3_Real_si <0x15a>;
603defm V_SAD_HI_U8 : VOP3_Real_si <0x15b>;
604defm V_SAD_U16 : VOP3_Real_si <0x15c>;
605defm V_SAD_U32 : VOP3_Real_si <0x15d>;
606defm V_CVT_PK_U8_F32 : VOP3_Real_si <0x15e>;
607defm V_DIV_FIXUP_F32 : VOP3_Real_si <0x15f>;
608defm V_DIV_FIXUP_F64 : VOP3_Real_si <0x160>;
609defm V_LSHL_B64 : VOP3_Real_si <0x161>;
610defm V_LSHR_B64 : VOP3_Real_si <0x162>;
611defm V_ASHR_I64 : VOP3_Real_si <0x163>;
612defm V_ADD_F64 : VOP3_Real_si <0x164>;
613defm V_MUL_F64 : VOP3_Real_si <0x165>;
614defm V_MIN_F64 : VOP3_Real_si <0x166>;
615defm V_MAX_F64 : VOP3_Real_si <0x167>;
616defm V_LDEXP_F64 : VOP3_Real_si <0x168>;
617defm V_MUL_LO_U32 : VOP3_Real_si <0x169>;
618defm V_MUL_HI_U32 : VOP3_Real_si <0x16a>;
619defm V_MUL_LO_I32 : VOP3_Real_si <0x16b>;
620defm V_MUL_HI_I32 : VOP3_Real_si <0x16c>;
621defm V_DIV_SCALE_F32 : VOP3be_Real_si <0x16d>;
622defm V_DIV_SCALE_F64 : VOP3be_Real_si <0x16e>;
623defm V_DIV_FMAS_F32 : VOP3_Real_si <0x16f>;
624defm V_DIV_FMAS_F64 : VOP3_Real_si <0x170>;
625defm V_MSAD_U8 : VOP3_Real_si <0x171>;
626defm V_MQSAD_PK_U16_U8 : VOP3_Real_si <0x173>;
627defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
628
629//===----------------------------------------------------------------------===//
630// CI
631//===----------------------------------------------------------------------===//
632
633multiclass VOP3_Real_ci<bits<9> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000634 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
635 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000636 let AssemblerPredicates = [isCIOnly];
637 let DecoderNamespace = "CI";
638 }
639}
640
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000641multiclass VOP3be_Real_ci<bits<9> op> {
642 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
643 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
644 let AssemblerPredicates = [isCIOnly];
645 let DecoderNamespace = "CI";
646 }
647}
648
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000649defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>;
Dmitry Preobrazhensky3bff0c82017-04-12 15:36:09 +0000650defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x175>;
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000651defm V_MAD_U64_U32 : VOP3be_Real_ci <0x176>;
652defm V_MAD_I64_I32 : VOP3be_Real_ci <0x177>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000653
654//===----------------------------------------------------------------------===//
655// VI
656//===----------------------------------------------------------------------===//
657
658let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
659
660multiclass VOP3_Real_vi<bits<10> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000661 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
662 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000663}
664
665multiclass VOP3be_Real_vi<bits<10> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000666 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
667 VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000668}
669
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000670multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
671 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
672 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
673}
674
Dmitry Preobrazhensky50805a02017-08-07 13:14:12 +0000675multiclass VOP3Interp_Real_vi<bits<10> op> {
676 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
677 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
678}
679
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000680} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
681
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000682let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
683
684multiclass VOP3_F16_Real_vi<bits<10> op> {
685 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
686 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
687}
688
689} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
690
691let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
692
693multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
694 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
695 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
696 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
697 let AsmString = AsmName # ps.AsmOperands;
698 }
699}
700
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000701multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
702 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
703 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
704 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
705 let AsmString = AsmName # ps.AsmOperands;
706 }
707}
708
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +0000709multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
710 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
711 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
712 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
713 let AsmString = AsmName # ps.AsmOperands;
714 }
715}
716
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000717} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
718
Dmitry Preobrazhensky895d3772017-03-22 13:31:01 +0000719defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
720defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000721
722defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
723defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
724defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
725defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
726defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
727defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
728defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
729defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
730defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
731defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
732defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
733defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
734defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
735defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
736defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
737defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
738defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
739defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
740defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
741defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
742defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
743defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
744defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
745defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
746defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
747defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
748defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
749defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
750defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
751defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
752defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
753defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
754defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
755defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
756defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
757defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
758defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
759defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
760defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
761defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
762
Dmitry Preobrazhensky14104e02017-04-12 17:10:07 +0000763defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
764
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000765defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>;
766defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>;
767defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
768defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
769defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
770
771defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
772defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
773defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
774defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
775defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
776
Dmitry Preobrazhenskyb865ef52017-08-16 15:16:32 +0000777defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
778defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
779defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
780defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
781defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000782
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +0000783defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
784defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
785
Dmitry Preobrazhensky50805a02017-08-07 13:14:12 +0000786defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
787defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
788defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
789
790defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
791defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
792defm V_INTERP_P2_F16 : VOP3Interp_Real_vi <0x276>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000793defm V_ADD_F64 : VOP3_Real_vi <0x280>;
794defm V_MUL_F64 : VOP3_Real_vi <0x281>;
795defm V_MIN_F64 : VOP3_Real_vi <0x282>;
796defm V_MAX_F64 : VOP3_Real_vi <0x283>;
797defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
798defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
799
800// removed from VI as identical to V_MUL_LO_U32
801let isAsmParserOnly = 1 in {
802defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
803}
804
805defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
806defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
807
808defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
809defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
810defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
811defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000812
Matt Arsenaultc9f25172017-02-27 21:04:41 +0000813defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
814defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
815defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
816defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
817defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
818defm V_OR3_B32 : VOP3_Real_vi <0x202>;
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000819defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
Matt Arsenault10268f92017-02-27 22:40:39 +0000820
Matt Arsenault03612632017-02-28 20:27:30 +0000821defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000822
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000823defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
824defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
825defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000826
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000827defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
828defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
829defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000830
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000831defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
832defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
833defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
834
835defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>;
836defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>;
837
838defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
839defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
840
841defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
842defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;