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Igor Bregerb4442f32017-02-10 07:05:56 +00001//===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the targeting of the Machinelegalizer class for X86.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#include "X86LegalizerInfo.h"
15#include "X86Subtarget.h"
Igor Breger531a2032017-03-26 08:11:12 +000016#include "X86TargetMachine.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +000017#include "llvm/CodeGen/TargetOpcodes.h"
Igor Bregerb4442f32017-02-10 07:05:56 +000018#include "llvm/CodeGen/ValueTypes.h"
19#include "llvm/IR/DerivedTypes.h"
20#include "llvm/IR/Type.h"
Igor Bregerb4442f32017-02-10 07:05:56 +000021
22using namespace llvm;
Igor Breger321cf3c2017-03-03 08:06:46 +000023using namespace TargetOpcode;
Igor Bregerb4442f32017-02-10 07:05:56 +000024
Kristof Beylsaf9814a2017-11-07 10:34:34 +000025/// FIXME: The following static functions are SizeChangeStrategy functions
26/// that are meant to temporarily mimic the behaviour of the old legalization
27/// based on doubling/halving non-legal types as closely as possible. This is
28/// not entirly possible as only legalizing the types that are exactly a power
29/// of 2 times the size of the legal types would require specifying all those
30/// sizes explicitly.
31/// In practice, not specifying those isn't a problem, and the below functions
32/// should disappear quickly as we add support for legalizing non-power-of-2
33/// sized types further.
34static void
35addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
36 const LegalizerInfo::SizeAndActionsVec &v) {
37 for (unsigned i = 0; i < v.size(); ++i) {
38 result.push_back(v[i]);
39 if (i + 1 < v[i].first && i + 1 < v.size() &&
40 v[i + 1].first != v[i].first + 1)
41 result.push_back({v[i].first + 1, LegalizerInfo::Unsupported});
42 }
43}
44
45static LegalizerInfo::SizeAndActionsVec
46widen_1(const LegalizerInfo::SizeAndActionsVec &v) {
47 assert(v.size() >= 1);
48 assert(v[0].first > 1);
49 LegalizerInfo::SizeAndActionsVec result = {{1, LegalizerInfo::WidenScalar},
50 {2, LegalizerInfo::Unsupported}};
51 addAndInterleaveWithUnsupported(result, v);
52 auto Largest = result.back().first;
53 result.push_back({Largest + 1, LegalizerInfo::Unsupported});
54 return result;
55}
56
Igor Breger531a2032017-03-26 08:11:12 +000057X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
58 const X86TargetMachine &TM)
59 : Subtarget(STI), TM(TM) {
Igor Bregerb4442f32017-02-10 07:05:56 +000060
61 setLegalizerInfo32bit();
62 setLegalizerInfo64bit();
Igor Breger321cf3c2017-03-03 08:06:46 +000063 setLegalizerInfoSSE1();
64 setLegalizerInfoSSE2();
Igor Breger605b9652017-05-08 09:03:37 +000065 setLegalizerInfoSSE41();
Igor Breger617be6e2017-05-23 08:23:51 +000066 setLegalizerInfoAVX();
Igor Breger605b9652017-05-08 09:03:37 +000067 setLegalizerInfoAVX2();
68 setLegalizerInfoAVX512();
69 setLegalizerInfoAVX512DQ();
70 setLegalizerInfoAVX512BW();
Igor Bregerb4442f32017-02-10 07:05:56 +000071
Kristof Beylsaf9814a2017-11-07 10:34:34 +000072 setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0, widen_1);
73 for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
74 setLegalizeScalarToDifferentSizeStrategy(BinOp, 0, widen_1);
75 for (unsigned MemOp : {G_LOAD, G_STORE})
76 setLegalizeScalarToDifferentSizeStrategy(MemOp, 0,
77 narrowToSmallerAndWidenToSmallest);
78 setLegalizeScalarToDifferentSizeStrategy(
79 G_GEP, 1, widenToLargerTypesUnsupportedOtherwise);
80 setLegalizeScalarToDifferentSizeStrategy(
81 G_CONSTANT, 0, widenToLargerTypesAndNarrowToLargest);
82
Igor Bregerb4442f32017-02-10 07:05:56 +000083 computeTables();
84}
85
86void X86LegalizerInfo::setLegalizerInfo32bit() {
87
Igor Breger42f8bfc2017-08-31 11:40:03 +000088 const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
Igor Breger29537882017-04-07 14:41:59 +000089 const LLT s1 = LLT::scalar(1);
Igor Bregerb4442f32017-02-10 07:05:56 +000090 const LLT s8 = LLT::scalar(8);
91 const LLT s16 = LLT::scalar(16);
92 const LLT s32 = LLT::scalar(32);
93
Igor Breger47be5fb2017-08-24 07:06:27 +000094 for (auto Ty : {p0, s1, s8, s16, s32})
95 setAction({G_IMPLICIT_DEF, Ty}, Legal);
96
Igor Breger2661ae42017-09-04 09:06:45 +000097 for (auto Ty : {s8, s16, s32, p0})
98 setAction({G_PHI, Ty}, Legal);
99
Kristof Beylsaf9814a2017-11-07 10:34:34 +0000100 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
Igor Bregera8ba5722017-03-23 15:25:57 +0000101 for (auto Ty : {s8, s16, s32})
102 setAction({BinOp, Ty}, Legal);
103
Igor Breger28f290f2017-05-17 12:48:08 +0000104 for (unsigned Op : {G_UADDE}) {
105 setAction({Op, s32}, Legal);
106 setAction({Op, 1, s1}, Legal);
107 }
108
Igor Bregera8ba5722017-03-23 15:25:57 +0000109 for (unsigned MemOp : {G_LOAD, G_STORE}) {
110 for (auto Ty : {s8, s16, s32, p0})
111 setAction({MemOp, Ty}, Legal);
112
113 // And everything's fine in addrspace 0.
114 setAction({MemOp, 1, p0}, Legal);
Igor Bregerf7359d82017-02-22 12:25:09 +0000115 }
Igor Breger531a2032017-03-26 08:11:12 +0000116
117 // Pointer-handling
118 setAction({G_FRAME_INDEX, p0}, Legal);
Igor Breger717bd362017-07-02 08:58:29 +0000119 setAction({G_GLOBAL_VALUE, p0}, Legal);
Igor Breger29537882017-04-07 14:41:59 +0000120
Igor Breger810c6252017-05-08 09:40:43 +0000121 setAction({G_GEP, p0}, Legal);
122 setAction({G_GEP, 1, s32}, Legal);
123
Igor Breger685889c2017-08-21 10:51:54 +0000124 // Control-flow
125 setAction({G_BRCOND, s1}, Legal);
126
Igor Breger29537882017-04-07 14:41:59 +0000127 // Constants
128 for (auto Ty : {s8, s16, s32, p0})
129 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
130
Igor Bregerc08a7832017-05-01 06:30:16 +0000131 // Extensions
Igor Bregerd48c5e42017-07-10 09:07:34 +0000132 for (auto Ty : {s8, s16, s32}) {
133 setAction({G_ZEXT, Ty}, Legal);
134 setAction({G_SEXT, Ty}, Legal);
Igor Breger1f143642017-09-11 09:41:13 +0000135 setAction({G_ANYEXT, Ty}, Legal);
Igor Bregerd48c5e42017-07-10 09:07:34 +0000136 }
Igor Bregerc08a7832017-05-01 06:30:16 +0000137
Igor Bregerc7b59772017-05-11 07:17:40 +0000138 // Comparison
139 setAction({G_ICMP, s1}, Legal);
140
141 for (auto Ty : {s8, s16, s32, p0})
142 setAction({G_ICMP, 1, Ty}, Legal);
Igor Bregerb4442f32017-02-10 07:05:56 +0000143}
Igor Bregerb4442f32017-02-10 07:05:56 +0000144
Igor Bregerf7359d82017-02-22 12:25:09 +0000145void X86LegalizerInfo::setLegalizerInfo64bit() {
Igor Bregerb4442f32017-02-10 07:05:56 +0000146
147 if (!Subtarget.is64Bit())
148 return;
149
150 const LLT s64 = LLT::scalar(64);
151
Igor Breger42f8bfc2017-08-31 11:40:03 +0000152 setAction({G_IMPLICIT_DEF, s64}, Legal);
Igor Breger47be5fb2017-08-24 07:06:27 +0000153
Igor Breger2661ae42017-09-04 09:06:45 +0000154 setAction({G_PHI, s64}, Legal);
155
Igor Bregerd5b59cf2017-06-28 11:39:04 +0000156 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
Igor Breger42f8bfc2017-08-31 11:40:03 +0000157 setAction({BinOp, s64}, Legal);
Igor Bregera8ba5722017-03-23 15:25:57 +0000158
Igor Breger1f143642017-09-11 09:41:13 +0000159 for (unsigned MemOp : {G_LOAD, G_STORE})
Igor Breger42f8bfc2017-08-31 11:40:03 +0000160 setAction({MemOp, s64}, Legal);
Igor Breger531a2032017-03-26 08:11:12 +0000161
162 // Pointer-handling
Igor Breger810c6252017-05-08 09:40:43 +0000163 setAction({G_GEP, 1, s64}, Legal);
164
Igor Breger29537882017-04-07 14:41:59 +0000165 // Constants
Igor Breger42f8bfc2017-08-31 11:40:03 +0000166 setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
Igor Bregerc08a7832017-05-01 06:30:16 +0000167
168 // Extensions
Igor Breger1f143642017-09-11 09:41:13 +0000169 for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
170 setAction({extOp, s64}, Legal);
Igor Breger1f143642017-09-11 09:41:13 +0000171 }
Igor Bregerc7b59772017-05-11 07:17:40 +0000172
173 // Comparison
Igor Breger42f8bfc2017-08-31 11:40:03 +0000174 setAction({G_ICMP, 1, s64}, Legal);
Igor Breger321cf3c2017-03-03 08:06:46 +0000175}
176
177void X86LegalizerInfo::setLegalizerInfoSSE1() {
178 if (!Subtarget.hasSSE1())
179 return;
180
181 const LLT s32 = LLT::scalar(32);
182 const LLT v4s32 = LLT::vector(4, 32);
Igor Bregera8ba5722017-03-23 15:25:57 +0000183 const LLT v2s64 = LLT::vector(2, 64);
Igor Breger321cf3c2017-03-03 08:06:46 +0000184
185 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
186 for (auto Ty : {s32, v4s32})
187 setAction({BinOp, Ty}, Legal);
Igor Bregera8ba5722017-03-23 15:25:57 +0000188
189 for (unsigned MemOp : {G_LOAD, G_STORE})
190 for (auto Ty : {v4s32, v2s64})
191 setAction({MemOp, Ty}, Legal);
Igor Breger21200ed2017-09-17 08:08:13 +0000192
193 // Constants
194 setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
Igor Breger321cf3c2017-03-03 08:06:46 +0000195}
196
197void X86LegalizerInfo::setLegalizerInfoSSE2() {
198 if (!Subtarget.hasSSE2())
199 return;
200
Igor Breger5c7211992017-09-13 09:05:23 +0000201 const LLT s32 = LLT::scalar(32);
Igor Breger321cf3c2017-03-03 08:06:46 +0000202 const LLT s64 = LLT::scalar(64);
Igor Breger842b5b32017-05-18 11:10:56 +0000203 const LLT v16s8 = LLT::vector(16, 8);
Igor Breger605b9652017-05-08 09:03:37 +0000204 const LLT v8s16 = LLT::vector(8, 16);
Igor Breger321cf3c2017-03-03 08:06:46 +0000205 const LLT v4s32 = LLT::vector(4, 32);
206 const LLT v2s64 = LLT::vector(2, 64);
207
208 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
209 for (auto Ty : {s64, v2s64})
210 setAction({BinOp, Ty}, Legal);
211
212 for (unsigned BinOp : {G_ADD, G_SUB})
Igor Breger842b5b32017-05-18 11:10:56 +0000213 for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
Igor Breger321cf3c2017-03-03 08:06:46 +0000214 setAction({BinOp, Ty}, Legal);
Igor Breger605b9652017-05-08 09:03:37 +0000215
216 setAction({G_MUL, v8s16}, Legal);
Igor Breger5c7211992017-09-13 09:05:23 +0000217
218 setAction({G_FPEXT, s64}, Legal);
219 setAction({G_FPEXT, 1, s32}, Legal);
Igor Breger21200ed2017-09-17 08:08:13 +0000220
221 // Constants
222 setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
Igor Breger605b9652017-05-08 09:03:37 +0000223}
224
225void X86LegalizerInfo::setLegalizerInfoSSE41() {
226 if (!Subtarget.hasSSE41())
227 return;
228
229 const LLT v4s32 = LLT::vector(4, 32);
230
231 setAction({G_MUL, v4s32}, Legal);
232}
233
Igor Breger617be6e2017-05-23 08:23:51 +0000234void X86LegalizerInfo::setLegalizerInfoAVX() {
235 if (!Subtarget.hasAVX())
236 return;
237
Igor Breger1c29be72017-06-22 09:43:35 +0000238 const LLT v16s8 = LLT::vector(16, 8);
239 const LLT v8s16 = LLT::vector(8, 16);
240 const LLT v4s32 = LLT::vector(4, 32);
241 const LLT v2s64 = LLT::vector(2, 64);
242
243 const LLT v32s8 = LLT::vector(32, 8);
244 const LLT v16s16 = LLT::vector(16, 16);
Igor Breger617be6e2017-05-23 08:23:51 +0000245 const LLT v8s32 = LLT::vector(8, 32);
246 const LLT v4s64 = LLT::vector(4, 64);
247
248 for (unsigned MemOp : {G_LOAD, G_STORE})
249 for (auto Ty : {v8s32, v4s64})
250 setAction({MemOp, Ty}, Legal);
Igor Breger1c29be72017-06-22 09:43:35 +0000251
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000252 for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
Igor Breger1c29be72017-06-22 09:43:35 +0000253 setAction({G_INSERT, Ty}, Legal);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000254 setAction({G_EXTRACT, 1, Ty}, Legal);
255 }
256 for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
Igor Breger1c29be72017-06-22 09:43:35 +0000257 setAction({G_INSERT, 1, Ty}, Legal);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000258 setAction({G_EXTRACT, Ty}, Legal);
259 }
Igor Breger617be6e2017-05-23 08:23:51 +0000260}
261
Igor Breger605b9652017-05-08 09:03:37 +0000262void X86LegalizerInfo::setLegalizerInfoAVX2() {
263 if (!Subtarget.hasAVX2())
264 return;
265
Igor Breger842b5b32017-05-18 11:10:56 +0000266 const LLT v32s8 = LLT::vector(32, 8);
Igor Breger605b9652017-05-08 09:03:37 +0000267 const LLT v16s16 = LLT::vector(16, 16);
268 const LLT v8s32 = LLT::vector(8, 32);
Igor Breger842b5b32017-05-18 11:10:56 +0000269 const LLT v4s64 = LLT::vector(4, 64);
270
271 for (unsigned BinOp : {G_ADD, G_SUB})
272 for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
273 setAction({BinOp, Ty}, Legal);
Igor Breger605b9652017-05-08 09:03:37 +0000274
275 for (auto Ty : {v16s16, v8s32})
276 setAction({G_MUL, Ty}, Legal);
277}
278
279void X86LegalizerInfo::setLegalizerInfoAVX512() {
280 if (!Subtarget.hasAVX512())
281 return;
282
Igor Breger1c29be72017-06-22 09:43:35 +0000283 const LLT v16s8 = LLT::vector(16, 8);
284 const LLT v8s16 = LLT::vector(8, 16);
285 const LLT v4s32 = LLT::vector(4, 32);
286 const LLT v2s64 = LLT::vector(2, 64);
287
288 const LLT v32s8 = LLT::vector(32, 8);
289 const LLT v16s16 = LLT::vector(16, 16);
290 const LLT v8s32 = LLT::vector(8, 32);
291 const LLT v4s64 = LLT::vector(4, 64);
292
293 const LLT v64s8 = LLT::vector(64, 8);
294 const LLT v32s16 = LLT::vector(32, 16);
Igor Breger605b9652017-05-08 09:03:37 +0000295 const LLT v16s32 = LLT::vector(16, 32);
Igor Breger842b5b32017-05-18 11:10:56 +0000296 const LLT v8s64 = LLT::vector(8, 64);
297
298 for (unsigned BinOp : {G_ADD, G_SUB})
299 for (auto Ty : {v16s32, v8s64})
300 setAction({BinOp, Ty}, Legal);
Igor Breger605b9652017-05-08 09:03:37 +0000301
302 setAction({G_MUL, v16s32}, Legal);
303
Igor Breger617be6e2017-05-23 08:23:51 +0000304 for (unsigned MemOp : {G_LOAD, G_STORE})
305 for (auto Ty : {v16s32, v8s64})
306 setAction({MemOp, Ty}, Legal);
307
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000308 for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
Igor Breger1c29be72017-06-22 09:43:35 +0000309 setAction({G_INSERT, Ty}, Legal);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000310 setAction({G_EXTRACT, 1, Ty}, Legal);
311 }
312 for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
Igor Breger1c29be72017-06-22 09:43:35 +0000313 setAction({G_INSERT, 1, Ty}, Legal);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000314 setAction({G_EXTRACT, Ty}, Legal);
315 }
Igor Breger1c29be72017-06-22 09:43:35 +0000316
Igor Breger605b9652017-05-08 09:03:37 +0000317 /************ VLX *******************/
318 if (!Subtarget.hasVLX())
319 return;
320
Igor Breger605b9652017-05-08 09:03:37 +0000321 for (auto Ty : {v4s32, v8s32})
322 setAction({G_MUL, Ty}, Legal);
323}
324
325void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
326 if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
327 return;
328
329 const LLT v8s64 = LLT::vector(8, 64);
330
331 setAction({G_MUL, v8s64}, Legal);
332
333 /************ VLX *******************/
334 if (!Subtarget.hasVLX())
335 return;
336
337 const LLT v2s64 = LLT::vector(2, 64);
338 const LLT v4s64 = LLT::vector(4, 64);
339
340 for (auto Ty : {v2s64, v4s64})
341 setAction({G_MUL, Ty}, Legal);
342}
343
344void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
345 if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
346 return;
347
Igor Breger842b5b32017-05-18 11:10:56 +0000348 const LLT v64s8 = LLT::vector(64, 8);
Igor Breger605b9652017-05-08 09:03:37 +0000349 const LLT v32s16 = LLT::vector(32, 16);
350
Igor Breger842b5b32017-05-18 11:10:56 +0000351 for (unsigned BinOp : {G_ADD, G_SUB})
352 for (auto Ty : {v64s8, v32s16})
353 setAction({BinOp, Ty}, Legal);
354
Igor Breger605b9652017-05-08 09:03:37 +0000355 setAction({G_MUL, v32s16}, Legal);
356
357 /************ VLX *******************/
358 if (!Subtarget.hasVLX())
359 return;
360
361 const LLT v8s16 = LLT::vector(8, 16);
362 const LLT v16s16 = LLT::vector(16, 16);
363
364 for (auto Ty : {v8s16, v16s16})
365 setAction({G_MUL, Ty}, Legal);
Igor Bregerb4442f32017-02-10 07:05:56 +0000366}